PCIe-based multi-core 8K decoding display method

Abstract

The invention relates to the technical field of video processing, in particular to a PCIe-based multi-core 8K decoding display method, which is implemented on the basis of an FPGA (Field Programmable Gate Array), a plurality of decoding chips and a CPU (Central Processing Unit), and is characterized in that the FPGA and the plurality of decoding chips are connected with the CPU through a PCIe bus; according to the method, data is controlled to be synchronously sent to four decoders for decoding through PCIe msi-x interruption, it is guaranteed that only one frame of data to be decoded exists in the decoders, the decoders are not cached, and therefore the smooth and synchronous display of videos is achieved. In addition, different DMA devices share the DMA memory, so that the data sending efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of video processing technology, and in particular to a multi-core 8K decoding and display method based on PCIe. Background Art

[0002] Each frame of 8K YUV42210bit video contains about 80MB of information, which is nearly twice the amount of information of YUV4208bit video, providing users with richer and more delicate video information. Among them, YUV is a color encoding method, which is often used in various video processing components. "Y" represents brightness (Luminance or Luma), that is, grayscale value, and "U" and "V" represent chrominance (Chrominance or Chroma), which is used to describe the color and saturation of the image and is used to specify the color of the pixel. However, 8K YUV42210bit video places high demands on the decoding capability of the GPU. Currently, only high-end professional graphics cards can provide decoding support. However, these professional graphics cards are expensive and large in size, and are not easy to carry. Most 8K decoders on the market can only decode 8K YUV4208bit videos, and the picture quality is poor. In order to solve the above problems, it is necessary to design a multi-core 8K decoding and display method based on PCIe. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a multi-core 8K decoding and display method based on PCIe. Four 4K decoding chips are used in conjunction with FPGA embedded design to successfully realize the decoding and synchronous display of 8KYUV42210bit video, effectively solving the problems that professional graphics cards are too expensive and inconvenient to carry, and other devices cannot decode and display.

[0004] The technical solution adopted by the present invention to solve the technical problem is:

[0005] A multi-core 8K decoding and display method based on PCIe is implemented based on FPGA, multiple decoding chips, and CPU, wherein the FPGA and multiple decoding chips are connected to the CPU via a PCIe bus; the method comprises:

[0006] The CPU receives the TS (Transport Stream) data to be decoded and displayed, and parses the TS data, and obtains the resolution and Tile information of the data according to the header information contained in the TS data; splits the 8K decoded data into four 4K ES data according to the Tile information, and puts them into the ring buffer cache;

[0007] The FPGAPCIe msi-x interrupt method is used to make the CPU send decoded data according to the FPGA clock. Specifically, the CPU sends the video frame rate information obtained after parsing to the FPGA through the PCIe bus;

[0008] FPGA controls the number of MSI-X interrupts generated per second according to the video frame rate information. After the CPU obtains the interrupt, it immediately takes a frame of data from the ring buffer and sends it to the four decoding chips for decoding. The use of interrupts can avoid using the cache of the decoding chip, thereby ensuring that the four 4K decoded by the four decoding chips belong to the same frame of 8K picture, thereby ensuring the synchronization of the four pictures.

[0009] The decoded raw data will be sent to the CPU via PCIe first, and then the CPU will use QDMA driver to send the raw data to FPGA via PCIe, which can reduce the time consumption caused by data copying and improve the transmission efficiency;

[0010] After receiving the decoded data, the FPGA first caches 3 frames, and then displays the first received frame of data according to the clock that triggers the MSI-X interrupt. After receiving the interrupt, the CPU sends a frame of ES data to the decoding chip for decoding to fill the FPGA cache, thereby achieving smooth playback and display.

[0011] Furthermore, if the TS is not sent to the CPU on time due to occasional network fluctuations, the threshold of the ring buffer is used for judgment. If it is below the lower threshold, the I frame is copied during parsing to increase the number of frames and prevent the black screen from being displayed due to no data decoding. Since the I frame is an independently encoded frame, copying the I frame will not cause decoding abnormalities.

[0012] Furthermore, the 8K decoded data is split into four 4K ES data using software such as gstreamer or ffmpeg according to the Tile information.

[0013] Furthermore, the data to be decoded and displayed is a local file or a network data stream.

[0014] Technical effects of the present invention:

[0015] Compared with the prior art, the present invention provides an 8Kyuv42210bit video decoding solution; a method for synchronously sending data to four decoders for decoding through PCIe msi-x interrupt control, ensuring that there is only one frame of data to be decoded in the decoder, and preventing the decoder from caching, thereby realizing a method for smooth synchronous display of the video. In addition, different DMA devices share DMA memory, thereby improving the method for data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1This is a flow chart of the multi-core 8K decoding and display method based on PCIe of the present invention;

[0017] Figure 2 This is a flow chart of the method for the decoding chip of the present invention to send data to FPGA. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the technical solution in the embodiments of the present invention is clearly and completely described below in conjunction with the accompanying drawings.

[0019] Example:

[0020] like Figure 1 As shown, this embodiment involves a multi-core 8K decoding and display method based on PCIe, which is implemented based on FPGA, multiple decoding chips, and CPU. The FPGA and multiple decoding chips are connected to the CPU through a PCIe bus.

[0021] The decoding and displaying method comprises:

[0022] The CPU receives the data TS (Transport Stream) to be decoded and displayed, and parses the data TS, and obtains the resolution and Tile information of the data according to the header information contained in the TS data; according to the Tile information, the 8K decoded data is split into four 4KES data using software such as gstreamer or ffmpeg, and put into the ring buffer cache; the data to be decoded and displayed is a local file or a network data stream, etc.

[0023] The FPGA clock and the CPU clock are from different sources, so the FPGAPCIe msi-x interrupt method is used to make the CPU send decoded data according to the FPGA clock. Specifically, the CPU sends the video frame rate information obtained after parsing to the FPGA through the PCIe bus.

[0024] FPGA controls the number of MSI-X interrupts generated per second according to the video frame rate information. After the CPU obtains the interrupt, it immediately takes a frame of data from the ring buffer and sends it to the four decoding chips for decoding. The use of interrupts can avoid using the cache of the decoding chip, thereby ensuring that the four 4K decoded by the four decoding chips belong to the same frame of 8K picture, thereby ensuring the synchronization of the four pictures. This solves the problem that when using decoder cache, due to the inconsistent decoding speed of the decoders, the accumulated time error will cause the decoded pictures to not belong to the same frame and the spliced ​​pictures to be out of sync.

[0025] Due to the different driver mechanisms, the decoding chip cannot directly send the decoded data to the FPGA. Figure 2As shown in the figure, the decoded raw data will be sent to the CPU through PCIe first, and the CPU will then use QDMA driver to send the raw data to FPGA through PCIe. By modifying the driver's shared DMA memory, the data sent by the decoding chip to the CPU is rearranged into the form required by the FPGA, and the time consumption caused by data copying is reduced, thus improving the transmission efficiency. MDMA uses the DMA controller of the decoding chip, and QDMA uses the DMA controller of the FPGA, so it does not consume CPU time.

[0026] After receiving the decoded data, the FPGA first caches 3 frames, and then displays the first received frame of data according to the clock that triggers the MSI-X interrupt. After receiving the interrupt, the CPU sends a frame of ES data to the decoding chip for decoding to fill the FPGA cache, thereby achieving smooth playback and display on the screen.

[0027] In the case where TS is not sent to the CPU on time due to occasional network fluctuations, the threshold of the ring buffer is used for judgment. If it is below the lower threshold, the I frame is copied during parsing to increase the number of frames and prevent the black screen from being displayed due to no data decoding. Since the I frame is an independently encoded frame, copying the I frame will not cause decoding abnormalities.

[0028] The 8Kyuv42210bit video decoding strategy proposed in the present invention synchronously sends data to four decoders for decoding through PCIe msi-x interrupt control, ensuring that there is only one frame of data to be decoded in the decoder, avoiding decoder cache, thereby achieving the effect of smooth and synchronous video presentation. In addition, the method also utilizes the shared DMA memory between different DMA devices, effectively improving the efficiency of data transmission.

[0029] The above-mentioned specific implementation modes are only specific cases of the present invention. The patent protection scope of the present invention includes but is not limited to the above-mentioned specific implementation modes. Any appropriate changes or modifications made thereto by any ordinary technician in the technical field in accordance with the claims of the present invention shall fall within the patent protection scope of the present invention.

Claims

1. A multi-core 8K decoding and display method based on PCIe, characterized in that: Based on FPGA, multiple decoding chips, and CPU, the FPGA and multiple decoding chips are connected to the CPU via a PCIe bus; the method includes: The CPU receives the data TS to be decoded and displayed, and parses the data TS, and obtains the resolution and Tile information of the data according to the header information contained in the TS data; splits the 8K decoded data into four 4K ES data according to the Tile information, and puts them into the ring buffer cache; The FPGAPCIe msi-x interrupt method is used to make the CPU send decoded data according to the FPGA clock. Specifically, the CPU sends the video frame rate information obtained after parsing to the FPGA through the PCIe bus; FPGA controls the number of MSI-X interrupts generated per second according to the video frame rate information. After the CPU obtains the interrupt, it immediately takes a frame of data from the ring buffer and sends it to four decoding chips for decoding. The decoded raw data will be sent to the CPU via PCIe first, and the CPU will then use QDMA driver to send the raw data to the FPGA via PCIe; After receiving the decoded data, the FPGA first caches 3 frames, and then displays the first received frame of data according to the clock that triggers the MSI-X interrupt. After receiving the interrupt, the CPU sends a frame of ES data to the decoding chip for decoding to fill the FPGA cache, thereby achieving smooth playback and display.

2. The PCIe-based multi-core 8K decoding and display method according to claim 1, characterized in that: In case that the TS is not sent to the CPU on time due to occasional network fluctuations, a judgment is made based on the threshold of the ring buffer. If it is below the lower threshold, the I frame is copied during parsing, thereby increasing the number of frames.

3. The PCIe-based multi-core 8K decoding and display method according to claim 1, characterized in that: Use gstreamer or ffmpeg software to split the 8K decoded data into four 4K ES data according to the Tile information.

4. The PCIe-based multi-core 8K decoding and display method according to claim 1, 2 or 3, characterized in that: The data to be decoded and displayed is a local file or a network data stream.

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