Semiconductor device

Abstract

A semiconductor device includes: a lower chip structure including a memory structure and a lower wiring structure connected to the memory structure; the upper chip structure is located on the lower chip structure and comprises an upper substrate, a lower substrate and a lower substrate; a peripheral transistor under the upper substrate; an intermediate wiring structure under the upper substrate and connected to the peripheral transistor; an upper wiring structure on the upper substrate; a first through-via penetrating the upper substrate between the upper wiring structure and the middle wiring structure, the first through-via connecting the upper wiring structure and the middle wiring structure; and a second through-via penetrating the upper substrate between the upper wiring structure and the lower wiring structure and extending downward, the second through-via connecting the upper wiring structure and the lower wiring structure.

Description

Technical Field

[0001] Example embodiments relate to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Research is being conducted to reduce the size of elements constituting semiconductor devices and to improve their performance. For example, in dynamic random access memory (DRAM), research is being conducted to reliably and stably form elements that have been reduced in size. Summary of the invention

[0003] One or more example embodiments provide a semiconductor device having improved integration.

[0004] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0005] According to aspects of an example embodiment, a semiconductor device may include: a lower chip structure, the lower chip structure including a storage structure and a lower wiring structure connected to the storage structure; and an upper chip structure, the upper chip structure being located on the lower chip structure, wherein the upper chip structure may include: an upper substrate; a peripheral transistor, the peripheral transistor being located below the upper substrate; an intermediate wiring structure, the intermediate wiring structure being located below the upper substrate and connected to the peripheral transistor; an upper wiring structure, the upper wiring structure being located on the upper substrate; a first through-via, the first through-via penetrating the upper substrate between the upper wiring structure and the intermediate wiring structure, the first through-via connecting the upper wiring structure and the intermediate wiring structure; and a second through-via, the second through-via penetrating the upper substrate between the upper wiring structure and the lower wiring structure and extending downward, the second through-via connecting the upper wiring structure and the lower wiring structure.

[0006] According to aspects of an example embodiment, a semiconductor device may include: a lower chip structure, the lower chip structure including a first storage area, a second storage area, and an extension area located between the first storage area and the second storage area; and an upper chip structure, the upper chip structure is located on the lower chip structure, wherein the lower chip structure may also include: a first bit line, the first bit line is located in the first storage area and extends into the extension area; a second bit line, the second bit line is located in the second storage area and extends into the extension area; and a routing lower wiring structure, the routing lower wiring structure is electrically connected to the first bit line and the second bit line, wherein the upper chip structure may include: an upper substrate; a peripheral transistor, the peripheral transistor vertically overlaps the first storage area and is located below the upper substrate; a routing intermediate wiring structure, the routing intermediate wiring structure is located below the upper substrate and connected to the peripheral transistor; a routing upper wiring structure, the routing upper wiring structure is located on the upper substrate; a first through-path, the first through-path penetrates the upper substrate and connects the routing upper wiring structure and the routing intermediate wiring structure; and a second through-path, the second through-path penetrates the upper substrate and connects the routing upper wiring structure and the routing lower wiring structure, wherein the second through-path is located on the extension area and the first through-path is located on the first storage area.

[0007] According to aspects of an example embodiment, a semiconductor device may include: a lower chip structure, the lower chip structure including a storage structure and a lower wiring structure connected to the storage structure; an upper chip structure, the upper chip structure being located on the lower chip structure, wherein the upper chip structure may include: an upper substrate; a peripheral transistor, the peripheral transistor being located below the upper substrate; an intermediate wiring structure, the intermediate wiring structure being located below the upper substrate and connected to the peripheral transistor; an upper wiring structure, the upper wiring structure being located on the upper substrate; and a through-via, the through-via penetrating at least the upper substrate, wherein the intermediate wiring structure may include intermediate pathways at respective different heights and intermediate wirings at respective different heights, wherein the upper wiring structure may include at least one upper pathway and at least one upper wiring, and wherein the number of intermediate wirings is greater than the number of at least one upper wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of certain example embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0009] Figures 1A to 7 is a diagram illustrating a semiconductor device according to one or more example embodiments;

[0010] Fig. 8A and Figure 8B is a diagram illustrating a semiconductor device according to one or more example embodiments;

[0011] Fig. 9Aand Fig. 9B is a diagram illustrating a semiconductor device according to one or more example embodiments;

[0012] Fig. 10A and Fig. 10B is a diagram illustrating a semiconductor device according to one or more example embodiments;

[0013] Fig.11A and Fig. 11B is a diagram illustrating a semiconductor device according to one or more example embodiments;

[0014] Fig.12 and Fig.13 is a diagram illustrating an example of a memory structure of a semiconductor device according to one or more example embodiments;

[0015] Fig.14 is a flowchart illustrating an example of a method of manufacturing a semiconductor device according to one or more example embodiments; and

[0016] FIG. 15A to FIG. 17B is a diagram illustrating an example of a method of manufacturing a semiconductor device according to one or more example embodiments. DETAILED DESCRIPTION

[0017] Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the accompanying drawings, and their redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and can be implemented in various other forms.

[0018] As used herein, expressions such as “at least one of…”, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression “at least one of a, b, and c” should be understood to include only a; only b; only c; both a and b; both a and c; both b and c; or all of a, b, and c.

[0019] Hereinafter, terms such as "upper", "middle" and "lower" may be replaced with other terms such as "first", "second" and "third" and may be used to describe elements of the specification. Terms such as "first", "second" and "third" may be used to describe different elements, but these elements are not limited by these terms, and the "first element" may be referred to as the "second element".

[0020] It should be understood that when an element or layer is referred to as being “on,” “over,” “on,” “under,” “under,” “connected to,” or “coupled to” another element or layer, it can be directly on, over, on, under, under, under, connected to, or coupled to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly over,” “directly on,” “directly under,” “directly under,” “directly under,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0021] Figures 1A to 7 is a diagram illustrating a semiconductor device according to one or more example embodiments.

[0022] Figure 1A is a perspective view illustrating a semiconductor device according to one or more example embodiments, and Figure 1B is a diagram illustrating a method according to one or more example embodiments Figure 1A A top view of a portion of memory body BA.

[0023] refer to Figure 1A and Figure 1B , a semiconductor device 1 according to example embodiments may include a lower chip structure LC and an upper chip structure UC located on the lower chip structure LC. The lower chip structure LC and the upper chip structure UC may be sequentially stacked in a vertical direction (Z direction).

[0024] The semiconductor device 1 may include a plurality of memory banks BA and a first peripheral region PER1. Each of the plurality of memory banks BA may include a lower region BAa in the lower chip structure LC and an upper region BAb in the upper chip structure UC.

[0025] The first peripheral region PER1 may include a first lower region PER1a in the lower chip structure LC and a first upper region PER1b in the upper chip structure UC. The first peripheral region PER1 may be a peripheral circuit region in which a peripheral circuit for inputting data or a command or power / ground is disposed.

[0026] Each memory body BA may include a memory region CR, extension regions EXTb and EXTw disposed adjacent to the memory region CR, and a peripheral circuit region PC located above the memory region CR (e.g., disposed higher than the memory region CR in a vertical direction). The memory region CR and the extension regions EXTb and EXTw may be disposed in a lower region BAa of the memory body BA of the lower chip structure LC, and the peripheral circuit region PC may be disposed in an upper region BAb of the memory body BA of the upper chip structure UC.

[0027] Each storage region CR may include a cell switching device having a gate electrode, a bit line electrically connected to the cell switching device, and a data storage structure electrically connected to the cell switching device. The gate electrode of the cell switching device may be a word line.

[0028] The extension region EXTb and EXTw may include an extension region EXTb disposed adjacent to the storage region CR in a first direction (X direction) and an extension region EXTw disposed adjacent to the storage region CR in a second direction (Y direction). The extension region EXTb disposed adjacent to the storage region CR in the first direction (X direction) may be a bit line extension region in which a bit line in the storage region CR extends, and the extension region EXTw disposed adjacent to the storage region CR in the second direction (Y direction) may be a word line extension region in which a word line in the storage region CR extends.

[0029] In example embodiments, the first direction (X direction) and the second direction (Y direction) may be perpendicular to each other. The first direction (X direction) and the second direction (Y direction) may be perpendicular to the vertical direction (Z direction).

[0030] The storage region CR may include a first storage region CR1 and a second storage region CR2 disposed adjacent to the first storage region CR1 and spaced apart from the first storage region CR1 by an extension region EXTb.

[0031] Each peripheral circuit region PC may include a sense amplifier region SAR, a sub word line driver region SWDR, and a second peripheral region PER2 located between the sense amplifier region SAR and the sub word line driver region SWDR.

[0032] Please refer to the attached Figure 2A , Figure 2B and Figure 2C Electrical connection between the first and second memory regions CR1 and CR2 included in the lower chip structure LC and the sense amplifier region SAR included in the upper chip structure UC is described.

[0033] Figure 2Ais a perspective view illustrating an electrical connection relationship of a semiconductor device according to one or more example embodiments. Figure 2B is a block diagram illustrating electrical connections between first and second memory regions CR1 and CR2 and a sense amplifier region SAR included in an upper chip structure UC in a semiconductor device according to one or more example embodiments. Figure 2C Yes Figure 2A and Figure 2B A view of the circuit of the sense amplifier SA is a view illustrating the electrical connection relationship between a sense amplifier SA1 among the sense amplifier SA, a bit line BL1 among multiple bit lines BL electrically connected to the first sense amplifier SA1, and a first complementary bit line BLB1 among multiple complementary bit lines BLB electrically connected to the first sense amplifier SA1.

[0034] refer to Figure 2A , Figure 2B and Figure 2C as well as Figure 1A and Figure 1B The first memory region CR1 may include a first memory structure including a bit line BL and a word line WL. The bit line BL may extend in a first direction (X direction), and the word line WL1 may extend in a second direction (Y direction) perpendicular to the first direction (X direction).

[0035] The second memory region CR2 may include a second memory structure including a bit line BLB and a word line WL2. The bit line BLB may extend in a first direction (X direction), and the word line WL2 may extend in a second direction (Y direction).

[0036] In the semiconductor device 1, when the first storage area CR1 is a normal storage area and the second storage area CR2 is a reference storage area, the bit line BL of the first storage area CR1 can be a bit line for reading out data in a data storage structure stored in the first storage area CR1, and the bit line BLB of the second storage area CR2 can be a complementary bit line.

[0037] Hereinafter, the bit line BL of the first memory region CR will be referred to as a “bit line”, and the bit line BLB of the second memory region CR2 will be referred to as a “complementary bit line”.

[0038] The sense amplifier region SAR may include a plurality of unit sense amplifier regions SARu. Each unit sense amplifier region SARu may include a first connection region SAC1, a second connection region SAC2, and a sense amplifier SA located between the first connection region SAC1 and the second connection region SAC2.

[0039] The semiconductor device 1 may include a routing structure CS for electrically connecting the bit line BL of the first memory region CR1 and the complementary bit line BLB of the second memory region CR2 to the unit sense amplifier region SARu.

[0040] The routing structure CS may include a first routing structure CS1 for electrically connecting the bit line BL of the first storage region CR1 to the first connection region SAC1 and a second routing structure CS2 for electrically connecting the complementary bit line BLB of the second storage region CR2 to the second connection region SAC2.

[0041] A plurality of bit lines BL of the first storage region CR1 may be provided and spaced apart from each other in the second direction (Y direction). A plurality of complementary bit lines BLB of the second storage region CR2 may be provided and spaced apart from each other in the second direction (Y direction).

[0042] The bit line BL of the first memory region CR1 may extend into the extension region EXTb and may be electrically connected to the first routing structure CS1. The complementary bit line BLB of the second memory region CR2 may extend into the extension region EXTb and may be electrically connected to the second routing structure CS2.

[0043] The first storage region CR1 and the second storage region CR2 may be electrically connected to the sense amplifier region SAR. The bit lines BL of the first storage region CR1 may include n bit lines BL1, BL2, ..., BLn, and the complementary bit lines BLB of the second storage region CR2 may include n complementary bit lines BLB1, BLB2, ..., BLBn. The sense amplifier SA of the sense amplifier region SAR may include n sense amplifiers SA1, SA2, ..., SAn. One sense amplifier SA1 among the sense amplifiers SA1, SA2, ..., SAn may be electrically connected to one bit line BL1 among the bit lines BL1, BL2, ..., BLn and one complementary bit line BLB1 among the complementary bit lines BLB1, BLB2, ..., BLBn.

[0044] The bit line BL and the sense amplifier SA may be electrically connected to each other through a first routing structure CS1 , and the complementary bit line BLB and the sense amplifier SA may be electrically connected through a second routing structure CS2 .

[0045] Each routing structure CS may include routing through-vias RTa and RTb and routing wiring structures RWa and RWb. For example, a first routing structure CS1 may include a first routing through-via RTa and a first routing wiring structure Rwa. A second routing structure CS2 may include a second routing through-via RTb and a second routing wiring structure RWb.

[0046] The first sense amplifier SA1 may include a plurality of transistors P1_a, P1_b, N1_a, and N1_b.

[0047] Transistors P1_a, P1_b, N1_a, and N1_b may include P1_a and P1_b transistors as P-channel transistors and N1_a and N1_b transistors as N-channel transistors. P1_a and P1_b transistors may be referred to as a pair of P-channel transistors, and N1_a and N1_b transistors may be referred to as a pair of N-channel transistors.

[0048] In example embodiments, the P-channel transistor may be a p-type metal oxide semiconductor (MOS) (PMOS) transistor, and the N-channel transistor may be an n-type MOS (NMOS) transistor.

[0049] The source of the P1_a transistor and the source of the P1_b transistor may be connected to the first control line LA through a first node ND1_a. The source of the N1_a transistor and the source of the N1_b transistor may be connected to the second control line LAB through a second node ND1_b.

[0050] The first node ND1_a and the second node ND1_b may be referred to as a first source node and a second source node, respectively.

[0051] The drain of the P1_a transistor and the drain of the N1_a transistor may be connected to the first bit line BL1 through the first drain node ND1_c. The first bit line BL1 may be electrically connected to the first drain node ND1_c through the first routing through via RTa and the first routing wiring structure Rwa.

[0052] The drain of the P1_b transistor and the drain of the N1_b transistor may be connected to the first complementary bit line BLB1 through the second drain node ND1_d. The first complementary bit line BLB1 may be electrically connected to the second drain node ND1_d through the second routing through via RTb and the second routing wiring structure RWb.

[0053] The first routing through-path RTa may include a first sub-routing through-path RTa1 and a second sub-routing through-path RTa2, and the second routing through-path RTb may include a third sub-routing through-path RTb1 and a fourth sub-routing through-path RTb2. The first sub-routing through-path RTa1 may be disposed in the first connection region SAC1, and the third sub-routing through-path RTb1 may be disposed in the second connection region SAC2. The second sub-routing through-path RTa2 and the fourth sub-routing through-path RTb2 may be disposed in the extension region EXTb.

[0054] The sense amplifier SA1 can sense and amplify the voltage change of the bit line BL1. When the sense amplifier SA1 performs the sensing and amplification operation, the internal power supply voltage of the semiconductor device 1 can be applied to the first node ND1_a through the first control line LA, and the second node ND1_b can be connected to the ground terminal through the second control line LAB.

[0055] Figure 2C The sense amplifier SA1 includes a pair of P-channel transistors and a pair of N-channel transistors and is implemented in a circuit configuration with cross coupling between the transistors, but this is an exemplary embodiment and the exemplary embodiment is not limited thereto. For example, it can be implemented in various circuit configurations. Figure 2C circuit of the sense amplifier SA1.

[0056] Next, we will refer to Figure 3A and Figure 3B As well as the above Figures 1A to 2C The electrical connection between the first and second storage regions CR1 and CR2 and the sense amplifier region SAR is described.

[0057] Figure 3A is a top plan view illustrating electrical connection between the first storage region CR1 and the second storage region CR2 according to one or more example embodiments. Figure 3B is a top plan view illustrating electrical connection between the first and second storage regions CR1 and CR2 and the sense amplifier region SAR according to one or more example embodiments.

[0058] refer to Figure 3A and Figure 3B as well as Figures 1A to 2C As described above, the first storage region CR1 may include the bit line BL, and the second storage region CR2 may include the complementary bit line BLB.

[0059] The extension region EXTb between the first storage region CR1 and the second storage region CR2 may include a first side extension region EXTb1 disposed adjacent to the first storage region CR1 and a second side extension region EXTb2 disposed adjacent to the second storage region CR2 .

[0060] The bit lines BL may include a first bit line BL1 and a second bit line BL2 disposed adjacent to each other. The complementary bit lines BLB may include a first complementary bit line BLB1 and a second complementary bit line BLB2 disposed adjacent to each other.

[0061] The bit line BL may extend from the first storage region CR1 to the first side extension region EXTb1 , and the complementary bit line BLB may extend from the second storage region CR2 to the second side extension region EXTb2 .

[0062] The first routing wiring structure RWa may include a first sub-routing lower wiring structure 25 a and a first sub-routing upper wiring structure 180 a 1 that are electrically connected to the second sub-routing through-via RTa2 .

[0063] The second routing wiring structure RWb may include a second sub-routing lower wiring structure 25 b and a second sub-routing upper wiring structure 180 a 2 electrically connected to the fourth sub-routing through-via RTb2 .

[0064] Connect the main description to Figure 3B The illustrated unit sense amplifier SARu includes a first bit line BL1 and a first complementary bit line BLB1.

[0065] The first sub-routing upper wiring structure 180a1 may extend from the first side extension area EXTb1 to the first connection area SAC1. The first sub-routing upper wiring structure 180a1 may be electrically connected to the second sub-routing through-via RTa2 in the first side extension area EXTb1, and may be electrically connected to the first sub-routing through-via RTa1 in the first connection area SAC1. Therefore, the first sub-routing upper wiring structure 180a1 may electrically connect the second sub-routing through-via RTa2 and the first sub-routing through-via RTa1.

[0066] The second sub-routing upper wiring structure 180a2 may extend from the second side extension area EXTb2 to the second connection area SAC2. The second sub-routing upper wiring structure 180a2 may be electrically connected to the fourth sub-routing through-path RTb2 in the second side extension area EXTb2, and may be electrically connected to the third sub-routing through-path RTb1 in the second connection area SAC2. Therefore, the second sub-routing upper wiring structure 180a2 may electrically connect the fourth sub-routing through-path RTb2 and the third sub-routing through-path RTb1.

[0067] The first sub-routing upper wiring structure 180a1 may include a first sub-routing upper wiring structure 180a1a and a first sub-routing upper wiring structure 180a1b. The first sub-routing upper wiring structure 180a1a may not vertically overlap with the sense amplifier SA, and the first sub-routing upper wiring structure 180a1b may vertically overlap with the sense amplifier SA. The second sub-routing upper wiring structure 180a2 may vertically overlap with the sense amplifier SA or at least be positioned within the width of the sense amplifier SA.

[0068] Next, we will refer to FIG. 4A to FIG. 4D Description Reference Figures 1A to 3B A cross-sectional structure of a semiconductor device 1 is described.

[0069] Figure 4A is a cross-sectional view illustrating a portion of a memory bank BA of a semiconductor device according to one or more example embodiments. Figure 4B is a cross-sectional view illustrating a portion of a first peripheral circuit PER1 of a semiconductor device according to one or more example embodiments. Figure 4C According to one or more example embodiments, Figure 4A A partial enlarged view of the area indicated by 'B'. Figure 4D is a diagram illustrating a method of performing a Figure 4A A partial magnified view of the area indicated by 'C'.

[0070] exist Figure 4A In the embodiment, the area indicated by 'CR1' may represent the first storage area of ​​the lower chip structure LC, the area indicated by 'EXTb' may represent the extension area, the area indicated by 'EXTb1' may represent the first extension area, and the area indicated by 'EXTb2' may represent the second extension area.

[0071] refer to FIG. 4A to FIG. 4D as well as Figures 1A to 3B As described above, the semiconductor device 1 may include a lower chip structure LC and an upper chip structure UC which are sequentially stacked.

[0072] As described above, the lower chip structure LC may have the first peripheral circuit region PER1 , the first storage region CR1 , the second storage region CR2 , and the extension region EXTb between the first storage region CR1 and the second storage region CR2 .

[0073] The lower chip structure LC may include a lower substrate 5, a storage structure MS and a power capacitor CAPp located on the lower substrate 5, a routing lower wiring structure (also referred to as a lower wiring structure) 25 located on the lower substrate 5 and electrically connected to the storage structure MS and the power capacitor CAPp, a lower insulating structure 20 located on the lower substrate 5 for covering or at least partially covering the storage structure MS and the routing lower wiring structure 25, and a lower bonding insulating layer 50 located on the lower insulating structure 20.

[0074] Each memory structure MS may include a word line ML, bit lines BLa and BLb, and a data storage structure DS. Each data storage structure DS may include a first electrode SN, a second electrode PL covering or at least partially covering the first electrode SN, and a dielectric layer DI between the first electrode SN and the second electrode PL.

[0075] The lower substrate 5 may include a lower semiconductor substrate and a device isolation region cSTI located on the lower semiconductor substrate. The word line WL may be embedded in the lower substrate 5.

[0076] The data storage structure DS may be a memory cell capacitor capable of storing data in a memory such as a dynamic random access memory (DRAM).

[0077] The first peripheral circuit region PER1 may include a power supply capacitor CAPp. The power supply capacitor CAPp may include a lower electrode ELa, an upper electrode ELb, and a dielectric layer DIb located between the lower electrode ELa and the upper electrode ELb. The lower electrode ELa may include a first lower electrode ELa1, a second lower electrode ELa2 located on the first lower electrode ELa1, and a third lower electrode ELa3 located on the second lower electrode ELa2. The third lower electrode ELa3 may be disposed at a height substantially the same as that of the first electrode SN.

[0078] The first storage region CR1 may include a first storage structure of the storage structure MS, and the second storage region CR2 may include a second storage structure of the storage structure MS.

[0079] The first memory structure of the first memory region CR1 may include a bit line indicated by BLa among the bit lines BLa and BLb, and the bit line BLa may be the bit line BL electrically connected to the above-mentioned sense amplifier SA.

[0080] The second storage structure of the second storage region CR2 may include a bit line indicated by BLb among the bit lines BLa and BLb, and the bit line BLb may be a complementary bit line BLB electrically connected to the above-mentioned sense amplifier SA.

[0081] Hereinafter, the BLa bit line will be referred to and described as a bit line BL electrically connected to the sense amplifier SA, and the BLb bit line will be referred to and described as a complementary bit line BLB electrically connected to the above sense amplifier SA.

[0082] The routing lower wiring structure 25 may include a first sub-routing lower wiring structure 25a electrically connected to the bit line BL, a second sub-routing lower wiring structure 25b electrically connected to the complementary bit line BLB, a third sub-routing lower wiring structure 25c electrically connected to the second electrode PL, and a fourth sub-routing lower wiring structure 25d electrically connected to the upper electrode ELb.

[0083] Each of the routing lower wiring structures 25 may include a vertical portion and a horizontal portion. For example, the first sub-routing lower wiring structure 25a may include a vertical portion 30a contacting and electrically connected to the bit line BL and a horizontal portion 35a connected to the vertical portion 30a on the vertical portion 30a, the second sub-routing lower wiring structure 25b may include a vertical portion 30b contacting and electrically connected to the complementary bit line BLB and a horizontal portion 35b connected to the vertical portion 30b on the vertical portion 30b, the third sub-routing lower wiring structure 25c may include a vertical portion 30c contacting and electrically connected to the second electrode PL and a horizontal portion 35c connected to the vertical portion 30c on the vertical portion 30c, and the fourth sub-routing lower wiring structure 25d may include a vertical portion 30d contacting and electrically connected to the upper electrode ELb and a horizontal portion 35d connected to the vertical portion 30d on the vertical portion 30d.

[0084] In each routing under wiring structure 25 , the vertical portions 30 a , 30 b , 30 c , and 30 d may be contact plugs, and the horizontal portions 35 a , 35 b , 35 c , and 35 d may be pads or interconnection lines including pads.

[0085] Upper surfaces of the horizontal portions 35 a , 35 b , 35 c , and 35 d may contact a lower surface of the lower bonding insulation layer 50 .

[0086] The upper chip structure UC may include an upper bonding insulating layer 150, an upper substrate 105, a peripheral transistor PTR, a routing intermediate wiring structure 125, an intermediate insulating structure 120, a routing upper wiring structure (also referred to herein as an input / output connection structure) 180a, an upper insulating structure 190, a covering insulating layer 193, an input / output connection structure 180b, an input / output pad 196, a first through-via 160, a second through-via 170, and a first insulating spacer 158 and a second insulating spacer 168.

[0087] The upper bonding insulating layer 150 may contact and bond to the lower bonding insulating layer 50. The lower bonding insulating layer 50 and the upper bonding insulating layer 150 may include the same material. Each of the lower bonding insulating layer 50 and the upper bonding insulating layer 150 may include at least one of silicon oxide, SiCN, and SiCON.

[0088] The upper substrate 105 may be disposed on the upper bonding insulating layer 150. The upper substrate 105 may include an upper semiconductor substrate 110, an upper active region pACT under the upper semiconductor substrate 110, and an upper device isolation region pSTI under the upper semiconductor substrate 110 defining the upper active region pACT.

[0089] Each peripheral transistor PTR may include an upper gate PGox and PGE located below the upper substrate 105, and an upper source / drain PSD located in an upper active region pACT on both sides of the upper gate PGox and PGE. The upper gate PGox and PGE may include an upper gate electrode PGE and an upper gate dielectric layer PGox located between the upper gate electrode PGE and the upper active region pACT.

[0090] The peripheral transistor PTR may include transistors PTR1 and PTR2 located above the storage structure MS of the first storage region CR1 and the second storage region CR2 (e.g., disposed higher in the vertical direction than the storage structure MS of the first storage region CR1 and the second storage region CR2), and a transistor PTR3 located above the first peripheral circuit region PER1 (e.g., disposed higher in the vertical direction than the first peripheral circuit region PER1). For example, the peripheral transistor PTR may include a first transistor PTR1 and a second transistor PTR2, and the first transistor PTR1 and the second transistor PTR2 may form a plurality of transistors P1_a, P1_b, N1_a, and N1_b (see FIG. 1 ) of the sense amplifier SA simultaneously with the plurality of transistors P1_a, P1_b, N1_a, and N1_b located above the storage structure MS of the first storage region CR1 (e.g., disposed higher in the vertical direction than the storage structure MS of the first storage region CR1). Figure 2C ). The transistors PTR1 and PTR2 may vertically overlap the memory structure MS of the first memory region CR1 and the second memory region CR2. The transistor PTR3 may vertically overlap the first peripheral circuit region PER1. The first transistor PTR1 and the second transistor PTR2 may vertically overlap the memory structure MS of the first memory region CR1.

[0091] The routing intermediate wiring structure 125 can electrically connect the peripheral transistors PTR to form a peripheral circuit. The routing intermediate wiring structure 125 can include vertical portions 130V, 133V, 136V, 139V, 142V, and 145V disposed at different heights and horizontal portions 130L, 133L, 136L, 139L, 142L, and 145L disposed at different heights.

[0092] In the routing intermediate wiring structure 125 , the horizontal portions 130L, 133L, 136L, 139L, 142L, and 145L may be two or more layers disposed at different heights.

[0093] In example embodiments, the "vertical portion" may be a plug or a via extending vertically, and the "horizontal portion" may be a pad extending horizontally or a wiring including a pad. Therefore, the "vertical portion" may be referred to as a plug or a via, and the "horizontal portion" may be referred to as an interconnect.

[0094] In example embodiments, terms such as “lower surface”, “upper surface”, “uppermost”, and “lowermost” may be described based on the drawings. For example, the uppermost horizontal portion of the horizontal portions 130L, 133L, 136L, 139L, 142L, and 145L may be formed based on the drawings. Figure 4A The horizontal portion indicated by 130L is closest to the upper substrate 105 .

[0095] The intermediate insulating structure 120 may be disposed between the upper substrate 105 and the upper bonding insulating layer 150. The peripheral gates PGox and PGE and the routing intermediate wiring structure 125 may be embedded in the intermediate insulating structure 120.

[0096] A lower surface of a lowermost horizontal portion 145L among the horizontal portions 130L, 133L, 136L, 139L, 142L, and 145L of the routing intermediate wiring structure 125 may contact an upper surface of the upper bonding insulating layer 150 .

[0097] The routing-on wiring structure 180a may include at least one vertical portion 182V or 184V and at least one horizontal portion 182L or 184L. In the routing-on wiring structure 180a, the vertical portions 182V and 184V may be disposed below the horizontal portions 182L and 184L.

[0098] The number of horizontal portions 130L, 133L, 136L, 139L, 142L, and 145L disposed at different heights among the routing middle wiring structure 125 may be greater than the number of at least one horizontal portion 182L or 184L disposed at different heights among the routing upper wiring structure 180a.

[0099] For example, in the routing wiring structure 180a, the horizontal portions 182L and 184L may be a connection line layer.

[0100] In another example, in the routing-on-wire structure 180 a , the horizontal portions 182L and 184L may be two or more wiring layers disposed at different heights.

[0101] The input / output connection structure 180 b may include vertical portions 182V, 184V, and 186 and horizontal portions 182L and 184L.

[0102] The upper insulating structure 190 may cover or at least partially cover the routing upper wiring structure 180 a and the input / output connection structure 180 b on the upper substrate 105 .

[0103] A capping insulating layer 193 may be disposed on the upper insulating structure 190 , and may serve to protect the semiconductor device 1 .

[0104] The input / output pad 196 may be electrically connected to the input / output connection structure 180 b on the input / output connection structure 180 b .

[0105] The first through via 160 may penetrate the upper substrate 105. The first through via 160 may electrically connect the routing upper wiring structure 180a and the routing middle wiring structure 125.

[0106] The first through via 160 may contact and be simultaneously electrically connected to the uppermost horizontal portion 130L among the horizontal portions 130L, 133L, 136L, 139L, 142L, and 145L of the routing intermediate wiring structure 125 .

[0107] Each of the first through vias 160 may include a conductive pillar 164 and a barrier layer 162 covering or at least partially covering side surfaces and a lower surface of the conductive pillar 164 .

[0108] The first through via 160 may include a through via 160a and an input / output through via 160b, the through via 160a being located above the first storage region CR1 (e.g., disposed higher than the first storage region CR1 in the vertical direction) and being electrically connected to the sense amplifier SA (see FIG. 1 ) through the routing intermediate wiring structure 125. FIG. 2A to FIG. 2C ), the input / output through via 160b is electrically connected to the input / output connection structure 180b located on the first peripheral circuit region PER1. The through via 160a may vertically overlap the first storage region CR1.

[0109] Each of the second through vias 170 may include a conductive pillar 174 and a barrier layer 172 covering or at least partially covering side surfaces and a lower surface of the conductive pillar 174 .

[0110] The second through-path 170 may be located above the extension region EXTb (e.g., arranged to be higher than the extension region EXTb in the vertical direction). The second through-path 170 may overlap vertically with the extension region EXTb. The second through-path 170 may penetrate the upper substrate 105 to extend downward, and penetrate the intermediate insulating structure 120, the upper bonding insulating layer 150, and the lower bonding insulating layer 50. The second through-path 170 may electrically connect the routing upper wiring structure 180a and the routing lower wiring structure 25. The second through-path 170 may include a second sub-routing through-path RTa2 and a fourth sub-routing through-path RTb2, the second sub-routing through-path RTa2 being electrically connected to the bit line BL through the first sub-routing lower wiring structure 25a, and the fourth sub-routing through-path RTb2 being electrically connected to the complementary bit line BLB through the second sub-routing lower wiring structure 25b.

[0111] The first through via 160 may have an inclined side surface such that its width decreases in a direction oriented from top to bottom. The second through via 170 may have an inclined side surface such that its width decreases in a direction oriented from top to bottom.

[0112] The first insulating spacer 158 may cover or at least partially cover a side surface of the first through via 160. The second insulating spacer 168 may cover or at least partially cover a side surface of the second through via 170.

[0113] The maximum width of each second through via 170 may be greater than the maximum width of each first through via 160. The height between the upper and lower surfaces of each second through via 170 may be greater than the height between the upper and lower surfaces of each first through via 160.

[0114] In the following, reference will be made to Figure 5A , Figure 5B , Figure 6 and Figure 7 Illustrative examples of routing structures are described.

[0115] Figure 5A is a diagram illustrating a method for electrically connecting a bit line BL and a sense amplifier SA (see FIG. Figure 2A , Figure 2B , Figure 2C and Figure 3B ) is a partially enlarged cross-sectional view of the routing structure. Figure 5B is a diagram illustrating a method for electrically connecting a complementary bit line BLB and a sense amplifier SA (see FIG. Figure 2A , Figure 2B , Figure 2C and Figure 3B ) is a partially enlarged cross-sectional view of the routing structure. Figure 6 is a partially enlarged cross-sectional view illustrating a routing structure connected to a first word line WL1 among word lines WL of a memory structure MS according to one or more example embodiments. Figure 7 is a partially enlarged cross-sectional view illustrating a routing structure of a second electrode PL electrically connected to the memory structure MS according to one or more example embodiments.

[0116] refer to Figure 5A as well as Figures 1A to 4D, the bit line BL of the storage structure MS in the first storage region CR1 can be electrically connected through the routing middle wiring structure 125 to the first sub-routing lower wiring structure 25a among the lower wiring structure 25, the second sub-routing through-path RTa2 among the second through-path 170, the first sub-routing upper wiring structure 180a1 among the routing upper wiring structure 180a, the first sub-routing through-path RTa1 among the first through-path 160, and the sense amplifier SA (see Figure 2A , Figure 2B , Figure 2C and Figure 3B ) of the first transistor PTR1 (see Figure 4A ).

[0117] The first sub-routing upper wiring structure 180 a 1 may electrically connect the first sub-routing through-via RTa 1 and the second sub-routing through-via RTa 2 .

[0118] The first sub-routing upper wiring structure 180a1 may include a vertical portion 182Va1 connected to the second sub-routing through-via RTa2, a vertical portion 182Va2 connected to the first sub-routing through-via RTa1, and a horizontal portion 182La2 for electrically connecting the vertical portions 182Va1 and 182Va2.

[0119] The horizontal portion 182La of the first sub-routing upper wiring structure 180a1 may be a single wiring layer disposed at any height level, but example embodiments are not limited thereto. For example, the horizontal portion 182La of the first sub-routing upper wiring structure 180a1 may include two or more wiring layers disposed at different heights.

[0120] refer to Figure 5B as well as Figures 1A to 5A , the complementary bit line BLB of the storage structure MS in the second storage region CR2 can be electrically connected to the second sub-routing lower wiring structure 25b among the lower wiring structure 25, the fourth sub-routing through-path RTb2 among the second through-path 170, the second sub-routing upper wiring structure 180a2 among the routing upper wiring structure 180a, the third sub-routing through-path RTb1 among the first through-path 160, and the sense amplifier SA (see Figure 2A , Figure 2B , Figure 2C and Figure 3B ) of the second transistor PTR2 (see Figure 4A ).

[0121] The second sub-routing upper wiring structure 180 a 2 may electrically connect the third sub-routing through-via RTb1 and the fourth sub-routing through-via RTb2 .

[0122] The second sub-routing upper wiring structure 180 a 2 may include vertical portions 182Vb1 , 184Vb1 , and 182Vb2 and horizontal portions 182Lb1 , 182Lb2 , and 184L.

[0123] The horizontal portions 182Lb1, 182Lb2, and 184L of the wiring structure 180a2 on the second sub-route may be two or more wiring layers disposed at different heights, but example embodiments are not limited thereto. For example, the horizontal portions 182Lb1, 182Lb2, and 184L of the wiring structure 180a2 on the second sub-route may include a single wiring layer disposed at any height level.

[0124] refer to Figure 6 as well as Figures 1A to 5B , one word line WL1 among the word lines WL can be electrically connected to the fifth sub-routing lower wiring structure 25e of the lower wiring structure 25, the sixth sub-routing through-path RTc2 among the second through-path 170, the third sub-routing upper wiring structure 180a3 among the routing upper wiring structure 180a, the fifth sub-routing through-path RTc1 among the first through-path 160, and the peripheral circuit including any one of the transistors PTR through the routing intermediate wiring structure 125.

[0125] The third sub-routing upper wiring structure 180a3 may electrically connect the fifth sub-routing through-via RTc1 and the sixth sub-routing through-via RTc2.

[0126] The third sub-routing upper wiring structure 180 a 3 may include vertical portions 182Vc1 and 182Vc2 and a horizontal portion 182Lc.

[0127] The horizontal portion 182Lc of the wiring structure 180a3 on the third sub-routing may be a single wiring layer disposed at any height level, but example embodiments are not limited thereto. For example, the horizontal portion 182Lc of the wiring structure 181a3 on the third sub-routing may include two or more wiring layers disposed at different heights.

[0128] refer to Figure 7 as well as Figures 1A to 6 The second electrode 35 of the data storage structure DS can be connected to the third sub-routing lower wiring structure 25c among the lower wiring structure 25, the eighth sub-routing through-path RTd2 among the second through-path 170, the fourth sub-routing upper wiring structure 180a4 among the routing upper wiring structure 180a, the seventh sub-routing through-path RTd1 among the first through-path 160, and a peripheral circuit including any one of the transistors PTR through the routing intermediate wiring structure 125.

[0129] The fourth sub-routing upper wiring structure 180 a 4 may electrically connect the seventh sub-routing through-via RTd1 and the eighth sub-routing through-via RTd2 .

[0130] The fourth sub-routing upper wiring structure 180 a 4 may include vertical portions 182Ve1 and 182Ve2 and a horizontal portion 182Le.

[0131] The horizontal portion 182Le of the fourth sub-routing upper wiring structure 180a4 may be a single wiring layer disposed at any height level, but example embodiments are not limited thereto. For example, the horizontal portion 182Le of the fourth sub-routing upper wiring structure 181a4 may include two or more wiring layers disposed at different heights.

[0132] Next, various modified examples of the elements of the above-described example embodiments will be described. Various modified examples of the elements of the above-described example embodiments will be described based on modified elements or replaced elements. The above-described elements may be directly referenced without further explanation, or their description may be omitted. In addition, the following modified or replaceable elements are described with reference to the following drawings, but the modified or replaceable elements may be combined with each other or with the aforementioned elements to form a semiconductor device according to an example embodiment of the present disclosure.

[0133] Fig. 8A and Figure 8B is a diagram illustrating a semiconductor device according to one or more example embodiments. Fig. 8A is a diagram illustrating a method of performing a Figure 4A A cross-sectional view of an element whose cross-sectional structure has been modified. Figure 8B According to one or more example embodiments, Fig. 8A The 'D' indicated area is a partial magnified view.

[0134] refer to Fig. 8A and Figure 8B The first through via 160 may penetrate the upper substrate 105 and may be replaced by a first through via 260 having a lower surface disposed at the same height as a portion of the upper gate electrode PGE. The routing intermediate wiring structure 125 may be replaced by a routing intermediate wiring structure 125a, which further includes an uppermost horizontal portion 128 disposed at the same height as the upper gate electrode PGE and a vertical portion 129 between the uppermost horizontal portion 128 and a next uppermost horizontal portion 130L below the uppermost horizontal portion 128.

[0135] The uppermost horizontal portion 128 may include at least two conductive layers 128 a and 128 b . The first through via 260 may penetrate at least one of the at least two conductive layers 128 a and 128 b and may be electrically connected to the uppermost horizontal portion 128 .

[0136] The semiconductor device 1 may further include a buffer dielectric layer 127 between the uppermost horizontal portion 128 and the upper substrate 105 .

[0137] The first through via 260 may include a conductive pillar 264 and a barrier layer 262 covering or at least partially covering side surfaces and a lower surface of the conductive pillar 264 .

[0138] The first through via 260 may have a lower surface contacting the uppermost horizontal portion 128. The lower surface of the first through via 260 may be disposed at a lower height than that of the upper substrate 105 and may be disposed at a higher height than that of the uppermost horizontal portion 128.

[0139] Fig. 9A and Fig. 9B is a diagram illustrating a semiconductor device according to one or more example embodiments. Fig. 9A is a diagram illustrating a method of performing a Figure 4A A cross-sectional view of an element whose cross-sectional structure has been modified. Fig. 9B According to one or more example embodiments, Fig. 9A The 'E' indicated area is a partial magnified view.

[0140] refer to Fig. 9A and Fig. 9B , the routing intermediate wiring structure 125 may be replaced with a routing intermediate wiring structure 125b, which further includes an uppermost vertical portion 328 located on the uppermost horizontal portion 130L.

[0141] The first through via 160 may penetrate the upper substrate 105 to extend downward, and may be replaced by a first through via 360 contacting the uppermost vertical portion 328. The first through via 360 may include a conductive pillar 364 and a barrier layer 362 covering or at least partially covering the side and lower surfaces of the conductive pillar 364.

[0142] The uppermost vertical portion 328 may be referred to as a “contact plug” or a “conductive via”.

[0143] The uppermost vertical portion 328 may extend into the first through via 36. Therefore, a lower end of the first through via 36 may be disposed at a higher height than an upper end of the uppermost vertical portion 328.

[0144] Fig. 10A and Fig. 10B is a diagram illustrating a semiconductor device according to one or more example embodiments. Fig. 10A is a diagram illustrating a method of performing a Figure 4A A cross-sectional view of an element whose cross-sectional structure has been modified. Fig. 10B According to one or more example embodiments, Fig. 10A The 'F' indicated area is a partial magnified view.

[0145] refer to Fig. 10A and Fig. 10B , the above-mentioned first through passage 160 can be replaced by a first through passage 460 including an upper through passage 460U and a lower through passage 460L.

[0146] The upper through via 460U may extend downward from the upper surface of the upper substrate 105 and have a lower surface inside the upper substrate 105. The lower through via 460L may extend upward from the lower portion of the upper substrate 105 to contact the upper through via 460U inside the upper substrate 105. The lower through via 460L may be electrically connected to the routing middle wiring structure 125.

[0147] A contact region in which the upper through via 460U and the lower through via 460L contact each other may be disposed at a height level between an upper surface of the upper substrate 105 and a lower surface of the upper substrate 105 .

[0148] The upper through via 460U includes a conductive pillar 462Ub and a barrier layer 464Ua covering or at least partially covering the side and lower surfaces of the conductive pillar 462Ub. The lower through via 460L may include a conductive pillar 462Lb and a barrier layer 464La covering or at least partially covering the side and upper surfaces of the conductive pillar 462Lb.

[0149] The first insulating spacer 158 may be replaced with a first insulating spacer 258 including an upper insulating spacer 258U covering or at least partially covering a side surface of the upper through via 460U and a lower insulating spacer 258L covering or at least partially covering a side surface of the lower through via 460L. The first through via 460 may be spaced apart from the upper substrate 105 by the first insulating spacer 258.

[0150] Fig.11A and Fig. 11B is a diagram illustrating a semiconductor device according to one or more example embodiments. Fig.11A is a diagram illustrating a method of performing a Figure 4A A cross-sectional view of an element whose cross-sectional structure has been modified. Fig. 11BAccording to one or more example embodiments, Fig.11A A partial magnified view of the area indicated by 'G'.

[0151] refer to Fig.11A and Fig. 11B , the first through passage 160 described above may be replaced by a first through passage 560 having an inclined side surface so that its width increases in a direction oriented from top to bottom. As described above, the second through passage 170 may have an inclined side surface so that its width decreases in a direction oriented from top to bottom. Therefore, one of the first through passage 560 and the second through passage 170 may have a positive inclination, while the other may have a negative inclination. The side surface of the first through passage 560 may have a different inclination from the side surface of the second through passage 170.

[0152] The first through via 560 may include a conductive pillar 464 and a barrier layer 562 covering or at least partially covering the side and upper surfaces of the conductive pillar 464. The first insulating spacer 158 may be replaced with a first insulating spacer 558 covering or at least partially covering the side surfaces of the first through via 560.

[0153] Fig.12 and Fig.13 is a diagram illustrating an example of a memory structure of a semiconductor device according to one or more example embodiments. Fig.12 and Fig.13 , the storage structure MS (see Figure 4A ) is an example of a lower chip structure LC. Fig.12 is a diagram illustrating the above-mentioned storage structure MS according to one or more example embodiments (see Figure 4A ) is a top view of an example. Fig.13 is a schematic diagram illustrating a method of performing a Fig.12 A cross-sectional view of the area cut by lines II' and II-II'.

[0154] refer to Fig.12 and Fig.13 , the lower base 5 of the lower chip structure LC may include a substrate 603, a cell active region 609a located on the substrate 603, and a cell device isolation region 606 disposed on the substrate 603 and disposed on the side surface of the cell active region 609a. The cell active region 609a may protrude from the substrate 603 in a vertical direction. The cell device isolation region 606 may be formed by shallow trench isolation. The cell device isolation region 606 may be formed of an insulating material such as silicon oxide and / or silicon nitride. Figure 4A The cell device isolation region cSTI may be formed simultaneously with the cell device isolation region 606 .

[0155] The lower chip structure LC may include a cell gate structure GSa embedded in the cell active region 609a and extending into the cell device isolation region 606, and a cell gate capping layer 612 on the cell gate structure GSa. The cell gate capping layer 612 may be formed of an insulating material.

[0156] The cell gate structure GSa and the cell gate capping layer 612 may be disposed in a cell gate trench crossing the cell active region 609 a and extending into the cell device isolation region 606 .

[0157] Each gate structure GSa may include a cell gate capping layer 617 and a cell gate electrode WL on the cell gate capping layer 617. The cell gate electrode WL may be a word line.

[0158] The lower chip structure LC may further include a first source / drain region 615a and a second source / drain region 615b disposed in the unit active region 609a. The unit gate structure GS and the first source / drain region 615a and the second source / drain region 615b may constitute a unit transistor TRc. The unit transistor TRc may be a unit switching device.

[0159] The lower chip structure LC includes: a buffer insulating layer 620, which is located on the cell active area 609a and the cell device isolation area 606; a bit line BL, which is arranged on the buffer insulating layer 620 and includes a plug portion BLP penetrating the buffer insulating layer 620; a bit line covering layer 650, which is located on the bit line BL; a cell contact structure 660a, which is arranged on both sides of the bit line BL and includes a pad portion extending onto the bit line covering layer 650; an insulating isolation structure 665, which is arranged between the pad portions of the cell contact structure 660a and extends downward; and an insulating spacer 655, which is located on the side surfaces of the bit line covering layer 650 and the bit line BL.

[0160] The plug portion BLP of the bit line BL may be electrically connected to the first source / drain region 615a. The cell contact structure 660a may be electrically connected to the second source / drain region 615b.

[0161] Figure 4A The data storage structure DS described in the foregoing may be disposed on the cell contact structure 660a and the insulating isolation structure 665. In the data storage structure DS, the first electrode SN may be electrically connected to the cell contact structure 660a, the dielectric layer DI may cover or at least partially cover the first electrode SN, and the second electrode PL may be disposed on the dielectric layer DI.

[0162] like Figure 4AAs described in the figure, the lower insulating structure 20 can cover or at least partially cover the data storage structure DS, the vertical portion 30c of the third sub-routing lower wiring structure 25c can contact the second electrode PL, and the upper surface of the horizontal portion 35c of the third sub-routing lower wiring structure 25c can contact the lower bonding insulating layer 50.

[0163] Next, refer to Figures 14 to 17B , an example of a method of forming a semiconductor device according to an example embodiment of the present disclosure will be described. Figures 14 to 17B middle, Fig.14 is a flowchart illustrating an example of a method of manufacturing a semiconductor device according to one or more example embodiments. Fig.15A and Fig. 15B is a cross-sectional view illustrating an example of a method of forming a lower chip structure according to one or more example embodiments. Fig.16A and Fig. 16B is a cross-sectional view illustrating an example of a method of forming a preliminary upper chip structure according to one or more example embodiments. Fig.17A and Fig. 17B is a cross-sectional view illustrating bonding of a lower chip structure and a preliminary upper chip structure according to one or more example embodiments. Fig.15A , Fig.16A and Fig.17A is with Figure 4A The cross-sectional structure corresponds to the cross-sectional view, and Fig. 15B , Fig. 16B and Fig. 17B is with Figure 4B The cross-sectional view corresponding to the cross-sectional structure.

[0164] refer to Fig.14 , Fig.15A and Fig. 15B In operation S10, a lower semiconductor chip structure including a lower bonding insulating layer 50 may be formed. The lower semiconductor chip structure may be as follows. Figure 4A and Figure 4B The lower semiconductor chip structure LC shown in the figure (see Figure 4A and Figure 4B ). Therefore, if Figure 4A As illustrated, the lower semiconductor chip structure may include a lower substrate 5 , a memory structure MS, a power capacitor CAPp, a lower insulating structure 20 , a routing lower wiring structure 25 , and a lower bonding insulating layer 50 .

[0165] refer to Fig.14 , Fig.16A and Fig. 16B , in operation S20 , a preliminary upper semiconductor chip structure including an upper bonding insulation layer 150 may be formed.

[0166] Forming a preliminary upper semiconductor chip structure may include: forming a preliminary upper substrate 105a; forming a peripheral transistor PTR on the preliminary upper substrate 105a; forming a routing intermediate wiring structure 125 and an intermediate insulating structure 120 covering or at least partially covering the routing intermediate wiring structure 125 on the preliminary upper substrate 105a; and forming an upper bonding insulating layer 150 on the routing intermediate wiring structure 125 and the intermediate insulating structure 120.

[0167] The formation of the preliminary upper base 105a may include forming a peripheral device isolation region pSTI for defining a peripheral active region pACT on the upper semiconductor substrate 110. Figure 4A and Figure 4B As described in , the routing intermediate wiring structure 125 may include vertical portions 130V, 133V, 136V, 139V, 142V, and 145V and horizontal portions 130L, 133L, 136L, 139L, 142L, and 145L.

[0168] refer to Fig.14 , Fig.16A and Fig. 16B In operation S30, the lower bonding insulating layer 50 and the upper bonding insulating layer 150 may be bonded to each other. Fig.15A and Fig. 15B The lower bonding insulating layer 50 of the lower chip structure LC in the Fig.16A and Fig. 16B The upper bonding insulation layer 150 of the preliminary upper chip structure is bonded to thereby bond the lower chip structure LC and the preliminary upper chip structure.

[0169] In operation S40, a rear protective layer 155 may be formed on the back side of the preliminary upper semiconductor chip structure. Thus, a preliminary upper chip structure UCa formed up to the rear protective layer 155 may be formed on the lower chip structure LC.

[0170] The rear protective layer 155 may include at least one insulating material layer. Fig.16A and Fig. 16B ) may include a rear protective layer 155 and may be formed by the upper substrate 105 .

[0171] In operation S50 , the through vias 160 and 170 may be formed. The through vias 160 and 170 may include a first through via 160 and a second through via 170 .

[0172] The first through via 160 may penetrate the upper substrate 105 to extend downward and may be connected to the routing middle wiring structure 125 .

[0173] The second through via 170 may penetrate the upper substrate 105 to extend downward and penetrate the intermediate insulating structure 120 , the upper bonding insulating layer 150 , and the lower bonding insulating layer 50 , and may be connected to the routing lower wiring structure 25 .

[0174] In one example, the first through via 160 and the second through via 170 may be formed simultaneously.

[0175] In another example, after forming the first through via 160 , the second through via 170 may be formed.

[0176] In another example, after forming the second through via 170 , the first through via 160 may be formed.

[0177] Reference again FIG. 4A to FIG. 4D In operation S60, routing wiring structures 180a and 180b may be formed. The routing wiring structures 180a and 180b may be formed on the preliminary upper chip structure UCa (see Fig.17A and Fig. 17B The routing upper wiring structures 180a and 180b may be embedded in the preliminary upper chip structure UCa (see Fig.17A and Fig. 17B ) in the upper insulating structure 190 thereon.

[0178] In operation S70, the input / output pad 196 may be formed. The capping insulating layer 193 may be formed on the upper insulating structure 190. The capping insulating layer 193 may have an opening exposing an upper surface of the input / output pad 196.

[0179] According to example embodiments, a semiconductor device may be provided that may include a lower semiconductor chip having a memory structure and an upper semiconductor chip having a peripheral circuit, thereby improving the integration degree of the semiconductor device.

[0180] Furthermore, an optimal routing structure for electrically connecting a lower semiconductor chip and an upper semiconductor chip may be provided to provide improved electrical characteristics to the semiconductor device.

[0181] Various and beneficial advantages and effects of the example embodiments are not limited to the above description and will be more easily understood in the course of describing specific example embodiments.

[0182] It is not excluded that each embodiment provided in the above description is associated with one or more features of another example or another embodiment additionally provided herein or not provided herein, but is consistent with the present disclosure.

[0183] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device include: A lower chip structure, the lower chip structure comprising a storage structure and a lower wiring structure connected to the storage structure; as well as an upper chip structure, the upper chip structure being located on the lower chip structure, Wherein, the upper chip structure comprises: upper base; A peripheral transistor, the peripheral transistor being located below the upper substrate; an intermediate wiring structure, the intermediate wiring structure being located below the upper substrate and connected to the peripheral transistor; an upper wiring structure, the upper wiring structure being located on the upper substrate; a first through via, the first through via penetrating the upper substrate between the upper wiring structure and the middle wiring structure, the first through via connecting the upper wiring structure and the middle wiring structure; and A second through via penetrates the upper substrate between the upper wiring structure and the lower wiring structure and extends downward, and the second through via connects the upper wiring structure and the lower wiring structure.

2. The semiconductor device according to claim 1, in, The lower chip structure further includes a lower bonding insulating layer, the lower bonding insulating layer being located on the storage structure and the lower wiring structure, and Wherein, the upper chip structure further includes an upper bonding insulation layer, which is bonded to the lower bonding insulation layer and is located below the upper substrate, the peripheral transistor and the intermediate wiring structure.

3. The semiconductor device according to claim 2, in, The second through via includes a portion penetrating the upper substrate, wherein the second through-via extends downwardly continuously from the portion penetrating the upper substrate, and The second through via penetrates the upper bonding insulating layer and the lower bonding insulating layer.

4. The semiconductor device according to claim 1, in, The peripheral transistor vertically overlaps the memory structure.

5. The semiconductor device according to claim 1, in, An upper surface of the first through via is at substantially the same height as an upper surface of the second through via, and The lower surface of the first through via is located at a height higher than that of the lower surface of the second through via.

6. The semiconductor device according to claim 1, in, A maximum width of the second through via is greater than a maximum width of the first through via.

7. The semiconductor device according to claim 1, in, The first through via includes a first conductive column and a first barrier layer, Wherein, the second through via comprises a second conductive column and a second barrier layer, and The second barrier layer at least partially covers the side surface of the second conductive column and the lower surface of the second conductive column.

8. The semiconductor device according to claim 7, in, The first barrier layer at least partially covers the side surface of the first conductive pillar and the lower surface of the first conductive pillar, and Wherein, the first barrier layer contacts the lower wiring structure.

9. The semiconductor device according to claim 7, in, The first barrier layer at least partially covers the side surface of the first conductive pillar and the upper surface of the first conductive pillar, and Wherein, the first barrier layer contacts the upper wiring structure.

10. The semiconductor device according to claim 1, further comprising: include: a first insulating spacer, the first insulating spacer being located on a side surface of the first through via; as well as a second insulating spacer, the second insulating spacer being located on a side surface of the second through via, wherein the first through via is separated from the upper substrate by the first insulating spacer, and The second through via is separated from the upper substrate by the second insulating spacer.

11. The semiconductor device according to claim 1, in, The storage structure includes: A cell switching device, wherein each of the cell switching devices comprises a first cell source / drain region, a second cell source / drain region and a cell gate electrode; bit lines respectively connected to the first cell source / drain regions of the cell switching devices; and a data storage structure connected to the second cell source / drain region of the cell switching device, and Wherein, the data storage structure includes: first electrodes, the first electrodes being respectively connected to the second unit source / drain regions of the unit switching devices; a second electrode configured to at least partially cover the first electrode; and A dielectric layer is located between the first electrode and the second electrode.

12. A semiconductor device, the semiconductor device include: A lower chip structure, the lower chip structure comprising a first storage area, a second storage area, and an extension area located between the first storage area and the second storage area; as well as an upper chip structure, the upper chip structure being located on the lower chip structure, Wherein, the lower chip structure further includes: a first bit line located in the first storage region and extending into the extension region; a second bit line located in the second storage region and extending into the extension region; and a routing lower wiring structure, the routing lower wiring structure being electrically connected to the first bit line and the second bit line, Wherein, the upper chip structure comprises: upper base; a peripheral transistor vertically overlapping the first storage region and located below the upper substrate; a routing intermediate wiring structure, the routing intermediate wiring structure being located below the upper substrate and connected to the peripheral transistor; A routing upper wiring structure, wherein the routing upper wiring structure is located on the upper substrate; a first through via that penetrates the upper substrate and connects the routing upper wiring structure and the routing middle wiring structure; and a second through via, the second through via penetrating the upper substrate and connecting the routing upper wiring structure and the routing lower wiring structure, wherein the second through passage is located on the extension area, and Wherein, the first through passage is located on the first storage area.

13. The semiconductor device according to claim 12, in, The lower chip structure further includes a lower bonding insulation layer, The upper chip structure further includes an upper bonding insulating layer bonded to the lower bonding insulating layer. wherein the peripheral transistors and the routing intermediate wiring structure constitute a sense amplifier, and Wherein, the readout amplifier is located between the upper substrate and the upper bonding insulating layer.

14. The semiconductor device according to claim 13, in, The second through via penetrates the upper substrate to continuously extend downward and penetrates the upper bonding insulating layer and the lower bonding insulating layer.

15. The semiconductor device according to claim 12, in, The routing wiring structure comprises: a first sub-routing lower wiring structure, the first sub-routing lower wiring structure connected to the first bit line; and A second sub-routing lower wiring structure, wherein the second sub-routing lower wiring structure is connected to the second bit line, The first through-path includes a first sub-routing through-path and a second sub-routing through-path, Wherein, the second through passage comprises: a third sub-routing through-via, the third sub-routing through-via being connected to the first sub-routing lower wiring structure; and A fourth sub-routing through-via is connected to the second sub-routing lower wiring structure, and Wherein, the routing wiring structure includes: a first sub-routing upper wiring structure, the first sub-routing upper wiring structure connecting the first sub-routing through-via and the third sub-routing through-via; and The second sub-routing upper wiring structure connects the second sub-routing through-via and the fourth sub-routing through-via.

16. The semiconductor device according to claim 15, in, The peripheral transistors and the routing intermediate wiring structure constitute a sense amplifier, Wherein, the lower chip structure also includes a data storage structure, wherein the first bit line is configured to sense data stored in the data storage structure, and Wherein, the second bit line comprises a complementary bit line.

17. The semiconductor device according to claim 12, in, The upper substrate comprises: an upper semiconductor substrate; a peripheral active region, the peripheral active region being located below the upper semiconductor substrate; and A peripheral device isolation region is located below the upper semiconductor substrate and defines a side surface of the peripheral active region.

18. A semiconductor device, the semiconductor device include: A lower chip structure, the lower chip structure comprising a storage structure and a lower wiring structure connected to the storage structure; an upper chip structure, the upper chip structure being located on the lower chip structure, Wherein, the upper chip structure comprises: upper base; A peripheral transistor, the peripheral transistor being located below the upper substrate; an intermediate wiring structure, the intermediate wiring structure being located below the upper substrate and connected to the peripheral transistor; an upper wiring structure, the upper wiring structure being located on the upper substrate; and a through via, the through via penetrating at least the upper substrate, The intermediate wiring structure includes intermediate paths at different heights and intermediate wirings at different heights. Wherein, the upper wiring structure includes at least one upper via and at least one upper wiring, and The number of the intermediate wirings is greater than the number of the at least one upper wiring.

19. The semiconductor device according to claim 18, in, The through passage comprises: a first through via, the first through via penetrating the upper substrate between the upper wiring structure and the middle wiring structure, the first through via connecting the upper wiring structure and the middle wiring structure; and a second through via, the second through via penetrating the upper substrate between the upper wiring structure and the lower wiring structure and extending downward, the second through via connecting the upper wiring structure and the lower wiring structure, and Wherein, the maximum width of the second through passage is greater than the maximum width of the first through passage.

20. The semiconductor device according to claim 19, in, The lower chip structure further includes a lower bonding insulating layer, and the lower bonding insulating layer is located on the storage structure and the lower wiring structure. The upper chip structure further comprises an upper bonding insulating layer, which is bonded to the lower bonding insulating layer and is located below the upper substrate, the peripheral transistor and the intermediate wiring structure. wherein the first through via is at a height higher than that of the upper bonding insulating layer, wherein the first through passage vertically overlaps the storage structure, wherein the second through passage includes a portion penetrating the upper substrate, wherein the second through-via extends downwardly continuously from the portion penetrating the upper substrate, and The second through via penetrates the upper bonding insulating layer and the lower bonding insulating layer.

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