Unit cell, stacked semiconductor device, and method of manufacturing the same

Abstract

The invention relates to a unit cell, a stacked semiconductor device, and a method of manufacturing the stacked semiconductor device. The unit cell may include an active layer, a separation region, and a gate. The active layer may include a first junction region, a second junction region, and a channel between the first junction region and the second junction region. A separation region may be formed in the active layer to separate the first junction region and the channel into at least two regions. A gate may be disposed in the separation region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2023-0078240, filed on Jun. 19, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments relate generally to semiconductor devices and methods of manufacturing the same, and more particularly, to a unit cell, a stacked semiconductor device including the unit cell, and a method of manufacturing the stacked semiconductor device. Background Art

[0004] To meet customer requirements for high performance and low cost, the integration level of semiconductor devices has increased over time.

[0005] Since the integration level of semiconductor devices is an important factor in determining semiconductor costs, it is desirable to increase the integration level. In two-dimensional (2D) or planar semiconductor devices, the integration level is determined by the occupied area of ​​a unit memory cell, and therefore is affected by the technology for forming fine patterns.

[0006] Since fine patterns may be formed using expensive equipment, although the integration of 2D semiconductor devices can be improved, the integration of 2D semiconductor devices is limited in terms of the customer's requirements for high performance and low cost as mentioned above. Therefore, a stacked semiconductor memory device including memory cells arranged in a three-dimensional (3D) structure has been considered. Summary of the invention

[0007] Various embodiments of the present disclosure may provide a unit cell having improved electrical characteristics.

[0008] Various embodiments of the present disclosure may also provide a stacked semiconductor device including the above-mentioned unit cell.

[0009] Various embodiments of the present disclosure may also provide a method of manufacturing the above-mentioned stacked semiconductor device.

[0010] According to an embodiment disclosed herein, a unit cell is provided. The unit cell may include an active layer, a separation region and a gate. The active layer may include a first junction region, a second junction region and a channel between the first junction region and the second junction region. The separation region may be formed in the active layer to separate the first junction region and the channel into at least two regions. The gate may be arranged in the separation region.

[0011] According to an embodiment disclosed herein, a stacked semiconductor device is provided. The stacked semiconductor device may include an active region, a separation region, a plurality of bit lines, a plurality of storage elements, and a gate. The active region may include an active layer and an insulating interlayer, and the active layer and the insulating interlayer are alternately stacked at least twice to form a plurality of active layers and an insulating layer. Each active layer may include a first junction region and a second junction region, and the first junction region and the second junction region are configured to form a channel substantially parallel to a first direction. A separation region may be formed in a plurality of active layers to separate the channel and the first junction region of each active layer into at least two bar regions. A bit line may be provided to each active layer. The bit line may be connected to the first junction region. A storage element may be provided to each active layer. The storage element may be electrically connected to the second junction region. A gate may be arranged in the separation region. The gate may extend in the stacking direction of the active layer to have an overlapping portion that overlaps with respect to each active layer. The separation region may be located between the gate and the bit line. The gate includes a common gate for a plurality of active layers.

[0012] In some embodiments, a length of the separation region between the gate and the bit line is longer than a distance between the gate and the second junction region.

[0013] In other embodiments, the separation region is further located between the gate and the second junction region.

[0014] In some embodiments, the distance between storage elements is substantially equal to or longer than the length of the separation region between the gate and the bit line.

[0015] According to an embodiment disclosed herein, a method for manufacturing a stacked semiconductor device is provided. In the method for manufacturing a stacked semiconductor device, an active layer and an insulating layer may be stacked at least twice to form a stacked structure. The active layer may include a first junction region and a second junction region. A separation region may be formed through a selected portion of each active layer to separate the first junction region into at least two strip regions. Corresponding to each active layer, a bit line may contact the first junction region separated into strip regions. Corresponding to each active layer, a storage element may be connected to each second junction region. A gate may be formed in the separation region to have an overlapping region with respect to each active layer.

[0016] For example, the active layer and the insulating layer in the active region may be etched to form a separation hole. Then, the separation hole may be filled with a dielectric material to form a separation region.

[0017] According to an embodiment disclosed herein, a unit cell for a three-dimensional semiconductor device is provided. The unit cell may include an active layer, a separation region, and a gate. The active layer may include a first junction region, a second junction region, and a channel between the first junction region and the second junction region. The separation region may be formed in the active layer to separate the first junction region and the channel into at least two regions. The gate may be arranged in the separation region. The gate may extend vertically beyond the separation region to connect to other active layers above the active layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1A is a plan view showing a unit cell according to various embodiments of the present disclosure;

[0020] Figure 1B is a perspective view showing a unit cell according to other embodiments of the present disclosure;

[0021] Figure 2A is a plan view showing a unit cell according to other embodiments of the present disclosure;

[0022] Figure 2B is a perspective view showing a unit cell according to various embodiments of the present disclosure;

[0023] Figure 3A and Figure 3B is a perspective view showing a stacked semiconductor device according to other embodiments of the present disclosure;

[0024] FIG. 4A to FIG. 15A is a plan view illustrating a method of manufacturing a stacked semiconductor device according to various embodiments of the present disclosure;

[0025] FIG. 4B to FIG. 15B is along FIG. 4A to FIG. 15A A cross-sectional view taken along line b-b';

[0026] FIG. 7C to FIG. 15C is a plan view illustrating a method of manufacturing a stacked semiconductor device according to various embodiments of the present disclosure; and

[0027] FIG. 7D to FIG. 15D is along FIG. 7C to FIG. 15C A cross-sectional view taken along line c-c'. DETAILED DESCRIPTION

[0028] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic illustrations of various embodiments and intermediate structures. As such, variations in the illustrated configurations and shapes, for example due to manufacturing techniques and / or tolerances, are within the scope of the present disclosure. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes shown herein, but deviations in configurations and shapes are included within the scope of the present disclosure.

[0029] The present disclosure is described with reference to the cross-sectional illustrations and / or plan illustrations of the embodiments shown herein. However, the described embodiments of the present disclosure should not be construed as limiting the inventive concept. Although some embodiments of the present disclosure will be shown and described, it will be understood by those of ordinary skill in the art that these embodiments may be changed without departing from the scope of the present disclosure.

[0030] As described above, as the integration of semiconductor devices increases, stacked semiconductor memory devices including memory cells arranged in a three-dimensional (3D) structure have been considered. However, because the memory cells of the stacked semiconductor memory device are stacked in a 3D structure, the elements in the stacked semiconductor memory device may not have desired electrical characteristics. The present disclosure was produced under this background.

[0031] Figure 1A is a plan view showing a unit cell according to various embodiments of the present disclosure, and Figure 1B is a perspective view illustrating a unit cell according to various embodiments of the present disclosure.

[0032] Reference Figure 1A and Figure 1B , the unit cell 100 may include a switching element T, a bit line BL, and a storage node SN. The storage node SN may be a part of a storage element.

[0033] The switching element T may include an active layer 110 and a gate 130. For example, the switching element T may be a transistor.

[0034] In some embodiments, the active layer 110 may include a semiconductor material. For example, the active layer 110 may include at least one or more of polysilicon, single crystal silicon, germanium, and silicon-germanium. The active layer 110 may include a first conductive type impurity having a low concentration.

[0035] The active layer 110 may have a long axis extending along a first direction D1 and a short axis extending along a second direction D2. The first direction D1 and the second direction D2 may be substantially perpendicular to each other. In addition, the third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2. The third direction D3 may be substantially perpendicular to a surface of the active layer 110, such as a stacking direction.

[0036] The active layer 110 may include a first junction region J1 and a second junction region J2. The first junction region J1 may be located at one side of the active layer 110. The second junction region J2 may be located at the other side of the active layer 110. The channel CH may be formed between the first junction region J1 and the second junction region J2 at the active layer 110. For example, the positions of the first junction region J1 and the second junction region J2 may provide that the channel CH has a direction substantially parallel to the first direction D1.

[0037] The first junction region J1 and the second junction region J2 may correspond to the drain and source of the transistor, respectively. The first junction region J1 and the second junction region J2 may include a second conductive type impurity opposite to the first conductive type impurity. For example, when the active layer 110 may include a p-type impurity, the first junction region J1 and the second junction region J2 may include an n-type impurity with a high concentration, such as, for example, arsenic (As), phosphorus (P), etc. In some embodiments, the low concentration may correspond to the general concentration of the active layer (e.g., in the channel layer) in the semiconductor device. The high concentration may correspond to the general concentration of the drain and source of the semiconductor device. The low concentration and the high concentration may be changed according to the characteristics of the semiconductor device.

[0038] The active layer 110 may include a separation region 120. The separation region 120 may separate the channel CH and the first junction region J1 of the active layer 110 into at least two strip regions B. For example, the long axis of the separation region 120 (i.e., the extension length of the separation region 120 along the first direction D1) may be shorter than the long axis of the active layer 110 (i.e., the extension length of the active layer 110 along the first direction D1). The short axis of the separation region 120 (i.e., the extension length of the separation region 120 along the second direction D2) may be shorter than the short axis of the active layer 110 (i.e., the extension length of the active layer 110 along the second direction D2). One end of the separation region 120 may face the second junction region J2.

[0039] In other embodiments, the separation region 120 may include an insulating material or a space filled with air.

[0040] Each of the strip-shaped regions B separated by the separation region 120 may include a portion of the channel CH and a portion of the first junction region J1. Each of the strip-shaped regions B may have substantially the same size, but is not limited thereto.

[0041] The gate 130 may be located between the first junction region J1 and the second junction region J2. For example, the gate 130 may be located in the separation region 120. The gate 130 may extend in the third direction D3. For example, the gate 130 may include a vertical gate extending vertically relative to the surface of the active layer 110, a vertical pillar gate, a vertical pillar word line, etc.

[0042] In various embodiments, the gate 130 may include at least one or more of a silicon-based material, a metal-based material, and a combination thereof. The gate 130 may include, for example, at least one or more of silicon, metal, metal nitride, metal silicide, and a combination thereof. Alternatively, the gate 130 may include, for example, at least one or more of polycrystalline silicon, titanium nitride, tungsten, and a combination thereof. The gate 130 may include at least one or two of polycrystalline silicon and titanium nitride doped with n-type impurities. The gate 130 may include a stacked layer having a titanium nitride layer and a tungsten layer. In addition, the gate 130 may include a conductive material having a low work function (e.g., not greater than about 4.5 eV) to reduce the threshold voltage of the transistor. A gate insulating layer 135 may be formed on the gate 130. The gate insulating layer 135 may insulate the gate 130 from the active layer 110. Hereinafter, the gate 130 may be a structure including the gate insulating layer 135.

[0043] like Figure 1A and Figure 1B As shown, the length of the separation region 120 between the gate 130 and the bit line BL may correspond to a first length a1 or a first distance. The length of the separation region 120 between the gate 130 and the second junction region J2 may correspond to a second length a2 or a second distance. In addition, the gate 130 may be spaced apart from the storage node SN or the storage element by a third length a3 or a third distance.

[0044] The first length a1 may be substantially equal to or different from the second length a2. The first length a1 may be longer or shorter than the second length a2.

[0045] The third length a3 may be substantially equal to or greater than the first length a1. For example, when the third length a3 may be longer than the first length a1, a gate induced drain leakage current (GIDL) caused by row hammering may be reduced. When the gate 130 may operate as a transfer gate, the charge in the storage node SN may be captured on the surface of the gate 130. Thereafter, when the gate 130 is not turned on, that is, when no voltage is applied to the gate 130, the charge captured on the surface of the gate 130 may electrically float and flow to other electrical components of the memory cell 100, such as the bit line BL closer to the storage node SN. In an embodiment, when the gate 130 operates as a transfer gate, since the storage node SN is spaced apart from the gate 130 by a third length a3 that is longer than the first length a1, the path through which the charge leaked from the storage node SN is transmitted to the gate 130 becomes longer. Therefore, the amount of charge captured by the gate 130 operating as a transfer gate may be reduced.

[0046] In addition, since the separation region 120 is interposed between the gate 130 and the bit line BL, when the gate is not turned on, the separation region 120 can block the charge captured on the gate 130 from flowing to the bit line BL receiving the voltage. Therefore, the charge loss of the storage node SN can be prevented. Leakage current caused by row hammering and GIDL can also be prevented.

[0047] like Figure 2A and Figure 2B As shown, the gate 130 may face the second junction region J2 without a gap. Specifically, only the gate insulating layer 135 may be located between the gate 130 and the second junction region J2. However, the gap between the gate 130 and the storage node SN, ie, the third length a3, may be substantially equal to or longer than the first length a1.

[0048] As described above, the bit line BL may be connected to the first junction region J1 separated into the strip region B. The bit line BL may extend in the second direction D2. For example, the bit line BL may be connected to at least two strip region B-shaped first junction regions J1 and the separation region 120 between the first junction regions J1.

[0049] The storage element may include a storage node SN, a storage electrode, a dielectric layer, and a plate electrode. The storage node SN may be electrically connected to the second junction region J2. The storage electrode may be in contact with the storage node SN.

[0050] According to various embodiments, a separation region 120 may be formed in the active layer 110 to control a gap between the gate 130 and the bit line BL. The separation region 120 between the gate 130 and the bit line BL may greatly reduce parasitic capacitance between the gate 130 and the bit line BL.

[0051] In addition, the separation region 120 may be further arranged between the gate 130 and the second junction region J2 to reduce parasitic capacitance. The separation region 120 may form a relatively large gap between the gate 130 and the storage node SN to reduce GIDL. The separation region 120 may reduce parasitic capacitance between the storage electrode and the bit line BL, between the plate electrode of the storage node and the bit line BL, and between the plate electrode of the storage node and the gate 130.

[0052] In addition, compared with the double gate structure, the vertical columnar gate 130 can reduce the channel inversion speed. Therefore, the threshold voltage characteristics of the transistor can be controlled. The gate 130 can be formed using a variety of conductive materials. As a result, the leakage current in the unit cell 100 caused by various reasons can also be reduced. Figure 1A , Figure 1B , Figure 2A and Figure 2B The active layers 110 in the semiconductor device may be vertically stacked to form a stacked semiconductor device.

[0053] Figure 3A and Figure 3B is a perspective view showing a stacked semiconductor device according to other embodiments of the present disclosure. Figure 3A and Figure 3B Three active layers stacked in one gate may be shown.

[0054] Reference Figure 3A The stacked semiconductor device 200 of these embodiments may include vertically stacked active layers 210a, 210b and 210c, a separation region 220, a gate 230, a plurality of bit lines BL1, BL2 and BL3, and a plurality of storage nodes SN1, SN2 and SN3.

[0055] The active layers 210a, 210b, and 210c may be stacked on each other and extend along the third direction D3. The active layers 210a, 210b, and 210c may be spaced apart from each other by a gap so that the active layers 210a, 210b, and 210c may be electrically isolated from each other. An insulating layer (not shown) may be interposed between the active layers 210a, 210b, and 210c. Each of the active layers 210a, 210b, and 210c may include a Figures 1A to 2B The first junction region J1, the channel CH, and the second junction region J2 described in the description of .

[0056] The separation region 220 may be located in the active layers 210a, 210b, and 210c. The separation region 220 may separate the channel CH and the first junction region J1 of each of the active layers 210a, 210b, and 210c into at least two strip regions B. The separation regions 220 of the active layers 210a, 210b, and 210c may be connected to each other. For example, the separation region 220 may have a plug structure formed through the active layers 210a, 210b, and 210c. In addition, the separation region 220 may include an insulating material.

[0057] The gate 230 may be located in the separation region 220. The gate 230 may extend in the separation region 220 of the active layers 210a, 210b, and 210c along the third direction D3. Therefore, the gate 230 may have a pillar structure so that the gate 230 may operate as a common gate of the active layers 210a, 210b, and 210c. A gate insulating layer 235 may be formed on the sidewall of the gate 230.

[0058] The bit lines BL1, BL2, and BL3 may be stacked on top of each other in the third direction D3 to correspond to the active layers 210a, 210b, and 210c. Each of the bit lines BL1, BL2, and BL3 may contact the first junction region J1 having the strip region B shape of the active layers 210a, 210b, and 210c. Similar to the active layers 210a, 210b, and 210c, the bit lines BL1, BL2, and BL3 may be electrically isolated from each other by an insulating layer. The bit lines BL1, BL2, and BL3 may extend along the second direction D2.

[0059] The storage nodes SN1, SN2, and SN3 may be electrically connected to the second junction region J2 of the active layers 210a, 210b, and 210c. The storage nodes SN1, SN2, and SN3 may be part of a storage element.

[0060] In some embodiments, the gate 230 may be spaced apart from the first junction region J1 by a first distance a11, ie, the length of the separation region 220 between the bit lines BL1, BL2, and BL3. The gate 230 may be spaced apart from the second junction region J2 by ​​a second distance a12. Figure 3B As shown, the gate 230 may face the second junction region J2 around the gate insulating layer 235 .

[0061] The gate 230 may be spaced apart from the storage elements (ie, the storage nodes SN1, SN2, and SN3) by a third distance a13. The third distance a13 may be longer than the first distance a11 to reduce GIDL.

[0062] FIG. 4A to FIG. 15A is a plan view illustrating a method of manufacturing a stacked semiconductor device according to various embodiments of the present disclosure. FIG. 4B to FIG. 15B is along FIG. 4A to FIG. 15A The cross-sectional view taken along the line b-b' in FIG. FIG. 7C to FIG. 15C is a plan view illustrating a method of manufacturing a stacked semiconductor device according to various embodiments of the present disclosure. FIG. 7D to FIG. 15D is along FIG. 7C to FIG. 15C A cross-sectional view taken along line c-c'.

[0063] Reference Figure 4A and Figure 4B , the first layers 305a, 305b, and 305c and the second layers 310a, 310b, and 310c may be stacked at least twice. The first layers 305a, 305b, and 305c and the second layers 310a, 310b, and 310c may be stacked on the lower layer 301. The lower layer 301 may include a circuit layer, a substrate having a circuit layer, an interposer having a circuit layer, a semiconductor device including at least one of a circuit layer and a memory cell, and the like.

[0064] The first layers 305a, 305b, and 305c may include a sacrificial layer. The second layers 310a, 310b, and 310c may include a semiconductor layer used as an active layer. The first layers 305a, 305b, and 305c and the second layers 310a, 310b, and 310c may have different etching selectivities.

[0065] For example, when the second layers 310 a , 310 b , and 310 c as active layers may include silicon, the first layers 305 a , 305 b , and 305 c may include silicon germanium (SiGe).

[0066] Alternatively, when the second layers 310 a , 310 b , and 310 c may include silicon germanium, the first layers 305 a , 305 b , and 305 c may include silicon or a material having an etching selectivity with respect to silicon germanium.

[0067] Reference Figure 5A and Figure 5B , the first layers 305 a , 305 b , and 305 c and the second layers 310 a , 310 b , and 310 c may be patterned to form a stack structure 320 .

[0068] For example, the stacked structure 320 may include a switch element region 320a, a bit line region 320b, and a storage region 320c. The first junction region, the second junction region, and the channel of the switch transistor may be formed in the switch element region 320a. The switch element region 320a may have a long axis substantially parallel to the first direction D1 and a short axis substantially parallel to the second direction D2. The switch element region 320a may include a separation hole H1 formed through the switch element region 320a.

[0069] The bit line region 320b may be located at a first end of the switching element region 320a. A sidewall of the bit line region 320b may be in contact with the switching element region 320a and may be adjacent to the separation hole H1.

[0070] The storage region 320c may be located at a second end of the switching element region 320a. A first junction formation region may be formed in the switching element region 320a in contact with the bit line region 320b. A second junction formation region may be formed in the switching element region 320a in contact with the storage region 320c.

[0071] For example, the separation hole H1 may be formed simultaneously with the stack structure 320. Alternatively, the separation hole H1 may be formed by a process different from a process for forming the stack structure 320.

[0072] Reference Fig. 6A and Figure 6B , a first insulating layer 325 and a sacrificial layer 330 may be formed on sidewalls of the stack structure 320 .

[0073] In some embodiments, the first insulating layer 325 may be formed on a surface of the stack structure 320. The first insulating layer 325 may be anisotropically etched to leave the first insulating layer 325 on a sidewall of the stack structure 320.

[0074] The space outside the stack structure 320 may be filled with a sacrificial layer 330. The sacrificial layer 330 may include a semiconductor material such as, for example, amorphous silicon, polycrystalline silicon, and / or epitaxially grown silicon. The sacrificial layer 330 may be planarized to have an upper surface substantially coplanar with an upper surface of the stack structure 320.

[0075] Reference Fig. 7A and Figure 7B , the sacrificial layer 330 may be patterned to form an initial gate line 330 a and a sacrificial plate line 330 b , thereby partially exposing a sidewall of the stack structure 320 .

[0076] In a plan view, the initial gate line 330a and the sacrificial plate line 330b may extend in the second direction D2. In addition, a portion of the initial gate line 330a may be located in the separation hole H1. The sacrificial plate line 330b may be located outside the storage area 320c.

[0077] For example, the initial gate line 330 a in the separation hole H1 may be spaced apart from the second junction forming region by a second distance a12 .

[0078] Or, if Figure 7C and Fig.7D As shown, the initial gate line 330 a in the separation hole H1 may contact the second junction forming region around the first insulating layer 325 .

[0079] Reference FIG. 8A to FIG. 8D The first layers 305a, 305b, and 305c of the stack structure 320 may be selectively removed to define the space sp1. For example, an etchant may be provided through the exposed sidewalls of the stack structure 320 to selectively remove the first layers 305a, 305b, and 305c.

[0080] Hereinafter, the selective removal or the selective etching may be performed using at least one of an etching process using a difference between etching selectivities of layers and a process for removing an exposed region using a mask.

[0081] Reference 9A to 9D , a second insulating layer 335 may be formed outside the stack structure 320 to fill the space sp1 and the separation hole H1.

[0082] The second insulating layer 335 may include a material having a gap-filling property and having a low dielectric constant. For example, the second insulating layer 335 may include a spin-on dielectric (SOD), but the present disclosure is not limited thereto.

[0083] The second insulating layer 335 in the space sp1 can electrically insulate the second layers 310a, 310b, and 310c of the stacked structure 320 from each other. The second insulating layer 335 in the separation hole H1 can electrically isolate the initial gate line 330a from the bit line 330b and / or electrically isolate the primary gate line 330a from the second junction formation region. The second insulating layer 335 outside the stacked structure 320 can be used as a device isolation layer configured to electrically isolate the stacked structures 320 from each other. The second insulating layer 335 in the separation hole H1 can correspond to the separation region 120 in FIG. 1.

[0084] Alternatively, the formation of the second insulating layer 335 may be omitted. The space sp1 and the separation hole H1 may be filled with air. The second insulating layer 335 c may be formed only outside the stack structure 320 .

[0085] Reference FIG. 10A to FIG. 10D , the preliminary gate line 330 a may be patterned to form a preliminary gate PG in the separation hole H1 .

[0086] For example, the initial gate line 330a outside the separation hole H1 may be removed to form the initial gate PG. The initial gate PG may be isolated from the second layers 310a, 310b, and 310c of the switching element region 320a by the first insulating layer 325. In addition, the initial gate PG may be isolated from the bit line region 320b and the second junction formation region by the second insulating layer 335b in the separation hole H1.

[0087] Reference FIG. 11A to FIG. 11D , the third insulating layer 340 may be formed in the space between the second insulating layers 335c.

[0088] The third insulating layer 340 may include a material substantially the same as that of the second insulating layers 335a, 335b, and 335c. The third insulating layer 340 may have a thickness corresponding to the height of the stacked structure 320. Similar to the second insulating layer 335c, the third insulating layer 340 may be used as a device isolation layer.

[0089] Reference FIG. 12A to FIG. 12D , a plurality of bit lines 350a, 350b, and 350c may be formed in the bit line region 320b. Specifically, the second layers 310a, 310b, and 310c of the bit line region 320b may be selectively removed to define a space between the second insulating layers 335c of the bit line region 320b. The space may be filled with a conductive material to form the bit lines 350a, 350b, and 350c.

[0090] In some embodiments, the bit lines 350a, 350b, and 350c may include, for example, one or more of conductive silicon, metal, metal nitride, metal silicide, and combinations thereof. The bit lines 350a, 350b, and 350c may include one or more of titanium nitride, tungsten, and combinations thereof. The bit lines 350a, 350b, and 350c may include a doped + At least one of polysilicon and titanium nitride with type impurities. The bit lines 350a, 350b, and 350c may include a stacked structure including a titanium nitride layer and / or a tungsten layer. The planar structure of the bit lines 350a, 350b, and 350c may be a stripe structure extending along the second direction D2.

[0091] In some embodiments, impurities may be implanted into the first layers 305a, 305b, and 305c of the switching element region 320a exposed by the spaces, i.e., the first junction formation region between the formation of the spaces and the formation of the bit lines 350a, 350b, and 350c, to form the first junction region J1. The first junction region J1 may include n-type impurities having a high concentration.

[0092] Therefore, the first junction region J1 and the bit lines 350 a , 350 b , and 350 c on the same layer or level may be connected to each other.

[0093] Reference FIG. 13A to FIG. 13D , n-type impurities having a high concentration may be implanted into the second junction formation region to form a second junction region J2.

[0094] Specifically, the sacrificial plate line 330 b may be selectively removed to form a plate space sp2 , thereby exposing the sidewall of the storage region 320 c .

[0095] The etchant may be provided through the exposed sidewall of the storage region 320c. Therefore, the second layers 310a, 310b and 310c of the storage region 320c may be selectively removed to define a storage space sp3 between the second insulating layer 335a of the storage region 320c. In addition, the second junction forming region of the switching element region 320a may also be exposed through the storage space sp3.

[0096] N-type impurities having a high concentration may be implanted into the second junction formation region, ie, the exposed first layers 305 a , 305 b , and 305 c of the switching element region 320 a to form a second junction region J2 .

[0097] Reference numerals 311a, 311b, and 311c may denote an active layer including first and second junction regions and a channel region. Reference numeral 321 may denote an active region including the stacked active layers 311a, 311b, and 311c.

[0098] Reference FIG. 14A to FIG. 14D , the storage element ST may be formed in the storage space sp3 and the plate space sp2.

[0099] In some embodiments, the storage element ST may include a storage node contact 355 , a storage electrode 360 ​​, a dielectric layer 365 , and a plate electrode 370 .

[0100] The storage node contact 355 may be formed on the second junction region J2 exposed by the storage space sp3. For example, the storage node contact 355 may include at least one or more of a polysilicon layer doped with impurities, a metal silicide layer, and a stacked layer including the polysilicon layer doped with impurities and the metal silicide layer.

[0101] The storage electrode 360 ​​may be conformally formed on the surface of the storage node contact 355 and the inner surface of the storage space sp3. The storage electrode 360 ​​may be formed by forming a conductive layer and etching back the conductive layer to expose the sidewall of the second insulating layer 335a. The storage electrode 360 ​​may have a cylindrical shape.

[0102] The storage electrode 360 ​​may include, for example, one or more of a metal layer, a noble metal layer, a metal nitride layer, a conductive metal oxide layer, a conductive noble metal oxide layer, a metal carbon layer, a metal silicide, and a combination thereof. For example, the storage electrode 360 ​​may include one or more of Ti, TiN, Ta, TaN, W, WN, Ru, RuO2, Ir, IrO2, Pt, Mo, MoO, TiN / W, and WN / W.

[0103] The dielectric layer 365 may be formed on the surface of the storage electrode 360. The dielectric layer 365 may correspond to a capacitor dielectric layer or a storage layer. The dielectric layer 365 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, a high-k material, and a combination thereof. The high-k material may have a dielectric constant higher than that of silicon oxide. For example, the dielectric constant of the material may be, for example, not less than about 20. The high-k material may include one or more of HfO2, ZrO2, Al2O3, La2O3, TiO2, Ta2O5, Nb2O5, and SrTiO3. Alternatively, the dielectric layer 360 may include a composite layer comprising at least two layers of the above materials.

[0104] The dielectric layer 365 may include a Zr-based oxide layer. The dielectric layer 365 may include a stacked structure including a ZrO2 layer. The dielectric layer 365 may include a ZA (ZrO2 / Al2O3) structure and / or a ZAZ (ZrO2 / Al2O3 / ZrO2) structure. The ZA structure may include an Al2O3 layer stacked on ZrO2. The ZAZ structure may include a ZrO2 layer, an Al2O3 layer, and a ZrO2 layer stacked in sequence. The ZA structure and the ZAZ structure may correspond to a ZrO2-based layer. Alternatively, the dielectric layer 365 may have a stacked structure including an HfO2 layer. The dielectric layer 365 may have a HA (HfO2 / Al2O3) structure and / or a HAH (HfO2 / Al2O3 / HfO2). The HA structure may include an Al2O3 layer stacked on a HfO2 layer. The HAH structure may include an HfO2 layer, an Al2O3 layer, and a HfO2 layer stacked in sequence. The HA structure and the HAH structure can be HfO2-based layers. In the ZA structure, the ZAZ structure, the HA structure, and the HAH structure, the band gap energy of the Al2O3 layer can be higher than the band gap energy of the ZrO2 layer and the HfO2 layer. The dielectric constant of the Al2O3 layer can be lower than the dielectric constant of the ZrO2 layer and the HfO2 layer. Therefore, the dielectric layer 365 can have a stacked structure including a high-k material and a high-bandgap material. The band gap energy of the high-bandgap material can be higher than the band gap energy of the high-k material. In addition to including the Al2O3 layer, the dielectric layer 365 can also include a SiO2 layer as another high-bandgap material. The dielectric layer 365 can include a high-bandgap material to suppress leakage current. The thickness of the high-bandgap material can be thinner than the thickness of the high-k material. Alternatively, the dielectric layer 365 can have a laminated structure (laminated structure) including high-k materials and high-bandgap materials stacked alternately. For example, the dielectric layer 365 may include, for example, one or more of a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) structure, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) structure, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) structure, and a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) structure. In the laminated structure, the thickness of the Al2O3 layer may be thinner than the thickness of the ZrO2 layer and the thickness of the HfO2 layer.

[0105] In addition, the dielectric layer 365 may have a stacked dielectric structure including a ZrO 2 layer, a HfO 2 layer, and an Al 2 O 3 layer, a laminated structure, or a hybrid structure thereof.

[0106] The plate electrode 370 may be filled in the storage space sp3 and the plate space sp2 on the dielectric layer 365 .

[0107] The plate electrode 370 may include a conductive material substantially the same as or different from that of the storage electrode 360. The plate electrode 370 may include a combination of a metal-based material and a silicon-based material.

[0108] An interface control layer for improving leakage current may be formed between the storage electrode 360 ​​and the dielectric layer 365 and / or between the dielectric layer 365 and the plate electrode 370. The interface control layer may include, for example, one or more of TiO2, Ta2O5, and Nb2O5.

[0109] The storage electrode 360 ​​may be located in the storage space sp3 by an etch-back process. Therefore, the stacked storage electrodes 360 may be separated from each other. In various embodiments, the storage node contact 355 and the storage electrode 360 ​​in the storage space sp3 may correspond to Figures 1A to 3B The storage node SN in.

[0110] The plate electrode 370 may cover the stacked storage electrode 360. That is, the stacked storage electrodes 360 may be separated from each other. The plate electrode 370 may extend in the third direction D3 without being disconnected, so that the plate electrode 370 may entirely overlap the stacked storage electrode 360.

[0111] Reference FIG. 15A to FIG. 15D , a gate 380 may be formed in the region where the initial gate PG is located to complete the stacked semiconductor device 300 .

[0112] Specifically, the preliminary gate PG may be selectively removed to form a gate space in the separation hole H1. In addition, the first insulating layer 325 between the active layers 311a, 311b, and 311c and the preliminary gate PG may also be removed together with the preliminary gate PG.

[0113] The gate insulating layer 375 may be conformally formed on the inner side surface of the gate space. The gate space with the gate insulating layer 375 may be filled with a gate conductive layer to form a gate 380 having a vertical column shape. The gate 380 may partially overlap with the stacked active layers 311a, 311b, and 311c, so that the gate 380 may operate as a common gate of the switching element at the active layers 311a, 311b, and 311c of the active region 321. The gate 380 may include, for example, one or more of a TiN / W layer, and polysilicon including conductive impurities, etc. Alternatively, in consideration of the threshold voltage characteristics of the switching transistor, the gate 380 may include a conductive layer having a low work function or a high work function.

[0114] For example, a portion of the gate 380 adjacent to the first junction region J1 and / or the second junction region J2 may include a conductive layer having a low work function. A portion of the gate 380 corresponding to the channel CH may include a conductive layer having a high work function.

[0115] According to various embodiments, a separation region may be formed between the gate and the bit line to define the distance between the gate and the storage node. Therefore, a separation region including an insulating material may be interposed between the gate and the bit line to reduce parasitic capacitance. In addition, because the size of the separation region may be determined according to the distance between the gate and the storage node, the GIDL may be additionally reduced. In addition, the switch element may be operated in a single gate type to control the threshold voltage.

[0116] The above embodiments of the present disclosure are intended to illustrate the present disclosure, rather than to limit the present disclosure. Various alternatives and equivalents are possible. The present disclosure is not limited to the embodiments described herein. The present disclosure is also not limited to any particular type of semiconductor device. Other additions, reductions and / or modifications are within the scope of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A unit cell, comprising: an active layer including a first junction region, a second junction region, and a channel between the first junction region and the second junction region; a separation region formed in the active layer to separate the first junction region and the channel into at least two parts; as well as A gate is disposed in the separation region.

2. The unit cell according to claim 1, wherein: The separation region includes an insulating material. 3 . The unit cell according to claim 1 , further comprising a bit line connected to one end of the first junction region.

4. The unit cell according to claim 3, wherein: A length of the separation region between the gate and the bit line is equal to or greater than a distance between the gate and the second junction region.

5. The unit cell according to claim 1, wherein: The gate electrode vertically extends through a surface of the active layer.

6. The unit cell according to claim 5, wherein: The gate includes at least one or more of a silicon layer, a metal layer, a metal nitride layer, a metal silicide layer, and a combination thereof. 7 . The unit cell according to claim 1 , further comprising a gate insulating layer on the gate. 8 . The unit cell according to claim 1 , further comprising a storage element including a storage node electrically connected to one end of the second junction region.

9. The unit cell according to claim 8, wherein: The distance between the gate and the storage node is substantially equal to or greater than the length of the separation region between the gate and a bit line.

10. A stacked semiconductor device, comprising: an active region, comprising an active layer and an insulating interlayer, the active layer and the insulating interlayer being alternately stacked at least twice to form a plurality of active layers and insulating layers, each of the active layers comprising a first junction region and a second junction region, the first junction region and the second junction region forming a channel substantially parallel to a first direction; a separation region formed in each of the active layers to separate the first junction region and the channel of each of the active layers into at least two strip-shaped regions; a plurality of bit lines arranged at each of the active layers and connected to the first junction region; a plurality of storage elements arranged at each of the active layers and electrically connected to the second junction region; as well as a gate which is arranged in the separation region, extends along the stacking direction of the active layers, and has an overlapping portion overlapping with respect to each of the active layers, The separation region is located between the common gate and the bit line, and the gate includes the common gate for the multiple active layers.

11. The stacked semiconductor device according to claim 10, wherein: The separation region includes an insulating material.

12. The stacked semiconductor device according to claim 10, wherein: A length of the separation region between the gate and the bit line is longer than a distance between the gate and the second junction region.

13. The stacked semiconductor device according to claim 12, wherein: The separation region is located between the gate and the second junction region.

14. The stacked semiconductor device according to claim 10, wherein: The distance between the gate and the storage element is substantially equal to or greater than the length of the separation region between the gate and the bit line. 15 . The stacked semiconductor device according to claim 10 , further comprising a gate insulating layer on the gate.

16. The stacked semiconductor device according to claim 15, wherein: The gate is spaced apart from the second junction region by a thickness of the gate insulating layer.

17. The stacked semiconductor device according to claim 10, wherein: The gate includes at least two conductive materials having different work functions.

18. The stacked semiconductor device according to claim 10, wherein: Each of the storage elements comprises: a plurality of storage electrodes electrically connected to the second junction region; a dielectric layer formed on the storage electrode; and A plate electrode is formed on the dielectric layer and overlaps the storage electrode.

19. A method for manufacturing a stacked semiconductor device, the method comprising: Alternately stacking active layers including first junction regions and second junction regions with insulating interlayers at least twice to form a stacked structure having a plurality of active layers, a plurality of first junction regions, and a plurality of second junction regions; forming a separation region passing through the active layer to separate the first junction region into at least two strip-shaped regions; making a bit line contact the first junction region separated into the at least two strip regions corresponding to each of the active layers; connecting a storage element to the second junction region corresponding to each of the active layers; as well as A gate is formed in the separation region to provide the gate having an overlapping portion with respect to each of the active layers.

20. The method according to claim 19, wherein: Forming the separation zone comprises: etching the active layer and the insulating layer in the active area to form separation holes; and The separation holes are filled with a dielectric material.

21. The method according to claim 20, wherein: Forming the gate includes: forming a gate space passing through the separation region; forming a gate insulating layer on a sidewall of the gate space; and A conductive layer is formed in the gate space having the gate insulating layer.

22. A unit cell for a three-dimensional semiconductor device, comprising: an active layer including a first junction region, a second junction region, and a channel between the first junction region and the second junction region; a separation region formed in the active layer to separate the first junction region and the channel into at least two parts; as well as A gate is arranged in the separation region and vertically extends beyond the separation region to be connected to other active layers above the active layer.

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