Semiconductor device

Abstract

A semiconductor device may include: a lower dielectric layer on a substrate; data storage patterns on the lower dielectric layer and spaced apart from each other in a first direction and a second direction; a unit dielectric layer on the lower dielectric layer and on the data storage pattern; voids in the cell dielectric layer and between data storage patterns among the data storage patterns; upper conductive contacts on the data storage patterns, respectively, and spaced apart from each other in the first direction and the second direction; and upper conductive lines on the upper conductive contact and spaced apart from each other in the second direction and extending in the first direction. Each of the upper conductive lines may be electrically connected to a respective one of the upper conductive contacts. Respective ones of the upper conductive contacts may be spaced apart from each other in the first direction.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a magnetic tunnel junction and a method of manufacturing the same. Background Art

[0002] As electronic products tend to be high speed and / or low power consumption, semiconductor memory devices incorporated in electronic products are increasingly required to have high speed and low operating voltage. In order to meet these requirements, magnetic memory devices have been developed as semiconductor memory devices. Because magnetic memory devices operate at high speed and have non-volatile properties, they have attracted considerable attention as next generation semiconductor memory devices.

[0003] In general, a magnetic memory device may include a magnetic tunnel junction (MTJ) pattern. The magnetic tunnel junction pattern includes two magnetic structures and a dielectric layer therebetween. The resistance of the magnetic tunnel junction pattern varies according to the magnetization directions of the two magnetic structures. For example, when the magnetization directions of the two magnetic structures are antiparallel, the magnetic tunnel junction pattern has a high resistance, and when the magnetization directions of the two magnetic structures are parallel, the magnetic tunnel junction pattern has a low resistance. The magnetic memory device can use the resistance difference between the high resistance and the low resistance of the magnetic tunnel junction pattern to write and read data.

[0004] In accordance with various demands of the electronics industry, various studies are being conducted on semiconductor devices having an embedded structure in which a magnetic tunnel junction pattern is provided between metal lines. Summary of the invention

[0005] Some embodiments of the inventive concept provide a semiconductor device capable of minimizing process defects and a method of manufacturing the semiconductor device.

[0006] Some embodiments of the inventive concept provide a semiconductor device capable of easily achieving high integration and a method of manufacturing the semiconductor device.

[0007] According to some embodiments of the present invention, a semiconductor device may include: a lower dielectric layer located on a substrate; a plurality of data storage patterns located on the lower dielectric layer and spaced apart from each other in a first direction and a second direction parallel to a top surface of the substrate, wherein the first direction and the second direction intersect each other; a unit dielectric layer located on the lower dielectric layer and located on the plurality of data storage patterns; a plurality of voids located in the unit dielectric layer and between data storage patterns in the plurality of data storage patterns; a plurality of upper conductive contacts located on the plurality of data storage patterns, respectively, and spaced apart from each other in the first direction and the second direction; and a plurality of upper conductive lines located on the plurality of upper conductive contacts and spaced apart from each other in the second direction, wherein the plurality of upper conductive lines extend in the first direction. Each of the plurality of upper conductive lines may be electrically connected to a corresponding upper conductive contact among the plurality of upper conductive contacts. The corresponding upper conductive contacts among the plurality of upper conductive contacts may be spaced apart from each other in the first direction.

[0008] According to some embodiments of the present inventive concept, a semiconductor device may include: a lower dielectric layer, the lower dielectric layer being located on a substrate; a plurality of data storage patterns, the plurality of data storage patterns being located on the lower dielectric layer and being spaced apart from each other in a first direction parallel to a top surface of the substrate; a unit dielectric layer, the unit dielectric layer being located on the lower dielectric layer and being located on the plurality of data storage patterns; a plurality of voids, the plurality of voids being located in the unit dielectric layer and between data storage patterns in the plurality of data storage patterns; a plurality of upper conductive contacts, the plurality of upper conductive contacts being respectively located on the plurality of data storage patterns and being spaced apart from each other in the first direction; and an upper conductive line, the upper conductive line being located on the plurality of upper conductive contacts and extending in the first direction. The plurality of upper conductive contacts may extend into an upper portion of the unit dielectric layer and may be respectively electrically connected to the plurality of data storage patterns. The upper conductive line may be electrically connected to the plurality of upper conductive contacts.

[0009] According to some embodiments of the present invention, a semiconductor device may include: a lower dielectric layer, the lower dielectric layer being located on a substrate; a plurality of data storage patterns, the plurality of data storage patterns being located on the lower dielectric layer and being spaced apart from each other in a first direction parallel to a top surface of the substrate; a unit dielectric layer, the unit dielectric layer being located on the lower dielectric layer and being located on the plurality of data storage patterns; a plurality of voids, the plurality of voids being located in the unit dielectric layer; a plurality of upper conductive contacts, the plurality of upper conductive contacts being respectively located on the plurality of data storage patterns and being spaced apart from each other in the first direction; and an upper conductive line, the upper conductive line being located on the plurality of upper conductive contacts and extending in the first direction. The upper conductive line may be electrically connected to the plurality of upper conductive contacts. The plurality of voids may not overlap with the plurality of upper conductive contacts in a second direction perpendicular to the top surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A circuit diagram illustrating a unit memory cell of a semiconductor device according to some embodiments of the inventive concept is shown.

[0011] Figure 2 A top view illustrating a semiconductor device according to some embodiments of the inventive concept is shown.

[0012] Figure 3A , Figure 3B , Figure 3C and Figure 3D Shown along Figure 2 Cross-sectional views taken along lines AA', BB', CC' and DD'.

[0013] Figure 4A and Figure 4B A cross-sectional view illustrating an example of a magnetic tunnel junction pattern in a semiconductor device according to some embodiments of the inventive concept is illustrated.

[0014] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig.9A , Fig. 9B , Fig. 9C and Fig.9DA cross-sectional view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0015] Fig.10 A top view illustrating a semiconductor device according to some embodiments of the inventive concept is shown.

[0016] Fig.11A , Fig. 11B and Fig. 11C Shown along Fig.10 Cross-sectional views taken along lines AA', BB' and CC'. DETAILED DESCRIPTION

[0017] Exemplary embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings.

[0018] Figure 1 A circuit diagram illustrating a unit memory cell of a semiconductor device according to some embodiments of the inventive concept is shown.

[0019] refer to Figure 1 , the unit memory cell MC may include a memory element ME and a selection element SE. The memory element ME and the selection element SE may be electrically connected in series with each other. The memory element ME may be connected between the bit line BL and the selection element SE. The selection element SE may be connected between the memory element ME and the source line SL and may be controlled by the word line WL. The selection element SE may include, for example, a bipolar transistor or a metal oxide semiconductor field effect transistor (MOSFET). As used herein, "element A is connected to element B" (or similar language) means that element A is physically connected and / or electrically connected to element B.

[0020] The memory element ME may include: a magnetic tunnel junction pattern MTJ, which includes a first magnetic pattern MP1 and a second magnetic pattern MP2; and a tunnel barrier pattern TBP, which is located between the first magnetic pattern MP1 and the second magnetic pattern MP2. One of the first magnetic pattern MP1 and the second magnetic pattern MP2 may be a reference magnetic pattern, which has a fixed magnetization direction regardless of the external magnetic field under normal use environment. The other of the first magnetic pattern MP1 and the second magnetic pattern MP2 may be a free magnetic pattern whose magnetization direction changes due to an external magnetic field between two stable magnetization directions. When the magnetization directions of the reference magnetic pattern and the free magnetic pattern are antiparallel to each other, the magnetic tunnel junction pattern MTJ may have a much larger resistance than when the magnetization directions of the reference magnetic pattern and the free magnetic pattern are parallel to each other. For example, the resistance of the magnetic tunnel junction pattern MTJ can be controlled by changing the magnetization direction of the free magnetic pattern. The memory element ME may utilize the difference in resistance depending on the magnetization direction of the reference magnetic pattern and the free magnetic pattern, and this mechanism may enable the unit memory cell MC to store data therein.

[0021] Figure 2 A top view illustrating a semiconductor device according to some embodiments of the inventive concept is shown. Figure 3A , Figure 3B , Figure 3C and Figure 3D Shown along Figure 2 Cross-sectional views taken along lines AA', BB', CC' and DD'. Figure 4A and Figure 4B A cross-sectional view illustrating an example of a magnetic tunnel junction pattern in a semiconductor device according to some embodiments of the inventive concept is illustrated.

[0022] refer to Figure 2 and FIG. 3A to FIG. 3D , a substrate 100 including a cell region CR and a peripheral region PR may be provided. The substrate 100 may be a semiconductor substrate including silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), or gallium arsenide (GaAs). The cell region CR may be a portion of the substrate 100 on which a Figure 1 The peripheral region PR may be a region of the memory cells MC, and the peripheral region PR may be another region of the substrate 100 on which a peripheral circuit for driving the memory cells MC is provided.

[0023] Wiring structures 102 and 104 may be disposed on a substrate 100. Wiring structures 102 and 104 may be disposed on a cell region CR and a peripheral region PR of the substrate 100. Wiring structures 102 and 104 may include a wiring line 102 vertically spaced apart from the substrate 100 and a wiring contact 104 connected to the wiring line 102. The wiring line 102 may be spaced apart from the top surface 100U of the substrate 100 along a direction (e.g., a third direction D3) perpendicular to the top surface 100U of the substrate 100. The wiring contact 104 may be disposed between the substrate 100 and the wiring line 102. Each of the wiring lines 102 may be electrically connected to the substrate 100 through a corresponding one of the wiring contacts 104. The wiring line 102 and the wiring contact 104 may include a metal (e.g., copper). As used herein, the terms "corresponding" and "correspondingly" may be used interchangeably with the terms "corresponding" and "correspondingly" unless the context clearly indicates otherwise.

[0024] Select the element (see, for example, Figure 1The SE of the substrate 100 may be disposed on the cell region CR of the substrate 100, and the peripheral transistor constituting the peripheral circuit may be disposed on the peripheral region PR of the substrate 100. The selection element and the peripheral transistor may be, for example, a field effect transistor. Each of the wiring lines 102 may be electrically connected to one terminal (e.g., a source terminal, a drain terminal, or a gate terminal) of a corresponding one of the selection element or the peripheral transistor through a corresponding one of the wiring contacts 104.

[0025] The wiring dielectric layer 110 may be disposed on the substrate 100 to be located on the wiring structures 102 and 104 (e.g., covering the wiring structures 102 and 104). The wiring dielectric layer 110 may be disposed on the cell region CR of the substrate 100 and may extend to the peripheral region PR of the substrate 100. The wiring dielectric layer 110 may expose the top surface of the uppermost wiring line in the wiring lines 102. That is, the wiring dielectric layer 110 may be absent or lacking on the top surface of the uppermost wiring line in the wiring lines 102. For example, the wiring dielectric layer 110 may have a top surface that is substantially coplanar with the top surface of the uppermost wiring line 102. The wiring dielectric layer 110 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0026] The first lower dielectric layer 120 may be disposed on the wiring dielectric layer 110 and may cover or overlap the exposed top surface of the uppermost wiring line 102. The first lower dielectric layer 120 may be disposed on the wiring dielectric layer 110 on the cell region CR and may extend onto the wiring dielectric layer 110 on the peripheral region PR. The first lower dielectric layer 120 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0027] The second lower dielectric layer 130 may be disposed on the first lower dielectric layer 120. The second lower dielectric layer 130 may be disposed on the first lower dielectric layer 120 on the cell region CR, and may extend onto the first lower dielectric layer 120 on the peripheral region PR. On the cell region CR and the peripheral region PR, the first lower dielectric layer 120 may be interposed between the wiring dielectric layer 110 and the second lower dielectric layer 130. The second lower dielectric layer 130 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The first lower dielectric layer 120 and the second lower dielectric layer 130 may constitute a lower dielectric layer.

[0028] The data storage pattern DS may be disposed on the second lower dielectric layer 130 on the cell region CR. The data storage pattern DS may be spaced apart from each other in a first direction D1 and a second direction D2 that intersect each other and are parallel to the top surface 100U of the substrate 100. That is, the first direction D1 and the second direction D2 may intersect each other and may each be parallel to the top surface 100U of the substrate 100, and the data storage pattern DS may be spaced apart from each other in the first direction D1 and the second direction D2. The second lower dielectric layer 130 on the cell region CR may have a recessed top surface 130RU that is recessed toward the substrate 100 between the data storage patterns DS. For example, a first portion of the second lower dielectric layer 130 located on the cell region CR may have a recessed top surface 130RU. The second lower dielectric layer 130 on the peripheral region PR may have a top surface 130U located at a height lower than the height of the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR. For example, a second portion of the second lower dielectric layer 130 on the peripheral region PR may have a top surface 130U. In this specification, the term "height" may indicate a distance measured from the top surface 100U of the substrate 100 in a third direction D3 perpendicular to the top surface 100U of the substrate 100. In other words, in a non-limiting example, the term "height" may indicate a distance in the third direction D3 (also referred to as a vertical direction), wherein the top surface 100U of the substrate 100 provides a reference plane.

[0029] The lower electrode contacts 140 may be disposed in the second lower dielectric layer 130 on the cell region CR and may be spaced apart from each other in the first direction D1 and the second direction D2. The lower electrode contacts 140 may be correspondingly disposed below the data storage pattern DS and electrically connected to the data storage pattern DS. For example, the lower electrode contacts 140 may be respectively located on the bottom surface of the data storage pattern DS and may be respectively electrically connected to the data storage pattern DS. Each of the lower electrode contacts 140 may penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130 on the cell region CR (i.e., extend therein) and may be connected to a corresponding one of the uppermost wiring lines 102. Each of the data storage patterns DS may be electrically connected to a corresponding selection element (e.g., see FIG. 1 ) through a corresponding lower electrode contact 140 and a corresponding uppermost wiring line 102. Figure 1 A terminal (e.g., a drain terminal) of SE).

[0030] The lower electrode contact 140 may have a top surface 140U located at a height higher than that of the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR. The lower electrode contact 140 may include at least one selected from a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium, and / or tantalum), a metal semiconductor compound (e.g., metal silicide), and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride).

[0031] Each of the data storage patterns DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked along a third direction D3 on the second lower dielectric layer 130. The magnetic tunnel junction pattern MTJ may be between the bottom electrode BE and the top electrode TE. The lower electrode contact 140 may be correspondingly connected to the bottom electrode BE of the data storage pattern DS. The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP between the first magnetic pattern MP1 and the second magnetic pattern MP2. The first magnetic pattern MP1 may be disposed between the bottom electrode BE and the tunnel barrier pattern TBP, and the second magnetic pattern MP2 may be disposed between the top electrode TE and the tunnel barrier pattern TBP. The bottom electrode BE may be, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The top electrode TE may include at least one selected from a metal (e.g., Ta, W, Ru, or Ir) and a conductive metal nitride (e.g., TiN).

[0032] refer to Figure 4A and Figure 4B , the first magnetic pattern MP1 may be a reference layer (e.g., a reference magnetic pattern) having a magnetization direction MD1 fixed in one direction, and the second magnetic pattern MP2 may be a free layer (e.g., a free magnetic pattern) having a magnetization direction MD2 that may be changed to be parallel or antiparallel to the magnetization direction MD1 of the first magnetic pattern MP1. Figure 4A and Figure 4B An example in which the second magnetic pattern MP2 is a free layer is shown, but the inventive concept is not limited thereto. Figure 4A and Figure 4B Unlike shown in FIG. 1 , the first magnetic pattern MP1 may be a free layer, and the second magnetic pattern MP2 may be a reference layer.

[0033] refer to Figure 4A, for example, the magnetization directions MD1 and MD2 of the first magnetic pattern MP1 and the second magnetic pattern MP2 may be perpendicular to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include at least one selected from an intrinsic perpendicular magnetization material and an extrinsic perpendicular magnetization material. The intrinsic perpendicular magnetization material may include a material having a perpendicular magnetization property even in the absence of external factors. The intrinsic perpendicular magnetization material may include at least one selected from a perpendicular magnetic material (e.g., CoFeTb, CoFeGd, CoFeDy), a perpendicular magnetic material having an L10 structure, a CoPt having a hexagonal close-packed (HCP) grid structure, and a perpendicular magnetic structure. The perpendicular magnetic material having an L10 structure may include at least one selected from FePt having an L10 structure, FePd having an L10 structure, CoPd having an L10 structure, and CoPt having an L10 structure. The perpendicular magnetic structure may include alternating and repeatedly stacked magnetic layers and non-magnetic layers. For example, the perpendicular magnetic structure may include at least one selected from (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, and (CoCr / Pd)n (where n is the number of stacked layers). The non-intrinsic perpendicular magnetization material may include a material having an intrinsic horizontal magnetization property or a perpendicular magnetization property caused by an external factor. For example, the non-intrinsic perpendicular magnetization material may have a perpendicular magnetization property due to the magnetic anisotropy caused by the junction between the tunnel barrier pattern TBP and the first magnetic pattern MP1 (or the second magnetic pattern MP2). The non-intrinsic perpendicular magnetization material may include, for example, CoFeB.

[0034] refer to Figure 4B As another example, the magnetization directions MD1 and MD2 of the first magnetic pattern MP1 and the second magnetic pattern MP2 may be parallel to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include a ferromagnetic material. The first magnetic pattern MP1 may also include an antiferromagnetic material for fixing the magnetization direction of the ferromagnetic material in the first magnetic pattern MP1.

[0035] Each of the first and second magnetic patterns MP1 and MP2 may include a Heusler alloy containing Co. The tunnel barrier pattern TBP may include at least one selected from a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium-zinc (MgZn) oxide layer, and a magnesium-boron (MgB) oxide layer.

[0036] Reference again Figure 2 and FIG. 3A to FIG. 3D , the covering dielectric layer 150 may be disposed on the second lower dielectric layer 130 on the cell region CR. The covering dielectric layer 150 may conformally cover or overlap the lateral surface (e.g., lateral surface) of each of the data storage patterns DS and the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR. When viewed in a top view, the covering dielectric layer 150 may surround the lateral surface of each of the data storage patterns DS. The covering dielectric layer 150 may conformally cover or overlap the lateral surfaces of the bottom electrode BE, the magnetic tunnel junction pattern MTJ, and the top electrode TE. When viewed in a top view, the covering dielectric layer 150 may surround the lateral surfaces of the bottom electrode BE, the magnetic tunnel junction pattern MTJ, and the top electrode TE. The covering dielectric layer 150 may include a nitride (e.g., silicon nitride).

[0037] The cell dielectric layer 160 may be disposed on the second lower dielectric layer 130 on the cell region CR, and may be located on the data storage pattern DS (e.g., may cover the data storage pattern DS). The cell dielectric layer 160 may fill the space between the data storage patterns DS. The cover dielectric layer 150 may be between the cell dielectric layer 160 and the lateral surface of each of the data storage patterns DS, and may extend between the cell dielectric layer 160 and the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR. The cell dielectric layer 160 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. For example, the cell dielectric layer 160 may include tetraethyl orthosilicate (TEOS) oxide.

[0038] The upper dielectric layer 170 may be disposed on the cell dielectric layer 160 on the cell region CR. The upper dielectric layer 170 may include a material different from that of the cell dielectric layer 160. The upper dielectric layer 170 may include silicon nitride (eg, SiCN).

[0039] A plurality of voids 160V may be disposed in the unit dielectric layer 160 and between the data storage patterns DS. The plurality of voids 160V may be disposed below the upper dielectric layer 170 and may be disposed on the second lower dielectric layer 130 and the cover dielectric layer 150. For example, the plurality of voids 160V may be located between the upper dielectric layer 170 and the second lower dielectric layer 130. Each of the plurality of voids 160V may vertically overlap with the recessed top surface 130RU of the second lower dielectric layer 130 in the third direction D3. As used herein, "element A overlaps element B in direction X" (or similar language) means that there is at least one line extending in direction X and intersecting elements A and B. The plurality of voids 160V may be spaced apart from each other in the first direction D1 and the second direction D2 on the second lower dielectric layer 130. The voids in the plurality of voids 160V may be disposed between data storage patterns in the plurality of data storage patterns DS spaced apart from each other in the first direction D1. At least one of the plurality of voids 160V may be disposed between pairs of data storage patterns spaced apart from each other in the first direction D1 in the data storage pattern DS (e.g., pairs of adjacent data storage patterns in the data storage pattern DS). Other of the plurality of voids 160V may be disposed between data storage patterns spaced apart from each other in the second direction D2 in the data storage pattern DS. At least one of the plurality of voids 160V may be disposed between another pair of data storage patterns spaced apart from each other in the second direction D2 in the data storage pattern DS (e.g., another pair of adjacent data storage patterns in the data storage pattern DS).

[0040] The peripheral dielectric layer 175 may be disposed on the second lower dielectric layer 130 on the peripheral region PR. The top surface 130U of the second lower dielectric layer 130 on the peripheral region PR may be located at a height lower than the height of the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR, and the peripheral dielectric layer 175 may be in contact with the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR. The peripheral dielectric layer 175 may have a top surface 175U located at the same height as the top surface 170U of the upper dielectric layer 170. The top surface 175U of the peripheral dielectric layer 175 may be coplanar with the top surface 170U of the upper dielectric layer 170.

[0041] The peripheral dielectric layer 175 may include a material different from that of the unit dielectric layer 160. The peripheral dielectric layer 175 may include a dielectric material whose dielectric constant (k) is less than that of the unit dielectric layer 160. The peripheral dielectric layer 175 may include a material different from that of the upper dielectric layer 170, and may include a dielectric material whose dielectric constant (k) is less than that of the upper dielectric layer 170. The unit dielectric layer 160 and the upper dielectric layer 170 may include a dielectric material whose dielectric constant (k) is greater than that of the peripheral dielectric layer 175. The peripheral dielectric layer 175 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. For example, the peripheral dielectric layer 175 may include a dielectric material whose dielectric constant (k) is equal to or less than 2.5 or 2.0, such as porous SiOC.

[0042] The upper conductive contact 180 may be disposed on the cell region CR. The upper conductive contact 180 may be correspondingly disposed on the data storage pattern DS, and may be spaced apart from each other in the first direction D1 and the second direction D2. The upper conductive contact 180 may be correspondingly connected to the data storage pattern DS. Each of the upper conductive contacts 180 may penetrate the upper dielectric layer 170, the upper portion of the cell dielectric layer 160, and the cover dielectric layer 150 (i.e., extend therein), and may be connected to the top electrode TE of the corresponding data storage pattern in the data storage pattern DS. The upper conductive contact 180 may contact the top electrode TE of the data storage pattern DS correspondingly. The upper dielectric layer 170 may expose the top surface 180U of the upper conductive contact 180. That is, the upper dielectric layer 170 may be absent or lacking on the top surface 180U of the upper conductive contact 180. Top surface 180U of upper conductive contact 180 may be located at the same height as top surface 170U of upper dielectric layer 170 and may be coplanar with top surface 170U of upper dielectric layer 170. Upper conductive contact 180 may include a conductive material such as metal (eg, copper).

[0043] The peripheral conductive line 182 may be disposed on the second lower dielectric layer 130 in the peripheral dielectric layer 175 and on the peripheral region PR. The peripheral dielectric layer 175 may be located on the peripheral conductive line 182 (e.g., may cover the peripheral conductive line). The peripheral conductive line 182 may have a top surface 182U that is exposed and not covered by the peripheral dielectric layer 175. That is, there may be no or lack of the peripheral dielectric layer 175 on the top surface 182U of the peripheral conductive line 182. The top surface 182U of the peripheral conductive line 182 may be substantially coplanar with the top surface 175U of the peripheral dielectric layer 175. The top surface 182U of the peripheral conductive line 182 may be located at the same height as the top surface 175U of the peripheral dielectric layer 175. The top surface 182U of the peripheral conductive line 182 may be located at the same height as the top surface 175U of the peripheral dielectric layer 175. The top surface 182U of the peripheral conductive line 182 may be located at the same height as the top surface 180U of the upper conductive contact 180 and the top surface 170U of the upper dielectric layer 170. Top surfaces 182U of peripheral conductive lines 182 may be coplanar with top surfaces 180U of upper conductive contacts 180 and top surface 170U of upper dielectric layer 170 .

[0044] Peripheral conductive contacts 184 may be disposed on the peripheral region PR and disposed below the peripheral conductive line 182. For example, the peripheral conductive contacts 184 may be located on the bottom surface of the peripheral conductive line 182. The peripheral conductive contacts 184 may be electrically connected to the peripheral conductive line 182. Each of the peripheral conductive contacts 184 may be in contact with a corresponding one of the peripheral conductive lines 182 without an interface. Each of the peripheral conductive contacts 184 and its corresponding peripheral conductive line 182 may be connected to form a single integral piece. Each of the peripheral conductive contacts 184 may penetrate the lower portion of the peripheral dielectric layer 175 (i.e., extend therein). Each of the peripheral conductive contacts 184 may penetrate the second lower dielectric layer 130 and the first lower dielectric layer 120 on the peripheral region PR (i.e., extend therein), and may be electrically connected to a corresponding one of the uppermost wiring lines 102. Each of the peripheral conductive lines 182 may be electrically connected to one terminal (eg, a source terminal, a drain terminal, or a gate terminal) of a corresponding peripheral transistor through a corresponding peripheral conductive contact 184 and a corresponding uppermost wiring line 102 .

[0045] The peripheral conductive line 182 and the peripheral conductive contact 184 may include a conductive material, such as a metal (eg, copper). The upper conductive contact 180, the peripheral conductive line 182, and the peripheral conductive contact 184 may include the same material.

[0046] The interlayer dielectric layer 190 may be disposed on the cell region CR and the peripheral region PR, and may be located on the top surface 170U of the upper dielectric layer 170, the top surface 180U of the upper conductive contact 180, the top surface 175U of the peripheral dielectric layer 175, and the top surface 182U of the peripheral conductive line 182 (e.g., may cover these top surfaces). The interlayer dielectric layer 190 may be located on the top surface 170U of the upper dielectric layer 170 (e.g., may cover the top surface), and may extend onto the top surface 180U of the upper conductive contact 180. The interlayer dielectric layer 190 may be located on the top surface 175U of the peripheral dielectric layer 175 (e.g., may cover the top surface), and may extend onto the top surface 182U of the peripheral conductive line 182. The interlayer dielectric layer 190 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0047] The upper via 195 may be disposed in the interlayer dielectric layer 190 on the cell region CR. The upper via 195 may be correspondingly disposed on the upper conductive contact 180 and may be spaced apart from each other in the first direction D1 and the second direction D2. The upper via 195 may be correspondingly connected to the upper conductive contact 180. The upper via 195 may penetrate the interlayer dielectric layer 190 (i.e., extend therein) and may be correspondingly connected to the upper conductive contact 180. The upper via 195 may correspondingly contact the top surface 180U of the upper conductive contact 180. The upper via 195 may include a conductive material, such as a metal (e.g., copper).

[0048] The upper conductive lines 200 may be disposed on the interlayer dielectric layer 190 on the cell region CR. The upper conductive lines 200 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. Each of the upper conductive lines 200 may have a linear shape that is elongated in the first direction D1. For example, each of the upper conductive lines 200 may extend longitudinally in the first direction D1. As used herein, the term “longitudinally” indicates the longest dimension. Each of the upper conductive lines 200 may be connected to a corresponding upper via in the upper vias 195 that is spaced apart from each other in the first direction D1, and may be electrically connected to a corresponding upper conductive contact in the upper conductive contact 180 that is spaced apart from each other in the first direction D1 through the corresponding upper via 195. Figure 1 The bit line BL may be composed of one of an upper conductive line 200, corresponding upper vias 195 spaced apart from each other in the first direction D1, and corresponding upper conductive contacts 180 spaced apart from each other in the first direction D1. The upper conductive line 200 may include a conductive material such as metal (eg, copper).

[0049] The upper conductive contacts 180 may be correspondingly disposed on the data storage patterns DS, and thus, the upper conductive contacts 180 may be horizontally (e.g., in the first direction D1 or the second direction D2) spaced apart from the plurality of voids 160V between the data storage patterns DS. Each of the plurality of voids 160V may be disposed between pairs of upper conductive contacts (e.g., pairs of adjacent upper conductive contacts in the upper conductive contacts 180) spaced apart from each other in the first direction D1 or the second direction D2 in the upper conductive contacts 180. Each of the plurality of voids 160V may not overlap with any of the upper conductive contacts 180 in the third direction D3. That is, each of the plurality of voids 160V may not overlap with the upper conductive contacts 180 in the third direction D3.

[0050] Among the plurality of voids 160V, the voids 160V spaced apart from each other in the first direction D1 may be disposed between the data storage patterns DS spaced apart from each other in the first direction D1 and between the upper conductive contacts 180 spaced apart from each other in the first direction D1 (see, for example, Figure 3A Each of the upper conductive lines 200 may have a linear shape elongated in the first direction D1, and may vertically overlap (eg, in the third direction D3) the gaps 160V spaced apart from each other in the first direction D1.

[0051] With the high integration of the semiconductor device including the data storage pattern DS, a plurality of voids 160V may be formed in the unit dielectric layer 160 between the data storage patterns DS. When a conductive line that penetrates the upper dielectric layer 170 and the upper portion of the unit dielectric layer 160 (i.e., extends therein) and is elongated in the first direction D1 is formed between the data storage patterns DS spaced apart from each other in the first direction D1, the conductive line may be connected to the data storage patterns DS spaced apart from each other in the first direction D1, and may vertically (e.g., in the third direction D3) overlap the voids 160V spaced apart from each other in the first direction D1. In this case, during the formation of the conductive line, the voids 160V may be filled with a conductive material, and thus a bridge fault (e.g., a bridging fault) may occur between the conductive lines adjacent to each other in the second direction D2.

[0052] According to the inventive concept, the upper conductive contacts 180 may be correspondingly disposed on the data storage pattern DS, and may be spaced apart from each other in the first direction D1 and the second direction D2. Therefore, the upper conductive contacts 180 may be spaced apart from the plurality of voids 160V horizontally (e.g., in the first direction D1 or the second direction D2), and each of the plurality of voids 160V may not overlap with any of the upper conductive contacts 180 in the third direction D3. The plurality of voids 160V may be disposed below the upper dielectric layer 170 between the upper conductive contacts 180, and may overlap vertically (e.g., in the third direction D3) with the upper dielectric layer 170 between the upper conductive contacts 180. In this case, during the formation of the upper conductive contacts 180, the plurality of voids 160V may be blocked by the upper dielectric layer 170, and as a result, may be prevented from being filled with a conductive material. Therefore, a bridge failure (e.g., no bridging failure) may not occur between the upper conductive contacts 180.

[0053] Therefore, according to embodiments of the inventive concept, a semiconductor device capable of easily achieving high integration and minimizing process defects may be provided.

[0054] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig.9A , Fig. 9B , Fig. 9C and Fig.9D A cross-sectional view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A Shown along Figure 2 A cross-sectional view taken along line AA'. Figure 5B , Figure 6B , Figure 7B , Figure 8B and Fig. 9B Shown along Figure 2 A cross-sectional view taken along line BB'. Figure 5C , Figure 6C , Figure 7C , Figure 8C and Fig. 9C Shown along Figure 2 A cross-sectional view taken along line CC'. Figure 5D , Fig.6D , Fig.7D , Fig.8D and Fig.9D Shown along Figure 2 For the sake of brevity of description, the reference Figure 1 , Figure 2 , FIG. 3A to FIG. 3D , Figure 4A and Figure 4B The discussion of the described semiconductor devices overlaps with redundant or repetitive descriptions.

[0055] refer to Figure 2 and FIG. 5A to FIG. 5D , a substrate 100 including a cell region CR and a peripheral region PR may be provided. Selecting elements (eg, see Figure 1 The selection element and the peripheral transistor may be formed on the substrate 100, and the wiring structures 102 and 104 may be formed on the selection element and the peripheral transistor. The wiring structures 102 and 104 may include a wiring line 102 spaced apart vertically (e.g., in the third direction D3) from the substrate 100, and may also include a wiring contact 104 connected to the wiring line 102. Each of the wiring lines 102 may be electrically connected to one terminal (e.g., a source terminal, a drain terminal, or a gate terminal) of a corresponding one of the selection element or the peripheral transistor through a corresponding one of the wiring contacts 104.

[0056] The wiring dielectric layer 110 may be formed on the substrate 100 and may be located on (eg, may cover) the wiring structures 102 and 104 . The wiring dielectric layer 110 may expose a top surface of an uppermost wiring line among the wiring lines 102 .

[0057] The first lower dielectric layer 120 may be formed on the wiring dielectric layer 110 and may cover or overlap the exposed top surface of the uppermost wiring line 102. The first lower dielectric layer 120 may be formed on the wiring dielectric layer 110 on the cell region CR and may extend onto the wiring dielectric layer 110 on the peripheral region PR.

[0058] The second lower dielectric layer 130 may be formed on the first lower dielectric layer 120. The second lower dielectric layer 130 may be formed on the first lower dielectric layer 120 on the cell region CR, and may extend onto the first lower dielectric layer 120 on the peripheral region PR.

[0059] The lower electrode contacts 140 may be formed in the second lower dielectric layer 130 on the cell region CR. Each of the lower electrode contacts 140 may penetrate (i.e., extend into) the first lower dielectric layer 120 and the second lower dielectric layer 130 on the cell region CR, and may be electrically connected to one of the uppermost wiring lines 102. The formation of the lower electrode contacts 140 may, for example, include: forming a lower contact hole penetrating (i.e., extending into) the first lower dielectric layer 120 and the second lower dielectric layer 130 on the cell region CR; forming a lower contact layer filling the lower contact hole on the second lower dielectric layer 130; and planarizing the lower contact layer until the top surface of the second lower dielectric layer 130 is exposed. In the planarization process, the lower electrode contacts 140 may be correspondingly partially formed in the lower contact holes.

[0060] The data storage pattern DS may be formed on the second lower dielectric layer 130 on the cell region CR. The data storage pattern DS may be correspondingly formed on the lower electrode contact 140 and electrically connected to the lower electrode contact 140.

[0061] Each of the data storage patterns DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked on the second lower dielectric layer 130. The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP between the first magnetic pattern MP1 and the second magnetic pattern MP2. The first magnetic pattern MP1 may be disposed between the bottom electrode BE and the tunnel barrier pattern TBP, and the second magnetic pattern MP2 may be disposed between the top electrode TE and the tunnel barrier pattern TBP. The formation of the data storage pattern DS may, for example, include: sequentially forming a bottom electrode layer and a magnetic tunnel junction layer on the second lower dielectric layer 130; forming a conductive mask pattern on the magnetic tunnel junction layer; and sequentially etching the magnetic tunnel junction layer and the bottom electrode layer using the conductive mask pattern as an etching mask. The magnetic tunnel junction layer may include a first magnetic layer, a tunnel barrier layer, and a second magnetic layer sequentially stacked on the bottom electrode layer. The magnetic tunnel junction layer and the bottom electrode layer may be formed by, for example, a sputtering process, a chemical vapor deposition process, or an atomic layer deposition process.

[0062] The magnetic tunnel junction layer and the bottom electrode layer may be etched to form a magnetic tunnel junction pattern MTJ and a bottom electrode BE, respectively. The etching of the magnetic tunnel junction layer may include etching the second magnetic layer, the tunnel barrier layer, and the first magnetic layer in sequence using the conductive mask pattern as an etching mask. The second magnetic layer, the tunnel barrier layer, and the first magnetic layer may be etched to form a second magnetic pattern MP2, a tunnel barrier pattern TBP, and a first magnetic pattern MP1. After the magnetic tunnel junction layer and the bottom electrode layer are etched, the conductive mask pattern may remain on the magnetic tunnel junction pattern MTJ, and the remaining portion of the conductive mask pattern may be defined as a top electrode TE.

[0063] An ion beam etching process using an ion beam may be used to perform an etching process for etching the magnetic tunnel junction layer and the bottom electrode layer. The ion beam may include inert ions. The etching process may cause the upper portion of the second lower dielectric layer 130 between the data storage patterns DS to be recessed. Therefore, the second lower dielectric layer 130 on the cell region CR may have a recessed top surface 130RU recessed toward the substrate 100. The recessed top surface 130RU of the second lower dielectric layer 130 may be located at a height lower than the height of the top surface 140U of the lower electrode contact 140. In addition, the etching process may cause the upper portion of the second lower dielectric layer 130 on the peripheral region PR to be recessed. The second lower dielectric layer 130 on the peripheral region PR may have a top surface 130U located at a height lower than the height of the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR.

[0064] The capping dielectric layer 150 may be formed on the second lower dielectric layer 130 on the cell region CR and may conformally cover or overlap the lateral surface of each of the data storage patterns DS. The capping dielectric layer 150 may conformally cover or overlap the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR and may extend onto the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR.

[0065] refer to Figure 2 and FIG. 6A to FIG. 6D , the cell dielectric layer 160 may be formed on the capping dielectric layer 150. The cell dielectric layer 160 may be formed on the capping dielectric layer 150 on the cell region CR so as to be located on the data storage pattern DS (e.g., covering the data storage pattern DS) and fill the space between the data storage patterns DS. The cell dielectric layer 160 may extend onto the capping dielectric layer 150 on the peripheral region PR. The cell dielectric layer 160 may be formed by using, for example, a high density plasma chemical vapor deposition (HDP CVD) process.

[0066] The increase in the integration of semiconductor devices may result in a decrease in the distance between the data storage patterns DS, and as a result, the cell dielectric layer 160 may not completely fill the space between the data storage patterns DS. Therefore, a plurality of voids 160V may be formed in the cell dielectric layer 160 between the data storage patterns DS and on the cell region CR. Each of the plurality of voids 160V may vertically overlap the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR along the third direction D3.

[0067] The upper dielectric layer 170 may be formed on the cell dielectric layer 160. The upper dielectric layer 170 may be formed on the cell dielectric layer 160 on the cell region CR and may extend onto the cell dielectric layer 160 on the peripheral region PR. A plurality of voids 160V may be provided under the upper dielectric layer 170 on the cell region CR.

[0068] refer to Figure 2 and 7A to 7D , a cell mask pattern CM may be formed on the upper dielectric layer 170 on the cell region CR. The cell mask pattern CM may expose the upper dielectric layer 170 on the peripheral region PR. The cell mask pattern CM may be, for example, a photoresist pattern.

[0069] The peripheral opening OP_P may be formed on the peripheral region PR, and may expose the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR. The formation of the peripheral opening OP_P may include performing an etching process using the cell mask pattern CM as an etching mask, the etching process removing the upper dielectric layer 170, the cell dielectric layer 160, and the capping dielectric layer 150 on the peripheral region PR. In the etching process, the upper dielectric layer 170, the cell dielectric layer 160, and the capping dielectric layer 150 on the peripheral region PR may be removed to expose the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR.

[0070] refer to Figure 2 and FIG. 8A to FIG. 8D , the unit mask pattern CM may be removed. The unit mask pattern CM may be removed by, for example, an ashing and / or a stripping process.

[0071] A peripheral dielectric layer 175 may be formed to fill the peripheral opening OP_P. The peripheral dielectric layer 175 may be in contact with the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR. The peripheral dielectric layer 175 may include a dielectric material whose dielectric constant is less than the dielectric constant of the unit dielectric layer 160 and the dielectric constant of the upper dielectric layer 170. The formation of the peripheral dielectric layer 175 may, for example, include: forming a dielectric layer to fill the peripheral opening OP_P; and, planarizing the dielectric layer until the top surface of the upper dielectric layer 170 is exposed. The dielectric layer may be formed by using, for example, a chemical vapor deposition process. The planarization process may be performed by using, for example, at least one selected from an etch-back process and a chemical mechanical polishing process.

[0072] refer to Figure 2 and 9A to 9D, the upper conductive contact 180 may be formed on the cell region CR. The upper conductive contact 180 may be correspondingly formed on the data storage pattern DS, and may be spaced apart from each other in the first direction D1 and the second direction D2. The formation of the upper conductive contact 180 may include: correspondingly forming an upper contact hole 180H on the data storage pattern DS; forming a conductive layer filling the upper contact hole 180H on the upper dielectric layer 170; and planarizing the conductive layer until the top surface 170U of the upper dielectric layer 170 is exposed. The upper contact holes 180H may be spaced apart from each other in the first direction D1 and the second direction D2 on the data storage pattern DS. The upper contact hole 180H may penetrate the upper dielectric layer 170, the upper portion of the cell dielectric layer 160, and the capping dielectric layer 150 (i.e., extend therein), and may correspondingly expose the top electrode TE of the data storage pattern DS.

[0073] The peripheral conductive line 182 and the peripheral conductive contact 184 may be formed in the peripheral dielectric layer 175 on the peripheral region PR. The formation of the peripheral conductive line 182 and the peripheral conductive contact 184 may include: forming a peripheral trench 182T penetrating the upper portion of the peripheral dielectric layer 175 (i.e., extending therein); forming a peripheral hole 184H extending from the bottom surface of the peripheral trench 182T toward the substrate 100; forming a conductive layer filling the peripheral trench 182T and the peripheral hole 184H on the peripheral dielectric layer 175; and planarizing the conductive layer until the top surface 175U of the peripheral dielectric layer 175 is exposed. Each of the peripheral holes 184H may penetrate the lower portion of the peripheral dielectric layer 175 on the peripheral region PR, the second lower dielectric layer 130, and the first lower dielectric layer 120 (i.e., extending therein), thereby exposing the top surface of the corresponding uppermost wiring line in the uppermost wiring line 102.

[0074] According to some embodiments, upper conductive contact 180, peripheral conductive line 182, and peripheral conductive contact 184 may be formed simultaneously with each other. For example, the formation of upper conductive contact 180, peripheral conductive line 182, and peripheral conductive contact 184 may include: forming a conductive layer on upper dielectric layer 170 and peripheral dielectric layer 175 to fill upper contact hole 180H, peripheral trench 182T, and peripheral hole 184H; and, planarizing the conductive layer until top surface 170U of upper dielectric layer 170 is exposed and top surface 175U of peripheral dielectric layer 175 is exposed.

[0075] Reference again Figure 2 and FIG. 3A to FIG. 3D , an interlayer dielectric layer 190 may be formed on the cell region CR and the peripheral region PR, and may be located on a top surface 170U of the upper dielectric layer 170, a top surface 180U of the upper conductive contact 180, a top surface 175U of the peripheral dielectric layer 175, and a top surface 182U of the peripheral conductive line 182 (e.g., may cover these top surfaces).

[0076] The upper via 195 may be formed in the interlayer dielectric layer 190 on the cell region CR. The upper via 195 may be formed on the upper conductive contact 180 correspondingly and may be spaced apart from each other in the first direction D1 and the second direction D2. The upper via 195 may penetrate the interlayer dielectric layer 190 (i.e., extend therein) and may be connected to the upper conductive contact 180 correspondingly.

[0077] The upper conductive lines 200 may be formed on the interlayer dielectric layer 190 on the cell region CR. The upper conductive lines 200 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. Each of the upper conductive lines 200 may have a linear shape elongated in the first direction D1. Each of the upper conductive lines 200 may be connected to a corresponding upper via 195 spaced apart from each other in the first direction D1, and may be electrically connected to a corresponding upper conductive contact 180 spaced apart from each other in the first direction D1 through the corresponding upper via 195.

[0078] Fig.10 A top view illustrating a semiconductor device according to some embodiments of the inventive concept is shown. Fig.11A , Fig. 11B and Fig. 11C Shown along Fig.10 A cross-sectional view taken along the lines A-A', B-B' and CC'. Fig.10 The cross-sectional view taken along the line D-D' can be compared with Figure 3D For the sake of brevity, the cross-sectional view of the reference will be briefly mentioned or omitted. Figure 1 , Figure 2 , FIG. 3A to FIG. 3D , Figure 4A and Figure 4B The discussion of the described semiconductor devices overlaps with redundant or repetitive descriptions.

[0079] refer to Fig.10 , FIG. 11A to FIG. 11C and Figure 3D , the data storage patterns DS may be disposed on the second lower dielectric layer 130 on the cell region CR and may be spaced apart from each other in the first direction D1 and the second direction D2. Among the data storage patterns DS, the data storage patterns DS in the first column may be spaced apart from each other in the first direction D1, and the data storage patterns DS in the second column may be spaced apart from each other in the first direction D1 (for example, see Fig.10 ). For example, in Fig.10In the embodiment of the present invention, the column direction may be a first direction D1, and the first column and the second column may be adjacent to each other in the second direction D2. The data storage pattern DS in the second column may be adjacent to the data storage pattern DS in the first column in the second direction D2, and may be offset from the data storage pattern DS in the first column in the first direction D1. In other words, the data storage pattern DS in the second column may not be aligned with the data storage pattern DS in the first column along the second direction D2. For example, the data storage pattern DS in the second column may be spaced apart from the data storage pattern DS in the first column in the first direction D1.

[0080] The cell dielectric layer 160 may be disposed on the second lower dielectric layer 130 on the cell region CR and may be located on the data storage pattern DS (e.g., may cover the data storage pattern DS). The cell dielectric layer 160 may fill the space between the data storage patterns DS. The upper dielectric layer 170 may be disposed on the cell dielectric layer 160 on the cell region CR.

[0081] A plurality of voids 160V may be disposed in the unit dielectric layer 160 and between the data storage patterns DS. The plurality of voids 160V may be spaced apart from each other in the first direction D1 and the second direction D2 on the second lower dielectric layer 130. The plurality of voids 160V may be disposed below the upper dielectric layer 170 and may be disposed on the second lower dielectric layer 130 and the cover dielectric layer 150. For example, the plurality of voids 160V may be located between the upper dielectric layer 170 and the second lower dielectric layer 130. Each of the plurality of voids 160V may vertically overlap with the recessed top surface 130RU of the second lower dielectric layer 130 in the third direction D3. The voids in the plurality of voids 160V may be spaced apart from each other in the first direction D1 between the data storage patterns DS in the first column and the data storage patterns DS in the second column. For example, at least one of the plurality of voids 160V may be located between one of the data storage patterns DS in the first column and one of the data storage patterns DS in the second column in a direction inclined relative to the first and second directions D1 and D2 (eg, a diagonal direction).

[0082] The upper conductive contacts 180 may be correspondingly disposed on the data storage pattern DS and may be spaced apart from each other in the first direction D1 and the second direction D2. Among the upper conductive contacts 180, the upper conductive contacts 180 in the first column may be spaced apart from each other in the first direction D1, and the upper conductive contacts 180 in the second column may be spaced apart from each other in the first direction D1 (for example, see Fig.10). The upper conductive contacts 180 in the second column may be adjacent to the upper conductive contacts 180 in the first column in the second direction D2, and may be offset from the upper conductive contacts 180 in the first column in the first direction D1. In other words, the upper conductive contacts 180 in the second column may not be aligned with the upper conductive contacts 180 in the first column along the second direction D2. For example, the upper conductive contacts 180 in the second column may be spaced apart from the upper conductive contacts 180 in the first column in the first direction D1. The upper conductive contacts 180 in the first column may be correspondingly disposed on and connected to the data storage patterns DS in the first column. The upper conductive contacts 180 in the second column may be correspondingly disposed on and connected to the data storage patterns DS in the second column.

[0083] The upper conductive contact 180 may be horizontally spaced apart (e.g., in the first direction D1 or the second direction D2) from the plurality of voids 160V between the data storage patterns DS. The voids in the plurality of voids 160V may be spaced apart from each other in the first direction D1 between the upper conductive contacts 180 in the first column and the upper conductive contacts 180 in the second column. Each of the plurality of voids 160V may not overlap with any of the upper conductive contacts 180 in the third direction D3. That is, each of the plurality of voids 160V may not overlap with the upper conductive contact 180 in the third direction D3.

[0084] The interlayer dielectric layer 190 may be disposed on the cell region CR and the peripheral region PR, and may be located on (e.g., may cover) the top surface 170U of the upper dielectric layer 170, the top surface 180U of the upper conductive contact 180, the top surface 175U of the peripheral dielectric layer 175, and the top surface 182U of the peripheral conductive line 182.

[0085] The upper vias 195 may be disposed in the interlayer dielectric layer 190 on the cell region CR. The upper vias 195 may be disposed on the upper conductive contacts 180 correspondingly and may be spaced apart from each other in the first direction D1 and the second direction D2. The upper vias 195 may be connected to the upper conductive contacts 180 correspondingly.

[0086] The upper conductive lines 200 may be disposed on the interlayer dielectric layer 190 on the cell region CR. The upper conductive lines 200 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. Each of the upper conductive lines 200 may be connected to a corresponding upper via 195 spaced apart from each other in the first direction D1. One of the upper conductive lines 200 may be electrically connected to the upper conductive contacts 180 in the first column through the corresponding upper via 195. Another of the upper conductive lines 200 may be electrically connected to the upper conductive contacts 180 in the second column through the corresponding upper via 195.

[0087] In addition to the above, the semiconductor device can be used with reference Figure 1 , Figure 2 , FIG. 3A to FIG. 3D , Figure 4A and Figure 4B The semiconductor devices described are basically the same.

[0088] According to the inventive concept, the increase in the integration of semiconductor devices can lead to a reduction in the distance between data storage patterns, and as a result, multiple gaps can be formed in the unit dielectric layer between the data storage patterns. The upper conductive contacts can be correspondingly arranged on the data storage patterns and can be spaced apart from each other in the first direction and the second direction. The upper conductive contacts can be horizontally (e.g., in the first direction or the second direction) spaced apart from the multiple gaps between the data storage patterns. Multiple gaps can be arranged below the upper dielectric layer and can vertically overlap with the upper dielectric layer between the upper conductive contacts. In this case, during the formation of the upper conductive contacts, the multiple gaps can be blocked by the upper dielectric layer, and as a result, can be prevented from being filled with conductive material. Therefore, bridge failures may not occur between the upper conductive contacts.

[0089] In summary, a semiconductor device capable of easily achieving high integration and minimizing process defects can be provided.

[0090] As used herein, the terms "includes," "comprising," "having," and any other variations thereof specify the presence of stated features, steps, operations, elements, parts, and / or groups, but do not preclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or groups thereof.

[0091] The foregoing description provides example embodiments for explaining the inventive concept. Therefore, the inventive concept is not limited to the embodiments described above, and those skilled in the art will appreciate that changes in form and detail may be made therein without departing from the scope of the inventive concept.

Claims

1. A semiconductor device, the semiconductor device include: a lower dielectric layer, the lower dielectric layer being located on the substrate; a plurality of data storage patterns located on the lower dielectric layer and spaced apart from each other in a first direction and a second direction parallel to a top surface of the substrate, wherein the first direction and the second direction intersect each other; a unit dielectric layer, the unit dielectric layer being located on the lower dielectric layer and on the plurality of data storage patterns; a plurality of voids located in the cell dielectric layer and between data storage patterns among the plurality of data storage patterns; a plurality of upper conductive contacts, the plurality of upper conductive contacts being respectively located on the plurality of data storage patterns and spaced apart from each other in the first direction and the second direction; and a plurality of upper conductive lines, the plurality of upper conductive lines being respectively located on the plurality of upper conductive contacts and spaced apart from each other in the second direction, wherein the plurality of upper conductive lines extend in the first direction; wherein each of the plurality of upper conductive lines is electrically connected to a corresponding upper conductive contact of the plurality of upper conductive contacts, and Wherein, the corresponding upper conductive contacts among the plurality of upper conductive contacts are spaced apart from each other in the first direction.

2. The semiconductor device according to claim 1, further comprising an upper dielectric layer located on the cell dielectric layer, in, The plurality of voids are located between the upper dielectric layer and the lower dielectric layer.

3. The semiconductor device according to claim 2, in, The plurality of upper conductive contacts extend into upper portions of the upper dielectric layer and the cell dielectric layer and are electrically connected to the plurality of data storage patterns, respectively.

4. The semiconductor device according to claim 3, in, Each of the plurality of data storage patterns includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode stacked along a third direction on the lower dielectric layer, wherein the third direction is perpendicular to the top surface of the substrate, wherein the top electrode is located between the magnetic tunnel junction pattern and each of the plurality of upper conductive contacts, and Wherein, each of the plurality of upper conductive contacts is in contact with the top electrode.

5. The semiconductor device according to claim 3, in, The upper dielectric layer is absent from top surfaces of the plurality of upper conductive contacts.

6. The semiconductor device according to claim 5, further comprising an interlayer dielectric layer located on the upper dielectric layer, in, The interlayer dielectric layer overlaps a top surface of the upper dielectric layer and extends onto the top surface of the plurality of upper conductive contacts.

7. The semiconductor device according to claim 6, further comprising a plurality of upper vias, the plurality of upper vias being located in the interlayer dielectric layer and respectively located on the plurality of upper conductive contacts, in, The plurality of upper vias extend into the interlayer dielectric layer and are electrically connected to the plurality of upper conductive contacts, respectively, wherein the plurality of upper conductive lines are located on the interlayer dielectric layer and are electrically connected to corresponding upper conductive contacts among the plurality of upper conductive contacts through corresponding upper vias among the plurality of upper vias, and Wherein, the corresponding upper passages among the plurality of upper passages are spaced apart from each other in the first direction.

8. The semiconductor device according to claim 1, in, the lower dielectric layer having a recessed top surface recessed toward the substrate between data storage patterns among the plurality of data storage patterns, wherein each of the plurality of voids overlaps the recessed top surface of the lower dielectric layer in a third direction, and Wherein, the third direction is perpendicular to the top surface of the substrate.

9. The semiconductor device according to claim 8, further comprising a plurality of lower electrode contacts located in the lower dielectric layer and respectively located on bottom surfaces of the plurality of data storage patterns, in, The plurality of lower electrode contacts extend into the lower dielectric layer and are electrically connected to the plurality of data storage patterns, respectively, and The height of the recessed top surface of the lower dielectric layer in the third direction is lower than the height of the top surfaces of the plurality of lower electrode contacts in the third direction, and the top surface of the substrate provides a reference plane.

10. The semiconductor device according to claim 1, in, The substrate includes a cell region and a peripheral region, wherein the lower dielectric layer is located on the cell region and extends onto the peripheral region, wherein the plurality of data storage patterns, the cell dielectric layer, the plurality of gaps, the upper conductive contacts, and the plurality of upper conductive lines are located on the cell region, wherein a first portion of the lower dielectric layer on the cell region has a concave top surface that is concave toward the substrate between data storage patterns among the plurality of data storage patterns, wherein a height of a top surface of a second portion of the lower dielectric layer on the peripheral region in a third direction is lower than a height of the recessed top surface of the first portion of the lower dielectric layer in the third direction, wherein the top surface of the substrate provides a reference plane, and Wherein, the third direction is perpendicular to the top surface of the substrate.

11. The semiconductor device according to claim 10, further comprising a peripheral dielectric layer located on the lower dielectric layer and on the peripheral region, in, The unit dielectric layer includes a dielectric material having a dielectric constant greater than a dielectric constant of the peripheral dielectric layer.

12. A semiconductor device, the semiconductor device include: a lower dielectric layer, the lower dielectric layer being located on the substrate; a plurality of data storage patterns located on the lower dielectric layer and spaced apart from each other in a first direction parallel to a top surface of the substrate; a unit dielectric layer, the unit dielectric layer being located on the lower dielectric layer and on the plurality of data storage patterns; a plurality of voids located in the cell dielectric layer and between data storage patterns among the plurality of data storage patterns; a plurality of upper conductive contacts, the plurality of upper conductive contacts being respectively located on the plurality of data storage patterns and spaced apart from each other in the first direction; as well as an upper conductive line, the upper conductive line being located on the plurality of upper conductive contacts and extending in the first direction, wherein the plurality of upper conductive contacts extend into the upper portion of the cell dielectric layer and are electrically connected to the plurality of data storage patterns, respectively, and Wherein, the upper conductive line is electrically connected to the plurality of upper conductive contacts.

13. The semiconductor device according to claim 12, further comprising an upper dielectric layer located on the cell dielectric layer, in, The plurality of voids are located between the upper dielectric layer and the lower dielectric layer.

14. The semiconductor device according to claim 13, in, The plurality of upper conductive contacts extend into the upper portions of the upper dielectric layer and the cell dielectric layer and are electrically connected to the plurality of data storage patterns, respectively.

15. The semiconductor device according to claim 14, in, Each of the plurality of data storage patterns comprises: Magnetic tunnel junction patterns; and a top electrode located between the magnetic tunnel junction pattern and each of the plurality of upper conductive contacts, Wherein, each of the plurality of upper conductive contacts is in contact with the top electrode.

16. The semiconductor device according to claim 14, further comprising a plurality of lower electrode contacts located in the lower dielectric layer and respectively located on bottom surfaces of the plurality of data storage patterns, in, The plurality of lower electrode contacts extend into the lower dielectric layer and are electrically connected to the plurality of data storage patterns, respectively. wherein the lower dielectric layer has a concave top surface that is concave toward the substrate between data storage patterns among the plurality of data storage patterns, wherein the height of the recessed top surface of the lower dielectric layer in the second direction is lower than the height of the top surfaces of the plurality of lower electrode contacts in the second direction, wherein the top surface of the substrate provides a reference plane, and Wherein, the second direction is perpendicular to the top surface of the substrate.

17. The semiconductor device according to claim 16, in, Each of the plurality of voids overlaps the recessed top surface of the lower dielectric layer in the second direction.

18. The semiconductor device according to claim 12, in, The substrate includes a cell region and a peripheral region, wherein the lower dielectric layer is located on the cell region and extends onto the peripheral region, wherein the plurality of data storage patterns, the cell dielectric layer, the plurality of gaps, the plurality of upper conductive contacts, and the upper conductive line are located on the lower dielectric layer and on the cell region, The semiconductor device further comprises a peripheral dielectric layer, the peripheral dielectric layer being located on the lower dielectric layer and on the peripheral region, and The unit dielectric layer includes a dielectric material having a dielectric constant greater than a dielectric constant of the peripheral dielectric layer.

19. The semiconductor device according to claim 18, in, A first portion of the lower dielectric layer on the cell region has a recessed top surface recessed toward the substrate between data storage patterns among the plurality of data storage patterns, wherein a height of a top surface of a second portion of the lower dielectric layer on the peripheral region in a second direction is lower than a height of a top surface of the recess of the first portion of the lower dielectric layer in the second direction, wherein the top surface of the substrate provides a reference plane, wherein the second direction is perpendicular to the top surface of the substrate, and Wherein, the peripheral dielectric layer contacts the top surface of the second portion of the lower dielectric layer.

20. A semiconductor device, the semiconductor device include: a lower dielectric layer, the lower dielectric layer being located on the substrate; a plurality of data storage patterns located on the lower dielectric layer and spaced apart from each other in a first direction parallel to a top surface of the substrate; a unit dielectric layer, the unit dielectric layer being located on the lower dielectric layer and on the plurality of data storage patterns; a plurality of voids, the plurality of voids being located in the unit dielectric layer; a plurality of upper conductive contacts, the plurality of upper conductive contacts being respectively located on the plurality of data storage patterns and spaced apart from each other in the first direction; as well as an upper conductive line, the upper conductive line being located on the plurality of upper conductive contacts and extending in the first direction, wherein the upper conductive line is electrically connected to the plurality of upper conductive contacts, and Wherein, the plurality of voids do not overlap with the upper conductive contact in a second direction perpendicular to the top surface of the substrate.

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