Method and circuitry for efficiently managing bureau branch history registers

Abstract

Methods and circuitry for efficiently managing bureau branch history registers are described. An example processor includes a pipeline including a plurality of stages, and a bit vector associated with each of the in-flight branches associated with the pipeline. The processor includes a recovery counter for tracking the number of bits that need to be recovered before the local branch history register is valid to participate in branch prediction. The processor includes branch predictor circuitry configured to set bits in a corresponding bit vector indicating an update of the local branch history register in response to the update of the local branch history register by the branch. The branch predictor circuitry is configured to, upon refresh, determine a value indicative of a degree of recovery required for each local branch history register affected by the refresh, and set a corresponding recovery counter to the value indicative of the degree of recovery required.

Description

Background Art

[0001] A multithreaded processor can fetch instructions belonging to a thread and execute them. When executing instructions for a thread, the processor can execute instructions that reference registers or memory locations. Due to the delays associated with accessing the referenced memory location, the processor may have to wait until the referenced memory location is accessed. Similarly, if an instruction requires multiple cycles to execute, subsequent instructions that depend on it will have to wait. In order to maintain efficiency, the processor can fetch instructions from different threads and start executing them. In this way, the processor can execute instructions more efficiently. This type of parallelism can be called thread-level parallelism. Another way to improve processor performance is to use instruction-level parallelism.

[0002] Speculative instruction fetching provides the instructions needed to exploit instruction-level parallelism of a program. The successful speculation of which instruction to fetch next may depend on the branch predictor's analysis of the program history. Such predictions may turn out to be inaccurate, and the processor may have to recover from mispredicted branches, including having to discard the results of incorrectly predicted instruction dependencies and re-execute instructions in the correct order. Recovery from mispredicted branches may be suboptimal. Summary of the invention

[0003] In one example, the present disclosure relates to a processor including a pipeline including a plurality of stages. The processor may further include a bit vector associated with each in-flight branch associated with the pipeline, wherein each bit vector has a bit corresponding to each local branch history register associated with the corresponding in-flight branch. The processor may further include a restore counter associated with each local branch history register for tracking the number of bits that need to be restored before the local branch history register is valid to participate in branch prediction.

[0004] The processor may also include a branch predictor circuit system configured to: in response to an update of a local branch history register by a branch, set a bit in a corresponding bit vector indicating the update of the local branch history register by the branch. The branch predictor circuit system may also be configured to: upon a refresh, determine a value indicating a desired degree of recovery for each local history register affected by the refresh, and set a corresponding recovery counter to a value indicating the desired degree of recovery.

[0005] In another example, the present disclosure is directed to a processor including a pipeline including a plurality of stages. The processor may further include a bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has a bit corresponding to each local branch history register associated with the corresponding in-flight branch. The processor may further include a restore counter associated with each local branch history register for tracking the number of bits that need to be restored before the local branch history register is valid to participate in branch prediction.

[0006] The processor may also include a branch predictor circuit system configured to: in response to the update of the local branch history register by the branch, set a bit in the corresponding bit vector indicating the update of the local branch history register by the branch. The branch predictor circuit system may also be configured to: when refreshing, identify all local branch history registers that need to be restored by performing a logical or operation on the bit vectors corresponding to the mispredicted branch and all branches younger than the mispredicted branch. The branch predictor circuit system may also be configured to: discard all bits of all identified local branch history registers that need to be restored, and set the value of each corresponding restore counter of all identified local branch history registers that need to be restored to the maximum value for the restore counter.

[0007] In yet another example, the present disclosure relates to a processor including a pipeline including a plurality of stages. The processor may further include a bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has a bit corresponding to each local branch history register associated with the corresponding in-flight branch. The processor may further include a restore counter associated with each local branch history register for tracking the number of bits that need to be restored before the local branch history register is valid to participate in branch prediction.

[0008] The processor may also include a branch predictor circuit system that is configured to, in response to an update of a local branch history register by a corresponding branch: (1) set a bit in a corresponding bit vector indicating an update of the local branch history register by the corresponding branch, and (2) set a bit in each of the bit vectors corresponding to all in-flight branches that are older than the corresponding branch. The branch predictor circuit system may also be configured to, upon refresh, identify all local branch history registers that need to be restored based on the bit vector corresponding to the mispredicted branch. The branch predictor circuit system may also be configured to discard all bits of all identified local branch history registers that need to be restored, and set the value of each corresponding restore counter of all identified local branch history registers that need to be restored to a maximum value for the restore counter.

[0009] This summary is provided to introduce selected concepts in a simplified form, which are further described in the detailed implementation details below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure is illustrated by way of example and not limitation in the accompanying drawings, in which like references indicate similar elements. Elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0011] Figure 1 is a schematic diagram of a processor including a branch predictor having a local branch history table and associated circuitry for efficiently managing the local branch history register according to one example;

[0012] FIG. 2A to FIG. 2D shows the training and use of a local branch history register associated with a single branch according to one example;

[0013] Figure 3 is a block diagram of a local branch history register and associated circuitry for identifying registers affected by a refresh according to one example;

[0014] Figure 4 is a block diagram of a local branch history register and associated circuitry for tracking the validity of registers participating in branch prediction according to one example;

[0015] Figure 5 An example of a first recovery method is provided that preserves the stage of a local branch history register to allow for faster recovery;

[0016] Figure 6 providing an example of a first implementation of a second recovery method;

[0017] Figure 7 providing an example of a second implementation of a second recovery method;

[0018] Figure 8 is based on an example for efficient management Figure 1 A flowchart of a method for providing a local branch history register for a processor in;

[0019] Fig. 9 is based on an example for efficient management Figure 1 A flowchart of another method for providing a local branch history register for a processor in; and

[0020] Fig.10 is based on an example for efficient management Figure 1A flowchart of another method for a local branch history register of a processor in FIG. DETAILED DESCRIPTION

[0021] The examples described in the present disclosure relate to methods and circuit systems for efficiently managing local branch history registers. As previously described, speculative instruction fetching provides instructions required to obtain instruction-level parallelism of a program. The successful speculation of the instruction to be fetched next may depend on the analysis of the program history by the branch predictor. Such predictions may turn out to be inaccurate, resulting in the processor having to abandon the results of incorrectly predicted instruction dependencies and re-execute instructions in the correct order. In a multi-threaded processor, many threads being executed in parallel may need to re-execute instructions based on incorrect predictions.

[0022] Despite the risk of misprediction, branch prediction is a performance-enhancing microarchitectural feature used in the front end of many high-performance processors. When encountering a branch instruction (e.g., an instruction that changes program control flow from sequential to non-sequential), the processor can pause until the branch is executed to provide the next fetch program counter (PC), or alternatively, the processor can use hardware that can predict the outcome of the branch in advance (before the branch is taken) and then use the predicted outcome to drive instruction fetch. This hardware is often called a branch predictor (BP).

[0023] The branch predictor can use program history to accurately predict branch results. Then, before the branch is actually executed, the prediction made by the branch predictor is used to guide the instruction acquisition unit. The branch predictor can be associated with the program history by tracking information about the previously executed branches. The program history can be captured using a history register. The history register can be a local history register (e.g., a history register by branch) or a global history register (e.g., a history register based on the results of the most recent X branches). In order to enhance the prediction, the state of the history register can be speculatively updated (using the predicted branch results) when predicting, so that the next prediction observes the history of all previous branches (e.g., its prediction uses a consistent but speculative history state). Because the state is speculatively updated, in the case of misprediction, all instructions younger than the mispredicted branch need to be refreshed, and the speculatively updated history register needs to be rolled back. This can be achieved by checkpointing the information before speculatively updating the history register.

[0024] The use of local history can significantly improve the accuracy of branch prediction. However, because the branch predictor may have several local history registers (e.g., 256 registers or even 512 registers), the recovery process from mis-speculation is complex and slow. A recovery implementation may need to traverse the list of refreshed branches to reverse the historical updates made to the corresponding history registers. This process (referred to as a "slow and iterative" recovery process) may require any number of cycles, depending on the number of branches refreshed. Another recovery implementation can invalidate all local history registers at refresh time, and then allow the local history registers to be refilled over time. Although this recovery process (referred to as the "invalidate all" recovery process) can result in faster recovery, the loss of all local program histories can seriously affect the accuracy of the branch predictor. In the present disclosure, techniques and structures that allow efficient management of local branch history registers are described.

[0025] Figure 1 1 is a schematic diagram of a processor 100 including a branch predictor 150 for efficiently managing a local branch history register according to an example. The processor 100 may be implemented as part of an integrated circuit. The processor 100 may include a pipeline 110 for processing instructions. The pipeline 110 may include multiple stages for processing instructions in a pipeline manner. In this example, the pipeline 110 may include stage 0 112, stage 1 114, stage 2 116, and stage N 118, where N is a positive integer. In this example, the branch predictor 150 may be included in stage 0 112. The branch predictor 150 may be coupled to certain other stages of the pipeline 110 according to the specific architecture of the processor. In this example, stage 1114 may be implemented as an instruction cache. Stage 0 112 including the branch predictor 150 may be configured as an acquisition stage. The branch predictor 150 may include hardware capable of predicting branch results in advance, and then using the predicted results to drive the acquisition of instructions. Stage 2 116 may be implemented as a decoder configured to decode the next instruction fetched by stage 0 112. Stage N 118 may be implemented as an execution stage for executing instructions.

[0026] Continue to refer Figure 1In this example, the branch predictor 150 may include a local branch history table 152 and a circuit system 154 for efficiently managing local branch history registers. The circuit system 154 may be implemented using digital logic. As an example, the circuit system 154 may include various types of logic gates, registers, counters, multiplexers, finite state machines, combinational logic, flip-flops, or other digital logic circuits for implementing various tasks for branch prediction. The branch predictor 150 may use program history to accurately predict branch results. The predictions made by the branch predictor 150 may then be used to guide the instruction fetch process. The branch predictor 150 may be associated with the program history by tracking information about previously executed branches. The program history may be captured using a history register. The history register may be a local history register (e.g., a history register stored by branch as part of the local branch history table 152) or a global history register (e.g., a history register based on the results of the most recent X branches). Although Figure 1 A number of components of processor 100 are shown arranged in a certain manner, but a greater or lesser number of components may be arranged differently. As an example, pipeline 110 of processor 100 may include other stages, including stages for implementing micro-op deformation logic blocks, renaming / allocation logic blocks, instruction schedulers, and register files.

[0027] FIG. 2A to FIG. 2D FIG. 1 shows the training and use of a local branch history register associated with a single branch (branch_A) according to an example. This example focuses on a single branch and its associated local branch history register. In this example, the local branch history register may include eight bits of history associated with a single branch (branch_A). Before making a prediction about branch_A, the branch predictor (e.g., Figure 1 The branch predictor 150 of FIG. 1 may access the contents 202 of the local branch history register associated with branch_A. Assuming that the predicted result is that the branch is taken (indicated by a logical value of 1), the contents 202 of the local branch history register may be updated to contents 204 (e.g., by shifting the bits in the register left and inserting a logical 1 as the least significant bit, such as Figure 1 The update may be performed shortly after the prediction and before the instruction passes through the rest of the processor pipeline (e.g., Figure 1 pipeline 110 of processor 100).

[0028] Figure 2B 1 shows the change in the contents of the local history register in response to the arrival of another instance of branch_A. Before making a prediction about the second instance of branch_A, the branch predictor (e.g., Figure 1The branch predictor 150 of FIG. 150 may access the contents 212 of the local branch history register associated with branch_A. Assuming the prediction result is that the branch is taken (indicated by a logical value of 1), the contents 212 of the local branch history register may be updated to contents 214 (e.g., by shifting the bits in the register left and inserting a logical 1 as the least significant bit, such as Figure 1 As before, the update can be performed shortly after the prediction and before the instruction passes through the rest of the processor pipeline (e.g., Figure 1 pipeline 110 of processor 100).

[0029] Figure 2C 1 shows the change in the local history register contents in response to the arrival of yet another instance of branch_A. Before making a prediction about the third instance of branch_A, the branch predictor (e.g., Figure 1 The branch predictor 150 of FIG. 150 may access the contents 222 of the local branch history register associated with branch_A. Assuming that the prediction result is that the branch is not taken (indicated by a logical value of 0), the contents 222 of the local branch history register may be updated to contents 224 (e.g., by shifting the bits in the register to the left and inserting a logical 0 as the least significant bit, such as Figure 1 As before, the update can be performed shortly after the prediction and before the instruction passes through the rest of the processor pipeline (e.g., Figure 1 The pipeline 110 of the processor 100).

[0030] Figure 2D 1 shows the change in the local history register contents in response to the arrival of yet another instance of branch_A. Before making a prediction about the fourth instance of branch_A, the branch predictor (e.g., Figure 1 The branch predictor 150 of FIG. 150 may access the contents 232 of the local branch history register associated with branch_A. Assuming that the prediction result is that the branch is not taken (indicated by a logical value of 0), the contents 232 of the local branch history register may be updated to contents 234 (e.g., by shifting the bits in the register to the left and inserting a logical 0 as the least significant bit, such as Figure 1 As before, the update can be performed shortly after the prediction and before the instruction passes through the rest of the processor pipeline (e.g., Figure 1 pipeline 110 of processor 100).

[0031] Figure 331 is a block diagram of a local branch history register (LBHR) and associated circuitry for identifying registers affected by a refresh according to an example. The local branch history table 310 may include local branch history registers (one register for each in-flight branch). Assuming there are N such in-flight branches, the local branch history table 310 may include N local branch history registers (e.g., LBHR1 312, LBHR2 314, LBHR3 316, LBHR4 318, and LBHRN 320). In this example, the associated circuitry for identifying registers affected by a refresh may include a branch bit vector 330. As used in this disclosure, the term "bit vector" means any data structure implemented in hardware for storing bits. Hardware structures, such as registers, may be used to implement a bit vector. In this example, each in-flight branch in a processor pipeline (e.g., associated with a branch in-flight branch) may be a branch bit vector. Figure 1 The pipeline 110 associated with the processor 100 of FIG. 100 will have an associated bit vector. Each bit in the bit vector corresponds to a local branch history register. In this example, bit 332 corresponds to LBHR1 312, bit 334 corresponds to LBHR2 314, bit 336 corresponds to LBHR3 316, bit 338 corresponds to LBHR4 318, and bit 340 corresponds to LBHRN 320. As an example, the branch bit vector 330 may correspond to a particular in-flight branch (e.g., regarding FIG. 2A to FIG. 2D In this example, when the local branch history register corresponding to the branch is updated (e.g., as previously described with respect to branch_A), FIG. 2A to FIG. 2D described), branch predictors (e.g., Figure 1 The branch predictor 150 of the branch predictor sets the corresponding bit in the bit vector of the branch. When refreshing, the branch predictor uses the bit vector of the branch being refreshed (and all younger branches) to identify the local branch history register that needs to be restored. In this example, if the bit in the bit vector corresponding to the local branch history register has a logic value of 1, indicating that the bit was set by the branch predictor, then the local branch history register and the local branch history registers associated with all younger branches will need to be restored. As previously described, Figure 1 The circuit system 154 associated with the branch predictor 150 may include various types of logic gates, registers, counters, multiplexers, finite state machines, combinational logic, flip-flops, or other digital logic circuits for implementing various tasks for branch prediction, including the management of bit vectors and local branch history registers.

[0032] Figure 44 is a block diagram of a local branch history register and associated circuitry for tracking the validity of registers participating in branch prediction according to an example. The local branch history table 410 may include local branch history registers (one register for each in-flight branch). Assuming there are N such in-flight branches, the local branch history table 410 may include N local branch history registers (e.g., LBHR1 412, LBHR2 414, LBHR3 416, LBHR4 418, and LBHRN 420). In this example, the associated circuitry for tracking the validity of registers participating in branch prediction may include a restore counter 430. In this example, each local branch history register has an associated unsigned restore counter. In this example, restore counter C1 432 corresponds to LBHR1 412, restore counter C2 434 corresponds to LBHR2 314, restore counter C3 436 corresponds to LBHR3 416, restore counter C4 438 corresponds to LBHR4 418, and restore counter CN 440 corresponds to LBHRN 420. Each restore counter corresponding to a local branch history register indicates the number of bits that need to be refilled (i.e., restored) before the local branch history register is valid or ready to participate in the next prediction. Therefore, in this example, the maximum value of the restore counter, and therefore its bit width, represents the history length. As previously described, the local branch history registers are speculatively updated regardless of the restore counter value. Only when the value of the restore counter is zero can the corresponding local branch history register be used for branch prediction. Otherwise, each time a branch speculatively updates the local history register, the restore counter is decremented by 1. As previously described, with Figure 1 The circuit system 154 associated with the branch predictor 150 may include various types of logic gates, registers, counters, multiplexers, finite state machines, combinational logic, flip-flops, or other digital logic circuits for implementing various tasks for branch prediction, including the management of bit vectors and local branch history registers.

[0033] Using a local branch history register, associated circuitry for identifying registers affected by a refresh, and associated circuitry for tracking the validity of registers participating in the previously described branch prediction, the present disclosure provides different methods for efficiently managing the local branch history register. One method retains the phase of the local branch history register to allow for faster recovery. Another method is simpler, but the recovery of the local branch history register is slower.

[0034] Figure 5An example of a first recovery method is provided that preserves the state of the local branch history registers to allow for faster recovery. To explain this method, in one example, a local branch history table 510 displays the state of the local branch history registers prior to detecting an erroneously speculated branch that requires refreshing. A recovery counter 520 includes a counter for each of the local branch history tables, which is displayed as a portion of the local branch history table 510. This example assumes that there are six in-flight branches (e.g., branches B_1, B_2, B_1, B_3, B_4, and B_2). A local branch history table 530 displays the state of the local branch history registers after being refreshed due to an erroneously speculated branch. A recovery counter 550 includes a counter for each of the local branch history registers displayed as a portion of the local branch history table 530. When a local branch history register is used in the prediction of a branch, the branch predictor sets the corresponding bit in the bit vector (similar to the previous description of the bit vector). Figure 3 is explained), as shown by the bit vector relative to the refreshed branch 560.

[0035] When refreshing in-flight branches (e.g., branches B_1, B_2, B_1, B_3, B_4, and B_2), the exact number of bits that need to be refilled for each local history register is calculated by adding the bit vectors of the branch being refreshed and all younger branches. The sum of the corresponding bits in the bit vectors, the value for the maximum local history length, and the current corresponding recovery counter value are used to reset the recovery counter for the local branch history register to: quantity "A" = min(max_local_hist_length, (sum_of_corresponding_bits_in_all_bit_vectors+corresponding_recovery_counter_current_value)). If the value of the recovery counter is set to the local branch history register length (e.g., Figure 5 ), the branch predictor invalidates all bits in the corresponding local branch history register. Otherwise, the branch predictor shifts the affected local branch history register to the right by the previously calculated amount "A". As the branch predictor continues to update these registers (as more branches are predicted), the branch predictor will restart a given invalidated local branch history register once all of its questionable bits have been replaced by new bits (in fact, when the value of the corresponding restore counter reaches zero).

[0036] Continue to refer Figure 5, in this example, the third bit from the top of the bit vector corresponds to branch B_1, the bottom bit of the bit vector corresponds to branch B_2, the second bit from the top of the bit vector corresponds to branch B_3, and another bit from the top of the bit vector corresponds to branch B_4. The sum of the corresponding bits in the bit vector is displayed to the left of the bit vector. Therefore, for this example, Table 1 below shows the calculated history length for each of the affected local history registers that need to be restored.

[0037]

[0038] Table 1

[0039] Based on the number of calculated history lengths that need to be restored, the bits in the local branch history table 530 are displayed with dashes. As shown in this example, the local branch history register 532 does not need any restoration because it is not affected by the refresh. Therefore, the entire history of the register is retained and the local branch history register 532 can be used by the branch predictor in the next prediction cycle. As another example, the local branch history register 534 needs to restore the least significant bit of the register. The branch predictor shifts the bits in the local branch history register 534 right by 1 bit. The updated recovery count is set to 1, and before it reaches zero, the local branch history register 534 is not used by the branch predictor for making any predictions. However, it is worth noting that the remaining bits of the local branch history register 534 are retained. The local branch history register 536 and the local branch history register 538 need to restore three bits. Therefore, the value of each recovery counter in the associated recovery counter is updated to 3. However, in each register in the local branch history register 536 and the local branch history register 536, three remaining bits are still retained. As a final example, the restore counter value corresponding to local branch history register 540 is set to the history register length (six bits in this example), and all six bits in the register are invalidated by the branch predictor.

[0040] As the branch predictor continues to update these registers (as more branches are predicted), the branch predictor will restart a given invalidated local branch history register once all of the suspect bits have been replaced with new bits (e.g., effectively, when the value of the corresponding restore counter reaches zero). Advantageously, a more practical approach to providing fast and accurate recovery is used, rather than rolling back all of the local branch history registers (which is a slow and expensive process). Furthermore, the restore counter enables a self-repairing local branch history rollback process to be performed in the background. In turn, this eliminates the need for a complex recovery mechanism or the need to invalidate the entire local branch history stored in the local branch history table when misspeculation occurs.

[0041] Figure 6 An example of a first implementation of the second recovery method is provided. Figure 5 The first method described is easier to implement, but recovery takes longer. To illustrate this method, local branch history table 610 shows the state of the local branch history register after it has been refreshed due to an incorrectly speculated branch. This example assumes five in-flight branches (branches B_1, B_2, B_1, B_2, and B_3). Recovery counters 620 include a counter for each of the local branch history tables shown as part of local branch history table 610. When a local branch history register is used in the prediction of a branch, the branch predictor sets the corresponding bit in the bit vector (similar to the previous description of the bit vector). Figure 3 is explained), as shown by the bit vector relative to the refreshed branch 640.

[0042] When an in-flight branch (e.g., branches B_1, B_2, B_1, B_2, and B_3) is flushed, the affected local history registers are identified by performing a logical OR operation on the bit vectors of the flushed branch and all younger branches. The result is a single bit vector 650 indicating which local history registers need to be restored. The branch predictor invalidates any local history registers whose corresponding bits are set in bit vector 650. Figure 6 As shown, in this example, after performing a logical "OR" operation on the bit vectors of the refreshed branch and all younger branches (e.g., the bit vector of refreshed branch 640), bit 652, bit 654, and bit 656 of bit vector 650 are set. Therefore, the branch predictor invalidates local branch history register 612, local branch history register 614, and local branch history register 616. In addition, the branch predictor sets the restore counter of any invalidated local history register to the maximum possible value for the restore counter (e.g., the local history register length). As shown in FIG. Figure 6As shown, in this example, the branch predictor sets the value of each of the resume counters 622, 624, and 626 to 6, which is equal to Figure 6 The bit width of the local branch history registers is shown. As the branch predictor continues to update these registers (as more branches are predicted), the branch predictor will restart a given invalidated local branch history register once all of its suspect bits have been replaced with new bits (in fact, when the value of the corresponding restore counter reaches zero).

[0043] Figure 7 An example of a second implementation of the second recovery method is provided. Figure 5 The first method described is easier to implement, but recovery takes longer. To illustrate this method, local branch history table 710 shows the state of the local branch history register after it is refreshed due to a misspeculated branch. This example also assumes five in-flight branches (branches B_1, B_2, B_1, B_2, and B_3), such as Figure 6 The recovery counter 720 includes a counter for each of the local branch history tables shown as part of the local branch history table 710. Figure 6 Unlike the first implementation of the second method described above, when a local branch history register is used in the prediction of a branch, the branch predictor not only sets the corresponding bit in the bit vector of the predicted branch (similar to the above description of Figure 3 As explained above), the corresponding bits are also set in the bit vectors of all older in-flight branches. As an example, suppose Figure 6 If branch B_3 shown in is the predicted branch, the branch predictor then sets a bit in each of the older in-flight branches (eg, branches B_1, B_2, B_1, and B_2).

[0044] Branching on the fly (e.g. Figure 6 , B_1, B_2, B_1, B_2, and B_3) shown in FIG. 1 , the affected local history registers are identified by examining only the bit vector associated with the refreshed branch (e.g., the mispredicted branch bit vector 750). In this example, this mispredicted branch bit vector 750 indicates the local history registers that need to be restored. The branch predictor invalidates any local history registers whose corresponding bits are set in the mispredicted branch bit vector 750. Figure 7As shown, in this example, bit 752, bit 754, and bit 756 of bit vector 750 for the misspeculated branch are set. Therefore, the branch predictor invalidates local branch history register 712, local branch history register 714, and local branch history register 716. In addition, the branch predictor sets the restore counter of any invalidated local history register to the maximum possible value for the restore counter (e.g., the local history register length). Figure 7 As shown, in this example, the branch predictor sets the value of each of the resume counters 722, 724, and 726 to 6, which is equal to Figure 7 The bit width of the local branch history registers is shown. As the branch predictor continues to update these registers (as more branches are predicted), the branch predictor will restart a given invalidated local branch history register once all of its suspect bits have been replaced with new bits (in fact, when the value of the corresponding restore counter reaches zero).

[0045] Figure 8 Based on an example for Figure 1 Flowchart 800 of a method for efficient management of a local branch history register of a processor 100. The method relates to a first recovery method (with respect to Figure 5 As described above, each of the steps described in the method may be performed by a branch predictor circuit system. Step 810 may include: in response to the branch updating the local branch history register, setting a bit in a corresponding bit vector indicating the branch updating the local branch history register. Figure 3 As described above, when the local branch history register corresponding to the branch is updated (e.g., as described above with respect to FIG. 2A to FIG. 2D ), the branch predictor circuitry sets the corresponding bit in the bit vector for the branch.

[0046] Step 820 may include, at refresh time, determining a value indicating the degree of recovery required for each local branch history register affected by the refresh, and setting a corresponding recovery counter to a value indicating the degree of recovery required. Figure 5The value indicating the degree of recovery for each local branch history register affected by the refresh is determined by the branch predictor circuit system by performing the following operations, including: (1) calculating the sum of the bits in all bit vectors associated with the mispredicted branch and all in-flight branches younger than the mispredicted branch as the corresponding first value, (2) adding the corresponding first value to the current value of the corresponding restore counter to determine the corresponding second value, and (3) determining the value indicating the degree of recovery for each local branch history register affected by the refresh as the minimum value of the restore counter maximum value and the corresponding second value.

[0047] Fig. 9 Based on an example for Figure 1 A flowchart of another method for efficient management of a local branch history register of a processor. This method relates to a second recovery method (about Figure 6 As previously described, each of the steps described in the method may be performed by a branch predictor circuit system. Step 910 may include: in response to the branch updating the local branch history register, setting a bit in a corresponding bit vector indicating the branch updating the local branch history register. Figure 3 As described above, when the local branch history register corresponding to the branch is updated (e.g., as described above with respect to FIG. 2A to FIG. 2D ), the branch predictor circuitry sets the corresponding bit in the bit vector for the branch.

[0048] Step 920 may include, when refreshing, identifying all local branch history registers that need to be restored by performing a logical OR operation on the bit vectors corresponding to the misspeculated branch and all branches younger than the misspeculated branch. Figure 6 As described above, when an in-flight branch (e.g., branches B_1, B_2, B_1, B_2, and B_3) is refreshed, the affected local history registers are identified by performing a logical OR operation on the bit vectors of the refreshed branch and all younger branches. The result is a single bit vector (e.g., Figure 6 The bit vector 650 in indicates which local history registers need to be restored.

[0049] Step 930 may include discarding all bits of all identified local branch history registers that need to be restored, and setting the value of each corresponding restore counter of all identified local branch history registers that need to be restored to a maximum value for the restore counter. Additional details associated with discarding bits and setting restore counters are provided with reference to FIG. Figure 6Furthermore, as previously described, as the branch predictor continues to update these registers (as more branches are predicted), the branch predictor will restart a given invalidated local branch history register once all of its questionable bits have been replaced by new bits (in fact, when the value of the corresponding restore counter reaches zero).

[0050] Fig.10 Based on an example for Figure 1 Flowchart 1000 of another method for efficient management of a local branch history register of a processor. This method relates to a second recovery method (about Figure 7 As previously described, each of the steps described in the method may be performed by a branch predictor circuit system. Step 1010 may include, in response to an update of a local branch history register for a corresponding branch: (1) setting a bit in a corresponding bit vector indicating the update of the local branch history register by the corresponding branch, and (2) setting a bit in each of the bit vectors corresponding to all in-flight branches older than the corresponding branch. As previously described with respect to Figure 6 As described above, when the local branch history register is used for branch prediction, the branch predictor not only sets the corresponding bit in the bit vector of the predicted branch (similar to the above description of Figure 3 As explained above), the corresponding bits are also set in the bit vectors of all older in-flight branches. As an example, suppose Figure 6 If branch B_3 shown in is the predicted branch, the branch predictor then predicts each in-flight branch of the older in-flight branches (e.g., Figure 6 The bits are set in the branches B_1, B_2, B_1 and B_2).

[0051] Step 1020 may include: when refreshing, identifying all local branch history registers that need to be restored based on the bit vector corresponding to the mispredicted branch. Figure 7 As explained, branching on the fly (e.g. Figure 6 When branches B_1, B_2, B_1, B_2, and B_3 (shown) are refreshed, the affected local history registers are updated by checking only the bit vectors associated with the refreshed branches (e.g., Figure 7 The incorrectly speculated branch bit vector 750) is identified.

[0052] Step 1030 may include discarding all bits of all identified local branch history registers that need to be restored, and setting the value of each corresponding restore counter of all identified local branch history registers that need to be restored to a maximum value for the restore counter. Additional details associated with discarding bits and setting restore counters are provided with respect to Figure 7 Furthermore, as previously described, as the branch predictor continues to update these registers (as more branches are predicted), the branch predictor restarts a given invalid local branch history register once all of the branch predictor's questionable bits have been replaced by new bits (in fact, when the value of the corresponding restore counter reaches zero).

[0053] In summary, in one example, the present disclosure relates to a processor including a pipeline including a plurality of stages. The processor may further include a bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has a bit corresponding to each local branch history register associated with the corresponding in-flight branch. The processor may further include a restore counter associated with each local branch history register for tracking the number of bits that need to be restored before the local branch history register is valid to participate in branch prediction.

[0054] The processor may also include a branch predictor circuit system configured to: in response to an update of a local branch history register by a branch, set a bit in a corresponding bit vector indicating an update of the local branch history register by the branch. The branch predictor circuit system is further configured to: upon a refresh, determine a value indicating a desired degree of recovery for each local history register affected by the refresh, and set a corresponding recovery counter to a value indicating the desired degree of recovery.

[0055] The refresh is associated with the mispredicted branch and all in-flight branches younger than the mispredicted branch. A value indicating a degree of restoration for each local branch history register affected by the refresh is determined by the branch predictor circuitry by performing the following operations, including: (1) calculating the sum of all bits in the bit vector associated with the mispredicted branch and all in-flight branches younger than the mispredicted branch as a corresponding first value, (2) adding the corresponding first value to a current value of a corresponding restore counter to determine a corresponding second value, and (3) determining the value indicating a degree of restoration for each local branch history register affected by the refresh as a minimum of a maximum value of the restore counter and a corresponding second value.

[0056] The branch predictor circuitry is configured to discard a number of bits equal to the value indicating the degree of restoration for each local branch history register affected by the refresh. The branch predictor circuitry is configured to discard all bits of the corresponding local branch history register if the value indicating the degree of restoration for the corresponding local branch history register is determined as having a maximum value of the restore counter. The branch predictor circuitry is configured to update the corresponding local branch history register affected by the refresh when an additional corresponding branch is predicted.

[0057] The branch predictor circuitry is configured to decrement the corresponding restore counter when updating the corresponding local branch history register. The branch predictor circuitry is configured to restart use of the corresponding local branch history register once the corresponding restore counter is decremented to a value of zero. The corresponding local branch history register can only be used by the branch predictor circuitry for branch prediction when the value of the corresponding restore counter is zero.

[0058] In another example, the present disclosure relates to a processor including a pipeline including a plurality of stages. The processor may further include a bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has a bit corresponding to each local branch history register associated with the corresponding in-flight branch. The processor may further include a restore counter associated with each local branch history register for tracking the number of bits that need to be restored before the local branch history register is valid to participate in branch prediction.

[0059] The processor may also include a branch predictor circuit system configured to: in response to the branch updating the local branch history register, set a bit in the corresponding bit vector indicating the branch updating the local branch history register. The branch predictor circuit system may also be configured to: when refreshing, identify all local branch history registers that need to be restored by performing a logical or operation on the bit vectors corresponding to the mispredicted branch and all branches younger than the mispredicted branch. The branch predictor circuit system may also be configured to: discard all bits of all identified local branch history registers that need to be restored, and set the value of each corresponding restore counter of all identified local branch history registers that need to be restored to the maximum value for the restore counter.

[0060] The branch predictor circuitry is configured to update the respective local branch history register affected by the refresh when an additional respective branch is predicted. The branch predictor circuitry is configured to decrement the respective restore counter when updating the respective local branch history register.

[0061] The branch predictor circuitry is configured to restart use of the corresponding local branch history register once the corresponding resume counter is decremented to a value of zero. The corresponding local branch history register can only be used by the branch predictor circuitry for branch prediction when the value of the corresponding resume counter is zero.

[0062] In yet another example, the present disclosure relates to a processor including a pipeline including a plurality of stages. The processor may further include a bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has a bit corresponding to each local branch history register associated with the corresponding in-flight branch. The processor may further include a restore counter associated with each local branch history register for tracking the number of bits that need to be restored before the local branch history register is valid to participate in branch prediction.

[0063] The processor may also include a branch predictor circuit system configured to: in response to an update of a local branch history register by a corresponding branch: (1) set a bit in a corresponding bit vector indicating an update of the local branch history register by the corresponding branch, and (2) set a bit in each of the bit vectors corresponding to all in-flight branches that are older than the corresponding branch. The branch predictor circuit system may also be configured to: upon refresh, identify all local branch history registers that need to be restored based on the bit vector corresponding to the mispredicted branch. The branch predictor circuit system may also be configured to: discard all bits of all identified local branch history registers that need to be restored, and set the value of each corresponding restore counter of all identified local branch history registers that need to be restored to the maximum value for the restore counter.

[0064] The branch predictor circuitry may be configured to update the corresponding local branch history register affected by the refresh when an additional corresponding branch is predicted. The branch predictor circuitry may be configured to decrement the corresponding restore counter when updating the corresponding local branch history register. The branch predictor circuitry may be configured to restart use of the corresponding local branch history register once the corresponding restore counter is decremented to a zero value.

[0065] Only when the value of the corresponding restore counter is zero, the corresponding local branch history register may be used by the branch predictor circuitry for branch prediction.The plurality of stages may include a fetch stage and the branch predictor circuitry may be included in the fetch stage.

[0066] It should be understood that the methods, modules and components described herein are merely exemplary. Alternatively, or additionally, the functions described herein may be performed at least in part by one or more hardware logic components. For example, but not limited to, illustrative types of hardware logic components that may be used include field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), etc. In an abstract but still clear sense, any arrangement of components that implement the same function is effectively "associated" so that the desired function is implemented. Therefore, any two components combined to implement a specific function here can be regarded as "associated" with each other so that the desired function is implemented, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be regarded as "operably connected" or "coupled" to each other to achieve the desired function. Just because a component, which may be any other implementation of a device, structure, system or function, is described herein as being coupled to another component does not mean that the component must be a separate component. As an example, a component A described as being coupled to another component B may be a subcomponent of component B, or component B may be a subcomponent of component A.

[0067] Functionality associated with some of the examples described in this disclosure may also include instructions stored in non-transitory media. The term "non-transitory media" as used herein refers to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Exemplary non-transitory media include non-volatile media and / or volatile media. Non-volatile media include, for example, hard disks, solid-state drives, magnetic disks or tapes, optical disks or tapes, flash memory, EPROM, NVRAM, PRAM or other such media, or network versions of such media. Volatile media include, for example, dynamic memories such as DRAM, SRAM, cache or other such media. Non-transitory media are different from transmission media, but can be used in conjunction with transmission media. Transmission media are used to transmit data and / or instructions to or from a machine. Exemplary transmission media include coaxial cables, fiber optic cables, copper wires, and wireless media, such as radio waves.

[0068] In addition, those skilled in the art will recognize that the boundaries between the functions of the above-mentioned operations are merely illustrative. The functions of multiple operations can be combined into a single operation, and / or the functions of a single operation can be distributed in additional operations. In addition, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments.

[0069] Although the present disclosure provides specific examples, various modifications and changes may be made without departing from the scope of the present disclosure as described in the following claims. Therefore, the specification and drawings are to be viewed in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems described herein with respect to specific examples are not intended to be construed as key, required, or essential features or elements of any or all of the claims.

[0070] Furthermore, the terms "a" or "an", as used herein, are defined as one or more than one. Furthermore, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that the introduction of another claim element by the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an". This is also true for the use of definite articles.

[0071] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements these terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other prioritization of these elements.

Claims

1. A processor, comprising: A pipeline, the pipeline comprising a plurality of stages; a bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has a bit corresponding to each local branch history register associated with the respective in-flight branch; a restore counter associated with each local branch history register for tracking the number of bits that need to be restored before the local branch history register is valid to participate in branch prediction; as well as A branch predictor circuitry is configured to: responsive to an update of a local branch history register by a branch, setting a bit in a corresponding bit vector indicating the update of the local branch history register by the branch, and At a refresh, a value indicative of a desired degree of restoration for each local history register affected by the refresh is determined, and a corresponding restore counter is set to the value indicative of the desired degree of restoration.

2. The processor of claim 1, wherein the flush pertains to a misspeculated branch and all in-flight branches younger than the misspeculated branch.

3. The processor of claim 2 , wherein the value indicative of a degree of restoration for each local branch history register affected by the refresh is determined by the branch predictor circuitry by performing the following operations, the operations comprising: calculating as a corresponding first value the sum of the bits in all bit vectors associated with the misspeculated branch and all in-flight branches younger than the misspeculated branch, adding the respective first value to a current value of a corresponding resume counter to determine a respective second value, and The value indicating the degree of restoration for each local branch history register affected by the refresh is determined as a minimum value of a maximum value of the restore counter and the corresponding second value.

4. A processor as claimed in claim 3, wherein the branch predictor circuitry is configured to discard a number of bits equal to the value indicating the degree of restoration for each local branch history register affected by a refresh.

5. The processor of claim 3 , wherein the branch predictor circuitry is configured to discard all bits of a corresponding local branch history register if the value indicating the degree of recovery for the corresponding local branch history register is determined as having the maximum value of the restore counter.

6. The processor of claim 4, wherein the branch predictor circuitry is configured to update respective local branch history registers affected by the refresh when additional respective branches are predicted.

7. A processor as claimed in claim 6, wherein the branch predictor circuitry is configured to decrement a corresponding resume counter when the corresponding local branch history register is updated.

8. A processor as claimed in claim 7, wherein the branch predictor circuitry is configured to restart use of the corresponding local branch history register once the corresponding resume counter is decremented to a value of zero.

9. The processor of claim 1, wherein a corresponding local branch history register is usable by the branch predictor circuitry for branch prediction only when the value of the corresponding resume counter is zero.

10. A processor, comprising: A pipeline, the pipeline comprising a plurality of stages; a bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has a bit corresponding to each local branch history register associated with the respective in-flight branch; a restore counter associated with each local branch history register for tracking the number of bits that need to be restored before the local branch history register is valid to participate in branch prediction; as well as A branch predictor circuitry is configured to: In response to an update of a local branch history register by a branch, setting a bit in a corresponding bit vector indicating the update of the local branch history register by the branch, At flush time, identifying all local branch history registers that need to be restored by performing a logical OR operation on the bit vectors corresponding to the misspeculated branch and all branches younger than the misspeculated branch, and All bits of all identified local branch history registers that need to be restored are discarded, and the value of each corresponding restore counter of all identified local branch history registers that need to be restored is set to the maximum value for the restore counter.

11. The processor of claim 10, wherein the branch predictor circuitry is configured to update respective local branch history registers affected by the refresh when additional respective branches are predicted.

12. The processor of claim 11, wherein the branch predictor circuitry is configured to decrement a respective resume counter when the respective local branch history register is updated.

13. A processor as claimed in claim 12, wherein the branch predictor circuitry is configured to restart use of the corresponding local branch history register once the corresponding resume counter is decremented to a value of zero.

14. The processor of claim 10, wherein a corresponding local branch history register is usable by the branch predictor circuitry for branch prediction only when the value of the corresponding resume counter is zero.

15. A processor, comprising: A pipeline, the pipeline comprising a plurality of stages; a bit vector associated with each of the in-flight branches associated with the pipeline, wherein each bit vector has a bit corresponding to each local branch history register associated with the respective in-flight branch; a restore counter associated with each local branch history register for tracking the number of bits that need to be restored before the local branch history register is valid to participate in branch prediction; as well as A branch predictor circuitry is configured to: In response to an update of a local branch history register by a corresponding branch: (1) setting a bit in a corresponding bit vector indicating the update of the local branch history register by the corresponding branch, and (2) setting a bit in each of the bit vectors corresponding to all in-flight branches older than the corresponding branch, At flush time, identifying all local branch history registers that need to be restored based on the bit vector corresponding to the misspeculated branch, and All bits of all identified local branch history registers that need to be restored are discarded, and the value of each corresponding restore counter of all identified local branch history registers that need to be restored is set to the maximum value for the restore counter.

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