Runtime mechanism for optimal shader

Abstract

Aspects presented herein relate to methods and apparatus for graphics processing, including devices, such as GPUs. The apparatus may receive a drawing call instruction set corresponding to the graphics workload, wherein the drawing call instruction set is associated with at least one runtime parameter. The apparatus may also obtain a first shader program associated with storing the data in the system memory and at least one second shader program associated with storing the data in the constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a stream processor based on executing the first shader program or the at least one second shader program.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. patent application serial number 17 / 664,033, entitled “RUN-TIME MECHANISM FOROPTIMAL SHADER” and filed on May 18, 2022, which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for graphics processing. Background Art

[0004] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, and each application may need to utilize a GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values, and can issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0005] The GPU of a device may be configured to perform processes in a graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) may be configured to perform processes for display processing. However, with the advent of wireless communications and smaller handheld devices, the need for improved graphics or display processing continues to increase. Summary of the invention

[0006] The following presents the summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify the key or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0007] In one aspect of the present disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a graphics processing unit (GPU), a central processing unit (CPU), or any apparatus that can perform graphics processing. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, wherein the set of draw call instructions is associated with at least one runtime parameter corresponding to information available at runtime of the graphics workload. The apparatus may also detect whether an index value (i) is less than the at least one runtime parameter; and if the index value (i) is less than the at least one runtime parameter, increment the index value (i). In addition, the apparatus may obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing the data in a constant memory. The apparatus may also calculate whether the at least one runtime parameter is less than or equal to the size of the constant memory, wherein the first shader program or the at least one second shader program is executed based on whether the at least one runtime parameter is calculated to be less than or equal to the size of the constant memory. The apparatus may also execute the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to the size of the constant memory. In addition, the device may store the data in the system memory or the constant memory based on whether the at least one runtime parameter is less than or equal to the size of the constant memory. In the case where the data is stored in the system memory, the device may also load the data from the system memory to the constant memory. In addition, the device may update or maintain the configuration of a shader processor or a stream processor at a graphics processing unit (GPU) based on executing the first shader program or the at least one second shader program. The device may also adjust the size of the constant memory based on whether to update or maintain the configuration of the shader processor or the stream processor.

[0008] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example content generation system.

[0010] Figure 2 is an example graphics processing unit (GPU).

[0011] Figure 3 is a diagram illustrating example components for processing data.

[0012] Figure 4 is a diagram illustrating example instructions for executing a shader.

[0013] Figure 5 is a diagram illustrating an example GPU.

[0014] Figure 6 is a diagram illustrating an example GPU.

[0015] Figure 7 is a diagram illustrating an example of a shader program generated by a compiler at a GPU.

[0016] Figure 8 is a diagram illustrating an example of a shader preamble generated by a compiler at a GPU.

[0017] Fig. 9 is a communication flow diagram illustrating example communications between GPU components and memory.

[0018] Fig.10 is a flow chart of an example method of graphics processing.

[0019] Fig.11 is a flow chart of an example method of graphics processing. DETAILED DESCRIPTION

[0020] In terms of graphics processing, the GPU may include a high-level sequencer (HLSQ) block that prepares context states, such as global registers, shader constants, buffer descriptors, instructions, etc., for one or more stream processors (SPs). Inside the HLSQ, there is an internal functional unit called a state processor, which is a single-fiber scalar processor that executes a special shader program called a preamble shader. The GPU compiler may generate a preamble shader to load constant data from different buffer objects and bind it to a single constant buffer, a post-processing constant buffer, etc. In some instances, the HLSQ may execute the preamble shader once and skip the main shader that executes the normal vertex shading or fragment shading program. In addition, in the case where the HLSQ decides to skip the execution of the preamble, the stream processor (SP) may execute the preamble, as well as process conventional graphics workloads, such as vertex shading or fragment shading. In addition, after the compiler generates shader binary code from a high-level shader language, the compiler may pass shader statistics to the GPU driver, such as general register (GPR) footprint, shader constant size, shader instruction size, etc. SP can be based on the setting of these context registers to establish SP internal resource configuration before executing shader program. That is, SP can use GPR footprint to configure GPR space partition, use constant ram size to configure local buffer (LB) partition, and use shader size to configure instruction cache (I$) partition, so these state values ​​can have a great impact on SP execution performance and efficiency. In the case where high-level programs remain the same, larger values ​​can cause performance degradation. In addition, because GPR, LB and I$ are shared by multiple shaders, efficient shaders can have a positive impact on other workloads, and vice versa. In some aspects, when the compiler compiles a high-level program from an application, due to some information that is not available at compile time but available at workload dispatch time (also referred to as runtime or runtime), it may not always generate the best shader. For example, some applications can define a variable size dynamic constant buffer, because the constant buffer size is unknown at compile time, so the compiler can use instructions to load values ​​from the variable size constant buffer to the GPR, and then execute the program sequence. In addition, the compiler can generate an optimal program sequence when the compiler realizes that the variable-size constant buffer size is small enough to fit in the SP constant memory (e.g., constant random access memory (RAM)). Compared with the aforementioned first sequence, the second sequence can use less GPR space, fewer arithmetic logic unit (ALU) instructions and / or eliminate constant loads per fiber. Therefore, compared with the first sequence, the second sequence can be more power efficient and perform well. In some examples, the application can use a portion of a large constant buffer so that the entire buffer can exceed the available space at the SP constant memory (e.g., constant RAM).However, the actual size of the constant data used may not be suitable for the available space in the constant memory (e.g., constant RAM). In addition, constant data or information may only be available at a single time instance (e.g., workload dispatch time). Aspects of the present disclosure can determine the size of the constant data or information stored in the constant memory. In some instances, the aspects presented herein can adjust the size of the constant memory based on the size of the constant data or information stored in the constant memory. In addition, aspects of the present disclosure can configure the availability of the constant memory so that constant data or information can be used to be stored in the constant memory at different time periods. For example, aspects of the present disclosure can determine the size of the variable dynamic constant buffer in different time periods. By doing so, aspects of the present disclosure can store constant data or information of different sizes at the variable dynamic constant buffer in different time periods.

[0021] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings herein, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functions, or structures and functions other than the various aspects of the disclosure set forth herein or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein can be embodied by one or more elements of the claims.

[0022] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of various aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or objectives. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The specific embodiments and drawings merely illustrate the present disclosure and do not limit the present disclosure, and the scope of the present disclosure is defined by the appended claims.

[0023] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0024] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as a processing unit). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic devices, discrete hardware circuits, and other suitable hardware configured to perform various functionalities described in the present disclosure. One or more processors in a processing system may execute software. Software may be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc., whether expressed in software, firmware, middleware, microcode, hardware description languages, or other terms. The term "application" may refer to software. As described herein, one or more technologies may refer to an application program configured to perform one or more functions, i.e., software. In such examples, the application program may be stored in a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute the application program. For example, the application program may be described as including a code that, when executed by the hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access the code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such examples, the components may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0025] Therefore, in one or more examples described herein, the described functions can be implemented in hardware, software or any combination thereof. In the case of being implemented with software, the functions can be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media can be any available medium that can be accessed by a computer. As an example and not limitation, such computer-readable media may include a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), an optical disk storage device, a magnetic disk storage device, other magnetic storage devices, a combination of computer-readable media of the above type, or any other medium that can be used to store instructions or data structure forms that can be accessed by a computer.

[0026] In summary, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices to improve rendering of graphics content and / or reduce load on a processing unit (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0027] As used herein, instances of the term "content" may refer to "graphics content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphics content" may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphics content" may refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphics content" may refer to content produced by a graphics processing unit.

[0028] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content (such as a frame) to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform synthesis on one or more rendering layers to generate a frame. For another example, the display processing unit may be configured to synthesize, mix or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on a frame, such as zooming in or out. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been mixed together to form the frame, that is, the frame includes two or more layers, and the frame including two or more layers may be subsequently mixed.

[0029] Figure 1 1 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frame for presentation thereon. In further examples, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be passed to another device. In some aspects, this may be referred to as split rendering.

[0030] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing, such as in the graphics processing pipeline 107. The content encoder / decoder 122 may include an internal memory 123. In some examples, the device 104 may include a display processor (such as a display processor 127) to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before being presented by one or more displays 131. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head mounted display, or any other type of display device.

[0031] Memory external to the processing unit 120 and the content encoder / decoder 122, such as the system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to the external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0032] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0033] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media, or any other type of memory.

[0034] According to some examples, the internal memory 121 or the system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or a propagating signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or the system memory 124 is non-removable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. For another example, the system memory 124 may not be removable from the device 104.

[0035] Processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, processing unit 120 may be integrated into the motherboard of device 104. In some examples, processing unit 120 may be present on a graphics card installed in a port in the motherboard of device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with device 104. Processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuit systems, or any combination thereof. In the case where the technology is partially implemented in software, processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0036] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuit systems, or any combination thereof. In the case where the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0037] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving functions described herein with respect to the device 104. In addition, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or positioning information. The transmitter 130 may be configured to perform any sending functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving functions and / or sending functions described herein with respect to the device 104.

[0038] See again Figure 1In some aspects, the processing unit 120 may include a shader component 198 configured to receive a set of draw call instructions corresponding to a graphics workload, wherein the set of draw call instructions is associated with at least one runtime parameter corresponding to information available at runtime of the graphics workload. The shader component 198 may also be configured to detect whether the index value (i) is less than the at least one runtime parameter; and if the index value (i) is less than the at least one runtime parameter, increment the index value (i). The shader component 198 may also be configured to obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. The shader component 198 may also be configured to calculate whether the at least one runtime parameter is less than or equal to the size of the constant memory, wherein the first shader program or the at least one second shader program is executed based on the at least one runtime parameter being calculated to be less than or equal to the size of the constant memory. The shader component 198 may also be configured to execute the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to the size of the constant memory. The shader component 198 may also be configured to store data in a system memory or a constant memory based on whether at least one runtime parameter is less than or equal to the size of the constant memory. The shader component 198 may also be configured to load data from the system memory to the constant memory when the data is stored in the system memory. The shader component 198 may also be configured to update or maintain the configuration of a shader processor or a stream processor at a graphics processing unit (GPU) based on executing a first shader program or at least one second shader program. The shader component 198 may also be configured to adjust the size of the constant memory based on whether to update or maintain the configuration of the shader processor or the stream processor. Although the following description may focus on display processing, the concepts described herein may be applicable to other similar processing techniques.

[0039] As described herein, a device such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an onboard computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments may be used to perform.

[0040] The GPU can process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU can process two types of data or data packets, such as context register packets and draw call data. The context register packet can be a set of global state information, such as information about global registers, shader programs, or constant data, which can adjust how the graphics context will be processed. For example, the context register packet may include information about the color format. In some aspects of the context register packet, there may be a bit indicating which workload belongs to the context register. In addition, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program can describe a certain operation, such as a color mode or color format. Therefore, the context register can define multiple states of the GPU.

[0041] The context state can be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) operates and / or in which mode the processing unit operates. To this end, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads (e.g., vertex or pixel workloads) in a pipeline based on context register definitions of a mode or state. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to assemble vertices. Since these modes or states may change, the GPU may need to change the corresponding context. In addition, the workload corresponding to the mode or state can follow the changed mode or state.

[0042] Figure 2 An example GPU 200 is illustrated in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, a second level (L2) cache (UCHE) 238, and a system memory 240. Although Figure 2 GPU 200 is shown to include processing units 220-238, but GPU 200 may include multiple additional processing units. In addition, processing units 220-238 are only examples, and any combination or order of processing units may be used in accordance with the present disclosure of the GPU. GPU 200 also includes command buffer 250, context register group 260, and context state 261.

[0043] like Figure 2 As shown, the GPU may parse the command buffer into context register packets (e.g., context register packets 260) and / or draw call data packets (e.g., draw call packets 212) using a CP (e.g., CP 210) or a hardware accelerator. Subsequently, the CP 210 may transmit the context register packets 260 or the draw call packets 212 to a processing unit or block in the GPU through a separate path. In addition, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed in the following manner: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0044] The GPU can render images in a variety of different ways. In some instances, the GPU can use rendering and / or tile rendering to render images. In a tile rendering GPU, the image can be divided or split into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning process, the image can be divided into different boxes or tiles. In some aspects, during the binning process, a visibility stream can be constructed in which visible primitives or drawing calls can be identified. In contrast to tile rendering, direct rendering does not divide the frame into smaller boxes or tiles. On the contrary, in direct rendering, the entire frame is rendered at once. In addition, some types of GPUs may allow both tile rendering and direct rendering.

[0045] Figure 3 300 is a diagram illustrating exemplary components (such as a processing unit 120 and a system memory 124) that may be identified in conjunction with a device 104 for processing data. In various aspects, the processing unit 120 may include a CPU 302 and a GPU 312. The GPU 312 and the CPU 302 may be formed as integrated circuits (e.g., SOCs) and / or the GPU 312 may be incorporated into a motherboard having the CPU 302. Alternatively, the CPU 302 and the GPU 312 may be configured as different processing units that are communicatively coupled to each other. For example, the GPU 312 may be incorporated on a graphics card mounted in a port of a motherboard including the CPU 302.

[0046] The CPU 302 may be configured to execute a software application that causes the display of graphical content (e.g., on the display 131 of the device 104) based on one or more operations of the GPU 312. The software application may issue instructions to a graphics application program interface (API) 304, which may be a runtime program that translates instructions received from the software application into a format that can be read by the GPU driver 310. After receiving instructions from the software application via the graphics API 304, the GPU driver 310 may control the operation of the GPU 312 based on the instructions. For example, the GPU driver 310 may generate one or more command streams placed in the system memory 124, in which the GPU 312 is instructed to execute the command streams (e.g., via one or more system calls). A command engine 314 included in the GPU 312 is configured to retrieve one or more commands stored in the command streams. The command engine 314 may provide commands from the command streams for execution by the GPU 312. The command engine 314 may be hardware of the GPU 312, software / firmware executed on the GPU 312, or a combination thereof. Although GPU driver 310 is configured to implement graphics API 304, GPU driver 310 is not limited to being configured according to any particular API. System memory 124 may store code for GPU driver 310, which CPU 302 may retrieve for execution. In an example, GPU driver 310 may be configured to allow communication between CPU 302 and GPU 312, such as when CPU 302 offloads graphics or non-graphics processing tasks to GPU 312 via GPU driver 310.

[0047] The system memory 124 may further store source code for one or more of the preamble shader 324 or the main shader 326. In such a configuration, the shader compiler 308 executing on the CPU 302 may compile the source code of the shaders 324 to 326 to create an object code or intermediate code that can be executed by the shader core 316 of the GPU 312 during runtime (e.g., when the shaders 324 to 326 are to be executed on the shader core 316). In some examples, the shader compiler 308 may precompile the shaders 324 to 326 and store the object code or intermediate code of the shader program in the system memory 124. The shader compiler 308 executing on the CPU 302 (or in another example, the GPU driver 310) may create a shader program having multiple components, including the preamble shader 324 and the main shader 326. The main shader 326 may correspond to a portion or all of the shader program excluding the preamble shader 324. The shader compiler 308 may receive instructions from a program executed on the CPU 302 to compile shaders 324 to 326. The shader compiler 308 may also identify constant load instructions and common operations in the shader program for including the common operations within the preamble shader 324 (rather than the main shader 326). The shader compiler 308 may identify such common instructions based on (currently undetermined) constants 306 to be included in the common instructions, for example. The constants 306 may be defined within the graphics API 304 as constants across the entire draw call. The shader compiler 308 may utilize instructions such as a preamble shader start to indicate the start of the preamble shader 324 and a preamble shader 324 end to indicate the end of the preamble shader. Similar instructions may be used for the main shader 326.

[0048] The shader core 316 included in the GPU 312 may include a GPR 318 and a constant memory 320. The GPR 318 may correspond to a single GPR, a GPR file, and / or a GPR library. Each GPR in the GPR 318 may store data accessible to a single thread. The software and / or firmware executed on the GPU 312 may be a shader program 324 to 326, which may be executed on the shader core 316 of the GPU 312. The shader core 316 may be configured to execute many instances of the same instruction of the same shader program in parallel. For example, the shader core 316 may execute a main shader 326 for each pixel defining a given shape. The shader core 316 may send and receive data from an application executed on the CPU 302. In an example, constants 306 for the execution of shaders 324 to 326 may be stored in a constant memory 320 (e.g., read / write constant RAM) or in the GPR 318. The shader core 316 may load the constants 306 into a constant memory 320. In other examples, execution of the preamble shader 324 may cause a constant value or set of constant values ​​to be stored in an on-chip memory such as the constant memory 320 (e.g., a constant RAM), GPU memory 322, or system memory 124. The constant memory 320 may include memory accessible by all aspects of the shader core 316, rather than only specific portions (such as values ​​stored in GPR 318) reserved for specific threads.

[0049] Figure 4 400 is a block diagram corresponding to an example instruction 450 for executing a shader 402 based on GPR allocation. GPRs can be variably allocated to shaders when the shader is compiled. However, as the number of GPRs 318 allocated to shader 402 increases, the corresponding number of threads that can reside in the GPU at the same time decreases. This effect caused by the increase in the number of allocated GPRs 318 can not only limit latency hiding, but also reduce the overall performance of the GPU. In order to balance the tradeoff between increasing the number of GPRs 318 allocated to shader 402 and increasing the number of threads that can reside in the GPU at the same time, shader 402 can be executed based on the minimum number of GPRs 318 for shader execution, so that there are no allocated GPR resources that are not used by shader 402.

[0050] The minimum number of GPRs 318 executing the shader 402 may be based on a constant / consistent value that does not change within the runtime of the shader 402 for a single draw call or kernel. Given that the compiler may not know the exact value of the constant 306 when compiling the shader 402, excess GPRs 318 may be allocated to the shader 402 to ensure sufficient availability of GPRs 318 for executing more complex paths / branches (e.g., complex branch 404) of the shader 402. In the event that the value of the constant 306 is known when the shader 402 is compiled, the compiler may be able to increase shader performance by eliminating certain branches from the shader 402 that utilize more GPRs 318 to execute and thereby reducing the number of GPRs 318 that will be allocated to the shader 402 after compilation. Alternatively, where the GPU driver can determine the value of constant 306 when submitting (e.g., queuing) shader 402 to the GPU, the compiler can generate multiple versions of shader 402, each with a different GPR allocation, and allow the GPU driver to select the version of shader 402 to be used at submission time.

[0051] In summary, the value of constant 306 may not be determined by the compiler at compile time or by the GPU driver at submission time. Although shader 402 may be configured to identify the value of constant 306 at runtime, the number of GPR 318 may have been assigned to shader 402 when runtime occurs, which may exceed the number of GPR 318 used to execute certain branches of shader 402. Therefore, even if the compiler can be configured to identify the variable as a constant at compile time, the exact value of the constant 306 may remain unknown during shader compilation, so that the constant value cannot be used to reduce GPR allocation. Shaders may have different flow control paths / branches based on a certain combination of constants 306. Constant 306 can be defined in the graphics API to remain the same across the entire draw call (e.g., during the entire life of the corresponding shape). That is, the constant 306 of a given value does not change from one pixel to the next pixel across the draw call on a per-pixel basis. For all pixels that execute the corresponding shape, the constant 306 remains unchanged during the entire shader life. A constant buffer (which may also be referred to as a uniform buffer) may be managed by a graphics API and reside in memory (eg, similar to a texture buffer or a frame buffer) that may be accessed by the shader 402 to provide constant / uniform values ​​across draw calls.

[0052] The executable shader program may include a preamble portion of the shader program and a main portion of the shader program (or simply referred to as a "preamble shader" 324 and a "main shader" 326). The preamble shader 324 may be a portion of the shader 402 that is executed only once per draw call or kernel. The preamble shader 324 may be executed before any thread is allowed to execute the main shader 326. The preamble shader 324 may also preload constant values ​​into the local memory of the GPU, where the constant values ​​may be used by multiple threads executing within the main shader 326. Thus, the constant values ​​may be fetched once per draw call by the preamble shader, rather than by the main shader for each thread (e.g., pixel) within a draw call. In an example, the preamble shader 324 may fetch the constant 306 from a local constant buffer. In some aspects, the constant 306 or the contents of the constant buffer may be stored in the system memory 124. When the constant 306 has a first value (e.g., constant value X), the main shader 326 may use a first number of GPRs 318 (e.g., 20 GPRs) to execute the complex branch 404. When the local constant has a second value (e.g., constant value Y), the main shader 326 may use a second number of GPRs 318 (e.g., 4 GPRs) to execute the simple branch 406. However, in the case where the local constant for the draw call is 0 and the complex branch 404 may not need to be executed, the shader 402 may still be executed, for example, based on an allocation of 20 GPRs instead of an allocation of 4 GPRs. Therefore, some of the GPRs 318 allocated to the shader 402 may be unnecessary / excessive.

[0053] Figure 5 An example GPU 500 is illustrated. More specifically, Figure 5 The stream processor (SP) system in GPU 500 is illustrated. Figure 5 As shown, GPU 500 includes a high level sequencer (HLSQ) 502, a VPC 504, a texture processor (TP) 506, a UCHE 508, a RB 510, and a VPC 512. GPU 500 also includes a SP 520, a main engine 522, a sequencer 524, a local memory 526, a wave scheduler and context registers 528, a texture (TEX) or load controller 530, an instruction cache 532, an execution unit (EU) 534, a general purpose register (GPR) 536, an output distributor 538, a constant RAM 540, and a texture distributor 542. The wave scheduler and context registers 528 may include one or more wave slots.

[0054] like Figure 5As shown, SP 520 may include traditional functional units or blocks, such as EU 534 or sequencer 524. EU 534 may perform or process some desired functions of the GPU. Sequencer 524 may allocate resources and local memory. In addition, sequencer 524 may allocate wave slots and any associated GPR 536 space. For example, when HLSQ 502 issues a pixel tile workload to SP 520, sequencer 524 may allocate wave slots or GPR 536 space. In some aspects, wave scheduler and context register 528 may execute pixel shaders or issue instructions to EU 534. EU 534 may also include an arithmetic logic unit (ALU) and / or an elementary function unit (EFU). In addition, TEX or load controller 530 may be considered an execution unit. In addition, TEX or load controller 530 may correspond to one or more units. For example, TEX may perform texture fetches and / or load controllers may perform memory fetches. In some aspects, instruction cache 532 may store programs to be executed. In addition, the constant RAM 540 can store constants or uniformly form constants that may be required. Figure 5 As further shown, SP 520 may interface with external blocks, such as HLSQ 502, VPC 504, TP 506, UCHE 508, RB 510, and VPC 512. These blocks 502-512 may utilize user-provided input and / or the SP may output results to these blocks or memory accesses.

[0055] like Figure 5As shown, each unit or block in GPU 500 can transmit data or information to other blocks. For example, HLSQ 502 can transmit commands to main engine 522. In addition, HLSQ 502 can transmit vertex threads, vertex attributes, pixel threads and / or pixel attributes to sequencer 524. VPC 504 can transmit certain coefficients to local memory 526. TP506 can transmit texture data to TEX or load controller 530. TP 506 can also receive texture requests from TEX or load controller 530, for example, via texture distributor 542, and bypass requests from local memory 526. In addition, TP 506 can transmit requests to UCHE 508 and receive texture elements (text elements) therefrom. UCHE 508 can also transmit memory data to TEX or load controller 530 and receive memory requests therefrom, and transmit memory data to RB 510 and receive memory requests therefrom. In addition, RB 510 can receive output in the form of colors from GPR 536, for example, via output distributor 538. The VPC 512 may also receive outputs in the form of vertices from the GPR 536, for example, via an output distributor 538. The GPR 536 may also transmit temporary data to and receive temporary data from the EU 534. In addition, the EU 534 may transmit address or predicate information to the wave scheduler and context registers 528, and receive constant data from the constant RAM 540. The TEX or load controller 530 may also transmit load or store data to / from the GPR 536, and transmit store data to and receive load data from the local memory 526. In addition, the TEX or load controller 530 may transmit global data to the constant RAM 540 and transmit update information to the instruction cache 532. The TEX or load controller 530 may also receive attribute data from the sequencer 524 and synchronization information from the wave scheduler and context registers 528. In addition, the wave scheduler and context registers 528 may receive decode information from the instruction cache 532 and thread data from the sequencer 524.

[0056] Figure 6 An example GPU 600 is illustrated. Figure 6 As shown, GPU 600 is similar to Figure 5 500 in FIG. 1 , but GPU 600 includes several different components. More specifically, Figure 6 The stream processor (SP) system in GPU 600 is illustrated. Figure 6As shown, GPU 600 includes HLSQ 602, TP 606, UCHE 608, RB 610, and VPC 612. GPU 600 also includes SP 620, main engine 622, sequencer 624, local buffer 626, wave scheduler 628, texture (TEX) 630, instruction cache 632, ALU 634, GPR 636, dispatcher 638, and memory (MEM) load store (LDST) 640.

[0057] like Figure 6As shown, each unit or block in GPU 600 can transmit data or information to other blocks. For example, HLSQ 602 can transmit commands to main engine 622. In addition, HLSQ 602 can transmit vertex threads, vertex attributes, pixel threads, pixel attributes and / or calculation commands to sequencer 624. TP 606 can receive texture requests from TEX 630 and transmit texture elements (textures) back to TEX 630. In addition, TP 606 can transmit memory read requests to UCHE 608 and receive memory data from the UCHE. UCHE 608 can also receive memory read or write requests from MEM LDST 640 and transmit memory data back to MEM LDST 640, and receive memory read or write requests from RB 610 and transmit memory data back to RB 610. In addition, RB 610 can receive output in the form of color from GPR 636, for example, via dispatcher 638. VPC 612 may also receive output in the form of vertices from GPR 636, for example, via dispatcher 638. GPR 636 may transmit address data or receive write-back data from MEM LDST 640. GPR 636 may also transmit temporary data to and receive temporary data from ALU 634. In addition, ALU 634 may transmit address or predicate information to wave scheduler 628 and receive instructions from wave scheduler 628. Local buffer 626 may transmit constant data to ALU 634. TEX 630 may also receive texture attributes from or transmit texture data to GPR 636 and receive constant data from local buffer 626. In addition, TEX 630 may receive texture requests from wave scheduler 628 and receive constant data from local buffer 626. MEM LDST 640 may transmit constant data to / receive constant data from local buffer 626. The sequencer 624 may pass wave data to the wave scheduler 628, and pass the data to the GPR 636. The main engine 622 may pass program data to the instruction cache 632, and pass constant data to the local buffer 626 and receive instructions from the MEM LDST 640. The instruction cache 632 may pass instructions or decode information to the wave scheduler 628. The wave scheduler 628 may pass read requests to the local buffer 626, and pass memory requests to the MEM LDST 640.

[0058] like Figure 6As further shown, the high-level sequencer (HLSQ) 602 can prepare one or more context states for the stream processor (SP) 620. For example, the HLSQ 602 can prepare context states for different types of data, such as global register data, shader constant data, buffer descriptors, instructions, etc. In addition, the HLSQ 602 can embed the context state into the command stream to the SP 620. The main engine 622 can parse the command stream from the HLSQ 602 and set the SP global state. In addition, the main engine 622 can fill or add to the instruction cache 632 and / or the local buffer 626 or the constant buffer. In some aspects, inside the HLSQ 602, there may be an internal functional unit called a state processor. The state processor can be a single-fiber scalar processor that can execute a special shader program (e.g., a preamble shader). The preamble shader can be generated by the GPU compiler to load constant data from different buffer objects. In addition, the preamble shader can bind the buffer object to a single constant buffer, such as a post-processing constant buffer. Additionally, the HLSQ 602 may execute the preamble shader and thus skip utilizing the primary shader. In some instances, the primary shader may execute different shading tasks, such as normal vertex shading and / or fragment shading programs.

[0059] In addition, if Figure 6 As shown, in the event that the HLSQ 602 decides to skip the execution of the preamble, the SP 620 may not be limited to executing the preamble. For example, the SP 620 may also process conventional graphics workloads, such as vertex shading and / or fragment shading. In some aspects, the SP 620 may utilize its execution units and storage to process computing tasks as a general-purpose GPU (GPGPU). Inside the SP 620, there may be multiple parallel instruction execution units, such as ALU, EFU, branch unit, TEX, general-purpose memory read and write (also known as LDST), etc. The SP 620 may also include on-chip storage memory, such as a general-purpose register (GPR) 636 that can store per-fiber private data. In addition, the SP 620 may include a local buffer 626 that stores per-shader or per-kernel constant data, per-wave uniform constants (also known as uGPRs), and per-compute workgroup (WG) local memory (LM). In addition, as Figure 6As shown, the dispatcher 638 can extract data from the GPR 636. The dispatcher 638 can also perform format conversion and then dispatch the final color to multiple rendering targets (RTs). Each RT can have one or more components, such as red (r) green (G) blue (B) alpha (A) (RGBA) data, or only the alpha component of the RGBA data. In addition, each RT can generally be stored in a vector GPR, that is, R3.0 can store red data, R3.1 can store green data, R3.2 can store blue data, etc. In addition, the driver program in the SP context register can be used to define the GPR identifier (ID) storing the RT data.

[0060] As above Figure 6 As shown in , the GPU may include a high-level sequencer (HLSQ) block that can prepare context states for one or more stream processors (SPs), such as global registers, shader constants, buffer descriptors, instructions, etc. The HLSQ can also embed the context state into the command stream to the SP, where the SP master engine can parse the command stream from the HLSQ and establish the SP global state, as well as fill the instruction cache and constant buffer. Inside the HLSQ, there is an internal functional unit called a state processor, which is a single-fiber scalar processor that executes a special shader program called a preamble shader. The GPU compiler can generate a preamble shader to load constant data from different buffer objects and bind it to a single constant buffer, a post-processing constant buffer, etc. In some instances, the HLSQ can execute the preamble shader once and skip the main shader that executes the normal vertex shading or fragment shading program.

[0061] In addition, as mentioned above Figure 6 As shown in , in the case where the HLSQ decides to skip the execution of the preamble, the stream processor (SP) can execute the preamble, as well as process conventional graphics workloads such as vertex shading or fragment shading. The SP can use its execution units and storage to process computing tasks as a general-purpose GPU (GPGPU). Inside the SP wave scheduler, there may be multiple parallel instruction execution units, such as an arithmetic logic unit (ALU), a basic function unit (EFU), a branch unit, a texture sampling unit (TEX), general-purpose memory read and write (also known as load storage (LDST)), etc. There are also on-chip storage memories, such as general registers (GPRs) that store per-fiber private data, local buffers (LBs) that store per-shader or per-kernel constant data, per-wave uniform data (also known as uGPRs), and per-computing workgroup (WG) local memory (LM).

[0062] In addition, after the compiler generates shader binary code from the high-level shader language, the compiler can pass shader statistics to the GPU driver, such as GPR footprint, shader constant size, shader instruction size, etc. The driver can then parse the shader statistics information into context registers and embed the information in the command stream. The GPU command processor (CP) block can decode the command stream and pass the context registers to the HLSQ. The SP can establish the SP internal resource configuration before executing the shader program based on the settings of these context registers. That is, the SP can use the GPR footprint to configure the GPR space partition, use the constant ram size to configure the LB partition, and use the shader size to configure the instruction cache (I$) partition, so these state values ​​can have a large impact on SP execution performance and efficiency. In the case where the high-level program remains the same, a larger value can result in reduced performance. In addition, because GPR, LB and I$ are shared by multiple shaders, efficient shaders can have a positive impact on other workloads, and vice versa.

[0063] In some aspects, when a compiler compiles a high-level program from an application, it may not always generate an optimal shader due to some information that is not available at compile time but available at workload dispatch time (also known as runtime or run time). For example, some applications may define a variable-size dynamic constant buffer, and because the constant buffer size is unknown at compile time, the compiler may use an LDC instruction to load values ​​from this variable-size constant buffer to a GPR, and then execute a program sequence. For example, the GPU may execute the following program sequence (i.e., a first sequence):

[0064] Iadd addr,buffer_base,offset / / calculate constant value memory address "addr"

[0065] ldc r1,mem[addr]; / / use ldc instruction to load constant toGPR r1

[0066] (sy)fmul.f32 r2,r0,r1 / / fetch constant data from memory andwrite back to

[0067] r1, then compute r2=r0*r1

[0068] In addition, the compiler can generate an optimal program sequence when the compiler realizes that the variable-size constant buffer size is small enough to fit in the SP constant memory (e.g., constant random access memory (RAM)). For example, the compiler can generate the following program sequence (i.e., the second sequence): fmul.f32 r1, r0, c100 (i.e., assuming the corresponding constant values ​​stored in c100). Compared with the aforementioned first sequence, the second sequence can use less GPR space, fewer ALU instructions, and / or eliminate constant loads per fiber. Therefore, compared with the first sequence, the second sequence can be more power efficient and perform well.

[0069] In some examples, an application may use a portion of a large constant buffer so that the entire buffer may exceed the available space at the SP constant memory (e.g., constant RAM). However, the actual size of the constant data used may fit into the available space in the constant memory (e.g., constant RAM). In addition, constant data or information may only be available at a single time instance (e.g., workload dispatch time). Based on the above, it may be beneficial to determine the size of the constant data or information stored in the constant memory. In addition, it may be beneficial for constant data or information to be available for storage at different time periods. Therefore, it may be beneficial to determine the size of the variable dynamic constant buffer at different time periods.

[0070] Aspects of the present disclosure can determine the size of the constant data or information stored in the constant memory. In some instances, the aspects presented herein can adjust the size of the constant memory based on the size of the constant data or information stored in the constant memory. In addition, aspects of the present disclosure can configure the availability of the constant memory so that the constant data or information can be used to be stored in the constant memory at different time periods. For example, aspects of the present disclosure can determine the size of the variable dynamic constant buffer at different time periods. By doing this, aspects of the present disclosure can store constant data or information of different sizes at the variable dynamic constant buffer at different time periods.

[0071] In some instances, aspects of the present disclosure may determine the size of a variable dynamic constant buffer at a specific time (such as when an HLSQ or SP executes a preamble). For example, some information may not be available at compile time, but may be available at a later time. For example, some information lost at compile time may become available at workload dispatch time. Therefore, this can create an optimization opportunity to store the lost information in a constant memory at another time (e.g., when an HLSQ or SP executes a preamble). That is, the aspects presented herein can check the actual size of a variable dynamic constant buffer and promote that portion of the information to a constant memory (e.g., a constant RAM) at a certain time (e.g., when an HLSQ or SP executes a preamble).

[0072] Some aspects of the present disclosure may utilize a process to optimize shader execution at a GPU. To this end, in some examples, an application may declare a large constant buffer that exceeds the size of a constant memory (e.g., a constant RAM size). For example, this may be implemented by the following code: Declare (Dcl) CB0

[4096] (i.e., the application declares a large constant buffer that exceeds the constant RAM size). In addition, a constant buffer parameter (i.e., CB_parameter) may be a constant parameter available at a particular time (e.g., workload dispatch time). In some instances, in the case where the index value (i) is less than the constant buffer parameter, the index value (i) may be incremented so that constant buffer data (e.g., CB0) may be stored at a constant buffer location based on the index value (i). This may be represented by the following code (e.g., a shader program), where CB_parameter is a constant parameter available at workload dispatch time (i.e., 16):

[0073] For(int i=0;i <CB_parameter;i++)

[0074] Use CB0[i]

[0075] In addition, in some instances, the compiler can generate multiple versions of the shader program. For example, the compiler can generate a first version of the shader program (i.e., default version #0) and a second version of the shader program (i.e., optimized version #1). In the first version of the shader program, constant buffer data (e.g., CB0) may not be promoted to constant memory (e.g., constant RAM). In addition, in the first version of the shader program, the main program can use a load from a constant load (LDC) instruction to load constant buffer data to a general purpose register (GPR). In the second version of the shader program, constant buffer data (e.g., CB0) can be promoted to constant memory (e.g., constant RAM). In addition, in the second version of the shader program, the main program can use direct access to constant memory, and therefore eliminate the LDC instruction. For example, the above steps can be completed by the following code:

[0076]

[0077] Figure 7 The diagram 700 illustrates examples of different shader programs generated by a compiler at a GPU. More specifically, Figure 7 Figure 700 in Figure 700 shows a default shader program 710 and an optimized shader program 720 generated by a compiler 702. Figure 7As shown, the default shader program 710 includes steps 712, 714, and 716. At step 712, the default shader program 710 stores the constant buffer (CB) data in the system memory. That is, the constant buffer data is not promoted to the constant memory. At step 714, the default shader program 710 runs the main shader program. At step 716, the default shader program 710 uses a load from constant (LDC) instruction to load the constant buffer data into a general purpose register (GPR). As shown in FIG. Figure 7 As further shown, the optimized shader program 720 includes steps 722, 724, and 726. At step 722, the optimized shader program 720 may store the constant buffer data in the constant memory. That is, the constant buffer data may be promoted to the constant memory. At step 724, the optimized shader program 720 may run the main shader program. At step 726, the optimized shader program 720 may use direct access to the constant memory to load the constant buffer data. By doing so, the optimized shader program 720 may eliminate the LDC instruction.

[0078] In addition, the compiler can create a class of preambles (e.g., preambles of shader programs) called dispatch shaders, which have new instructions for setting shader state (SSS) context registers. For example, the dispatch shader can initiate a dispatch shader start (DPSS) and obtain constant buffer parameters from a constant memory (e.g., constant RAM). The dispatch shader can then compare the constant buffer parameters with the constant memory size, and in the case where the constant buffer parameters are less than or equal to the constant memory size, the dispatch shader can generate a predicate (P0). In the case where the predicate (P0) is true, the dispatch shader can then generate a new SSS instruction to set the GPR footprint for the optimized version (i.e., version #1) of the shader program, and generate a new SSS instruction to set a constant length (constantLength) for the optimized version. In addition, in the case where the predicate (P0) is true, the dispatch shader can set a shader code (ShaderCode) descriptor. For example, the dispatch shader may generate new SSS instructions to set a certain shader size (e.g., version #1 shader size), address offset, etc. for an optimized version of the shader program. In the case where the predicate (P0) is false, the dispatch shader may use the default version of the shader program (i.e., version #0). In the default version, the dispatch shader may set the GPR footprint (GPRfootprint) for the default version, and set the constant length (constantLength) for the default version. In addition, in the default version, the context register may be set to be optional, such as having a shader code descriptor. After this, the preamble or dispatch shader may end (e.g., dispatch shader end (DPSE)). In some instances, the above steps may be accomplished by the following code:

[0079]

[0080] Figure 8 The diagram 800 illustrates examples of different shader preambles generated by a compiler at a GPU. More specifically, Figure 8 The diagram 800 in FIG. 8 shows the default preamble 810 and the dispatch shader 820 generated by the compiler 802. Figure 8As shown, the default preamble 810 includes steps 812, 814, and 816. At step 812, the default preamble 810 can start the default preamble. At step 814, the default preamble 810 can set the GPR footprint (GPRfootprint) for the default preamble. In addition, at step 814, the default preamble 810 can set a constant length (constantLength) for the default preamble. In addition, at step 814, the default preamble 810 can set a shader code (ShaderCode) descriptor for the default preamble. At step 816, the default preamble 810 can end the default preamble.

[0081] like Figure 8 Further shown, the dispatch shader 820 includes steps 822, 824, 826, 828, and 829. The dispatch shader 820 can be a preamble (e.g., a preamble of a shader program) with an update instruction for setting a shader state (SSS) context register. At step 822, the dispatch shader 820 can start the dispatch shader. At step 824, the dispatch shader 820 can obtain constant buffer (CB) parameters. At step 826, the dispatch shader 820 can compare the CB parameters with the size of the constant memory. In addition, at step 826, the dispatch shader 820 can generate a predicate (P0). In the case where the predicate is false, at step 828, the dispatch shader 820 can switch to a default preamble (e.g., default preamble 810). In the case where the predicate is true, at step 829, the dispatch shader 820 can set a GPR footprint for the dispatch shader. In addition, at step 829, the dispatch shader 820 may set a constant length (constantLength) for the dispatch shader. In addition, at step 829, the dispatch shader 820 may set a shader code (ShaderCode) descriptor for the dispatch shader. Thereafter, the dispatch shader 820 may jump to a preamble end step that ends the dispatch shader.

[0082] In some aspects of the present disclosure, on the hardware side of the GPU, a high-level sequencer (HLSQ), a stream processor (SP), or a shader processor may include several functionalities. For example, the HLSQ, SP, or shader processor may identify a dispatch shader. After identifying the dispatch shader, the HLSQ, SP, or shader processor may load and dispatch the corresponding shader version. The HLSQ, SP, or shader processor may also decode a set shader state (SSS) instruction. By decoding the SSS instruction, the HLSQ, SP, or shader processor may update a draw call or kernel context registers, such as GPR footprints, constant sizes, and the like.

[0083] In addition, in some instances, the GPU hardware can transmit the collected feedback information (i.e., determining the loop count of the constant RAM size, the shader version assigned, etc.) to the system memory allocated by the driver at runtime. The driver can then collect the feedback information to perform deeper optimizations. For example, the driver can recompile the shader with the collected runtime information to create a more efficient shader version. For example, the driver can use the sampling or loading instructions in the loop to expand the loop to form a larger sampling or loading instruction group to reduce the memory extraction delay. In addition, the driver can add new shader versions or eliminate irrelevant shader versions to reduce compilation time.

[0084] In addition, by utilizing the new SSS instructions, the aspects presented herein can eliminate shader-related context registers from driver programming. By doing so, when the HLSQ, SP, or shader processor executes the shader program, the HLSQ, SP, or shader processor can decode the context register directly from the shader instruction. This process can reduce the transition overhead between the compiler, driver, and command processor (CP) at the GPU. In addition, the amount of CP processing HLSQ SP state cycles can also be reduced.

[0085] Aspects of the present disclosure may include several benefits or advantages. For example, the aspects presented herein may provide an area-efficient (i.e., hardware area cost increment is close to zero), power-efficient, and good-performance way for a compiler to generate optimal shader code. The aspects presented herein may achieve this efficient way by eliminating redundant instructions using a runtime optimization mechanism including runtime available information. The aspects of the present disclosure may also reduce the GPR footprint by using a runtime optimization mechanism. In addition, the aspects presented herein may eliminate redundant memory loads in the main program regarding per-pixel / per-fiber calls by using a runtime optimization mechanism. By using the aforementioned runtime optimization mechanism, there may be an increase in the number of frames per second (FPS) (e.g., 14% FPS increase). In addition, by using the aforementioned runtime optimization mechanism, there may be a reduction in SP constant load (e.g., 90% SP constant load reduction potential) achieved by optimizing a single shader (e.g., a single shader in a forwardDraw1 surface).

[0086] Fig. 9 FIG. 9 is a communication flow diagram 900 of a graphical process according to one or more techniques of the present disclosure. Fig. 9 As shown, diagram 900 includes example communications between components of a GPU (or other graphics processor), such as GPU component 902, GPU component 904, and memory 906 (e.g., system memory, double data rate (DDR) memory, or constant memory), in accordance with one or more techniques of this disclosure.

[0087] At 910, the GPU component 902 may receive a draw call instruction set corresponding to a graphics workload (e.g., receiving data 912 from the GPU component 904), wherein the draw call instruction set is associated with at least one runtime parameter corresponding to information available at a runtime of the graphics workload. In some instances, one of the at least one runtime parameter may be a constant buffer parameter corresponding to a size of a constant memory or a size of a constant buffer. Furthermore, the at least one runtime parameter may be associated with a texture filtering mode for the graphics workload. The runtime of the graphics workload may be a workload dispatch time at the GPU. Furthermore, the graphics workload may be at least one of a pixel workload at the GPU or a computational workload at the GPU.

[0088] At 920, GPU component 902 may detect whether index value (i) is less than at least one runtime parameter; and if index value (i) is less than at least one runtime parameter, increment index value (i). If index value (i) is incremented, at least one second shader program may be executed and data may be stored in constant memory.

[0089] At 930, GPU component 902 may obtain a first shader program associated with storing data in system memory and at least one second shader program associated with storing the data in constant memory. In addition, GPU component 902 may generate the first shader program and the at least one second shader program. In some aspects, obtaining the first shader program and the at least one second shader program may include generating the first shader program and the at least one second shader program. The first shader program may be a default shader program and the at least one second shader program may be an optimized shader program.

[0090] At 940 , the GPU component 902 may calculate whether the at least one runtime parameter is less than or equal to the size of the constant memory, wherein the first shader program or the at least one second shader program is executed based on whether the at least one runtime parameter is calculated to be less than or equal to the size of the constant memory.

[0091] At 950, GPU component 902 can execute the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to the size of the constant memory. In some aspects, the first shader program can be executed if the at least one runtime parameter is greater than the size of the constant memory, and the at least one second shader program can be executed if the at least one runtime parameter is less than or equal to the size of the constant memory.

[0092] At 960, GPU component 902 may store data in system memory or constant memory (e.g., store data 962 in memory 906) based on whether at least one runtime parameter is less than or equal to the size of the constant memory. In the case where at least one runtime parameter is greater than the size of the constant memory, the data may be stored in the system memory, and in the case where at least one runtime parameter is less than or equal to the size of the constant memory, the data may be stored in the constant memory. The system memory may be a double data rate (DDR) random access memory (RAM), and the constant memory may be a constant RAM or an on-chip memory. In addition, the data may be constant buffer data associated with the constant memory or a constant buffer.

[0093] At 970 , GPU component 902 may load the data from system memory to constant memory, if the data is stored in system memory.

[0094] At 980, the GPU component 902 can update or maintain the configuration of a shader processor or a stream processor at a graphics processing unit (GPU) based on executing the first shader program or at least one second shader program. In some aspects, in the case of executing the first shader program, the configuration of the shader processor or the stream processor can be maintained as a first configuration, and in the case of executing at least one second shader program, the configuration of the shader processor or the stream processor can be updated to a second configuration. In addition, in the case of executing the first shader program and updating the configuration of the shader processor or the stream processor, the amount of pixel calculation can be reduced.

[0095] At 990 , the GPU component 902 can adjust the size of the constant memory based on whether to update or maintain the configuration of the shader processor or the stream processor.

[0096] Fig.10 1000 is a flowchart of an example method of graphics processing according to one or more techniques of the present disclosure. The method can be performed by a GPU (a device for graphics processing), a graphics processor, a CPU, a wireless communication device, and / or a combination thereof. Figures 1 to 9 The examples are performed using any device that can perform graphics processing. The methods described herein may provide several benefits, such as improved resource utilization and / or power savings.

[0097] At 1002, a GPU may receive a draw call instruction set corresponding to a graphics workload, wherein the draw call instruction set is associated with at least one runtime parameter corresponding to information available at runtime of the graphics workload, such as in conjunction with Figures 1 to 9 For example, Fig. 9As described in 910 of the embodiment, the GPU component 902 may receive a drawing call instruction set corresponding to a graphics workload, wherein the drawing call instruction set is associated with at least one runtime parameter corresponding to information available at runtime of the graphics workload. In addition, step 1002 may be performed by Figure 1 In some examples, one of the at least one runtime parameter may be a constant buffer parameter corresponding to a size of a constant memory or a size of a constant buffer. In addition, the at least one runtime parameter may be associated with a texture filtering mode for a graphics workload. The runtime of the graphics workload may be a workload dispatch time at the GPU. In addition, the graphics workload may be at least one of a pixel workload at the GPU or a computational workload at the GPU.

[0098] At 1006, the GPU may obtain a first shader program associated with storing data in system memory and at least one second shader program associated with storing the data in constant memory, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 930 of , the GPU component 902 can obtain a first shader program associated with storing data in the system memory and at least one second shader program associated with storing the data in the constant memory. In addition, step 1006 can be performed by Figure 1 In some aspects, obtaining the first shader program and the at least one second shader program may include generating the first shader program and the at least one second shader program. The first shader program may be a default shader program and the at least one second shader program may be an optimized shader program.

[0099] At 1010, the GPU may execute the first shader program or at least one second shader program based on whether the at least one runtime parameter is less than or equal to the size of the constant memory, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 950 of the present invention, the GPU component 902 can execute the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to the size of the constant memory. In addition, step 1010 can be performed by Figure 1 In some aspects, a first shader program may be executed when at least one runtime parameter is greater than the size of the constant memory, and at least one second shader program may be executed when at least one runtime parameter is less than or equal to the size of the constant memory.

[0100] At 1016, the GPU may update or maintain a configuration of a shader processor or a stream processor at a graphics processing unit (GPU) based on executing the first shader program or the at least one second shader program, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 980 of , the GPU component 902 can update or maintain the configuration of the shader processor or stream processor at the graphics processing unit (GPU) based on executing the first shader program or at least one second shader program. In addition, step 1016 can be performed by Figure 1 In some aspects, when executing a first shader program, the configuration of the shader processor or stream processor may be maintained as a first configuration, and when executing at least one second shader program, the configuration of the shader processor or stream processor may be updated to a second configuration. In addition, when executing the first shader program and updating the configuration of the shader processor or stream processor, the amount of pixel calculation may be reduced.

[0101] Fig.11 1100 is a flowchart of an example method of graphics processing according to one or more techniques of the present disclosure. The method can be performed by a GPU (a device for graphics processing), a graphics processor, a CPU, a wireless communication device, and / or a combination thereof. Figures 1 to 9 The examples are performed using any device that can perform graphics processing. The methods described herein may provide several benefits, such as improved resource utilization and / or power savings.

[0102] At 1102, the GPU may receive a draw call instruction set corresponding to a graphics workload, wherein the draw call instruction set is associated with at least one runtime parameter corresponding to information available at runtime of the graphics workload, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 910 of the embodiment, the GPU component 902 may receive a drawing call instruction set corresponding to a graphics workload, wherein the drawing call instruction set is associated with at least one runtime parameter corresponding to information available at runtime of the graphics workload. In addition, step 1102 may be performed by Figure 1 In some examples, one of the at least one runtime parameter may be a constant buffer parameter corresponding to a size of a constant memory or a size of a constant buffer. In addition, the at least one runtime parameter may be associated with a texture filtering mode for a graphics workload. The runtime of the graphics workload may be a workload dispatch time at the GPU. In addition, the graphics workload may be at least one of a pixel workload at the GPU or a computational workload at the GPU.

[0103] At 1104, the GPU may detect whether the index value (i) is less than at least one runtime parameter; and if the index value (i) is less than at least one runtime parameter, increment the index value (i), such as in combination with Figures 1 to 9 For example, Fig. 9 As described in 920 of the embodiment, the GPU component 902 can detect whether the index value (i) is less than at least one runtime parameter; and if the index value (i) is less than at least one runtime parameter, the index value (i) is incremented. In addition, step 1104 can be performed by Figure 1 In the case where the index value (i) is incremented, at least one second shader program may be executed and data may be stored in the constant memory.

[0104] At 1106, the GPU may obtain a first shader program associated with storing data in system memory and at least one second shader program associated with storing the data in constant memory, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 930 of , the GPU component 902 can obtain a first shader program associated with storing data in the system memory and at least one second shader program associated with storing the data in the constant memory. In addition, step 1106 can be performed by Figure 1 In some aspects, obtaining the first shader program and the at least one second shader program may include generating the first shader program and the at least one second shader program. The first shader program may be a default shader program and the at least one second shader program may be an optimized shader program.

[0105] At 1108, the GPU may calculate whether the at least one runtime parameter is less than or equal to the size of the constant memory, wherein the first shader program or the at least one second shader program is executed based on whether the at least one runtime parameter is calculated to be less than or equal to the size of the constant memory, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 940 of the present invention, the GPU component 902 can calculate whether the at least one runtime parameter is less than or equal to the size of the constant memory, wherein the first shader program or the at least one second shader program is executed based on whether the at least one runtime parameter is calculated to be less than or equal to the size of the constant memory. In addition, step 1108 can be performed by Figure 1 The processing unit 120 in the embodiment is used for execution.

[0106] At 1110, the GPU may execute the first shader program or at least one second shader program based on whether the at least one runtime parameter is less than or equal to the size of the constant memory, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 950 of the present invention, the GPU component 902 can execute the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to the size of the constant memory. In addition, step 1110 can be performed by Figure 1 In some aspects, a first shader program may be executed when at least one runtime parameter is greater than the size of the constant memory, and at least one second shader program may be executed when at least one runtime parameter is less than or equal to the size of the constant memory.

[0107] At 1112, the GPU may store data in system memory or constant memory based on whether the at least one runtime parameter is less than or equal to the size of the constant memory, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 960 of , the GPU component 902 can store data in the system memory or the constant memory based on whether the at least one runtime parameter is less than or equal to the size of the constant memory. In addition, step 1112 can be performed by Figure 1 The processing unit 120 in the embodiment of the present invention is executed. In the case where at least one runtime parameter is greater than the size of the constant memory, the data can be stored in the system memory, and in the case where at least one runtime parameter is less than or equal to the size of the constant memory, the data can be stored in the constant memory. The system memory can be a double data rate (DDR) random access memory (RAM), and the constant memory can be a constant RAM or an on-chip memory. In addition, the data can be constant buffer data associated with the constant memory or the constant buffer.

[0108] At 1114, in the case where the data is stored in the system memory, the GPU may load the data from the system memory into the constant memory, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 970 of , in the case where the data is stored in the system memory, the GPU component 902 can load the data from the system memory to the constant memory. In addition, step 1114 can be performed by Figure 1 The processing unit 120 in the embodiment is used for execution.

[0109] At 1116, the GPU may update or maintain a configuration of a shader processor or a stream processor at a graphics processing unit (GPU) based on executing the first shader program or the at least one second shader program, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 980 of , the GPU component 902 can update or maintain the configuration of the shader processor or stream processor at the graphics processing unit (GPU) based on executing the first shader program or at least one second shader program. In addition, step 1116 can be performed by Figure 1 In some aspects, when executing a first shader program, the configuration of the shader processor or stream processor may be maintained as a first configuration, and when executing at least one second shader program, the configuration of the shader processor or stream processor may be updated to a second configuration. In addition, when executing the first shader program and updating the configuration of the shader processor or stream processor, the amount of pixel calculation may be reduced.

[0110] At 1118, the GPU may adjust the size of the constant memory based on whether to update or maintain the configuration of the shader processor or stream processor, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 990 of FIG. 1 , the GPU component 902 can adjust the size of the constant memory based on whether to update or maintain the configuration of the shader processor or stream processor. In addition, step 1118 can be performed by Figure 1 The processing unit 120 in the embodiment is used for execution.

[0111] In a configuration, a method or apparatus for graphics processing is provided. The apparatus may be a GPU, a graphics processor, or some other processor that can perform graphics processing. In various aspects, the apparatus may be a processing unit 120 within a device 104, or may be some other hardware within the device 104 or another device. The apparatus (e.g., processing unit 120) may include a component for receiving a draw call instruction set corresponding to a graphics workload, wherein the draw call instruction set is associated with at least one runtime parameter corresponding to information available at runtime of the graphics workload; a component for obtaining a first shader program associated with storing data in a system memory and at least one second shader program associated with storing the data in a constant memory; a component for executing the first shader program or at least one second shader program based on whether the at least one runtime parameter is less than or equal to the size of the constant memory; a component for updating or maintaining a configuration of a shader processor or a stream processor at a graphics processing unit (GPU) based on executing the first shader program or the at least one second shader program; a component for updating or maintaining a configuration of a shader processor or a stream processor at a graphics processing unit (GPU) based on whether the at least one runtime parameter is less than or equal to the constant memory .... a component for storing data in a system memory or a constant memory according to the size of a memory; a component for loading data from the system memory to the constant memory when the data is stored in the system memory; a component for detecting whether the index value (i) is less than at least one runtime parameter; a component for incrementing the index value (i) when the index value (i) is less than at least one runtime parameter; a component for calculating whether the at least one runtime parameter is less than or equal to the size of the constant memory, wherein the first shader program or the at least one second shader program is executed based on whether the at least one runtime parameter is calculated to be less than or equal to the size of the constant memory; a component for adjusting the size of the constant memory based on whether to update or maintain the configuration of the shader processor or the stream processor; and a component for generating the first shader program and the at least one second shader program.

[0112] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the described graphics processing techniques can be used by a GPU, a graphics processor, or some other processors that can perform graphics processing to implement the runtime mechanism for the optimal shader described herein. Compared with other graphics processing techniques, this can also be implemented at a low cost. In addition, the graphics processing techniques herein can improve or accelerate data processing or execution. In addition, the graphics processing techniques herein can improve resource or data utilization and / or resource efficiency. In addition, various aspects of the present disclosure can utilize runtime mechanism techniques for optimal shaders to improve memory bandwidth efficiency and / or increase processing speed at the GPU.

[0113] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is merely an illustration of the exemplary method. It should be understood that the specific order or hierarchy of the blocks in the process / flowchart can be rearranged based on design preferences. Further, some blocks can be combined or omitted. The attached method claims provide the elements of each block in a sample order, but are not meant to be limited to the specific order or hierarchy provided.

[0114] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be interpreted as being preferred or having advantages over other aspects.

[0115] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” may be interpreted as “and / or” if the context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout the present disclosure that are known or will later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. Words such as "module," "mechanism," "element," and "device" cannot replace the word "component." Therefore, no claim element will be understood as a component plus function unless the element is explicitly stated using the phrase "component for..."

[0116] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. In the event that any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored or sent on a computer-readable medium as one or more instructions or codes.

[0117] According to the present disclosure, the term "or" may be understood as "and / or" in the absence of context dictating otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used with some features disclosed herein but not others, features not using such language may be understood to have such implicit meanings in the absence of context dictating otherwise.

[0118] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. In the case where any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on a computer-readable medium or sent on a computer-readable medium as one or more instructions or codes. Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of a computer program from one place to another. In this way, a computer-readable medium may generally correspond to (1) a non-transient tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices, magnetic disk storage devices, or other magnetic storage devices. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0119] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuit systems. Therefore, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0120] The technology of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs) or IC groups (e.g., chipsets). Various components, modules or units are described in the present disclosure to emphasize the functional aspects of devices configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. On the contrary, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with suitable software and / or firmware. Therefore, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the technology described herein. In addition, these technologies can be fully implemented in one or more circuits or logic elements.

[0121] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0122] Before presenting the graphics content to the allocated video memory, a portion of the memory may need to be cleared to remove the content presented in the previous frame. The application can call an API to perform a clear operation, and the driver can translate this API into a GPU native command for the clear operation. A color value may exist with the clear command (which is called "clear color"). When this clear command is identified, the GPU can rewrite part of the memory with the clear color. In some aspects, the memory can be cleared but not reproduced in the current frame. This can happen when the camera is turned away from the scene or when certain conditions are met, and the application can choose to skip presenting the content as an optimization. This may occur in transient textures, such as in the middle of a 3D rendering pipeline. Such transient textures can be rendered first, and then later used as input textures by another drawing.

[0123] The aforementioned transient textures can be used by TEX (e.g., Figure 6630 in SP 620 in . When a transient texture can be cleared but not presented, TEX can return a clear color. Effectively, the transient texture can be represented by a single value, which is the clear color. Therefore, the TEX operation can be replaced by the clear color as an immediate value. In addition, the associated memory read business can be saved. When the clear color is a certain value (e.g., 0.0), the impact of the replacement may not be local. In this case, several more instructions affected by the TEX load result may also receive a 0 value. The compiler can detect this situation and propagate the impact. In addition, this can reduce the amount of shader instructions.

[0124] In order to replace the TEX operation with an immediate clear color value, the driver can detect the situation where the texture is cleared but not rendered, and let the compiler know the ID and clear color of these textures. The compiler can prepare at least one or more versions of the shader other than the default version. In at least one more version, the compiler can replace the TEX operation with a clear color as a constant, and then propagate the impact when the clear color is 0. During the shader preamble, the shader can obtain the ID and clear color of the "clear but not rendered" texture, decide which shader version to use, and issue the corresponding SSS instruction accordingly. In addition, by utilizing the aforementioned runtime optimization mechanism, there may be performance improvements (e.g., 4% FPS improvement) and workload reduction (e.g., 1% DDR business reduction) by optimizing a single shader. Although the application of the aspects presented herein can focus on constant optimization usage, there are other categories to which the current mechanism can also be applied (e.g., texture descriptors are known at runtime). In some aspects, in the case where the sample instruction is declared to enable the level of detail (LOD), but the LOD is a fixed value (i.e., 0), the hardware can disable pixel promotion due to LOD calculation.

[0125] Aspect 1 is an apparatus for graphics processing, the apparatus comprising at least one processor coupled to a memory and configured to: receive a draw call instruction set corresponding to a graphics workload, wherein the draw call instruction set is associated with at least one runtime parameter corresponding to information available at runtime of the graphics workload; obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing the data in a constant memory; execute the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to a size of the constant memory; and update or maintain a configuration of a shader processor or a stream processor at a graphics processing unit (GPU) based on executing the first shader program or the at least one second shader program.

[0126] Aspect 2 is an apparatus according to aspect 1, wherein the at least one processor is further configured to: store the data in the system memory or the constant memory based on whether the at least one runtime parameter is less than or equal to the size of the constant memory.

[0127] Aspect 3 is an apparatus according to any one of Aspects 1 and 2, wherein when the at least one runtime parameter is greater than the size of the constant memory, the data is stored in the system memory, and wherein when the at least one runtime parameter is less than or equal to the size of the constant memory, the data is stored in the constant memory.

[0128] Aspect 4 is an apparatus according to any one of aspects 1 to 3, wherein the at least one processor is further configured to: load the data from the system memory to the constant memory when the data is stored in the system memory.

[0129] Aspect 5 is an apparatus according to any one of Aspects 1 to 4, wherein the at least one processor is further configured to: check whether the index value is less than the at least one runtime parameter; and if the index value (i) is less than the at least one runtime parameter, increment the index value (i).

[0130] Aspect 6 is a device according to any one of aspects 1 to 5, wherein the at least one second shader program is executed and the data is stored in the constant memory while the index value (i) is incremented.

[0131] Aspect 7 is a device according to any one of Aspects 1 to 6, wherein the at least one processor is further configured to: calculate whether the at least one runtime parameter is less than or equal to the size of the constant memory, wherein the first shader program or the at least one second shader program is executed based on whether the at least one runtime parameter is calculated to be less than or equal to the size of the constant memory.

[0132] Aspect 8 is a device according to any one of Aspects 1 to 7, wherein when executing the first shader program, the configuration of the shader processor or the stream processor is maintained as a first configuration, and wherein when executing at least one second shader program, the configuration of the shader processor or the stream processor is updated to a second configuration.

[0133] Aspect 9 is an apparatus according to any one of aspects 1 to 8, wherein when the first shader program is executed and the configuration of the shader processor or the stream processor is updated, the amount of pixel calculation is reduced.

[0134] Aspect 10 is an apparatus according to any one of aspects 1 to 9, wherein the at least one processor is further configured to: adjust the size of the constant memory based on whether to update or maintain the configuration of the shader processor or the stream processor.

[0135] Aspect 11 is a device according to any one of Aspects 1 to 10, wherein the first shader program is executed when the at least one runtime parameter is greater than the size of the constant memory, and wherein the at least one second shader program is executed when the at least one runtime parameter is less than or equal to the size of the constant memory.

[0136] Aspect 12 is an apparatus according to any one of aspects 1 to 11, wherein one of the at least one runtime parameter is a constant buffer parameter corresponding to the size of the constant memory or the size of a constant buffer.

[0137] Aspect 13 is an apparatus according to any one of aspects 1 to 12, wherein the at least one runtime parameter is associated with a texture filtering mode for the graphics workload.

[0138] Aspect 14 is an apparatus according to any one of aspects 1 to 13, wherein the runtime of the graphics workload is a workload dispatch time at the GPU.

[0139] Aspect 15 is an apparatus according to any one of aspects 1 to 14, wherein the graphics workload is at least one of a pixel workload at the GPU or a computational workload at the GPU.

[0140] Aspect 16 is an apparatus according to any one of Aspects 1 to 15, wherein in order to obtain the first shader program and the at least one second shader program, the at least one processor is configured to: generate the first shader program and the at least one second shader program.

[0141] Aspect 17 is an apparatus according to any one of aspects 1 to 16, wherein the first shader program is a default shader program and the at least one second shader program is an optimized shader program.

[0142] Aspect 18 is an apparatus according to any one of aspects 1 to 17, wherein the system memory is a double data rate (DDR) random access memory (RAM), and wherein the constant memory is a constant RAM or an on-chip memory.

[0143] Aspect 19 is an apparatus according to any one of aspects 1 to 18, wherein the data is constant buffer data associated with the constant memory or constant buffer.

[0144] Aspect 20 is an apparatus according to any one of aspects 1 to 19, wherein the apparatus is a wireless communication device, the apparatus further comprising at least one of an antenna or a transceiver coupled to the at least one processor.

[0145] Aspect 21 is a graphics processing method for implementing any one of aspects 1 to 20.

[0146] Aspect 22 is a device for performing graphics processing, the device comprising means for implementing any one of aspects 1 to 20.

[0147] Aspect 23 is a non-transitory computer-readable medium storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement any one of aspects 1 to 20.

Claims

1. A device for graphics processing, the device comprising: Memory; as well as at least one processor coupled to the memory and configured to: receiving a draw call instruction set corresponding to a graphics workload, wherein the draw call instruction set is associated with at least one runtime parameter corresponding to information available at a runtime of the graphics workload; obtaining a first shader program associated with storing data in a system memory and at least one second shader program associated with storing the data in a constant memory; executing the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to a size of the constant memory; as well as A configuration of a shader processor or a stream processor at a graphics processing unit (GPU) is updated or maintained based on executing the first shader program or the at least one second shader program.

2. The apparatus of claim 1 , wherein the at least one processor is further configured to: The data is stored in the system memory or the constant memory based on whether the at least one runtime parameter is less than or equal to the size of the constant memory.

3. The apparatus of claim 2 , wherein in a case where the at least one runtime parameter is greater than the size of the constant memory, the data is stored in the system memory, and wherein in a case where the at least one runtime parameter is less than or equal to the size of the constant memory, the data is stored in the constant memory.

4. The apparatus of claim 2, wherein the at least one processor is further configured to: In case the data is stored in the system memory, the data is loaded from the system memory to the constant memory.

5. The apparatus of claim 1 , wherein the at least one processor is further configured to: detecting whether the index value (i) is less than the at least one runtime parameter; and In case the index value (i) is less than the at least one runtime parameter, the index value (i) is incremented. 6 . The apparatus of claim 5 , wherein the at least one second shader program is executed and the data is stored in the constant memory in a case where the index value (i) is incremented.

7. The apparatus of claim 1 , wherein the at least one processor is further configured to: The at least one runtime parameter is calculated to be less than or equal to the size of the constant memory, wherein the first shader program or the at least one second shader program is executed based on the at least one runtime parameter being calculated to be less than or equal to the size of the constant memory.

8. The apparatus of claim 1 , wherein in a case where the first shader program is executed, the configuration of the shader processor or the stream processor is maintained as a first configuration, and wherein in a case where the at least one second shader program is executed, the configuration of the shader processor or the stream processor is updated to a second configuration. 9 . The apparatus according to claim 1 , wherein in a case where the first shader program is executed and the configuration of the shader processor or the stream processor is updated, an amount of pixel calculation is reduced.

10. The apparatus of claim 1, wherein the at least one processor is further configured to: The size of the constant memory is adjusted based on whether the configuration of the shader processor or the stream processor is updated or maintained.

11. The apparatus of claim 1 , wherein the first shader program is executed if the at least one runtime parameter is greater than the size of the constant memory, and wherein the at least one second shader program is executed if the at least one runtime parameter is less than or equal to the size of the constant memory. 12 . The apparatus of claim 1 , wherein one of the at least one runtime parameter is a constant buffer parameter corresponding to the size of the constant memory or a size of a constant buffer.

13. The apparatus of claim 1, wherein the at least one runtime parameter is associated with a texture filtering mode for the graphics workload.

14. The apparatus of claim 1, wherein the runtime of the graphics workload is a workload dispatch time at the GPU.

15. The device of claim 1, wherein the graphics workload is at least one of a pixel workload at the GPU or a computational workload at the GPU. 16 . The apparatus of claim 1 , wherein to obtain the first shader program and the at least one second shader program, the at least one processor is configured to: generate the first shader program and the at least one second shader program. 17 . The apparatus of claim 1 , wherein the first shader program is a default shader program and the at least one second shader program is an optimized shader program.

18. The apparatus of claim 1, wherein the system memory is a double data rate (DDR) random access memory (RAM), and wherein the constant memory is a constant RAM or an on-chip memory.

19. The apparatus of claim 1, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein the apparatus is a wireless communication device, and wherein the data is constant buffer data associated with the constant memory or constant buffer.

20. A graphics processing method, the graphics processing method comprising: receiving a draw call instruction set corresponding to a graphics workload, wherein the draw call instruction set is associated with at least one runtime parameter corresponding to information available at a runtime of the graphics workload; obtaining a first shader program associated with storing data in a system memory and at least one second shader program associated with storing the data in a constant memory; executing the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to a size of the constant memory; as well as A configuration of a shader processor or a stream processor at a graphics processing unit (GPU) is updated or maintained based on executing the first shader program or the at least one second shader program.

21. The method according to claim 20, further comprising: The data is stored in the system memory or the constant memory based on whether the at least one runtime parameter is less than or equal to the size of the constant memory.

22. The method of claim 21 , wherein in a case where the at least one runtime parameter is greater than the size of the constant memory, the data is stored in the system memory, and wherein in a case where the at least one runtime parameter is less than or equal to the size of the constant memory, the data is stored in the constant memory, and the method further comprises: In case the data is stored in the system memory, the data is loaded from the system memory to the constant memory.

23. The method according to claim 20, further comprising: detecting whether the index value (i) is less than the at least one runtime parameter; as well as In a case where the index value (i) is less than the at least one runtime parameter, the index value (i) is incremented, wherein in a case where the index value (i) is incremented, the at least one second shader program is executed and the data is stored in the constant memory.

24. The method according to claim 20, further comprising: The at least one runtime parameter is calculated to be less than or equal to the size of the constant memory, wherein the first shader program or the at least one second shader program is executed based on the at least one runtime parameter being calculated to be less than or equal to the size of the constant memory.

25. The method of claim 20, wherein in a case where the first shader program is executed, the configuration of the shader processor or the stream processor is maintained as a first configuration, and in a case where the at least one second shader program is executed, the configuration of the shader processor or the stream processor is updated to a second configuration, and wherein in a case where the first shader program is executed and the configuration of the shader processor or the stream processor is updated, the amount of pixel calculation is reduced.

26. The method according to claim 20, further comprising: The size of the constant memory is adjusted based on whether to update or maintain the configuration of the shader processor or the stream processor, wherein the first shader program is executed when the at least one runtime parameter is greater than the size of the constant memory, and wherein the at least one second shader program is executed when the at least one runtime parameter is less than or equal to the size of the constant memory.

27. The method of claim 20, wherein one of the at least one runtime parameter is a constant buffer parameter corresponding to the size of the constant memory or a size of a constant buffer, wherein the at least one runtime parameter is associated with a texture filtering mode for the graphics workload, wherein the runtime of the graphics workload is a workload dispatch time at the GPU, and wherein the graphics workload is at least one of a pixel workload at the GPU or a compute workload at the GPU.

28. The method of claim 20, wherein obtaining the first shader program and the at least one second shader program comprises: The first shader program and the at least one second shader program are generated, wherein the first shader program is a default shader program and the at least one second shader program is an optimized shader program, wherein the system memory is a double data rate (DDR) random access memory (RAM), and wherein the constant memory is a constant RAM or an on-chip memory, and wherein the data is constant buffer data associated with the constant memory or a constant buffer.

29. A device for graphics processing, the device comprising: means for receiving a draw call instruction set corresponding to a graphics workload, wherein the draw call instruction set is associated with at least one runtime parameter corresponding to information available at runtime of the graphics workload; means for obtaining a first shader program associated with storing data in a system memory and at least one second shader program associated with storing the data in a constant memory; means for executing the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to a size of the constant memory; as well as Means for updating or maintaining a configuration of a shader processor or a stream processor at a graphics processing unit (GPU) based on executing the first shader program or the at least one second shader program.

30. A computer readable medium storing computer executable code for graphics processing, the code when executed by a processor causing the processor to: receiving a draw call instruction set corresponding to a graphics workload, wherein the draw call instruction set is associated with at least one runtime parameter corresponding to information available at a runtime of the graphics workload; obtaining a first shader program associated with storing data in a system memory and at least one second shader program associated with storing the data in a constant memory; executing the first shader program or the at least one second shader program based on whether the at least one runtime parameter is less than or equal to a size of the constant memory; as well as A configuration of a shader processor or a stream processor at a graphics processing unit (GPU) is updated or maintained based on executing the first shader program or the at least one second shader program.

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