Carrier ring with tongues

Abstract

A carrier ring with a tongue for use with a semiconductor processing apparatus is provided. The ring may include a plurality of tongues surrounding an inner periphery of the interior. The ring and tongue may have a plurality of physical characteristics configured to enable backside deposition of more semiconductor substrates compared to rings lacking these physical characteristics. These characteristics of the ring and the tongues may include an inner diameter of the ring, an inner diameter of the tongues, a number of tongues, a width of the tongues, and an angle of the tongues relative to a plane. These characteristics may reduce substrate contact regions and increase deposition regions near the substrate edge, thereby improving uniformity of film thickness.

Description

Incorporated by Reference

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application identified in the concurrently filed PCT application form to which this application claims the benefit or priority is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] The manufacture of semiconductor devices generally involves depositing a stack of multiple layers on a wafer substrate. Deposition and other processing are generally performed on one side of the substrate, which is generally referred to as the front side of the substrate. As the deposited layers accumulate, they may introduce stresses into the substrate. Huge compressive or tensile stresses may cause the substrate to bend, thereby deviating from the plane of the substrate (e.g., the average mid-plane of the semiconductor substrate), which is not desirable. The substrate may be highly sensitive to such deviations. Depositing a film on the back side of the substrate can counteract this bending and increase the deposition area on the same substrate.

[0003] The descriptions of background and context contained herein are provided only for the purpose of presenting the context of the disclosure as a whole. Many of the present inventions are the work of the inventors, and simply because such work is described in the background section or presented as context elsewhere in this article, it does not mean that it will be considered as prior art. Summary of the invention

[0004] In one aspect of the present disclosure, a carrier ring is disclosed. In some embodiments, the carrier ring is configured as a carrier ring for supporting a semiconductor substrate, and the carrier ring includes: a ring having an outer portion and an inner portion, and defining a plane, the inner portion having an inner periphery, the inner periphery having a first diameter of about 298.4 to 299.5 millimeters (mm); and a plurality of inwardly extending tongues disposed around the inner periphery of the inner portion of the ring, the plurality of inwardly extending tongues having an inner edge defining a circle having a second diameter of about 296.0 mm to 298.5 mm.

[0005] In some variations, the first diameter of the inner portion of the ring is approximately 299.0 mm; and the second diameter of the plurality of inwardly extending tongues is approximately 297.0 mm.

[0006] In some variations, the plurality of inwardly extending tabs includes at least 8 inwardly extending tabs.

[0007] In some variations, at least one of the plurality of inwardly extending tabs has a width of approximately 0.5 mm to 1.5 mm.

[0008] In some variations, the width of the at least one of the plurality of inwardly extending tabs is approximately 1.0 mm.

[0009] In some variations, at least one of the plurality of inwardly extending tongues includes at least a portion of a top surface that is not parallel to or perpendicular to the plane but is angled.

[0010] In some variations, the angle of the portion of the top surface is between approximately 5 and 20 degrees relative to the plane.

[0011] In some variations, the top surface of the at least one of the plurality of inwardly extending tongues comprises a minimum contact area (MCA) configured to be in physical contact with the semiconductor substrate.

[0012] In some variations, the outer portion is about 0.3 mm to 0.7 mm thick and the inner portion is about 0.1 mm to 0.5 mm thick.

[0013] In some variations, at least a portion of the plurality of inwardly extending tongues disposed about the inner perimeter of the inner portion of the ring are configured to form one or more conductive grounding points on the semiconductor substrate.

[0014] In some embodiments, the carrier ring is configured to support a semiconductor substrate, and the carrier ring includes: a ring including an interior configured to support the semiconductor substrate during backside deposition on the semiconductor substrate, the ring defining a plane; and 8 to 15 inwardly extending tongues arranged around the interior of the ring and configured to contact the semiconductor substrate during the backside deposition on the semiconductor substrate; wherein at least one of the 8 to 15 inwardly extending tongues has a width of approximately 0.5 mm to 1.5 mm.

[0015] In some variations, the at least one of the 8 to 15 inwardly extending tabs comprises a top surface having an angle of less than about 15 degrees relative to the plane.

[0016] In some variations, the 8 to 15 inwardly extending tongues have an inner edge defining a first diameter of approximately 296.0 mm to 298.5 mm; and wherein the 8 to 15 inwardly extending tongues have an outer edge attached to the ring and defining a second diameter of approximately 298.4 mm to 299.5 mm.

[0017] In some variations, at least a portion of the 8 to 15 inwardly extending tongues are configured to allow one or more conductive grounding points to be formed on the semiconductor substrate.

[0018] In another aspect of the present disclosure, a method for depositing one or more layers on the back side of a semiconductor substrate is disclosed. In some embodiments, the method includes: (a) supporting the semiconductor substrate on a carrier ring, the carrier ring including: a ring having an outer portion and an inner portion and defining a plane, the inner portion having an inner periphery, the inner periphery having a first diameter of about 298.4 millimeters (mm) to 299.5 mm; and a plurality of inwardly extending tongues disposed around the inner periphery of the inner portion of the ring, the plurality of inwardly extending tongues having an inner edge defining a circle having a second diameter of about 296.0 mm to 298.5 mm; and (b) exposing the back side of the semiconductor substrate to a processing condition, the processing condition causing the one or more layers to be deposited on the back side of the semiconductor substrate.

[0019] In some variations, the processing conditions that cause deposition of the one or more layers include exposure to a chemical precursor of at least one of the one or more layers.

[0020] In some variations, at least one of the one or more layers on the back side of the semiconductor substrate includes polysilicon, silicon oxide, silicon nitride, or any combination thereof.

[0021] In some variations, the first diameter of the inner portion of the ring is approximately 299.0 mm; and the second diameter of the plurality of inwardly extending tongues is approximately 297.0 mm.

[0022] In some variations, the plurality of inwardly extending tabs includes at least 8 inwardly extending tabs, at least one of the at least 8 inwardly extending tabs having a width of approximately 0.5 mm to 1.5 mm.

[0023] In some embodiments, at least one of the plurality of inwardly extending tongues includes at least a portion of a top surface that is neither parallel nor perpendicular to the plane but has an angle with respect to the plane, and the angle is between approximately 5 degrees and 20 degrees relative to the plane.

[0024] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A and 1B is a block diagram depicting a substrate processing system for performing a process on a substrate according to some embodiments.

[0026] Figure 2A is a simplified diagram of the locations of the carrier ring and tongues according to some embodiments.

[0027] Figure 2B is the film thickness and Figure 2AA diagram of the relationship between example angular positions of the load-bearing rings.

[0028] Figure 3A is a diagram depicting a semiconductor substrate and various concentric radial points.

[0029] Figure 3B is a map showing a map of exemplary radial data points.

[0030] Figure 3C is a table indicating examples of average deposited film thickness at various radii.

[0031] Figure 3D is a graph that plots the difference between an example maximum average film thickness and a given film thickness at an angular position along a circle defined by a given radius.

[0032] Figure 3E A graph is shown indicating exemplary level differences along angular positions, determined by subtracting an exemplary maximum average film thickness from a given film thickness.

[0033] Figure 4 is a graph indicating exemplary thickness differential variation as a function of radius of a substrate placed on a carrier ring.

[0034] Figure 5A is a simplified diagram depicting components of a substrate processing system according to some embodiments.

[0035] Figure 5B and 5C According to some embodiments Figure 5A Close-up of a cross-section of the load ring.

[0036] Fig. 6A is a perspective view of a carrier ring according to some embodiments.

[0037] Figure 6B According to some embodiments Fig. 6A Top view of the carrier ring.

[0038] Figure 6C According to some embodiments Fig. 6A A close-up top view of the tongue of the load-bearing ring.

[0039] Fig.6D According to some embodiments Figure 6C A three-dimensional image of the tongue.

[0040] Fig. 6E According to some embodiments, Figure 6C Cross-sectional view of the tongue and the load ring.

[0041] Fig. 6FAccording to some embodiments, Figure 6C A cross-section of the cross section without the tongue and of the load ring.

[0042] Figure 7 is a diagram depicting one embodiment having various optimizations associated with at least one tongue of a carrier ring.

[0043] Figure 8 Depicted is a comparison of a prior art carry ring and tongue with an exemplary carry ring and tongue disclosed herein, in a tongue position and a non-tongue position, according to some embodiments.

[0044] Fig. 9 is a diagram of a semiconductor wafer on a carrier ring having a plurality of tongues according to some embodiments.

[0045] Fig.10 is an illustration of a processed wafer that may be clamped on a susceptor chuck according to some embodiments.

[0046] Fig.11 is a flow chart depicting a method of obtaining an apparatus configured to support a semiconductor substrate according to some embodiments.

[0047] Fig.12 is a flow chart depicting a method of depositing one or more layers on a backside of a semiconductor substrate according to some embodiments. DETAILED DESCRIPTION

[0048] The present disclosure relates to carry rings for use in semiconductor processing.

[0049] The dimensions of features (e.g., lines, traces, circuits, etc.) fabricated on a wafer substrate may be susceptible to distortion due to slight positioning or bending deviations of the substrate, since the features (which may reach the nanometer scale) may require precise processing. In addition, such substrates are typically thin and susceptible to internal stresses or tensile / compressive stresses, particularly during the manufacturing process (deposition, etching, heating, layering, etc.). In addition, certain processing steps (e.g., photolithography) are very precise and may produce undesirable results if the substrate is not substantially flat. The problem may manifest as lithography out of focus. For example, in the context of 3D NAND (three-dimensional not-AND) devices, bending is particularly prone to occur where large material stacks are deposited, where 3D NAND is a non-volatile flash memory in which memory cells are stacked in multiple layers. In the case of significant bending, it may have an adverse effect on subsequent processing steps. For example, if the bending is too large, the substrate may not be properly clamped.

[0050] One exemplary stack that may cause these problems is a stack having alternating layers of oxide and nitride (e.g., silicon oxide, silicon nitride, silicon oxide, silicon nitride). Another exemplary stack that may cause bowing includes alternating layers of oxide and polysilicon (e.g., silicon oxide, polysilicon, silicon oxide, polysilicon). Other examples of stack materials that may cause problems include, but are not limited to, tungsten and titanium nitride. The materials in these stacks can be deposited via chemical vapor deposition techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or via direct metal deposition (DMD) and the like. These examples are not intended to be limiting.

[0051] To combat the bowing problem, some techniques involve adjusting the deposition process to reduce or counteract the internal stress in the deposited layer. For example, some methods involve depositing a film on the back side of the substrate, such as using chemical vapor deposition (CVD) to deposit a high stress dielectric film on the back side of the substrate. If the internal stress of the backside film is the same type (tensile or compressive) and comparable in magnitude to the internal stress generated on the front side, the backside film effectively counteracts and corrects the bowing. As a result, the substrate can have a more neutral bow, meaning it will become flatter and less curved.

[0052] In various embodiments, the material deposited on the back side of the substrate can be a dielectric material. In some cases, oxides and / or nitrides (e.g., silicon oxide / silicon nitride) can be used. Examples of usable silicon-containing reactants include, but are not limited to, silanes, halosilanes, and aminosilanes. Silanes contain hydrogen and / or carbon groups, but do not contain halogen. Examples of silanes are silane (SiH4), disilane (Si2H6), and organosilanes, such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di(tert-butyl)silane, allylsilane, sec-butylsilane, tert-hexylsilane, isopentylsilane, tert-butyldisilane, di(tert-butyl)disilane, etc. Halosilanes contain at least one halogen group, and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes are iodosilane, bromosilane, chlorosilane, and fluorosilane. Although halosilanes, particularly fluorosilanes, may form reactive halide species that can etch silicon materials, in some embodiments described herein, no silicon-containing reactants are present when the plasma is ignited. Specific chlorosilanes include silicon tetrachloride (SiCl4), silicon trichloride (HSiCl3), silicon dichloride (H2SiCl2), monochlorosilane (ClSiH3), chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di(tert-butyl)chlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane, and the like. Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are monoaminosilane (H3Si(NH2)4), diaminosilane (H2Si(NH2)2), triaminosilane (HSi(NH2)3) and tetraaminosilane (Si(NH2)4), as well as substituted monoaminosilanes, diaminosilanes, triaminosilanes and tetraaminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2, BTBAS), tert-butyl silylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, etc. A further example of aminosilane is trisilylamine (N(SiH3)3).Other possible silicon-containing reactants include tetraethyl orthosilicate (TEOS), as well as cyclic and acyclic TEOS variants such as tetramethoxysilane (TMOS), fluorotriethoxysilane (FTES), trimethylsilane (TMS), octamethyltetracyclosiloxane (OMCTS), tetramethyltetracyclosiloxane (TMCTSO), dimethyldimethoxysilane (DMDS), hexamethyldisilazane (HMDS), hexamethyldisiloxane (HMDSO), hexamethyltricyclosiloxane (HMCTSO), dimethyldiethoxysilane (DMDEOS), methyltrimethoxysilane (MTMOS), tetramethyldisiloxane (TMDSO), divinyltetramethyldisiloxane (VSI2), methyl Triethoxysilane (MTEOS), dimethyltetramethoxydisiloxane (DMTMODSO), ethyltriethoxysilane (ETEOS), ethyltrimethoxysilane (ETMOS), hexamethoxydisilane (HMODS), bis(triethoxysilyl)ethane (BTEOSE), bis(trimethoxysilyl)ethane (BTMOSE), dimethylethoxysilane (DMEOS), tetraethoxydimethyldisiloxane (TEODMDSO), tetrakis(trimethylsiloxy)silane (TTMSOS), tetramethyldiethoxydisiloxane (TMDEODSO), triethoxysilane (TIEOS), trimethoxysilane (TIMEOS) or tetrapropoxysilane (TPOS).

[0053] Example nitrogen-containing reactants include, but are not limited to, ammonia, hydrazine, amines (e.g., carbon-containing amines), such as methylamine, dimethylamine, ethylamine, isopropylamine, tert-butylamine, di(tert-butyl)amine, cyclopropylamine, sec-butylamine, cyclobutylamine, isopentylamine, 2-methylbutane-2-amine, trimethylamine, diisopropylamine, diethylisopropylamine, di(tert-butyl)hydrazine, and aromatic amines, such as aniline, pyridine, and benzylamine. The amines may be primary, secondary, tertiary, or quaternary (e.g., tetraalkylammonium compounds). Nitrogen-containing reactants may contain heteroatoms other than nitrogen, such as hydroxylamine, tert-butyloxycarbonylamine, and N-tert-butylhydroxylamine are all nitrogen-containing reactants.

[0054] Examples of oxygen-containing reactants include oxygen, ozone, nitric oxide, carbon monoxide, nitrogen oxides, nitrogen dioxide, sulfur oxides, sulfur dioxide, oxygenated hydrocarbons (C x H y O z ), water, mixtures thereof, etc.

[0055] In recent semiconductor processing equipment, a substrate may be located on a pedestal during semiconductor processing operations. The pedestal may be a so-called shower pedestal, which is a pedestal-like structure with a large number of gas distribution ports distributed throughout its upper surface (just as there are many gas distribution ports distributed throughout the bottom of a showerhead). The gas distribution ports may be fluidly connected to one or more plenums located within the shower pedestal. The one or more plenums may further be fluidly connected to one or more process gas sources, which are controllable to allow process gas to flow out of the shower pedestal through the gas distribution ports.

[0056] The semiconductor processing tool may also have one or more carrier ring supports that may be configured to support a carrier ring, which may further support a substrate during processing operations. The one or more carrier ring supports may be designed to allow the carrier ring and any substrate supported thereby to be held in an elevated position above the shower pedestal such that a gap exists between the shower pedestal and the substrate to which processing gas can be delivered. Thus, the semiconductor processing tool allows the bottom side of the substrate to be affected by substrate processing operations, rather than the top side of the substrate, thereby allowing films to be deposited on the back side of the substrate.

[0057] However, the carrier ring may include tabs that block backside film deposition on areas of the substrate that overlap these tabs. It is desirable to maximize or optimize the available deposition space to allow for the fabrication of additional or larger components. Even adding just a few square mm on the backside of a 200 mm, 300 mm, or 450 mm substrate can improve the space efficiency of manufacturing.

[0058] Therefore, what is desired is a carrier ring whose physical features balance the size, shape, number and other parameters associated with the tongues of the carrier ring.

[0059] The following terms are used throughout this specification:

[0060] As used herein, "wafer bow" may refer to deformation of a wafer. Wafer bow may occur during manufacturing, such as due to stress during deposition of material on the active surface of a wafer substrate. Wafer bow may occur during various types of manufacturing, such as when depositing large material stacks. Wafer bow may cause complications in subsequent processing steps. For example, if the amount of bow is too large, the wafer may not be properly clamped. In addition, if certain processing steps (e.g., photolithography) are performed on an excessively bowed wafer, undesirable results may occur.

[0061] Wafer bow can be measured as the deviation of the average or median distance of the surface of the wafer from a reference plane. The median surface point of the wafer can be the center point of the wafer (e.g., in the case of concave bow or dome bow) or an edge point and / or the average edge point of the wafer (e.g., in the case of warp or convex bow).

[0062] As used herein, "platform" refers to the top surface of an electrostatic chuck (ESC) on which a wafer being manufactured is placed. There may be a gap between the wafer and the platform surface (eg, upper surface), which is generally referred to herein as "d".

[0063] As used herein, "base" may refer to a structure or housing that supports or includes the platform.

[0064] The terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" may be used interchangeably. It will be understood by one of ordinary skill in the art to which the present invention pertains that the term "partially fabricated integrated circuit" may refer to a semiconductor wafer during any of a number of stages of integrated circuit fabrication being performed thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm, or 450 mm. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles of manufacture, such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components (such as backplanes for pixelated display devices), flat panel displays, micromechanical devices, and the like. The workpiece may be of various shapes, sizes, and materials.

[0065] As used herein, "semiconductor device manufacturing operations" are operations performed during the manufacture of semiconductor devices. As mentioned herein, such manufacturing operations are sometimes referred to as "processing" or "machining". Examples of processing include depositing materials on a substrate, selectively etching materials from a substrate, and ashing of photoresists on a substrate. Typically, the entire manufacturing process includes multiple semiconductor device manufacturing operations, each of which is performed in its own semiconductor manufacturing tool (e.g., a plasma reactor, an electroplating tank, a chemical mechanical planarization tool, a wet etching tool, etc.). Categories of semiconductor device manufacturing operations include subtractive processing, such as etching processing and planarization processing, and additive processing, such as deposition processing (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etching processing, substrate etching processing includes the processing of etching a mask layer, or more broadly, the processing of etching any material layer previously deposited and / or otherwise residing on the substrate surface. Such etching processing can etch a stack of multiple layers in a substrate.

[0066] "Fabrication equipment" refers to equipment in which manufacturing processes are performed. Fabrication equipment typically has a processing chamber in which a workpiece resides during processing. Typically, when in use, the fabrication equipment performs one or more semiconductor device fabrication operations. Examples of fabrication equipment for semiconductor device fabrication include deposition reactors, such as plating tanks, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive processing reactors, such as dry etch reactors (e.g., chemical and / or physical etch reactors), wet etch reactors, and ashers.

[0067] When referred to herein, the manufacturing equipment is sometimes referred to simply as a "processing chamber". In various embodiments, the processing chamber is generally a sealed enclosure in which the substrate is fixed during processing. The processing chamber may include components related to the delivery and removal of gases. It may also include components related to the generation of plasma in the chamber and the control of the properties of the plasma. It may include components for controlling pressure, including evacuating the chamber. In the context of the present disclosure, the processing chamber may include a pedestal on which the substrate is located when processing is performed. The pedestal may be equipped with a chuck such as an ESC to hold the substrate in place during processing. Substrate handling system

[0068] Figure 1A 1 is a block diagram depicting a substrate processing system 100 for performing processing on a substrate 128 (also referred to as a wafer) according to some embodiments. As shown, the substrate processing system can include a chamber 102. A central column can be configured to support a pedestal when processing the top surface of the substrate 128 (e.g., forming a film on the top surface of the substrate 128), or when processing on the back side of the substrate 128. In some embodiments disclosed herein, the pedestal can be referred to as a showerhead pedestal 106. The showerhead 104 can be disposed above the showerhead pedestal 106.

[0069] In some embodiments, the showerhead 104 can be electrically connected to the power supply 122 through the matching network 125. The power supply 122 can be controlled by the control module 120 (e.g., a controller). In some embodiments, power can be provided to the showerhead pedestal 106 instead of the showerhead 104. The control module 120 can be configured to operate the substrate processing system 100 by executing process inputs and controls for a particular process recipe. Depending on whether the top surface of the substrate 128 is receiving the deposited film or the bottom surface of the substrate 128 is receiving the deposited film, the control module 120 can set various operating inputs for the process recipe, such as power levels, time parameters, process gases, mechanical movement of the substrate 128, and / or the height of the substrate 128 relative to the showerhead pedestal 106.

[0070] In some embodiments, the central column may also include lift pins that are controlled by lift pin controls. These lift pins may be used to lift the substrate 128 from the showerhead base 106, allowing the end effector (not shown) to pick up the substrate 128, and to lower the substrate 128 after the end effector places the substrate 128. The end effector may also place the substrate 128 over the spacer 130. As described below, the size of the spacer 130 may be designed to provide a controlled substrate separation between the top surface of the showerhead 104 (facing the substrate 128) and the top surface of the showerhead base 106 (facing the substrate 128).

[0071] In some embodiments, the substrate processing system 100 may further include a first gas manifold 108 connected to a first gas source 110 (e.g., a gas chemical supply and / or an inert gas from a facility). The control module 120 may control delivery of the first gas source 110 through the first gas manifold 108 in accordance with the process being performed above the top surface of the substrate 128. The selected gas may then be flowed into the showerhead 104 and distributed in the volume of space defined between the faces of the showerhead 104 facing the substrate 128 when the substrate 128 is positioned above the susceptor.

[0072] In some embodiments, the substrate processing system 100 may further include a second gas manifold 112 connected to a second gas source 114 (e.g., a gas chemical supply and / or an inert gas from a facility). The control module 120 may control the delivery of the second gas source 114 through the second gas manifold 112 in accordance with the processing performed above the bottom surface of the substrate 128. The selected gas may then be flowed into the showerhead 104 and distributed in the volume of space defined between the faces of the showerhead base 106, wherein the faces face the lower surface or lower side (e.g., backside) of the substrate 128 when the substrate 128 is located above the spacer 130. The spacer 130 may be provided for a spacing that optimizes deposition on the lower surface of the substrate 128 while reducing deposition on the top surface of the substrate 128. In some embodiments, while deposition is directed to the lower surface of substrate 128, an inert gas may flow over the top surface of substrate 128 via showerhead 104, thereby pushing reactant gases away from the top surface and enabling reactant gases from showerhead pedestal 106 to be directed to the lower surface of substrate 128.

[0073] In addition, these gases may or may not be premixed. Appropriate valves and mass flow control mechanisms may be used to ensure that the correct gases are delivered during deposition and plasma processing of the process. The process gases may leave the chamber 102 via an outlet. A vacuum pump (e.g., a one-stage or two-stage mechanical dry pump and / or a molecular pump) may draw out the process gases and maintain an appropriate low pressure within the reactor through a closed loop controlled flow restriction device (e.g., a throttle valve or a pendulum valve).

[0074] In some embodiments, the carry ring 124 can surround an outer region of the showerhead base 106. When the top surface of the substrate 128 is being processed, such as when a material is being deposited thereon, the carry ring 124 can be configured to be located above a carry ring support area that is located one step below the wafer support area in the center of the showerhead base 106. The top surface of the carry ring 124 is generally coplanar with the top surface of the substrate 128. The carry ring 124 can include an outer edge side of its disk structure, such as an outer radius, and a wafer edge side of its disk structure, such as an inner radius closest to where the substrate 128 is located. The carry ring 124 can be associated with an inner diameter (ID). The inner diameter can extend to the inner periphery of the carry ring and generally surround a substrate (e.g., substrate 128) in the processing chamber. The wafer edge side of the carry ring 124 can also include a plurality of contact support structures or "tongues" that can be configured to lift the substrate 128 when the carry ring 124 is held by the spacer 130. The carrier ring 124 may include a plurality of tongues, the number of which is selected within a certain range (e.g., below Figure 2A 1 and 2) to support the substrate 128 during processing. Additional details regarding the implementation of the tongues will be described later.

[0075] Figure 1B 1 is a block diagram depicting another substrate handling system 150 for processing a substrate 128 according to some embodiments. In some embodiments, a spider fork 132 may be used to elevate a carrier ring 124 and maintain the carrier ring 124 at its processing height, e.g., to allow deposition in the lower surface (backside) of the substrate 128. Thus, the carrier ring 124 may be elevated along with the substrate 128. In some implementations, the carrier ring 124 may be transferred to another station in a multi-station system, for example. Film thickness variation

[0076] Figure 2Ais a simplified diagram of the positions of the carrier ring 200 and the tongues 202 according to some embodiments. In some embodiments, six tongues 202 can be arranged around the inner periphery of the carrier ring 200. The tongues of the carrier ring create "shadows" where the backside deposition layer is not deposited on a substrate placed on the carrier ring, or the backside deposition layer is deposited to a lesser extent than in the areas outside the shadows of the tongues.

[0077] In some embodiments, the carrier ring 200 can have an inner dimension 204, such as 299.0 mm. In some embodiments, there can be a notch tab 206. The notch tab 206 can help prevent the plasma from reaching the front side of the substrate, as the substrate typically includes a wafer notch, which can be susceptible to leakage. The notch tab 206 can help align the semiconductor substrate with the carrier ring so that the substrate is in a desired orientation before processing (e.g., for the aforementioned plasma blocking). Processing can result in, for example, deposition of a film in the back side of the substrate, as described elsewhere herein.

[0078] Figure 2B is a graph of film thickness versus exemplary angular position of the carrier ring 200. The film thickness may be non-uniform across the substrate surface. Specifically, at Figure 2A The thickness of the deposited film is relatively low at the six corner positions corresponding to the positions of the six tongues 202. In this case, the six tongues significantly reduce the film thickness at the edge of the substrate, as shown in box 220.

[0079] like Figure 2A and 2B As shown, the deposition barrier created by tongue 202 provides an opportunity to increase deposition volume, for example, by allowing more process gas to diffuse under the tongue. Increasing deposition volume has advantages, such as using more of the substrate during processing (reducing shadowing effects, and space and cost efficient use of "real estate") and / or reducing impedance variations at the carrier ring.

[0080] Figure 3A 3 is a diagram depicting a semiconductor substrate 300 and its various concentric radial points. For example, a first radial point 302 is 1 mm from the center point of the semiconductor substrate 300, and a second radial point 304 is 1 mm from the center point. 17 mm. The third radial point 306 is 6 mm away from the center point. Figure 3A It can be seen that between the aforementioned r1 to r 17 Various other radial points within the radius. In one scenario, thickness variations and local deviations from flatness occur primarily starting at a radius of r1 mm. r1, r6 and r 17represents the radius from the center point of the semiconductor substrate 300. Example values ​​of these radii may range from 120 mm to 148.2 mm, but various values ​​and ranges (eg, lower than 120 mm and / or higher than 148.2 mm) may be evaluated depending on the semiconductor substrate and its implementation.

[0081] Figure 3B 3 is a map 310 showing a map of exemplary radial data points defined by xy coordinates, with the center being located at an origin 312 of a circle corresponding to the shape of semiconductor substrate 300 . Figure 3B We can also see that the radius r 17 The second radial point 304 of mm.

[0082] Figure 3C 320, which indicates examples of average deposited film thickness at various radii. For example, at a radius of r6 mm, assume that the average deposited thickness is determined to be 6138 arbitrary units (e.g., nanometers (nm)). The film thickness can be measured using conventional methods or measurement tools (e.g., spectroscopic ellipsometry, thickness monitors, interferometers, surface profilers, or scanning electron microscopes). It is noteworthy that in this example, r6 = 6138 arbitrary units is the average thickness from r1 mm to r 17 The highest of all average thicknesses measured with a radius of mm.

[0083] Figure 3D is a graph 330 depicting the difference between an exemplary maximum average film thickness 332 and a given film thickness 334 at an angular position along a circle defined along a given radius of the carrier ring. Figure 3D In the example, select r 17 The radius of mm, i.e., the outermost radius measured, is compared with the exemplary maximum average film thickness 332 (r6). The graph 330 shows the exemplary maximum average film thickness 332 as a dashed line to indicate the data points (e.g., corresponding to Figure 3B The solid line of the map 310 shown in FIG. 3 represents a given film thickness 334, where the data points correspond to the thickness measured at the corresponding radial position (expressed in degrees). The given film thickness 334 represents the thickness of the film when the tongue (e.g., Figure 2A The thickness at the angular position corresponding to the tongue 202 in the middle may be relatively low. The figure also depicts r6 mm and r 17 Simplified diagram 340 of two radii of mm.

[0084] Using the aforementioned data, such as data points associated with map 310, data points associated with table 320, and / or data points associated with graph 330, a "level difference" (D) between the maximum average film thickness and a given film thickness 334 can be measured. Existing measurement techniques may only measure a percentage of non-uniformity or an average film thickness, thereby providing a comprehensive measure of uniformity. The level difference can indicate the variation in film thickness at discrete points and can more clearly indicate the severity of a wide range of thicknesses. Figure 3E A graph 350 is shown indicating exemplary level differences along angular positions determined by subtracting an exemplary maximum average film thickness 332 from a given film thickness 334. The solid line 351 representing the level differences clearly emphasizes the differences between those angular positions corresponding to the tongues where the peaks 354 are located.

[0085] Performing lithography or other downstream processes that rely on substrate uniformity (where there is little or no deviation from true flatness at any location on the substrate) may introduce errors, especially in areas of the substrate where less backside material is deposited. Therefore, it is desirable to keep the level difference below a certain amount. In some exemplary applications, it may be specified that the level difference should be kept below an arbitrary unit of a specified amount, such as below the dashed line 352. One such example may be 700nm. The aforementioned level difference is measured as a "level difference" problem that exceeds a certain amount (e.g., a peak 354 at the location of the tongue, where D exceeds the dashed line 352 or another threshold level) and can indicate that the resulting substrate has non-uniform film deposition and / or potential deposition that is not achieved at the tongue location. In some cases, depending on the application, the configuration (e.g., number, physical shape) of the tongue and / or the carrier ring, and / or the curvature caused by processing, a level difference exceeding a certain amount (e.g., dashed line 352) may result in yield loss and / or slower substrate processing (e.g., slower lithography processing), which may be expensive, time-consuming and therefore undesirable results.

[0086] also, Figure 4 4 is a graph 400 indicating an exemplary thickness differential variation associated with the radius of a substrate placed on a carrier ring. As shown, the film thickness relative to a central portion of the substrate (e.g., a radius greater than r1 mm) can decrease as the radius approaches the edge of the distal end of the substrate (e.g., near r 17 mm radius) and decreases more rapidly (the "derivative" of the thickness change). Portions of the carry ring (e.g., portions that may be adjacent to the substrate) may physically at least partially block the reaction with, for example, the deposition gas. In some cases, the thickness may drop to zero at the exact edge of the substrate (e.g., at r 边缘In addition to the aforementioned problem of level differences causing spikes at the tongue location (thickness variation related to radial position), the thickness drop near the edge of the substrate (the "edge effect" of thickness variation related to radial distance) may also cause film thickness non-uniformity. However, during substrate processing, it is desirable to keep the film thickness consistent over the entire radius.

[0087] Thus, the present disclosure describes optimized carry rings and associated structures (eg, tongues) that, among other things, minimize substrate contact area (which increases deposition area near the substrate edge, thereby increasing film thickness uniformity), and minimize such edge effects. Carrier ring configuration

[0088] Figure 5A 5 is a simplified diagram that depicts components of a substrate processing system 500 according to some embodiments. In some embodiments, the substrate processing system 500 can be an example of the substrate processing system 100 or 150. The substrate processing system 500 can include a showerhead 502 disposed above a showerhead base 504. A carrier ring 506 can be disposed between the showerhead 502 and the showerhead base 504 and can be an annular structure. Figure 5A A cross section of a carrier ring 506 is shown having a cross section portion 506a (also labeled "A") and a cross section portion 506b (also labeled "B"). The cross section portions may have symmetry; the dimensions of the cross section portions may apply substantially equally to each cross section. For example, cross section portion 506a may measure a thickness of about 0.1 to 0.5 mm (e.g., 0.3 mm in some embodiments) all around the carrier ring 506, while cross section portion 506b may measure a thickness of about 0.3 to 0.7 mm (e.g., 0.5 mm in some embodiments) all around the carrier ring 506. The carrier ring 506 may have an inner diameter (ID) 508 and an outer diameter (OD) 510 that allow a substrate (e.g., a wafer 512) to be placed on the carrier ring 506, such as above the "A" portion and adjacent to the "B" portion. The wafer 512 may be round to fit the carrier ring 506. A plasma 514 may be formed or extinguished below the wafer 512.

[0089] In some embodiments, the ID 508 of the carrier ring may be selected to have a diameter of 298.4 mm to 299.5 mm. For example, in some cases, the ID 508 of the carrier ring may have a diameter of 299.0 mm. Thus, using a carrier ring with an ID of 299.0 mm, a wafer with a diameter of 300 mm may be placed on the carrier ring 506 and expose a substantial portion of the back surface of the wafer for processing (backside deposition, etching, etc.).

[0090] Figure 5B and5C is a close-up view of a cross-sectional portion of a carrier ring 506 according to some embodiments. Figure 5B As shown, in some parts of the carrier ring 506, the inner diameter includes a tongue 506c. In some embodiments, the tongue 506c can be a support structure for the wafer 512. For example, the tongue 506c can prevent the wafer 512 from falling from the carrier ring 506. In some implementations, the tongue 506c can have an inclined or tapered surface, forming an angle 520 with one or more of the top surfaces 516a, 516b of the cross-sectional portions 506a, 506b. In various embodiments, the angle 520 may not be parallel or perpendicular to the plane associated with the top surface 516a or 516b (or both). In some cases, the angle 520 may be between about 5 degrees and 20 degrees, such as about 15 degrees or less, such as about 11.1 degrees, from the plane 518 defined by the top surface 516a. The top surface 516a (the tongue extends inwardly from it) can interface with the wafer 512 (e.g., supported by physical contact).

[0091] In some implementations, a plurality of tongues may be disposed around the inner diameter of the carrier ring 506. In addition, the plurality of tongues may be inwardly extending tongues, the outer edges of which are attached to the ring and define the inner diameter. In some cases, the inner diameter may be selected from a range of 296.0 to 299.5 mm, such as 297.0 mm. The number of the plurality of tongues may be selected (e.g., at least 8, or the number may be selected from a range of at least 5 to a maximum of 15, or at least 8 to a maximum of 15, such as 12) to ensure that the wafer 512 does not fall off the carrier ring 506 (e.g., in the event that one or more tongues are deformed or broken), nor does it cause the wafer 512 to tilt when the wafer 512 is placed on the carrier ring 506. It is critical to keep the wafer completely level, because processing on a tilted wafer may render the resulting deposition, etching, etc. partially or completely unusable. For example, a good lithography image may not be obtained; for example, line width may be lost. If the number of tongues is less than a certain number (e.g., 3 or 4), the carrier ring 506 may still be at risk of tilting or falling, for example, when being moved. If the number of tongues exceeds a certain number (eg, 15), excessive diminishing returns may be introduced due to unnecessary blocking of surface area (eg, for backside deposition) and / or unnecessary carry ring 506 manufacturing costs.

[0092] like Figure 5C As shown, in some portions of the carrier ring 506, the inner diameter does not have a tongue, such as the portion having a relatively non-tapered surface as shown in cross-sectional portion 506a. However, in some embodiments, cross-sectional portion 506a may have a beveled portion 522. The location of the tongue, for example Figure 5B The position shown may have a beveled portion that continues into the tongue 506c.

[0093] Fig. 6A is a perspective view of a carrier ring 600 according to some embodiments. In some embodiments, the carrier ring 600 may be Figure 5A An example of a carrier ring 506 is depicted. Carrier ring 600 can have an inner diameter 602 measured from one end of inner perimeter 604 to an opposite end of inner perimeter 604. Inner perimeter 604 can be defined by an inner wall of an interior of carrier ring 600, wherein cross-sectional portion 506a is an example of the interior. In some implementations, inner diameter 602 can be selected from a range of 298.4 mm to 299.5 mm. An example of inner diameter 602 can be 299.0 mm.

[0094] Figure 6B 600 according to some embodiments. The inner diameter 602 of the carrier ring 600 can extend between opposite ends of the inner periphery 604, such as Fig. 6A In some embodiments, a plurality of inwardly extending tongues (e.g., tongue 606) may be disposed around the inner periphery 604 of (the interior of) the carrier ring 600 and separated by tongue-free locations 607. The majority of the inner periphery does not have tongues and may have a configuration such as Figure 5C Tongue-less cross-section configuration shown.

[0095] In various implementations of the carrier ring 600, 5 to 15 tongues may extend inwardly from the inner periphery 604 of the carrier ring 600. For example, in one such implementation, 12 tongues may be disposed around the inner periphery 604. In some cases, the tongues may be spaced apart at substantially equal distances from one another. However, in some cases, the tongues may be spaced apart at specified positions, wherein the positions are at unequal distances from one another. For example, the tongues may be grouped, such as placed in pairs at six equidistant and / or equiangular positions. In other cases, there may be other grouping schemes, such as three, four, or six groups of equal number, or groups of unequal number.

[0096] Figure 6C is a top view close-up of tongue 606 according to some embodiments. Fig.6D is a perspective view of tongue 606 according to some embodiments. In some embodiments, tongue 606 extends or protrudes inward to at least partially support or provide support for a semiconductor substrate (eg, wafer 512). Fig. 6E According to some embodiments, Figure 6C A cross-sectional view of the tongue 606 and the carrier ring 600 of cross section AA.

[0097] In some embodiments, the tongue 606 may have an inclined top surface that forms an angle with the plane defined by the top surface of the inner periphery 604. In some implementations, the angle may be about 11.1 degrees. The angle may be selected from a range, such as between 5 degrees and 20 degrees (including the endpoints), or between 10 degrees and 12 degrees (including the endpoints). In other implementations, the angle may be neither parallel nor perpendicular to the plane, for example, an angle of less than 15 degrees or less than 10 degrees may be selected with the plane. The inclined surface of the tongue may allow, for example, deposition gas to reach the back surface of the substrate. In some cases, some tongues may have different angles from each other. For example, at least one of the tongues may be inclined to form 11.1 degrees with the plane, and at least another of the tongues may be inclined to form 5 degrees with the plane. In some cases, the angle may be inclined without being consistent over the length of the entire tongue. The angle may be measured at the base of the tongue, i.e., at the position closest to the inner diameter of the carrier ring. In some cases, some of the tongues may not have an inclined top surface, in which case the non-inclined tongues may be disposed at a lower height relative to the inclined tongues to prevent the non-inclined tongues from directly contacting the substrate.

[0098] In some embodiments, the inner diameter of the tongue can be selected from a range of 296.0 mm to 299.5 mm, such as 297.0 mm. In some cases, the inner diameter of the tongue can be defined by the inner edge of a circle defining the tongue; that is, the inner edge defining the circle can have a diameter of 296.0 to 299.5 mm, such as about 296.0 to 298.5 mm, such as 270.0 mm. In some embodiments, the tongue 606 can have a maximum length of 10.0 mm (e.g., Fig. 6E In other words, in some implementations, the tongue 606 can have a length 608 less than 10.0 mm, such as 2.0 mm, 1.5 mm, or 1.0 mm. In some cases, the lengths of some tongues can be different from each other. For example, at least one of the tongues can have a length of 2.0 mm, while at least another of the tongues can have a length of 1.5 mm.

[0099] In some embodiments, tongue 606 can have a maximum width of 2.0mm. In other words, in some implementations, tongue 606 can have a width less than 2.0mm, such as between 0.5 and 1.5mm, such as 1.0mm. In some embodiments, tongue 606 can have a minimum width of about 0.5mm. In some cases, some tongues can have widths different from each other. For example, at least one of these tongues can have a width of 1.0mm, and at least another of these tongues can have a width of 0.7mm. In some cases, the width in the length direction of the entire tongue may be uneven. The width may be measured at the terminal end of the tongue, and the width of the tongue can be wider or narrower than 1.0mm, for example, along the length direction.

[0100] Fig. 6F According to some embodiments, Figure 6C FIG. 6 is a cross-sectional view of a cross-section BB without a tongue position 607 and a cross-sectional view of a carrier ring 600. In some embodiments, the inner periphery may include a beveled portion located at at least one edge, such as Figure 5C The beveled portion 522 is shown in FIG.

[0101] In different implementations of the carrier ring 600 or the inwardly extending tongues (e.g., tongues 606), the number of tongues, the angle of the tongues, the inner diameter of the carrier ring, the length of the tongues, and / or the width of the tongues may be selected depending on the type of gas used, the presence of plasma, the need for plasma real estate, and / or the application. The above dimensions may be summarized as follows.

[0102] In some embodiments, the inner diameter of the carrying ring 704 can be selected from a range of about 298.4mm to 299.5mm, for example 299.0mm. In some embodiments, the carrying ring 704 can include a plurality of tongues (one of which is shown). In some implementations, the inner diameter of these multiple tongues can be selected from a range of 296.0mm to 299.5mm, for example 297.0mm. In some implementations, the number of the multiple tongues can be selected from a range of at least 5 to a maximum of 15 (e.g., 12), above which the benefits of the tongues may be diminishing. In some embodiments, the width of at least one tongue 702 can be 0.5mm to 2.0mm, for example a width of 1.0mm. In some embodiments, the length of at least one tongue 702 can have a maximum length of about 10.0mm. In some embodiments, the downward inclination angle between the top surface of at least one tongue 702 can be selected from a range of less than 15 degrees, for example 11.1 degrees. Figure 7 is a diagram depicting one embodiment having various optimizations associated with at least one tongue 702 of a carrier ring 704 .

[0103] The aforementioned physical characteristics of the aforementioned carrier ring 704 and / or at least one tongue 702 of the carrier ring 704 may in some cases represent a reduction or increase in some dimensions or parameters of the tongue and the carrier ring. For example, the tongue may have a larger inner diameter, and the width and / or length of the tongue may be reduced, and / or the tongue may include an inclined portion to accommodate more deposition by allowing more processing gas to reach the backside area. In addition, the carrier ring may have a larger inner diameter to minimize edge effects. However, smaller tongues and larger inner diameters may increase the risk that the substrate held and supported by the carrier ring 704 may become unstable and prone to tilting. For example, the risk of tilting may be greater when the substrate is nested on the carrier ring, or the risk of falling from the inner periphery of the carrier ring may be greater. Therefore, in order to further accommodate potential risks, the number of tongues may be increased (e.g., to 12) to prevent the occurrence of such risks.

[0104] As an exemplary embodiment, at least one tongue 702 can have a width of about 1.0 mm, a length of about 2.0 mm, and a downward inclination angle measured at about 11.1 degrees. In addition, the carrier ring 704 can have an inner diameter of about 299.0 mm, and 12 tongues arranged substantially equidistantly and / or substantially equiangularly.

[0105] In other examples, the aforementioned considerations can be balanced. Consider an embodiment in which a width is selected to be slightly smaller (e.g., a width of 0.8 mm). In order to accommodate smaller tongues, the number of tongues can be increased (e.g., to 14 or 15) to ensure that the substrate does not fall or tilt. Next, consider another embodiment that preferentially uses a smaller inner diameter (e.g., 298.5 mm). Considering the increased stability of the substrate, the angle can be greatly increased to ensure that the processing gas reaches the tongue area. Each of these embodiments, as well as a large number of other combinations of these ring and tongue characteristics can help reduce horizontal differences, minimize the contact area of ​​the substrate (e.g., the minimum contact area as described below), and ultimately minimize edge effects (e.g., softening the transition of film thickness relative to radial distance) and achieve consistent film thickness. Furthermore, minimizing the substrate contact area based on the aforementioned physical characteristics of the tongues (including the selection of the inner diameter of the carrier ring, the inner diameter of the tongues, the number of tongues, the width of the tongues, the downward tilt angle of the tongues, or a combination thereof) can achieve more backside deposition on the substrate (e.g., the substrate location corresponding to the tongues) compared to another carrier ring (which has tongues lacking these physical characteristics). For example, the tongues of another carrier ring (lacking the aforementioned physical characteristics) would be larger, thereby reducing backside deposition. Figure 7 Increasing the inner diameter of at least one tongue 702 versus decreasing the width of the at least one tongue 702 is indicated.

[0106] Figure 8 A comparison of existing carrier rings and tongues according to some embodiments and exemplary carrier rings and tongues disclosed herein, in tongue positions and tongueless positions, is depicted. In some embodiments, the exemplary carrier ring and tongue 806a can be characterized by a smaller minimum contact area (MCA) 808 compared to prior art embodiments 802a and 804a. MCA can refer to an area of ​​a carrier ring (e.g., the top surface of the interior of the carrier ring) that can interface with (e.g., physically contact and / or support) a substrate (e.g., wafer 810). It is desirable to reduce or minimize the MCA, for reasons such as increasing the deposition area on the back side of the wafer 810 and reducing particles. Particles can refer to foreign matter (e.g., dust particles) that hinder deposition, etching, or other processing performed on the wafer 810, and these particles may originate from other surfaces (e.g., the carrier ring) or be caused by contact with other surfaces. Therefore, the generation of particles can be minimized by reducing the contact area with the carrier ring.

[0107] In some embodiments, the exemplary carrier ring and tongue 806a can be characterized by having an inclined tongue portion 812. In some implementations, the inclination can be at an angle of less than 15 degrees (e.g., about 11.1 degrees), where the angle is measured relative to a plane 814 defined by the top area of ​​the interior of the carrier ring. The inclined tongue portion 812 can terminate at an end having a predetermined height (e.g., about 0.09 mm). In some variations, this height can vary depending on the geometry and physical properties of the tongue (e.g., the angle of inclination, the inner diameter or length of the tongue).

[0108] In contrast, in the prior art embodiments 802a and 804a, the MCA can be significantly larger. In addition, there can be no tilt at the tongue. Therefore, the wafer 810 can have more contact with the carrier ring.

[0109] In some embodiments, the tongue-free position and tongue 806b of the exemplary carrier ring can further reduce the MCA by, for example, reducing the inner diameter 818 of the carrier ring (e.g., relative to one or more of the existing embodiments 802b, 804b). In some embodiments, the thickness of the carrier ring can also be reduced. In some implementations, the thickness of the inner and outer portions of the carrier ring can be approximately 0.3 mm and 0.5 mm, respectively. The smaller thickness of the inner and outer portions can help adjust or match the impedance of the wafer, thereby achieving more uniform deposition and minimizing the aforementioned edge effects. Dorsal foundation

[0110] Fig. 99 is a diagram of a semiconductor wafer 900 on a carrier ring 902 having a plurality of tongues according to some embodiments. The back side of the semiconductor wafer 900 and the carrier ring are depicted to illustrate one tongue 904 of the plurality of tongues. In some embodiments, some or all of the plurality of tongues may be, for example, as described above with respect to FIG. 5A to FIG. 8 An example of the tongues extending inwardly as described above. In other words, the tongues can have physical properties (e.g., tongue ID, smaller width, tilt angle, etc.) selected from the above-specified ranges. When the semiconductor wafer 900 is supported by the carrier ring 902 and the tongues (including the tongue 904), it can be processed (backside deposition, etching, etc.).

[0111] It should be understood that the foregoing applies equally to some or all of the tongues that may be present on the carrier ring 902. According to some embodiments, there may be up to 6, 8, 12, or 15 tongues, some or all of which may have different shapes and sizes. FIG. 5A to FIG. 8 The physical properties described in the embodiments.

[0112] Fig.10 is a processed wafer 900' (e.g., from Fig. 9 ), the wafer may be clamped on a pedestal chuck 1002 (e.g., an ESC). During subsequent processing of the processed wafer 900', one of the potential causes of failure is that charge may accumulate when the back side of the processed wafer 900' is fully coated. This may cause harmful effects. For example, electrons may be diverted due to the application of the electron beam 1004.

[0113] However, as described herein (including Fig. 9 ), some shadowing effects may remain from the tongue and / or inner periphery of the carrier ring 902. By retaining some undeposited areas under the tongue of the carrier ring, a clear conductive path 1006 is provided as a conductive grounding point between the pedestal chuck 1002 and the processed wafer 900'. In some embodiments, as a result of retaining multiple undeposited areas under the tongue of the carrier ring, multiple conductive grounding points may exist (e.g., one conductive grounding point or area for each carrier ring tongue).

[0114] Since the larger the ground path, the less backside deposition, the shielding effect caused by the tongue can be an additional factor used to balance the aforementioned considerations. Other considerations that need to be balanced may include increasing the deposition area, reducing the level difference, preventing front side deposition while allowing back side deposition, in order to prevent the processed wafer 900' from tilting or falling off the inner periphery of the carrier ring.

[0115] For example, depending on the application or desired results, some embodiments of the carrier rings and tongues described herein may balance the desirability of reducing level differences or reducing MCA (e.g., based on the carrier ring ID, tongue ID, tongue width, tongue angle, etc.) with using more contact area to allow for open electrical contact area. However, in some cases, more open electrical contact area may be allowed by providing additional tongues (e.g., 12 or more), some of which are non-tilted and in contact with the processed wafer 900'. Countless combinations of the physical characteristics of the disclosed carrier rings and tongues may be balanced to achieve the advantages described herein. method

[0116] Fig.11 is a flow chart that depicts a method 1100 for obtaining an apparatus configured to support a semiconductor substrate according to some embodiments. One or more functions of the method 1100 may be performed or caused by a computerized device or system. Fig.11 Means for performing the functions depicted in one or more steps shown in the process include hardware and / or software components of such a computerized device or system, such as a controller device, a computerized system, or a computer-readable device, which includes a storage medium for storing computer-readable and / or computer-executable instructions, which, when executed by a processor device, are configured to cause at least one processor device or computerized device to perform operations. A controller can be one example of a computerized device or system. A processing chamber can be another example of a computerized device or system. Exemplary components of a processing chamber (including a controller) are shown in Figure 1A and 1B A more detailed description is given in .

[0117] It should also be noted that the operations of method 1100 may be performed in any suitable order, not necessarily in the order in which they are performed. Fig.11 In addition, method 1100 may include: Fig.11 More or fewer operations are shown to obtain the device.

[0118] At block 1102, the method 1100 may include manufacturing a ring-like structure having an inner diameter. The ring-like structure may have a substantially circular structure (e.g., a load-bearing ring) with an inner portion and an outer portion. In some embodiments, the inner diameter of the ring-like structure may be from 298.4 mm to 299.5 mm and extend from the center of the substantially circular structure to the inner periphery of the inner portion. In some cases, the inner diameter may be approximately 299.0 mm.

[0119] At frame 1104, the method 1100 may include forming a plurality of inwardly extending tongues around the inner diameter of the ring structure. In some embodiments, the number of tongues may be selected within the range of 5 to 15. In some implementations, 12 tongues may be provided around the inner diameter of the ring structure. In some variants, these tongues may be formed in equidistant and equiangular positions. In some variants, the tongues may be formed in groups, such as having two tongues in six positions that are equidistant and equiangular from each other.

[0120] In some embodiments, the plurality of inwardly extending tongues may have one or more physical properties that enable backside deposition of more semiconductor substrates (compared to a ring-like structure formed by a plurality of tongues lacking the one or more properties). In some implementations, the one or more physical properties may include an inner diameter associated with the plurality of tongues, a width of the plurality of tongues, and an angle of at least a portion of a top surface associated with the plurality of tongues relative to a plane defined by the ring-like structure.

[0121] In some variations, the inner diameter associated with the plurality of tongues may be from 296.0 mm to 299.5 mm. In some examples, the inner diameter of the tongue may be approximately 297.0 mm.

[0122] In some variations, the angle of at least a portion of these top surfaces can be selected in a range of less than 15 degrees, wherein the at least a portion of these top surfaces are collectively configured to interface with (e.g., physically contact and / or support) a semiconductor substrate. In some examples, the angle can be downward at about 11.1 degrees relative to the plane defined by the type of ring structure. In some cases, the angle may not be uniform over the length of the entire tongue. The angle can be measured at the base of the tongue, closest to the inner diameter of the carrier ring. Alternatively, an average of multiple angles can be selected.

[0123] In some variations, the width of the plurality of tongues may be from 0.5 mm to 2.0 mm. In some examples, the width of the tongue may be about 1.0 mm. In some cases, the width may not be uniform over the length of the tongue. The width may be measured at the terminal end portion of the tongue, and the width of the tongue may be wider or narrower than 1.0 mm along the length of the tongue.

[0124] The physical properties of the above-described carrier ring and its tongue can help reduce MCA, increase processing or deposition (e.g., on the back side of the semiconductor substrate), reduce particles, reduce edge effects, and ultimately achieve more consistent film thickness (which can be measured, for example, by reduced level differences). More specifically, the physical properties of the above-described tongue allow for more backside deposition because it introduces minimal coverage on the back side of the semiconductor substrate compared to, for example, some existing carrier rings, which may have larger tongues that would cover more backside area, which would prohibit the amount of deposition that can occur using the carrier rings described herein.

[0125] Fig.12 is a flow chart that depicts a method 1200 of depositing one or more layers on the back side of a semiconductor substrate according to some embodiments. One or more functions of the method 1200 may be performed or caused by a computerized device or system. Fig.12 Means for performing the functions depicted in one or more steps shown in the process include hardware and / or software components of such a computerized device or system, such as a controller device, a computerized system, or a computer-readable device, which includes a storage medium for storing computer-readable and / or computer-executable instructions that, when executed by a processor device, are configured to cause at least one processor device or computerized device to perform operations. A controller can be one example of a computerized device or system. A processing chamber can be another example of a computerized device or system. Exemplary components of a processing chamber (including a controller) are shown in Figure 1A and 1B A more detailed description is given in .

[0126] It should also be noted that the operations of method 1200 may be performed in any suitable order, not necessarily in the order in which they are performed. Fig.12 In addition, method 1200 may include: Fig.12 More or fewer operations may be performed to deposit the layers as shown.

[0127] At block 1202, the method 1200 may include supporting a semiconductor substrate on a carrier ring. In some embodiments, the carrier ring may be Figures 6A to 6F The carrier ring 600 shown, Figure 7 The carrier ring 704 or Figure 8 An example of a carrier ring is shown. The carrier ring may have one or more physical characteristics of the aforementioned carrier rings, including a specific inner diameter of the carrier ring, an inner diameter of the plurality of inwardly extending tongues, a number of the plurality of inwardly extending tongues, a width of the plurality of inwardly extending tongues, and / or an angle of the plurality of inwardly extending tongues.

[0128] In some embodiments, the semiconductor substrate may be Figure 1A and1B An example of a substrate 128 is shown. In some embodiments, the semiconductor substrate may be Figures 5A to 5C , the wafer 512 shown in 6E and 6F, Figure 8 The wafer or Fig. 9 An example of a semiconductor wafer 900 is shown.

[0129] In some embodiments, the semiconductor substrate can be placed on top of the interior of the carrier ring and surrounded by the exterior of the carrier ring. In some implementations, the interior can be defined by cross-sectional portion 506a and the exterior can be defined by cross-sectional portion 506b, such as Figures 5A to 5C shown.

[0130] At box 1204, the method 1200 may include exposing the back side of the semiconductor substrate to processing conditions that cause one or more layers to be deposited on the back side of the semiconductor substrate. In some embodiments, the processing conditions include exposure to a chemical precursor of at least one of the one or more layers. For example, a silicon-containing reactant, a nitrogen-containing reactant, or an oxygen-containing co-reactant may be used as the chemical precursor. In some embodiments, at least one of the one or more layers on the back side of the semiconductor substrate includes polysilicon, silicon oxide, silicon nitride, or any combination thereof. In some implementations, multiple layers may be alternately deposited or stacked, such as alternating silicon oxide layers and silicon nitride layers. Examples of other chemical precursors and stacking materials are listed elsewhere herein.

[0131] In some implementations, the controller (e.g., 120) is part of a system and the system may be part of the above examples, including a processing chamber or another system including an ESC. Such a system may include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronic devices for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronic device may be referred to as a "controller" which may control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the controller may be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools connected or docked with a specific system and other transfer tools and / or load locks.

[0132] In general, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuit can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions sent to the controller in the form of various individual settings (or program files) that define operating parameters for performing specific processing on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during processing of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0133] In some implementations, the controller may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or may be all or part of a wafer fab host system that may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a processing operation, check the history of past processing operations, check trends or performance criteria for multiple processing operations, to change the parameters of the current processing, set processing steps to follow the current processing, or start a new processing. In some examples, a remote computer (e.g., a server) may provide a processing recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify the parameters of each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of processing to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., processing and control as described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer), which combine to control processing on the chamber.

[0134] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used for processing and / or preparing semiconductor wafers.

[0135] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in material transport to transport wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0136] A system and method are now provided that provide improved clamping or clamping performance over conventional systems. The methods, devices, and systems described above enable the flexible use of various clamping modes (e.g., bipolar and / or monopolar) compared to conventional systems, and achieve this goal while using modifications to the prior art. Thus, embodiments of the improved clamping system now include configurations involving one or more power sources.

[0137] Various modifications of the implementations described in this disclosure may be apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations without departing from the spirit or scope of the disclosure. Therefore, the claims are not intended to be limited to the implementations shown herein, but are to be consistent with the broadest scope consistent with the disclosure, the principles and novel features disclosed herein.

[0138] Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations, either individually or in any suitable subcombination. Furthermore, while features may be described above as functioning in a particular combination, or even initially claimed as such a combination, in some cases one or more features may be removed from the combination, and the claimed combination may be directed to subcombinations or variations of subcombinations.

[0139] Similarly, although the operations are depicted in a particular order in the figure, this should not be understood as requiring these operations to be performed in the particular order shown or in a continuous order, or requiring the execution of all depicted operations to achieve the desired result. In addition, the figure may schematically depict one or more exemplary processes in the form of a flow chart. However, other operations that are not depicted can be incorporated into the example processing schematically depicted. For example, before, after, at the same time or between any depicted operations, one or more additional operations can be performed. In some cases, multitasking and parallel processing may be advantageous. In addition, in the implementation scheme described above, the separation of various system components should not be understood as requiring such separation to be achieved in all implementation schemes, and it should be understood that the program components and systems described can usually be integrated in a single software product or packaged into multiple software products. In addition, other implementation schemes also fall within the scope of the following claims. In some cases, the operations described in the claims can be performed in different orders, and the desired results can still be achieved.

Claims

1. A carrier ring configured to support a semiconductor substrate, the carrier ring comprising: a ring having an outer portion and an inner portion and defining a plane, the inner portion having an inner perimeter having a first diameter of approximately 298.4 to 299.5 millimeters (mm); as well as A plurality of inwardly extending tongues are disposed about the inner periphery of the inner portion of the ring, the plurality of inwardly extending tongues having an inner edge defining a circle having a second diameter of approximately 296.0 mm to 298.5 mm.

2. The carrier ring according to claim 1, wherein: The first diameter of the inner portion of the ring is about 299.0 mm; and The second diameter of the plurality of inwardly extending tongues is approximately 297.0 mm.

3. The carrier ring according to claim 1, wherein: The plurality of inwardly extending tongues includes at least 8 inwardly extending tongues.

4. The carrier ring according to claim 1, wherein: At least one of the plurality of inwardly extending tabs has a width of approximately 0.5 mm to 1.5 mm.

5. The carrier ring according to claim 4, wherein: The width of the at least one of the plurality of inwardly extending tabs is approximately 1.0 mm.

6. The carrier ring according to claim 1, wherein: At least one of the plurality of inwardly extending tongues includes at least a portion of a top surface that is not parallel to or perpendicular to the plane but is angled.

7. The carrier ring according to claim 6, wherein: The angle of the portion of the top surface is between approximately 5 and 20 degrees relative to the plane.

8. The carrier ring according to claim 6, wherein: The top surface of the at least one of the plurality of inwardly extending tongues includes a minimum contact area (MCA) configured to make physical contact with the semiconductor substrate.

9. The carrier ring according to claim 1, wherein: The outer portion is approximately 0.3 mm to 0.7 mm thick, while the inner portion is approximately 0.1 mm to 0.5 mm thick.

10. The carrier ring according to claim 1, wherein: At least a portion of the plurality of inwardly extending tongues disposed about the inner periphery of the inner portion of the ring are configured to form one or more electrically conductive grounding points on the semiconductor substrate.

11. A carrier ring configured to support a semiconductor substrate, the carrier ring comprising: a ring including an inner portion configured to support the semiconductor substrate during backside deposition on the semiconductor substrate, the ring defining a plane; as well as 8 to 15 inwardly extending tongues disposed around the interior of the ring and configured to contact the semiconductor substrate during the backside deposition on the semiconductor substrate; Wherein, at least one of the 8 to 15 inwardly extending tongues has a width of about 0.5 mm to 1.5 mm.

12. The carrier ring according to claim 11, wherein: The at least one of the 8 to 15 inwardly extending tabs includes a top surface having an angle of less than about 15 degrees relative to the plane.

13. The carrier ring according to claim 11, wherein: The 8 to 15 inwardly extending tongues have inner edges defining a first diameter of approximately 296.0 mm to 298.5 mm; and Wherein, the 8 to 15 inwardly extending tongues have an outer edge attached to the ring and defining a second diameter of approximately 298.4 mm to 299.5 mm.

14. The carrier ring according to claim 11, wherein: At least a portion of the 8 to 15 inwardly extending tongues are configured to allow one or more conductive grounding points to be formed on the semiconductor substrate.

15. A method of depositing one or more layers on the back side of a semiconductor substrate, the method comprising: (a) supporting the semiconductor substrate on a carrying ring, wherein the carrying ring comprises: a ring having an outer portion and an inner portion defining a plane, the inner portion having an inner perimeter having a first diameter of approximately 298.4 millimeters (mm) to 299.5 mm; and a plurality of inwardly extending tongues disposed about the inner periphery of the inner portion of the ring, the plurality of inwardly extending tongues having inner edges defining a circle having a second diameter of approximately 296.0 mm to 298.5 mm; and (b) exposing the backside of the semiconductor substrate to processing conditions that cause the one or more layers to be deposited on the backside of the semiconductor substrate.

16. The method according to claim 15, wherein: The processing conditions that cause deposition of the one or more layers include exposure to a chemical precursor of at least one of the one or more layers.

17. The method according to claim 15, wherein: At least one of the one or more layers on the back side of the semiconductor substrate includes polysilicon, silicon oxide, silicon nitride, or any combination thereof.

18. The method of claim 15, wherein: The first diameter of the inner portion of the ring is about 299.0 mm; and The second diameter of the plurality of inwardly extending tongues is approximately 297.0 mm.

19. The method according to claim 15, wherein: The plurality of inwardly extending tabs include at least 8 inwardly extending tabs, at least one of the at least 8 inwardly extending tabs having a width of approximately 0.5 mm to 1.5 mm.

20. The method according to claim 15, wherein: At least one of the plurality of inwardly extending tongues includes at least a portion of a top surface that is neither parallel nor perpendicular to the plane but has an angle, and the angle is between about 5 degrees and 20 degrees relative to the plane.

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