Semiconductor chip comprising a reliability-enhanced patterned

Abstract

The present disclosure relates to a semiconductor chip having an aluminum layer, where the aluminum layer has a structure that receives at least a portion of a surface on which copper or epoxy resin is additionally deposited, and where the structure forms a peak on the portion of the surface, occupying 20% to 80% of the portion of the surface.

Description

Technical Field

[0001] The present description relates to top interconnects of electronic devices and methods of making the same. Background Art

[0002] The interconnection technology of power electronic devices generally includes a so-called "top interconnection", the function of which is to electrically connect the semiconductor device to the metal lead frame.

[0003] Existing interconnect technologies for top interconnects may include aluminum-based interconnects, such as Figure 1 As shown in the embodiment, it may include:

[0004] o A metallization layer of aluminum (Al) or its alloys (containing less than 5% Cu and / or 5% Si) with a thickness typically between 2 and 10 μm. This layer is generally delivered by the semiconductor chip manufacturer together with the chip and is deposited on areas on the upper surface of the semiconductor chip. The existing technology for selectively depositing metal layers on certain areas of the silicon chip is based on subtractive transfer or additive transfer lithography processes:

[0005] oIn the subtractive transfer process:

[0006] • First, a continuous metal film of uniform thickness is deposited using a deposition method (usually physical vapor deposition, such as sputtering or evaporation).

[0007] • Then, a resist layer is deposited on the metal surface except where the metal layer is not needed.

[0008] This is usually done using a photolithography process.

[0009] Finally, wet etching is used to remove the exposed metal surface and remove the resist layer.

[0010] oIn the additive transfer process:

[0011] First, one or two resist layers are selectively deposited on the surface where the metal layer is not required.

[0012] • Then, a uniform metal layer is deposited over the resist and final metallized surface.

[0013] Finally, the resist is removed, thereby stripping the metal layer from the unwanted surface.

[0014] o Aluminum wire (or aluminum ribbon) is connected between the Al metallization layer and the lead frame. This interconnection is usually completed by the power module manufacturer when assembling the power module. According to the prior art, the process of connecting the aluminum wire and forming a bond with the Al metallization layer is the so-called "ultrasonic bonding" process, in which ultrasonic energy and pressure are used to attach the wire to the metallization layer to promote the metallization layer and the wire in a solid state (not melted)

[0015] It is important to note that more reliable bonds are usually formed when in contact with flatter aluminum surfaces.

[0016] Aluminum-based interconnects are the standard technology used in the industry today. However, the transition from aluminum to copper interconnect technology is beneficial for several reasons:

[0017] o Copper wire bonding is seen as a next-generation top interconnect packaging solution that enables reliable bonding at higher maximum operating temperatures. Several manufacturers have demonstrated significantly improved reliability of copper-based interconnects compared to aluminum-based interconnects (interconnect life is typically improved by 10 times) due to more stable wire bonds;

[0018] o Better compatibility with higher bandgap chip materials (SiC and GaN) that can operate at higher temperatures;

[0019] o Stronger current carrying capacity, so it is compatible with high current density devices (Si-based devices or high bandgap semiconductor devices);

[0020] o Enhanced short-circuit protection during the turn-off process of high-frequency pulse width modulation (PWM) operation. Compared with classic aluminum-based metallization layers, the greater thermal capacity of copper, combined with greater metallization thickness, provides a higher thermal buffer to prevent the chip from overheating during high-frequency thermal events, thereby improving the short-circuit reliability of the package;

[0021] oCompatible with standard printed circuit board technology, thus enabling the embedding of power electronics chips into printed circuit boards,

[0022] This provides the added benefit of lower parasitic capacitance and lower thermal impedance.

[0023] On the other hand, Figure 2 In the first embodiment shown in the embodiment of the present invention, the copper-based interconnection in the prior art may generally include:

[0024] oDiffusion barriers that prevent copper from diffusing into the semiconductor device, reacting with it and changing its electronic properties. Such diffusion barriers can be thin layers of tantalum (Ta) or tantalum nitride (TaN), titanium (Ti) or titanium nitride (TiN), W deposited by sputtering or chemical vapor deposition. Diffusion barrier layers are usually deposited by the chip manufacturer. These diffusion barrier layers are not composed of aluminum and therefore require the chip manufacturer to implement a non-standard, specific process. Currently, such chips are not widely available to module manufacturers.

[0025] o The copper metallization layer, typically more than 10 μm thick, is usually deposited by means of an electrolytic process (electroplating).

[0026] oUse ultrasonic wedge bonding to connect thick (>250μm) copper wires to the metallization layers.

[0027] like Figure 3 As shown in the embodiment of the present invention, other prior art copper-based interconnection technologies may include:

[0028] o Standard Al metallization layers deposited, for example, by sputtering. Therefore, in this case, the module manufacturer can use standard chips;

[0029] oAg sintering layer deposited between the chip and the copper layer by a pressurized or pressureless process;

[0030] oAttaching copper foil to the Ag sintered layer during the sintering process;

[0031] oUse ultrasonic wedge bonding to connect thick (>250μm) copper wires to the metallization layers.

[0032] Therefore, from the above description of the current state of the art, it can be seen that copper wire bonding technology is superior to aluminum wire bonding technology in many aspects. However, both of these existing technology solutions have problems:

[0033] -exist Figure 2 In the solution shown, depositing a thin diffusion barrier layer on top of the semiconductor chip is a non-standard process that is not widely used in the industry at present, so such chips with Cu metallization layers are not widely available to power module manufacturers.

[0034] -exist Figure 2 In the solution shown, depositing a thin diffusion barrier layer on top of the semiconductor chip is an additional expensive manufacturing step. In addition, the process is also critical because a very high degree of cleanliness and uniformity is required for the diffusion barrier to work effectively.

[0035] -exist Figure 3 In the solution shown, where a standard Al metallization layer is used in the copper-based top interconnect, failure of the Al layer and thus delamination between the semiconductor and the Ag sintered layer limits the module’s lifetime. The failure occurs due to crack propagation within the top Al metallization layer. Figure 3 Such failure is shown between the Si IGBT layer and the top Ag sintered layer.

[0036] - In addition, Figure 3 In the solution shown, an Ag layer is used to connect the Al metallization layer and the copper layer.

[0037] The choice of Ag layer was mainly due to the reliability of Ag sintered interconnects and the availability of this technology. However, using this connection adds process steps and usually requires time-consuming and energy-intensive heat treatment steps during product manufacturing.

[0038] Therefore, to overcome the above limitations, it is desirable to directly connect the copper layer to the aluminum layer. However, since the adhesion strength of Cu on Al may be poor, it is difficult to form a reliable copper-aluminum interface. The adhesion failure of the aluminum-copper bond is caused by several factors, which can be divided into extrinsic factors and intrinsic factors:

[0039] oExtrinsic factors: Thermomechanical stress generated at the Al-Cu interface is the driving force for bond failure. Temperature changes during product manufacturing and use will generate stress at the joint due to the different thermal expansion coefficients of the materials present in the stacked assembly. In the semiconductor interconnect material layer geometry, the metallization layer is very thin compared to the thickness of the semiconductor wafer, and the stress is strongest at the edge of the wafer, and most of it is shear in nature (commonly referred to as "mode II loading");

[0040] oInternal factors:

[0041] Native oxide layer: Both aluminum and copper tend to form an oxide layer when exposed to air. This prevents the formation of strong metallic bonds at the atomic level, which greatly reduces the strength of adhesion. Therefore, when making Al-Cu bonds, for example by chemical or electrochemical methods (without electrolysis or electroplating), the oxide layer is usually removed and the surface is protected from further oxidation by depositing a nanoscale layer (the so-called "passivation layer") or by applying a barrier layer of typically less than 2 μm.

[0042] Al and Cu react when exposed to high temperatures. Cu and Al form an intermetallic phase that is mechanically weak and more susceptible to oxidation and corrosion. In addition, the reaction involves a volume change that can produce cracks or voids ("Kirkendal voids") even in the absence of thermomechanical stress. Therefore,

[0043] A thin, non-reactive interfacial coating (typically less than 2 μm) is also beneficial.

[0044] Despite the use of an interfacial coating or passivation layer, the adhesion strength between Al and Cu may not be sufficient to provide a reliable bond at least comparable to the state of the art. Therefore, the first problem to be solved by the present disclosure is the poor adhesion strength between Al and Cu, preventing the generation of a reliable Al-Cu bond.

[0045] Furthermore, in conventional power modules, the power semiconductor chips are usually protected from the environment by a potting compound, which is usually poured in the form of a heated liquid at the end of the potting process and further solidifies after cooling. The purpose of this potting compound is to:

[0046] - Protects chips and their interconnecting components from dust, oxidation and corrosion.

[0047] -Prevent electrical breakdown between electrically connected components separated by high voltage differences.

[0048] Therefore, the encapsulation compound needs to have the properties of high isolation value, low moisture absorption and low diffusion rate. In addition, the thermomechanical properties of these materials should not impose additional thermomechanical stress on critical package components (such as the top aluminum interconnect).

[0049] The encapsulation compounds of the prior art can be divided into the following categories:

[0050] - Silicone gel-type materials, which generally provide sufficiently high breakdown voltages and can be used over a wide temperature range (typically -50°C to 200°C). They have flexible mechanical properties and have negligible impact on component thermomechanical stresses;

[0051] -Epoxy-based potting compounds, which generally offer better isolation values ​​than silicone gel materials, are considered as the next generation of isolation materials for high voltage power modules. However, due to their higher elastic limit and larger thermal expansion coefficient, stress may be generated at the interface between the semiconductor die and the packaging material.

[0052] It may be desirable to use epoxy-based encapsulation materials to protect electronic components from dust, corrosion, and moisture, as these materials may be more suitable than silicone gel in harsh environments and high-voltage applications. However, due to the high elastic strength and hardness of epoxy resins, combined with the high coefficient of thermal expansion, stress may be generated at the interface between the semiconductor device and the epoxy resin, resulting in adhesion failure delamination.

[0053] The second problem is related to the poor adhesion strength between Al and epoxy-based encapsulation materials, which prevents a reliable bond between the metallization layer and the epoxy. Failure occurs when thermal (or hygrothermal) stresses overcome the adhesion strength of the bond due to (cyclic) temperature exposure (e.g. during reflow, power cycling) during processing or during product use. The vapor pressure contained in the initially small interfacial pores increases the interfacial stresses and causes the encapsulation material to fail (the “popcorn” effect). The end result of the presence of a poorly isolated vapor layer can be the failure of the power electronic system due to electrical breakdown at high voltages.

[0054] The present invention aims to improve the situation caused by at least the above two problems.

[0055] To this end, the present invention proposes a semiconductor chip having an aluminum layer, wherein the aluminum layer has structures of at least a portion of the surface receiving additional deposition, and wherein the structures form peaks on the portion of the surface occupying 20% ​​to 80% of the portion of the surface.

[0056] As described in the embodiments below, this structure forms an interlocking structure with the additional deposition, and the shear adhesion strength between the aluminum layer and the additional deposition assembled thereon is improved, thereby improving the reliability of the assembly.

[0057] In an example of an embodiment, the aluminum layer is a metallization layer, and its average thickness T is typically between 2 μm and 15 μm.

[0058] In an example of one embodiment, the average thickness of the aluminum layer is T, the length of the structure is L, and the length L measures the average distance between first adjacent peaks of the structure, and has a relationship with the average thickness T as L<10*T.

[0059] In an example of an embodiment, the aluminum layer has an average thickness T, and the structure has a depth D, which measures the average depth of the peaks and is related to the average thickness T as D>0.2*T.

[0060] In an example of an embodiment, the peaks may form a periodic sinusoidal shape in at least one profile section of the structure (as described below). Figure 7 shown).

[0061] In an embodiment, the top of the peak has a ridge (as described below). Fig. 9 shown).

[0062] The semiconductor chip mentioned above may be, for example, a power semiconductor chip or the like.

[0063] At least in this application, the additional deposition may include copper, or may include epoxy.

[0064] Furthermore, the surface of the aluminum layer may include at least one additional portion different from the portion including the structure, and the additional portion may be configured as an electrical connection of the aluminum layer (as described below). Fig.10 shown). Summary of the invention

[0065] The present disclosure also aims to provide a method for manufacturing a semiconductor chip having an aluminum layer, the method comprising:

[0066] - depositing said aluminum layer,

[0067] - forming a structure on at least a portion of the top surface of the aluminum layer; and

[0068] - forming an additional deposit at least on said portion,

[0069] The structure forms a peak on the portion, and the peak occupies 20% to 80% of the portion.

[0070] In an example of an embodiment, forming the structure may include:

[0071] - spatially selectively depositing a mask on said portion, said mask protecting the aluminum layer underneath from being affected by etching;

[0072] - etching said portion; and

[0073] - removing the mask,

[0074] And / or, in combination or alternatively:

[0075] - spatially selectively depositing a mask on said portions, said mask preventing aluminum from being deposited thereon;

[0076] - depositing aluminum on said portion; and

[0077] - removing the mask.

[0078] Alternatively or in combination, forming the structure may comprise using a machining tool to deform the top surface of the portion and create the peak.

[0079] In one embodiment, forming the structure may further include applying a pressing tool on top of the peak to form a ridge in the top of the peak.

[0080] Further details are presented in the following description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] [ Figure 1 ]

[0082] Figure 1 An aluminum-based top interconnect of a semiconductor chip according to the prior art is shown.

[0083] [ Figure 2 ]

[0084] Figure 2 A first type of copper-based top interconnect according to the prior art is shown (solution "A").

[0085] [ Figure 3 ]

[0086] Figure 3 A second type of copper-based top interconnect according to the prior art is shown (solution "B").

[0087] [ Figure 4 ]

[0088] Figure 4 Shown are problems that occur due to poor adhesion strength of the Cu-Al interface in an example of an embodiment (top) and a proposed solution to the mixed cohesive / adhesive failure mode (bottom).

[0089] [ Figure 5 ]

[0090] Figure 5 Shown are problems that occur due to poor adhesion strength of the Cu encapsulation polymer in an example of an embodiment (top) and a proposed solution to the mixed cohesive / adhesive failure mode (bottom).

[0091] [ Figure 6 ]

[0092] Figure 6 A cross-sectional view of an embodiment of a structured Al metallization layer is shown, more particularly, the structured Al metallization layer having a pillar structure with stress protrusions.

[0093] [ Figure 7 ]

[0094] Figure 7 A cross-sectional view of an embodiment of a structured Al metallization layer is shown, more particularly, the structured Al metallization layer having a periodic sinusoidal shape in at least one direction.

[0095] [ Figure 8 ]

[0096] Figure 8 is a top view of an embodiment of a structured Al metallization layer, wherein the black regions indicate the area portions exposed to the formed structures.

[0097] [ Fig. 9 ]

[0098] Fig. 9 An embodiment of a suspended structure by applying a pressure having a direction of vector P is shown.

[0099] [ Fig.10 ]

[0100] Fig.10 An example of portions of the surface of an aluminum layer are shown which are placed aside to create electrical contacts therein to connect the aluminum layer.

[0101] [ Fig.11 ]

[0102] Fig.11 A comparison is shown between a semiconductor chip (Si or SiC chip) comprising an aluminum layer according to the prior art (left) and the same semiconductor chip comprising a structured aluminum layer according to the present disclosure. DETAILED DESCRIPTION

[0103] This embodiment enables avoiding the above-mentioned problem of poor adhesion strength of the Cu-Al interface by providing a specific geometry of a non-planar structured interface between the Al metallization layer and the Cu metallization layer.

[0104] In the following, "Al-Cu interface" refers to the joint between the Al metallization layer of the semiconductor wafer and the copper layer fixed to the metallization layer. Additional thin layers may be present at the interface between the Al and Cu layers (for example, for the purpose of removing oxides during manufacturing or preventing corrosion / oxidation during product use), but in the following, these layers are considered to be part of the joint because the thickness of these layers is smaller than the thickness of the Al metallization layer or the Cu metallization layer (typically less than 2μm for each layer).

[0105] Furthermore, this embodiment makes it possible to avoid the above-mentioned problem of poor adhesion strength of the Al potting compound interface by using a non-planar structured Al metallization layer surface.

[0106] The effect of using a structured metallized surface is to create an interlocking structure between the aluminum metallization layer and the material assembled onto it, namely:

[0107] - copper layers for high reliability copper-based interconnects, or

[0108] - Polymers used as encapsulation materials (eg epoxy resins).

[0109] In situations where shear stresses dominate at or near the interface, which is often the case with semiconductor wafer packaging material interfaces, interlocking structures are particularly effective in avoiding adhesion failures. A more reliable bond is created when a structured interface is used because the strength of the interface is increased by the presence of the interlocking structure, which enables additional plastic or viscoelastic energy dissipation in the bulk of the material away from the interface, such as Figure 4 (Realization of Cu-Al interface) and Figure 5 (Implementation of Cu encapsulated polymer) as shown:

[0110] - In the absence of interlocking structure ( Figure 4 In the case of the Al-Cu interface or the Al-polymer interface, the adhesion fails due to the poor adhesion strength of the components: the crack mainly propagates at the interface,

[0111] - In the presence of interlocking structures ( Figure 5 In the case of the composite (bottom image), the interface fails in a mixed adhesion / cohesion mode: the crack propagates both at the interface and in the bulk of the component. Since the physical bond in the bulk is stronger than that at the interface, a more reliable bond results.

[0112] In relation to Al-polymer encapsulation Figure 5 The same effect can be seen above.

[0113] Then it can be noted that the structure of the aluminum layer can be implemented in several cases (for example, for depositing a copper layer or a resin layer on a structured surface adjacent to the aluminum layer). Of course, such a structure can be implemented in other cases (for example, for depositing a silver layer).

[0114] Accordingly, the present disclosure can be directed to a semiconductor chip having an aluminum layer, wherein the layer includes a structure that receives an additional deposition (which can be a resin layer, a copper layer, etc.). More specifically, the structure forms peaks on the surface, occupying 20% to 80% of the surface.

[0115] In other words, the exposed area fraction A (which measures the area formed by the higher points (or "peaks") of the structure) is preferably in the range of 20% < A < 80%, more preferably in the range of 30% < A < 70%, and even more preferably in the range of 40% < A < 60%, i.e., for example, about 50%.

[0116] The semiconductor chip described above can be more specifically a power semiconductor chip.

[0117] The aluminum layer can be more specifically a metallization layer.

[0118] In an embodiment of the implementation, for an aluminum layer having an average thickness T, the structure can have a length L, which measures the average distance between adjacent peaks of the structure, and the relationship with the average layer thickness is L < 10*T.

[0119] In an embodiment of the implementation, for an aluminum layer having an average thickness T, the structure can have a depth D, which measures the average depth of the structure, and the relationship between the characteristic depth and the average metallization thickness is D > 0.2*T.

[0120] Accordingly, the shear adhesion strength between the metallization layer and the material assembled thereon is increased, thereby improving the reliability of the component.

[0121] Embodiments are given below.

[0122] "Aluminum" refers to a small amount of impurities dissolved or precipitated below the aluminum material. For example, aluminum can have a purity of 6N (99.9999% pure) or 3N (99.9%), and the remaining elements are intentionally or unintentionally present in the material to adjust its mechanical, electrical properties, or its resistance to electromigration. In another embodiment, impurities are intentionally added to the material to improve its mechanical, electrical properties, or its resistance to electromigration. For example, less than 1% of silicon and / or less than 1% of copper are added to increase the material hardness or strength, and / or reduce electromigration.

[0123] In one example of an implementation, the aforementioned "at least a portion of the metallization layer" is the entire surface of the metallization layer. In the following implementations where portions of the metallization layer are to be connected (eg, by wire bonding), such portions may not be structured.

[0124] In one example of an implementation, the structure has the following features:

[0125] The average metallization thickness T is in the range between 2 μm and 15 μm, preferably in the range between 3 μm and 8 μm, for example 5 μm.

[0126] The characteristic length L is of the same order of magnitude as the metallization thickness, for example L=3*T, or preferably L=2*T, or for example L=T, for example L=5 μm.

[0127] The feature depth D is a significant fraction of the metallization thickness, for example more than 20%, preferably more than 50% of the metallization thickness, for example 3 μm.

[0128] The area fraction A is between 30% and 70%, or even between 40% and 60%, or even 50%.

[0129] In this embodiment, when the aluminum metallization layer is then adhered to an adjacent material forming an interface having relatively poor adhesion strength, the shear stress applied to the interface is distributed toward the body of the aluminum metallization layer and the body of the adjacent material, thereby advantageously reducing the risk of adhesion failure between the two materials.

[0130] Depending on the manufacturing process, dimension D may be repeatable or may show significant variations across the metallization surface. For example, dimension D may vary between 5% of the metallization thickness and 50% of the metallization thickness in a regular or random manner.

[0131] Exemplary structures include a square pattern or a ridge pattern ( Figure 6 and 7 The structure may include discrete raised hills arranged in a hexagonal pattern or any periodic arrangement. Alternatively, the structure may include isolated hills or ridges separated by different distances L (i.e., in a randomly distributed manner, such as the structure may not be periodic). For example, the distance L may vary between 0.1D and 10D, preferably between 0.5D and 2D, where D is the average depth.

[0132] The characterization of the structure (measurement of D, L and T) can be done using the following measurement tools and methods:

[0133] - A profilometer that measures contours (2D) or surfaces (3D) (such as a mechanical profilometer or an optical profilometer)

[0134] the height of the instrument, and

[0135] - Sectioning of semiconductor wafers and metals using standard microsectioning sample preparation techniques (cutting, mirror polishing)

[0136] The layers are then observed using a microscope, possibly combined with image analysis tools to extract the semiconductor-metal

[0137] The outline of the interface.

[0138] The following data processing methods should be used to analyze the profiles:

[0139] - Measurement of T: The distance between the semiconductor-aluminum interface and the average height of the aluminum metallization layer using microsection microscope images.

[0140] - For regular surface structures where L and D can be clearly determined, direct measurement can be performed from the surface profile,

[0141] No statistical analysis tools are required.

[0142] -For structures with statistically significant variations in structure size:

[0143] The measurement of D can be done using the average arithmetic mean of the profile: Average roughness Ra (for

[0144] 2D measurement) or Sa (for 3D measurement), and use the formula D = 2*Ra or D =

[0145] 2*Sa(ISO4287:1997).

[0146] • The length L can be measured using the mean width parameters PSm, RSm, WSm (ISO 4287:1997).

[0148] The area fraction A can be calculated using the Rpk parameter according to ISO 13565-2 or by using the Rpk parameter according to ISO 13565-

[0149] 3 is measured by the Spk parameter, and the Rpk and Spk parameters are evaluated according to the area material ratio A.

[0150] In an embodiment, the structure is prevented from having stress concentrators, or in other words, its shape is selected so as to minimize the presence of stress concentrators. Stress concentrators mean the presence of sharp corners at the structure, which will act as stress concentration centers at the metallization layer and the material deposited thereon. It is generally believed that the stress σR at the sharp corner of radius R is inversely proportional to the value of the square root of radius R, and is related to the remote stress intensity σ as follows:

[0151]

[0152] So, for example, reference Figure 6 In the right part of the structure, the stress in the vicinity of the corners of radii R1 and R2 increases as R1 and R2 decrease, so cohesive failure will start at these points. Therefore, in an advantageous embodiment, it is possible to choose to maximize the radius of curvature of the structure, such as Figure 7 In the embodiment shown, the maximum radius is close to D. For example, the cross-section of the structure gives an interface that preferably approximates a sine wave with period 2D and amplitude D.

[0153] A profile cut along a single direction can have a periodic shape (e.g. Figure 8 ), or even the profile cut along two perpendicular directions of the structured surface can have a periodic mountain shape surrounded by a valley shape (as shown in the right part of Figure 8 ).

[0154] The present description may also be directed to methods for constructing aluminum metallization layers, including, for example, the following:

[0155] - patterning the wafer using a subtractive transfer process or an additive transfer process, using standard metallization techniques, in order to obtain a continuous aluminum layer of thickness T+D at defined locations on the semiconductor chip, and

[0156] - A subtractive transfer process is used to selectively remove thickness in both directions at defined areas of the aluminum layer.

[0157] Thus, advantageously, the structure can be added on a standard semiconductor chip with a standard aluminum metallization.Module manufacturers can easily implement the present process on any standard aluminum metallization.

[0158] The subtractive transfer process may include a photolithography process and, for example, follow the following steps:

[0159] First, using methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD)

[0160] Deposition methods such as electroplating or (electro)plating methods are used to deposit continuous films of metal with uniform thickness.

[0161] A resist layer is then deposited over the metal surface except where the metal layer is not needed. This is usually performed using a photolithography process.

[0162] Finally, wet etching is used to remove the exposed metal surface and the resist layer is removed.

[0163] PVD methods may include evaporation and RF sputtering methods.

[0164] Instead of etching, a mechanical process such as grinding, sandblasting, chemically assisted mechanical polishing (CMP), or other processes that use a larger grain size (i.e., a grain size larger than conventional processes) may be performed to obtain Figure 6 or Figure 7 The non-square structure shown in .

[0165] Another alternative to etching is a non-uniform chemical process, such as non-uniform etching, due to the random nature of etching processes, such as pitting processes.

[0166] Alternatively or in combination, a plasma etching process may be used to remove a portion of the aluminum.

[0167] Alternatively or in combination, aluminum may be added using a screen printing process only at raised locations of the structure, and the structure may subsequently be subjected to heat treatment to provide a structure with mechanical strength comparable to bulk aluminum.

[0168] More generally, the Al metallization layer may be constructed by selectively adding a thickness of aluminum at defined areas of a first deposited aluminum layer (using an additive transfer process). Embodiments of an additive transfer process may include:

[0169] selectively depositing at least one resist layer on the surface on which the aluminum layer should not be deposited,

[0170] • Then, a uniform layer of aluminum is deposited over the resist and final metallization surface.

[0171] Finally, the resist is removed, so that the aluminum layer is peeled off from the unwanted surface.

[0172] An additional step of applying pressure on the top exposed area of ​​the structured aluminum layer may be performed to plastically deform the structure and form a protrusion with a negative slope on top thereof.

[0173] This embodiment may advantageously improve the tensile and shear adhesion strength of the structure.

[0174] Examples in Fig. 9 and may include using Figure 6 or Figure 7 The structure shown has square or wavy protrusions, and the pressure forming tool is brought into contact with the top of the exposed area, and then pressure is applied using a flat tool to plastically deform the final overhang structure. Fig. 9 As shown, the peak of the structure eventually takes on a humped shape at its top.

[0175] In an embodiment, the tool may be controlled in a displacement mode such that the structure is only partially deformed and the formation of a flat metallization layer or closed pores in the metallization layer is avoided. For example, the displacement of the tool may be limited by the presence of a stopper (e.g. Fig. 9lateral side of the display).

[0176] In addition to improving adhesion in shear mode, such an overhang structure can improve adhesion in tension mode when the metallized layer is in contact with the second material, ie, when a force is applied in a direction out of the plane of the metallized surface.

[0177] Only a portion of the metallization layer may be structured. For example, the structure should not be applied to the region of the connecting conductors of the layer.

[0178] Thus, advantageously, the metallization improves the reliability of the interconnection to adjacent layers, and does not compromise the reliability of the interconnection to the conductive lines.

[0179] In the following Fig.10 In the case of a PCB, the area where the aluminum wire bonds are connected (e.g. using an ultrasonic bonding process) is flat and unstructured. Higher wire bond reliability is usually associated with bonding to smooth surfaces, so it is best to exclude structuring in areas that are slightly larger than the wire bond surface, for example in areas with dimensions of 1000μm × 2000μm or 400μm × 1000μm in the case where the wires have been attached using an ultrasonic bonding process.

[0180] The present disclosure is also directed to a power electronic module comprising one or several semiconductor chips, wherein at least one of the semiconductor chips is encapsulated using an epoxy-based encapsulation compound.

[0181] Therefore, this structure improves the bonding between the semiconductor chip and the epoxy-based encapsulation compound, and increases the reliability of the bonding between aluminum and the epoxy compound.

[0182] For example, epoxy-based potting compounds have good wetting properties with Al metallization layers, and during the potting process, the epoxy-based potting compounds form a conformal interface with the Al metallization structure by penetrating into the structure. The wetting properties of the potting compound with respect to the Al metallization structure can be measured using a sessile drop technique, where the epoxy is placed in contact with the Al metallization layer in a liquid state, and parameters such as the Young's angle are measured in the liquid state or after curing, the Young's angle being less than 90°, preferably less than 60°, preferably less than 30°. The standard definition of the Young's angle is the angle formed by the epoxy gas surface and the metallized epoxy surface.

[0183] Epoxy-based potting compounds are materials in which epoxy resin accounts for a large volume fraction, such as greater than 20% or greater than 50%, and the other components of the material are additive particles to give the material appropriate properties, such as a thermal expansion coefficient of 5ppm / K to 30ppm / K, or a thermal conductivity better than pure epoxy resin. For example, the mixed volume ratio of aluminum oxide particles to epoxy resin is greater than 40%, or greater than 70%.

[0184] During the encapsulation process, a pressure difference can be applied between the liquid encapsulant and one or several cavities of the power module, which form a volume between:

[0185] - The substrate of the semiconductor chip (usually a combination of one or more ceramic isolation plates and metal connecting leads,

[0186] possibly fixed to a copper plate), and

[0187] - A housing or cover made of a hard polymer material (possibly with power and control terminals to connect the semiconductor chip to external circuitry).

[0188] As a result, epoxy-based encapsulants can better fill the structure, the process yield is higher, and the reliability of the bond between the aluminum and the epoxy compound is improved.

[0189] When the challenge of creating a conformal interface between the aluminum metallization layer and the epoxy encapsulant cannot be overcome solely by using an epoxy with good wetting characteristics (e.g., due to unacceptably high viscosity and therefore processing time), the application of a pressure differential can be used to create a substantially non-porous, gas-free aluminum-epoxy interface.

[0190] The volume to be encapsulated may be substantially closed except for the vent holes for the input of the epoxy resin and for the escape of gases during processing. The epoxy-based sealant is filled in the above volume, and a pressure difference compared to atmospheric pressure, such as +1 bar, or +10 bar, or +100 bar, is applied at the epoxy resin inlet of the volume.

[0191] The volume to be encapsulated can be substantially closed except for an inlet for injecting epoxy and a vent for extracting gas before or during processing. Gas is first pumped out of the cavity, for example to a sufficiently low pressure (e.g. 100 mbar, or 10 mbar, or 1 mbar), and then the epoxy-based sealant is filled into the volume.

[0192] Alternatively, in another embodiment, several cycles of pressure / fill events are applied, as described in previous embodiments, with filling being performed with an epoxy-based potting compound pressure of +0 bar (ie atmospheric pressure) or at a pressure above atmospheric pressure.

[0193] Standard compression molding processes can also be used to apply pressure on the epoxy-based sealant.

[0194] The copper metallization layer may be in contact with the structured aluminum metallization layer.

[0195] The copper metal semiconductor interconnect stack is more robust against thermomechanical fatigue due to the interlocking structure, and copper metal cannot diffuse into the semiconductor due to the diffusion barrier properties of the aluminum metallization layer.

[0196] The minimum aluminum metallization layer thickness TD / 2 may be greater than 2 μm, preferably greater than 3 μm, preferably greater than 5 μm, so that the aluminum metallization layer has a minimum thickness sufficient to act as a diffusion barrier layer against copper diffusion.

[0197] A thin (<2 μm) interfacial layer may be present between the copper layer and the structured aluminum metallization layer to provide one or more of the following properties: a corrosion or reaction barrier between aluminum and copper, or oxidation resistance at the interface, good wetting characteristics between aluminum and copper during the copper deposition process. For example, such a diffusion barrier layer may be Ti, TiN, Ta, TaN, Au, Ni, Pd, Ag, or any conductive metal, and may be deposited using prior art deposition processes such as PVD, CVD, electroplating, electroless plating.

[0198] The average copper layer thickness may be between 5 μm and 50 μm, preferably between 10 μm and 30 μm.

[0199] The reliability of the components can be increased by a factor of 2, preferably by a factor of 10 (reliability is assessed using a standard test procedure such as AQG324).

[0200] The copper-metal-semiconductor interconnect may be deposited using an electroplating process including at least some of the following steps:

[0201] -1 / Preparing a structured aluminum metallization layer, then,

[0202] -2 / Use a degreaser to clean the surface, then,

[0203] -3 / Chemically etch the aluminum surface using acid, then,

[0204] -4 / Activate the surface with one or more zincate baths, then,

[0205] -5 / optionally deposit one or more thin (<2 μm) layers using electroplating or electroless plating, then,

[0206] -6 / depositing a copper layer using only electroplating or electroless plating processes, or a combination of electroplating or electroless plating processes followed by a PVD or CVD process, and then optionally,

[0207] -7 / Flatten the copper surface using mechanical or chemical mechanical polishing process.

[0208] For example, in step 2, the surface is cleaned using a degreasing agent (such as isopropyl alcohol and / or acetone and / or ethanol) and then rinsed in demineralized water.

[0209] For example, in step 3, the surface is etched using a solution containing nitric acid, and / or chloric acid, and / or sodium difluoride, and / or sulfuric acid, and / or chromic acid, and / or hydrofluoric acid to remove a surface layer less than 1 μm, preferably less than 100 nm, and expose the aluminum surface free of oxides and foreign elements.

[0210] For example, in step 6, a thin seed layer (<2 μm) of copper may be deposited using PVD or CVD techniques, and the remainder of the metallization copper material deposited using a plating method (generally less expensive).

[0211] For example, in step 7, the non-planar copper surface is flattened using prior art chemical mechanical polishing, such as attaching the bottom of the semiconductor to a first rotating surface, and / or contacting a second grinding rotating surface parallel to the first rotating surface with the copper layer to remove excess copper material by mechanical grinding, possibly assisted by chemical action.

[0212] The resulting structure is Fig.11 Shown.

[0213] The above-proposed embodiments may be applied to technical fields requiring high adhesion strength between aluminum and other materials such as polymer materials or copper.

[0214] A common problem in component assembly is the poor adhesion strength between aluminum and such materials as epoxy resins. The main reasons are the rapid oxidation of aluminum and the reduced adhesion strength between oxidized aluminum and oxide-free aluminum. For example, the above-described embodiments allow to achieve an improved adhesion strength between aluminum and epoxy resins despite the presence of an oxide layer and thus open up the possibility of assembling aluminum components using epoxy-based adhesives. Such application areas may be epoxy coatings for corrosion protection of aluminum, thermally efficient aluminum heat sink assembly (e.g. to power modules), general electronic packaging, PCB assembly to aluminum, etc.

[0215] Other embodiments may be implemented to structure the aluminum surface prior to bonding. For example, a structuring tool suitable for the relevant technical field may be used. For example, it may be more time and cost effective to structure a larger aluminum surface (e.g., from a heat sink) using machining techniques than using photolithography techniques.

[0216] Embodiments may also be applicable to technical fields where low-cost but reliable interconnections between copper and electronic devices are required and copper may cause contamination to semiconductor devices (mainly Si and SiC devices). In general, copper has higher electrical conductivity and lower thermal expansion coefficient than aluminum. For example, such application areas may be in the fields of photovoltaic solar cells (currently using screen-printed aluminum back metallization), Si and / or SiC power modules (for traction, factory automation, automotive, industrial drives, embedded drives, charging stations, solar inverters, etc.), general electronic devices, etc.

Claims

1. A semiconductor chip comprising an aluminum layer, wherein: The aluminum layer has structures on at least a portion of the surface receiving the additional deposition, and wherein the structures form peaks on the portion of the surface occupying 20% ​​to 80% of the portion of the surface.

2. The semiconductor chip according to claim 1, wherein: The aluminum layer is a metallization layer having an average thickness T between 2 μm and 15 μm.

3. The semiconductor chip according to claim 1 or 2, wherein: The aluminum layer has an average thickness T, and the structures have a length L, which measures the average distance between first adjacent peaks of the structures and is related to the average thickness T as L<10*T.

4. The semiconductor chip according to any one of claims 1 to 3, wherein: The aluminum layer has an average thickness T, and the structure has a depth D, which measures the average depth D of the peaks and is related to the average thickness T as D>0.2*T.

5. The semiconductor chip according to any one of claims 1 to 4, wherein: The peaks form a periodic sinusoidal shape in at least one profile section of the structure.

6. The semiconductor chip according to any one of claims 1 to 5, wherein: The top of the peak has a ridge.

7. The semiconductor chip according to any one of claims 1 to 6, wherein: The semiconductor chip is a power semiconductor chip.

8. The semiconductor chip according to any one of claims 1 to 7, wherein: The surface of the aluminum layer includes at least one additional portion different from the portion including the structural body and configured for electrical connection of the aluminum layer.

9. The semiconductor chip according to any one of claims 1 to 8, wherein: The additional deposit includes copper.

10. The semiconductor chip according to any one of claims 1 to 8, wherein: The additional deposition includes epoxy.

11. A method for manufacturing a semiconductor chip having an aluminum layer, the method comprising: - depositing said aluminum layer; - forming a structure on at least a portion of the top surface of the aluminum layer; as well as - forming an additional deposit at least on said portion, The structure forms a peak on the portion, and the peak occupies 20% to 80% of the portion.

12. The method according to claim 11, wherein: Forming the structure includes: - spatially selectively depositing a mask on said portion, said mask protecting the aluminum layer underneath from being affected by etching; - etching said portion; and - removing the mask.

13. The method according to claim 11 or 12, wherein: Forming the structure includes: - spatially selectively depositing a mask on said portions, said mask preventing aluminum from being deposited thereon; - depositing aluminum on said portion; and - removing the mask.

14. The method according to any one of claims 11 to 13, wherein: Forming the structure includes using a machining tool to deform the top surface of the portion and create the peak.

15. The method according to any one of claims 11 to 14, wherein: Forming the structure also includes applying a pressing tool on top of the peak to form a ridge in the top of the peak.

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