Cascode normally-off switch with driver and self-biasing

Abstract

An electronic assembly includes a semiconductor device package. The semiconductor device package includes a conductive structure package base, a first terminal configured to be connected to an inductive load, and a second terminal configured to be connected to a common node or circuit ground. The package also includes an enhancement mode transistor and a depletion mode III-N transistor in a cascode configuration. The enhancement mode transistor, the IC controller and the gate driver are monolithically integrated on a common silicon substrate, in which an anode of the rectifier diode is connected to a drain of the enhancement mode transistor, and a cathode of the rectifier diode is connected to a voltage input terminal of the IC controller, and the energy storage capacitor has a first terminal connected to the cathode of the rectifier diode and a second terminal connected to the conductive structure package base.

Description

Technical Field

[0001] The disclosed technology relates to semiconductor electronic devices and circuits designed for power conversion and related systems. Background Art

[0002] Power converters are commonly used to convert one DC voltage level to another, or to convert an AC voltage to a DC voltage. As the demand and requirements for electronic systems such as mobile devices, computers, power supplies, and electric vehicles continue to grow, the desire to improve power conversion efficiency is also expanding. Consumer electronic devices are often manufactured without an internal power supply, and are instead powered by a small power supply built directly into the AC plug. These power supplies can absorb some power (e.g., from the wall) even when they are not supplying power to a load (e.g., a mobile phone). Switching power converters use active elements (e.g., bipolar junction transistors) that repeatedly absorb energy even when the system is "offline" or idle. Considering how many power converters of this type are in use, and considering the fact that they are rarely unplugged or disconnected from the input power, this energy absorption can be high. Typical topologies used in switching power converters are forward, flyback, boost, and buck converters.

[0003] Switching power converters typically require low voltage control circuitry, such as an integrated circuit (eg, an IC controller), that can switch the main power devices, such as power MOSFETs, on and off in response to the output voltage and current required by the power converter. Figure 1 FIG. 2 shows a switching power supply of the prior art. Figure 1 As shown, the power stage in the switching power supply 100 has several main elements, including a power switch 10 (such as a silicon MOSFET), an IC controller 11 that generates a signal (e.g., at a pulse width modulation pin) to turn the power switch "on" and "off", and a gate drive circuit 12 (e.g., an amplifier) ​​that applies the signal to the power switch 10. The power supply 100 may include a current sense (CS) connector 13, one side of which is connected to the source of the power switch 10 and the other side is connected to the CS pin of the IC controller 11. The current sense connector may have a resistive element 14, which is connected between the current sense node connection at the source of the power switch and a common node or ground rail. The power switch 10 is connected in series with an inductive element 15 (such as an inductor or transformer winding). The inductive element is connected to a positive input voltage 16, which may be an outlet or wall power (e.g., 120V or 240V or higher). The second inductive component 19 is magnetically coupled to the first inductive component 15 and is used to generate a switch supply power to the output terminal 18.

[0004] Offline power converters, such as when the power supply 100 is idle, face challenges when starting up (or coming online) due to the mismatch between the high voltage input power 16 (e.g., from the wall) and the low voltage power requirements of the IC controller 11. Conventional power converters, such as Figure 1 The prior art uses an array of components shown in the dashed area 110 to generate An input voltage (e.g., 12V-35V) is input to power or start the IC controller 11. The array of components may include a high voltage bipolar junction (BJT) transistor 20, a resistor 21, a diode 22 (which may be a Zener diode), a capacitor 23, a resistor 24, and a Zener diode 25. In addition to the main winding of the inductor component 15, the power supply 100 also includes an auxiliary winding 17. The auxiliary winding 17 from the inductor component can generate energy to power the IC controller during normal operation, and the IC controller 11 input voltage The requirement can be provided by the auxiliary winding 17 and adjusted by the resistor 26, the diode 27 (which can be a Zener diode) and the capacitor 28. The main disadvantage of using the startup circuit of the power supply 100 shown in the dashed area 110 is the use of the active component BJT transistor 20. When the power supply 100 is used in high voltage applications, such as those requiring 350V or more, the BJT switch 20 may dissipate a large amount of power, especially when the power supply is idle. As a result, alternative designs for startup power converters are needed to improve converter efficiency and reduce cost. Summary of the invention

[0005] This article describes a system-in-package (SIP) configuration for which low voltage enhancement mode devices and high voltage depletion mode III-N devices are used to start up a power converter. The low voltage enhancement mode devices, high voltage depletion mode III-N devices, controller ICs, gate drivers, and startup components can be integrated into a single electronic component module. When there is no need to distinguish any transistors or switches or diodes, the term device will be used to refer to them collectively.

[0006] In a first aspect, an electronic assembly is described. The electronic assembly includes a semiconductor device package. The semiconductor device package includes a conductive structure package base, a first terminal configured to be connected to an inductive load, and a second terminal configured to be connected to a common node or circuit ground. The package also includes an enhancement mode transistor and a depletion mode transistor. The depletion mode III-N transistor has a drain electrode, a source electrode, and a gate electrode. The enhancement mode transistor has a drain electrode, a source electrode, and a gate electrode. The drain electrode of the depletion mode III-N transistor is electrically connected to the first terminal, the source electrode of the depletion mode III-N transistor is electrically connected to the drain electrode of the enhancement mode transistor, the gate electrode of the depletion mode III-N transistor is electrically connected to the conductive structure package base, and the source electrode of the enhancement mode transistor is electrically connected to the conductive structure package base. The enhancement mode transistor is monolithically integrated with an IC controller and a gate driver on a common silicon substrate, wherein the anode of a rectifier diode is connected to the drain of the enhancement mode transistor and the cathode of the rectifier diode is connected to a voltage input terminal of the IC controller, and a storage capacitor has a first terminal and a second terminal, the first terminal is connected to the cathode of the rectifier diode, and the second terminal is connected to the conductive structure package base.

[0007] In a second aspect, an electronic circuit is described. The electronic circuit includes a first winding of an inductive component coupled to a high voltage node and a second winding of an inductive component coupled to a drain of a high voltage depletion mode transistor. The drain of the low voltage enhancement mode transistor is electrically connected to the source of the depletion mode transistor, the gate of the depletion mode transistor is electrically connected to the source of the enhancement mode transistor, and the source of the enhancement mode transistor is connected to circuit ground. The circuit also includes an IC controller, the IC controller includes at least four pins, wherein the first pin is a voltage input pin, the second pin provides a pulse width modulated output signal, the third pin is a current sensing pin electrically connected to the source of the enhancement mode transistor, and the fourth pin is electrically connected to circuit ground. The gate drive includes an input connected to the second pin and an output connected to the gate of the enhancement mode transistor, and the anode of the diode is electrically connected to the drain of the enhancement mode transistor, the cathode of the diode is electrically connected to the IC controller input pin, and the first terminal of the capacitor is electrically connected to the cathode of the diode and the second terminal of the capacitor is electrically connected to the circuit ground, wherein the enhancement mode transistor, the IC controller, the gate driver, the diode and the capacitor are monolithically integrated into a discrete semiconductor IC device.

[0008] In a third aspect, an electronic package is described. The electronic package includes a conductive structure packaging base, a first terminal, a second terminal, a first electronic component, and a second electronic component. The first electronic component includes a monolithic integrated circuit formed on a common silicon substrate. The monolithic integrated circuit includes an IC controller, a gate driver, a low voltage enhancement mode silicon MOSFET, and an IC controller startup circuit. The second electronic component includes a high voltage depletion mode GaN transistor with a gate to source threshold voltage, wherein the source electrode of the depletion mode GaN transistor is electrically connected to the drain electrode of the enhancement mode silicon MOSFET transistor. The first terminal is electrically connected to the drain electrode of the depletion mode GaN transistor and the second terminal is electrically connected to the conductive structure packaging base. The gate electrode of the depletion mode GaN transistor and the source electrode of the enhancement mode silicon MOSFET transistor are electrically connected to the conductive packaging base, wherein the IC controller The node is coupled to the drain electrode of an enhancement mode silicon MOSFET within the monolithic integrated circuit.

[0009] The electronic circuits and / or transistors described herein may include one or more of the following features. A rectifier diode and a storage capacitor may form an IC startup circuit, and the IC startup circuit may be monolithically integrated with an enhancement mode transistor on a common substrate. The depletion mode III-N transistor may be a high voltage GaN HEMT having a breakdown voltage greater than 600V and a gate to source threshold voltage of -15V or less. The enhancement mode transistor may be a low voltage silicon MOSFET device having a breakdown voltage greater than the absolute value of the depletion mode transistor threshold voltage. The source and drain electrodes of the depletion mode transistor may be on a first side of a III-N material structure above an electrically conductive substrate, and the gate electrode may be on a second side of the III-N material structure opposite the first side.

[0010] The IC controller may include a ground terminal connected to a conductive structure package base, a current sensing terminal electrically connected to a source electrode of an enhancement mode transistor, and a gate drive terminal connected to a gate electrode of the enhancement mode transistor. When the first terminal of the package is biased at a voltage greater than 300V, the second terminal of the package may be connected to circuit ground, and when the electronic component is in an off state, the drain of the enhancement mode transistor may maintain a positive voltage between +15V and +25V relative to the source electrode of the enhancement mode transistor, and a startup voltage may be provided from the drain of the enhancement mode transistor to the IC controller. The rectifier diode need not be a Zener diode.

[0011] The threshold voltage of the GaN HEMT device can be less than -12V. When the electronic circuit is idle or offline, the drain to source voltage of the enhancement mode transistor can be greater than +10V. When the circuit is idle or offline, a startup voltage can be provided to a voltage input pin of an IC controller from the drain to source voltage of the enhancement mode transistor. The discrete semiconductor IC device and the GaN HEMT device can be assembled into a single electronic component package. The single electronic component package can include a conductive structure package base, a substrate of the discrete semiconductor IC device, and a substrate of the GaN HEMT device can be physically attached to the conductive structure package base. The IC controller startup circuit can include coupling between the drain electrode of the enhancement mode silicon MOSFET and Capacitor and diode between nodes. When the depletion mode GaN transistor is biased below the gate-to-source threshold voltage, the drain-to-source voltage of the enhancement mode silicon MOSFET can be biased at +12V or higher.

[0012] As used herein, a "hybrid enhancement mode electronic device or component" or simply a "hybrid device or component" is an electronic device or component formed by a depletion mode transistor and an enhancement mode transistor, wherein the depletion mode transistor is capable of achieving a higher operating and / or breakdown voltage than the enhancement mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement mode transistor, whose breakdown and / or operating voltage is as high as the breakdown and / or operating voltage of the depletion mode transistor. That is, the hybrid enhancement mode device or component includes at least 3 nodes with the following properties. When the first node (source node) and the second node (gate node) are maintained at the same voltage, the hybrid enhancement mode device or component can block a positive high voltage (i.e., a voltage greater than the maximum voltage that the enhancement mode transistor can block) applied to the third node (drain node) relative to the source node. When the gate node is maintained at a sufficiently positive voltage relative to the source node (i.e., greater than the threshold voltage of the enhancement mode transistor), current flows from the source node to the drain node, or when a sufficiently positive voltage is applied to the drain node relative to the source node, current flows from the drain node to the source node. When the enhancement mode transistor is a low voltage device and the depletion mode transistor is a high voltage device, the hybrid assembly can operate similar to a single high voltage enhancement mode transistor. The breakdown voltage and / or maximum operating voltage of the depletion mode transistor can be at least two times, at least three times, at least five times, at least ten times, or at least twenty times the breakdown voltage and / or maximum operating voltage of the enhancement mode transistor.

[0013] As used herein, the term III-nitride or III-N material, layer, device, etc. refers to a material composed according to the stoichiometric formula A material or device composed of a compound semiconductor material, wherein is about 1, and , , and III-N materials, layers, or devices may be formed or prepared by growing directly on a suitable substrate (e.g., by metal organic chemical vapor deposition) or by growing on a suitable substrate, separating from the original substrate, and bonding to another substrate.

[0014] As used herein, two or more contacts or other items (such as conductive channels or components) are said to be "electrically connected" if they are connected by a material that is sufficiently conductive to ensure that the potential at each of the contacts or other items always tends to be the same (e.g., approximately the same) under any biasing conditions.

[0015] As used herein, "drain electrode", "source electrode" and "gate electrode" refer to a portion of a source, drain or gate of a device for electrical connection to an external structure or device. For example, a drain of a device can be electrically connected to another device by forming a wire bond on the drain electrode.

[0016] As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent a large current (such as a current greater than 0.001 times the operating current during normal conduction) from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, while the transistor, device, or component blocks the voltage applied thereto, the total current flowing through the transistor, device, or component will not be greater than 0.001 times the operating current during normal conduction. Devices with off-state currents greater than this value exhibit high losses and low efficiency and are generally unsuitable for many applications, particularly power switching applications.

[0017] As used herein, a "high voltage device," such as a high voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS), is an electronic device optimized for high voltage applications. That is, when the device is turned off, it is capable of blocking high voltages, such as about 300 V or more, about 600 V or more, or about 1200 V or more, and when the device is turned on, it has a sufficiently low on-resistance (ON) for the application in which it is used. ), for example, when a large amount of current passes through the device, it experiences sufficiently low conduction losses. A high voltage device may be able to block at least a voltage equal to the high voltage power supply or the maximum voltage in the circuit in which it is used. A high voltage device may be able to block 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltage required by the application. In other words, a high voltage device can block 0V to at least All voltages between is the maximum voltage that a circuit or power supply can supply, and It can be, for example, 300V, 600V, 1200V, 1700V, 2500V or other suitable blocking voltage required by the application. For a bidirectional or four-quadrant switch, when the switch is turned off, the blocking voltage can be less than a certain maximum value ( , such as 300V or 600V, 1200V, etc.), and when the switch is turned on, the current can be in either direction.

[0018] As used herein, a "III-N device" is a device having a conducting channel formed in a III-N material. A III-N device may be designed to operate as a transistor or switch, wherein the state of the device is controlled by a gate terminal, or designed to operate as a two-terminal device, which blocks current flow in one direction and conducts in the other direction without a gate terminal. A III-N device may be a high voltage device suitable for high voltage applications. In such a high voltage device, when the device is biased off (e.g., the voltage on the gate relative to the source is less than the device threshold voltage), it is at least capable of supporting all source-drain voltages less than or equal to the high voltage in the application in which the device is used, which may be, for example, 100V, 300V, 600V, 1200V, 1700V, 2500V or higher. When the high voltage device is biased (e.g., the voltage on the gate relative to the source or associated power supply terminal is greater than the device threshold voltage), it is capable of conducting a large amount of current with a low on-voltage (i.e., a low voltage between the source and drain terminals or between the relative power supply terminals). The maximum allowed on-voltage is the maximum on-state voltage that can be maintained in the application in which the device is used.

[0019] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one layer relative to other layers. Thus, for example, a layer located above or below another layer may be directly in contact with the other layer, or may have one or more intervening layers. Additionally, a layer located between two layers may be directly in contact with both layers, or may have one or more intervening layers. Conversely, a first layer located "above" a second layer is in contact with the second layer. Additionally, the relative position of one layer relative to other layers is provided assuming that operations are performed relative to a substrate, without regard to the absolute orientation of the substrate.

[0020] In a typical power switch application using a high voltage switching transistor, the transistor is in one of two states during most of the time. In the first state, which is usually referred to as the "on state", the voltage of the gate electrode relative to the source electrode is higher than the transistor threshold voltage, and a large amount of current flows through the transistor. In this state, the voltage difference between the source and the drain is usually low, usually not more than a few volts, such as about 0.1-5 volts. In the second state, which is usually referred to as the "off state", the voltage of the gate electrode relative to the source electrode is lower than the transistor threshold voltage, and no large amount of current flows through the transistor except for the off state leakage current. In the second state, the voltage range between the source and the drain can be from about 0V to the value of the circuit high voltage power supply, which may be as high as 100V, 300V, 600V, 1200V, 1700V or higher in some cases, but may be lower than the breakdown voltage of the transistor. In some applications, the inductive element in the circuit causes the voltage between the source and the drain to be even higher than the circuit high voltage power supply. Additionally, there is a short time immediately after the gate is turned on or off, during which the transistor is in a transition mode between the above two states. When the transistor is in the off state, this is referred to as a "blocking voltage" between the source and drain. As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent a large current (e.g., a current greater than 0.001 times the average operating current during normal on-state conduction) from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, the total current flowing through the transistor, device, or component will not be greater than 0.001 times the average operating current during normal on-state conduction while the transistor, device, or component is blocking the voltage applied thereto.

[0021] The details of one or more disclosed embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Additional features and variations may also be included in the embodiments. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a circuit diagram of a power converter in the prior art.

[0023] Figure 2 is a circuit schematic of a hybrid III-N device in a cascode configuration.

[0024] Figure 3 is a circuit diagram of a power converter using a cascode configuration.

[0025] Figure 4 is a circuit schematic of a power converter with a monolithically integrated controller.

[0026] Figure 5 is a circuit diagram of the system-in-package power converter.

[0027] Fig. 6A and Figure 6B is a cross-sectional diagram of a III-N depletion mode power device.

[0028] Figure 7 is a plan view of the system power converter within the package.

[0029] Like reference numbers in the various drawings represent like elements. DETAILED DESCRIPTION

[0030] This article describes a system-in-package (SIP) configuration for which low voltage enhancement mode transistors and high voltage depletion mode III-N transistors are used to start a switching power converter. The low voltage enhancement mode transistors, high voltage depletion mode III-N transistors, controller ICs, gate drivers, and startup components can be integrated into a single electronic component package or module. In addition, the low voltage devices, controller elements, and startup components can be monolithically integrated and formed with a common IC substrate. Compared to traditional power conversion solutions, SIPs can have reduced component count and integration efficiency, thereby reducing production costs and improving system performance.

[0031] Typical power semiconductor devices (such as Figure 1 The power MOSFET in 10 is made of silicon (Si) semiconductor material. Recently, wide bandgap materials (such as III-N materials) have been considered for use in power devices due to their excellent properties. III-nitride or III-N semiconductor devices (such as gallium nitride (GaN / AlGaN) HEMT devices) are now becoming attractive candidates to carry high currents, support high voltages, and provide very low on-resistance and fast switching times.

[0032] Most conventional III-N HEMT and related transistor devices are normally-on (i.e. have a negative threshold voltage), meaning that they are on at zero gate-to-source voltage ( ) when conducting current. These devices with negative threshold voltage are called depletion mode (D-mode) devices. In power electronics, normally-off devices (i.e. devices with positive threshold voltage) are preferably used, which conduct current at zero Normally off devices are often referred to as enhanced mode (E-mode) devices.

[0033] To date, reliable fabrication and operation of high voltage E-mode III-N transistors has proven to be very difficult. An alternative to a single high voltage E-mode III-N transistor is to combine a high voltage D-mode III-N transistor with a low voltage silicon E-mode FET in a cascode configuration. Figure 2 As shown, the cascode configuration 200 includes a high voltage D-mode III-N device 32 and a low voltage E-mode device 30 to form a hybrid III-N device 210. The source of the D-mode device 32 is electrically connected to the drain of the E-mode device 30 at node 33. The gate of the D-mode device 32 is electrically connected to the source of the E-mode device 30 through a connector 31. The gate of the E-mode device 30 can be used as the gate electrode 34 of the hybrid device 210 and can be controlled by a standard gate drive value (such as 1.6V to 20V). Figure 2 The device shown configured in the cascode configuration 200 can be operated in the same manner as a single high voltage E-mode transistor, where the drain of the D-mode device serves as the drain electrode 35 of the hybrid device 210 and the source of the E-mode device 30 serves as the source electrode of the hybrid III-N device 210, and in many cases achieves the same or similar output characteristics as a single high voltage normally-off transistor.

[0034] Figure 3 A schematic diagram of a switching power supply 300 is shown, wherein Figure 2 The hybrid III-N device 210 replaces Figure 1 The hybrid III-N device 210 includes a high voltage depletion mode (D-mode) III-N device 32, such as a GaN HEMT transistor. The III-N device 32 may have a breakdown voltage greater than 600V and may be capable of supporting a drain-source current greater than 15A ( ).

[0035] Depletion mode III-N devices are normally-on devices, i.e., when the gate to source voltage is biased at zero volts, the device is "on", and when the gate to source voltage of the III-N device is biased at a negative voltage less than the device threshold voltage, the device is "off". For example, the III-N device 32 may have a substantially negative threshold voltage of -15V, and the device may be biased "off" by biasing the gate to source voltage at -20V or lower (where lower is considered more negative). In some embodiments, the III-N device has a negative threshold voltage between -12V and -30V. The threshold voltage required for the III-N device 32 is critical to the startup voltage requirements of the power supply 300, and will be more clearly outlined further in this specification. The hybrid III-N device 210 includes a low voltage enhancement mode (E-mode) device 30, such as a silicon MOSFET transistor. The enhancement mode device 30 may have a threshold voltage between 1.6V-6V. The breakdown voltage of the enhancement mode device 30 may be greater than the absolute value of the threshold voltage of the depletion mode III-N device 32. The depletion mode III-N device 32 and the enhancement mode device 30 may be co-packaged in a single hybrid electronic component package.

[0036] The source of the III-N device 32 is electrically connected to the drain of the E-mode device 30 at a node 33. The gate of the III-N device 32 is electrically connected to the source of the E-mode device 30 through a connection line 31. The switching power supply 300 includes an inductive component 15 having a plurality of windings (such as a transformer), each winding having a pair of terminals. A first terminal of a first winding of the inductive component 15 can be coupled to an input power supply 16, and a second terminal of the first winding is electrically connected to the drain of the III-N device 32. A second inductive component 19 is magnetically coupled to the first inductive component 15 and is used to generate a switch supply power to an output terminal 18.

[0037] The gate of the low voltage enhancement mode device can serve as the gate of the hybrid III-N device 210. An integrated circuit (IC) controller 11 and a gate driver 12 can be used to transmit a pulse width modulation (PWM) signal to control the gate drive mode to meet the output requirements of the power supply 300. The IC controller 11 may include at least 4 input / output pins or terminals. The first pin may be a voltage input pin or , a second pin can provide a PWM signal to the gate driver 12, a third pin can connect the current sensing (CS) loop 13 to the source of the enhancement mode device 30, and a fourth pin can be connected to the circuit ground or a common node. Optionally, the current sensing loop 13 may require a sense resistor 14 to be configured between the current sensing loop 13 and the common node or circuit ground.

[0038] Switching power converters such as power supply 300 typically require low voltage control circuitry, such as IC controller 11, that can turn the main power device (i.e., hybrid device 210) on and off in response to the output voltage and output current required by the power converter. The cascode configuration of hybrid device 210 can easily provide the low voltage startup needs of IC controller 11 when the power supply is in an "offline" or idle state. For example, IC controller 11 may require +10 to +35 volts to start. When the hybrid device 210 is in the "off" state, the high voltage D-mode III-N device blocks the input voltage (e.g., voltage from the wall), and the drain-to-source voltage of the E-mode device 30 is stabilized near the absolute value of the threshold voltage of the D-mode III-N device 32. Since the gate of the D-mode device 32 is tied (i.e., electrically connected) to the source of the E-mode device 30, the gate voltage of the D-mode device 32 is substantially fixed at or near 0V. This means that if the D-mode device 32 has a negative gate-to-source threshold voltage of -15V, the voltage node 33 between the source of the D-mode device 32 and the drain of the E-mode device 30 will remain at around +15V (relative to the source of the E-mode device 30) while the hybrid III-N device is biased in the "off" state. For example, when the D-mode III-N device is in the "off" state and blocks the high voltage input supply, the drain-to-source voltage of the E-mode device 30 can be maintained within + / -5 volts or + / -2 volts of the absolute value of the threshold voltage of the D-mode III-N device 32. When the power supply is in the "offline" or idle state and the hybrid device 210 blocks the high voltage input supply, the voltage maintained at the voltage node 33 (i.e., the gate-to-source voltage of the E-mode device 30) can fully supply the voltage required to "start" the IC controller 11.

[0039] The simplified required startup circuitry of the power supply 300 is shown in the dashed area 310. The anode of the rectifier diode 36 can be electrically connected to the voltage node 33 between the source of the D-mode device 32 and the drain of the E-mode device 30. The cathode of the diode 36 can be connected to the first terminal of the energy storage capacitor 37 and the IC controller 11. Input voltage terminal. The second terminal of the energy storage capacitor 37 can be connected to a common node or circuit ground. Compared to the Zener diode required in circuit 100, the rectifier diode 36 can be a standard pn diode in circuit 300. This can further improve circuit efficiency because Zener diodes are less energy efficient than standard pn diodes due to dissipating power in reverse conduction mode. Among them, in the "off" state, the voltage maintained between the D-mode and E-mode devices of the hybrid device in the cascode configuration is used to power the startup requirements of the IC controller 11. The value of the energy storage capacitor 37 can be selected depending on the power consumption requirements of the IC controller 11. For example, the input voltage 16 can be greater than 600V, and the III-N device 32 can be capable of "blocking" a voltage greater than the input voltage. When the hybrid device 210 "blocks" the input voltage, the voltage at the source of the III-N device 33 can be, for example, around +15V, and is thereby used to power the startup of the IC controller 11.

[0040] and Figure 1 Compared with the startup circuit system shown in the dashed area 110, the startup voltage is drawn from the input voltage 16. Figure 1 The complexity of the power supply 100 and the power supply 300 is greatly reduced. In addition, by eliminating the need to start the conventional switching power supply Figure 1 The BJT transistor 20 (or JFET or N-channel start-up MOSFET) can reduce power loss and improve efficiency. Figure 1 The active and passive component count of the startup circuit system 110 is at least 9 components, with Figure 3 Compared to the startup circuit system 310 shown, it can be reduced to only two components (a diode and a capacitor). The power supply 300 does not require Figure 1 The auxiliary winding 17 of the inductive component 15 is shown to power the IC controller 11, which may result in a significant increase in size and weight of the power converter.

[0041] Figure 4 4 shows a schematic diagram of a switching power supply 400. The power supply 400 is similar to Figure 3400 is a power supply 300 of the present invention, except that the power supply 400 includes a monolithic IC 410. The monolithic IC 410 includes an enhancement mode FET device 30, an IC controller 11, and a gate driver 12, which are monolithically integrated and formed on a common device substrate (e.g., a silicon substrate). Optionally, the monolithic IC 410 may also include a current sense resistor 14 integrated on the common substrate. The features of the power supply 400 can be assembled into a single electronic component package 420. The component package 420 can include a conductive structural package base (not shown) that is configured as a circuit ground. The depletion mode III-N transistor 32, the monolithic IC 410, the rectifier diode 36, and the energy storage capacitor 37 can be mounted to the structural package base. The second terminal of the capacitor 37 can be electrically connected to the package base.

[0042] Figure 5 Schematic diagram of a switching power supply 500 is shown. The power supply 500 is similar to Figure 4 400, except that the power supply 500 includes a monolithic IC 510. The monolithic IC 510 is similar to the monolithic IC 410, except that the monolithic IC 510 also includes the required startup circuit system (indicated by area 310), which is monolithically integrated into the same common substrate (e.g., a silicon substrate) as the IC controller 11, the gate driver 12, and the E-mode device 30. It should be understood that the monolithic IC 510 includes two different physical parts, namely different non-overlapping areas on the common substrate. The first part includes the low voltage enhancement mode transistor 30, and the second part 512 includes the startup circuit system 310, the IC controller 11 and the gate driver 12. The startup circuit system 310 may include at least Figure 3 The diode 28 and the capacitor 25 are shown in the dashed area 310. The anode of the diode 28 is electrically connected to the drain of the enhancement mode device 30 and is integrated with the metal wiring layer internally.

[0043] In addition, the monolithic IC 510 and the depletion mode III-N device 32 can be assembled into a single electronic component package 520 to form a simplified system-in-package (SIP) configuration. The SIP package 520 includes a co-package of the high voltage III-N device 32, the low voltage MOSFET 30, the gate driver 12, the IC controller 11, and the startup circuitry, which are co-integrated into a single package. When the package 520 is co-packaged with the monolithic IC device 510, the component count of the SIP package 520 can be reduced to include only two discrete electronic semiconductor components, wherein the first discrete component is the high voltage III-N device 32 and the second discrete component is the monolithic IC 510. The SIP package 520 may include at least two terminals, wherein the first terminal is configured to be connected to an inductive component (e.g., Figure 4The first discrete component and the second discrete component are physically mounted to the structural package base.

[0044] Fig. 6A FIG. 1 shows a cross-sectional view of a depletion mode III-N device 600 that can be used as a Figure 3 . The III-N device 600 includes a substrate 60, which may be formed of silicon, sapphire, silicon carbide, GaN, or other suitable materials. A III-N material structure 61 is formed over the substrate 60. The III-N material structure 61 may include a III-N buffer layer 62 (e.g., AlN / AlGaN / GaN), a III-N channel layer 63 (e.g., GaN), and a III-N barrier layer 64 (e.g., AlGaN). The III-N barrier layer 64 has a higher bandgap than the III-N channel layer 63.

[0045] The composition difference between the barrier layer 64 and the channel layer 63 results in a two-dimensional electron gas channel 69 (i.e., a 2DEG channel) in a region of the channel layer 63 near the interface of the barrier layer 63. While the gate electrode 67A is biased at zero volts, the 2DEG channel 69 can extend continuously between the source electrode 65 and the drain electrode 66 so that the III-N device 600 is characterized as a depletion mode device.

[0046] An insulating layer 68 (e.g., a SiN passivation layer or a gate dielectric layer) is formed over the top surface of the III-N material structure 61 and between the gate electrode 67A and the top surface of the III-N material structure 61. The thickness of the insulating layer 68 between the gate electrode 67A and the top surface of the III-N material structure 61 can be used to adjust the threshold voltage of the device, where a thicker insulating layer at this location drives the threshold voltage more negative. The III-N device 600 is a lateral device characterized in that the source electrode 65 and the drain electrode 66 are formed on the same side of the III-N material structure. As shown in FIG. Fig. 6A As shown, drain electrode 66 , source electrode 65 , and gate electrode 67A each include a portion of the electrode extending above insulating layer 68 , and allow electrical connection to the outside of each electrode by, for example, wire-bond.

[0047] Figure 6B is a cross-sectional view of a depletion mode III-N device 610 similar to Fig. 6A However, the III-N device 610 has a gate connected substrate, which allows the gate electrode to be formed on the side of the III-N material structure opposite the source and drain electrodes. Figure 6B As shown, the gate 67B includes a metal portion 67' that extends beyond the device active region 602 (i.e., the active region is located between the source and drain) into the passive region 603, which is electrically isolated from the 2DEG channel 69, for example, by an ion implantation step. A via 605 is formed through the III-N material structure to the surface of a substrate 606. The substrate 606 can be an electrically conductive substrate silicon substrate, such as a p+ or n+ doped substrate. The metal portion 67' of the gate 67B is formed in the via 605 in the passive region 603 and contacts the conductive substrate 606. A metal layer is formed on one side of the back side of the substrate to form a gate electrode 607.

[0048] If an insulating substrate, such as a sapphire substrate, is used, the via 605 may extend through the entire thickness of the substrate (not shown), and a metal portion 67' may be formed in the via 605 and electrically connected to a metal layer formed on the back side of the substrate. A source electrode 65 and a drain electrode 66 are formed on a first side of the III-N material structure 61, and a gate electrode 607 is formed on a second side opposite the first side. When the III-N device 610 is implemented as Figure 3 When using a depletion mode III-N device in 32, packaging complexity is reduced by eliminating the need for gate connection wire bonds.

[0049] Figure 7 7 is a plan view of an electronic component 700, such as an electronic module or package, which contains a plurality of semiconductor devices. The electronic component 700 includes an electronic component package 710, which may be similar to Figure 5 The electronic assembly 700 includes a system in package (SIP) 520 previously described in the prior art and includes a conductive structure package base 720. The electronic assembly 700 includes as few as two discrete semiconductor devices. The first discrete semiconductor device is a high voltage depletion mode device. In the electronic assembly 700, Figure 6B The III-N device 610 is used to form Figure 5 The second discrete semiconductor device is a low voltage enhancement mode device monolithically integrated with an IC controller and gate driver. In assembly 700, Figure 5 The monolithic IC 510 shown in FIG. 5 may be used as the second discrete semiconductor device.

[0050] Figure 7The monolithic IC 510 shown may include a first portion including a low voltage enhancement mode transistor 30, and a second portion 512 including components required for startup, an IC controller, and a gate driver. The assembly 700 includes at least one first terminal 52, which may be configured to connect to an inductive component and extends from the package 520 and is electrically connected to the drain electrode 66 of the III-N device 610. The conductive structure package base 710 may be configured to connect to a common mode or circuit ground. The second terminal 54 (which may be configured to connect to a common mode or system ground) extends from the package 520 and is electrically connected to the package base 520.

[0051] The substrate of the depletion mode III-N device 610 is directly mounted and electrically connected to the package base 520, so that the gate electrode 607 of the device 610 is electrically connected to the package base 520. The enhancement mode device 30 can be a lateral MOSFET device, such as an LDMOS type device, in which the source electrode and the drain electrode are both formed on the same side of the device (i.e., the top side). In this case, the source electrode 65 of the III-N device 610 can be electrically connected to the drain electrode 71 of the enhancement mode device 30 by, for example, wire bonding. In another embodiment, an LDMOS type device can be used, in which the source electrode is formed on the bottom side of the device opposite the drain electrode (not shown), so that the source electrode can be directly electrically connected and physically mounted to the package conductive structure base. The source electrode 71 of the device 30 can be connected to the conductive package base 520 by wire bonding. The monolithic IC 510 includes a second portion 512, wherein the portion 512 includes an integrated circuit for forming a startup circuit system, an IC controller, and a gate driver. The startup circuit system can be powered by and electrically connected to the drain electrode 71 through an internal metal wiring connection. The PWM of the IC controller and gate driver may be connected to the gate electrode of the enhancement mode device 30 through internal metal wiring connections.

[0052] When using system-in-package solutions such as Figure 7 The integrated electronic assembly 700 shown in FIG. Figure 4 , Figure 5 and Figure 6A-6B The efficiency and manufacturing assembly requirements of a switching power supply can be greatly improved when the circuit schematic shown in FIG. 1 is used. The overall component count and cost are reduced. The system "off-line" efficiency is improved by eliminating the active components used in the startup power supply.

[0053] A variety of implementations have been described. However, it will be appreciated that various modifications may be made without departing from the spirit and scope of the techniques and apparatus described herein. Accordingly, other implementations are within the scope of the appended claims.

Claims

1. An electronic component comprising: A semiconductor device package, the semiconductor device package comprising: a conductive structure package base, a first terminal configured to be connected to an inductive load, and a second terminal configured to be connected to a common node or circuit ground, A depletion mode III-N transistor having a drain, a source and a gate, An enhancement mode transistor having a drain, a source and a gate, IC controller, and Gate driver; wherein the drain of the depletion mode III-N transistor is electrically connected to the first terminal, the source of the depletion mode III-N transistor is electrically connected to the drain of the enhancement mode transistor, the gate of the depletion mode III-N transistor is electrically connected to the conductive structure package base, the source of the enhancement mode transistor is electrically connected to the conductive structure package base, and wherein the enhancement mode transistor is monolithically integrated with the IC controller and the gate driver on a common silicon substrate; a rectifying diode having an anode connected to the drain of the enhancement mode transistor and a cathode connected to a voltage input terminal of the IC controller; and A storage capacitor has a positive side connected to the cathode of the rectifier diode and a negative side connected to the conductive structure package base.

2. The electronic component according to claim 1, wherein: The rectifying diode and the energy storage capacitor form an IC startup circuit, and the IC startup circuit and the enhancement mode transistor are monolithically integrated on the common silicon substrate.

3. The electronic component according to claim 1, wherein: The depletion mode III-N transistor is a high voltage GaN HEMT with a breakdown voltage greater than 600V and a gate to source threshold voltage of -15V or less.

4. The electronic component according to claim 3, wherein: The enhancement mode transistor is a low voltage silicon MOSFET device having a breakdown voltage greater than the absolute value of the depletion mode transistor threshold voltage.

5. The electronic component according to claim 1, wherein: The depletion mode transistor has a source electrode and a drain electrode on a first side of a III-N material structure above an electrically conductive substrate, and a gate electrode on a second side of the III-N material structure opposite the first side.

6. The electronic component according to claim 5, wherein: The gate electrode is electrically connected to the conductive structure package base through the electrically conductive substrate of the depletion mode III-N transistor.

7. The electronic component according to claim 4, wherein: The IC controller also includes a ground terminal connected to the conductive structure package base, a current sensing terminal electrically connected to a source electrode of the enhancement mode transistor, and a gate drive terminal connected to a gate electrode of the enhancement mode transistor.

8. The electronic component according to claim 7, wherein: When the first terminal of the package is biased at a voltage greater than 300 V, the second terminal of the package is connected to circuit ground, and the electronic component is in an off state, the drain of the enhancement mode transistor maintains a positive voltage between +15 V and +25 V relative to the source electrode of the enhancement mode transistor, and a startup voltage is provided from the drain of the enhancement mode transistor to the IC controller.

9. The electronic module according to claim 7, wherein: The rectifying diode is not a Zener diode.

10. An electronic circuit comprising: a high voltage depletion mode transistor having a gate, a source, a drain, and a threshold voltage; a low voltage enhancement mode transistor having a gate, a source and a drain, wherein the drain of the low voltage enhancement mode transistor is electrically connected to the source of the depletion mode transistor, the gate of the depletion mode transistor is electrically connected to the source of the enhancement mode transistor, and the source of the enhancement mode transistor is configured to be connected to circuit ground; an inductor component having a first winding configured to be electrically connected to a high voltage power source and a second winding electrically connected to a drain of the high voltage depletion mode transistor; an IC controller comprising at least four pins, wherein a first pin is a voltage input pin, a second pin provides a pulse width modulated output signal, a third pin is a current sensing pin electrically connected to a source of the enhancement mode transistor, and a fourth pin is configured to be electrically connected to the circuit ground; a gate driver comprising an input connected to the second pin and an output connected to a gate of the enhancement mode transistor; a diode having an anode electrically connected to the drain of the enhancement mode transistor and a cathode electrically connected to the IC controller voltage input pin; and a capacitor having a positive side and a negative side, the positive side being electrically connected to the cathode of the diode and the negative side being configured to be electrically connected to the circuit ground, wherein the enhancement mode transistor, the IC controller, the gate driver, the diode and the capacitor are monolithically integrated into a discrete semiconductor IC device.

11. The electronic circuit according to claim 10, wherein: The discrete semiconductor IC device is a silicon-based device and the depletion mode transistor is a GaN HEMT device.

12. The electronic circuit according to claim 11, wherein The threshold voltage of the GaN HEMT device is -12V or lower.

13. The electronic circuit according to claim 12, wherein: The high voltage depletion mode transistor is configured such that a drain to source voltage of the enhancement mode transistor is maintained within 2V of an absolute value of the threshold voltage of the high voltage depletion mode transistor when the high voltage depletion mode transistor is in an off state and blocking the high voltage power supply.

14. The electronic circuit of claim 13, wherein the coupling between the voltage input pin of the IC controller and the drain of the enhancement mode transistor is such that when the high voltage depletion mode transistor is in an off state and blocks the high voltage power supply, a voltage required to start the IC controller is supplied from the coupling.

15. The electronic circuit according to claim 14, wherein: The discrete semiconductor IC device and the GaN HEMT device are assembled into a single electronic component package.

16. The electronic circuit according to claim 15, wherein The single electronic component package includes a conductive structure package base, and the substrate of the discrete semiconductor IC device and the substrate of the GaN HEMT device are directly mounted and physically attached to the conductive structure package base.

17. An electronic package comprising: Conductive structure packaging base; a first terminal and a second terminal; as well as a first electronic assembly comprising a monolithic integrated circuit formed on a common silicon substrate, and wherein the monolithic integrated circuit comprises an IC controller, a gate driver, a low voltage enhancement mode silicon MOSFET, and an IC controller startup circuit; a second electronic component comprising a high voltage depletion mode GaN transistor having a gate to source threshold voltage; and wherein the source electrode of the depletion mode GaN transistor is electrically connected to the drain electrode of the enhancement mode silicon MOSFET transistor, the first terminal is electrically connected to the drain electrode of the depletion mode GaN transistor and the second terminal is electrically connected to the conductive package base, the gate electrode of the depletion mode GaN transistor and the source electrode of the enhancement mode silicon MOSFET transistor are electrically connected to the conductive package base, and the IC controller A node is coupled to a drain electrode of the enhancement mode silicon MOSFET within the monolithic integrated circuit.

18. The electronic package of claim 17, wherein: The IC controller startup circuit includes a circuit coupled to the A capacitor and a diode between the node and the drain electrode of the enhancement mode silicon MOSFET.

19. The electronic package of claim 18, wherein: The gate-to-source threshold voltage of the depletion mode GaN transistor is less than -12V.

20. The electronic package of claim 19, wherein: When the depletion mode GaN transistor is biased below the gate-to-source threshold voltage of the GaN transistor, the drain-to-source voltage of the enhancement mode silicon MOSFET is biased at +12V or higher.

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