Method and apparatus for determining result of addition of multiple input binary numbers

Abstract

Methods and apparatus for segmented addition into an accumulation register using one or more carry track registers, where the accumulation register includes a first plurality of qubits, each qubit representing a respective bit of a first binary number, and each carry track register includes a plurality of qubits representing a respective binary number. In one aspect, a method includes inserting one or more carry track registers into an accumulation register at respective predetermined qubit positions of the accumulation register, respectively; initializing each quantum bit of each carry track register in a normal state; applying one or more subtraction operations to the accumulation register, wherein each subtraction operation subtracts a state of a respective carry track register from a corresponding portion of the accumulation register; and adding the one or more input binary numbers to the accumulation register using segmented addition.

Description

[0001] This application is a divisional application of the invention patent application with application date of March 27, 2020, application number 202080024944.6, and invention name “Inadvertent carry track register for performing segmented addition”. Background Art

[0002] This specification relates to quantum computing.

[0003] Classical computers have a memory made up of bits, each of which can represent either zero or one. Quantum computers maintain sequences of quantum bits, called qubits, where each qubit can represent zero, one, or any quantum superposition of zero and one. Quantum computers operate by setting the qubits in an initial state and, for example, controlling the qubits according to a series of quantum logic gates. Summary of the invention

[0004] This specification describes techniques for performing piecewise addition using oblivious carry track registers.

[0005] In general, one innovative aspect of the subject matter described in this specification can be implemented by a method of piecewise addition using one or more carry rail registers into an accumulation register, wherein the accumulation register includes a first plurality of qubits, each qubit representing a corresponding bit of a first binary number, and wherein each carry rail register includes a plurality of qubits representing the corresponding binary number, the method comprising: inserting one or more carry rail registers into the accumulation register at corresponding predetermined qubit positions of the accumulation register; initializing each qubit of each carry rail register in a positive state; applying one or more subtraction operations to the accumulation register, wherein each subtraction operation subtracts the state of the corresponding carry rail register from a portion of the accumulation register starting at the predetermined qubit position where the corresponding initialized carry rail register is inserted and ending at the qubit position before the next inserted carry rail or the most significant bit of the first binary number; and adding the one or more input binary numbers to the accumulation register using piecewise addition.

[0006] Other implementations of these aspects include corresponding computer systems, apparatuses, and computer programs recorded on one or more computer storage devices, each of which is configured to perform the actions of the method. A system of one or more classical and / or quantum computers may be configured to perform specific operations or actions by installing software, firmware, hardware, or a combination thereof on the system, which software, firmware, hardware, or a combination thereof in operation causes the system to perform the actions. One or more computer programs may be configured to perform specific operations or actions by including instructions that, when executed by a data processing device, cause the device to perform the actions.

[0007] The above and other implementations may each optionally include one or more of the following features, alone or in combination. In some implementations, adding one or more input binary numbers to an accumulation register using segmented addition includes: separating the input binary numbers into segments corresponding to portions of the accumulation register between each carry track register, performing a corresponding addition operation on each corresponding input binary number to add the input binary number to a state of the portion of the corresponding accumulation register, wherein a carry from the addition operation is added to the state of the corresponding carry track register of the portion of the accumulation register.

[0008] In some implementations, inserting one or more carry track registers into the accumulation register at corresponding predetermined qubit positions of the accumulation register includes inserting a predetermined number of carry track registers at even intervals.

[0009] In some implementations, subtracting the state of the corresponding carry rail register from the portion of the accumulation register starting at the predetermined qubit position where the corresponding initialized carry rail register was inserted and ending at the qubit position before the next inserted carry rail or the most significant bit of the first binary number includes: subtracting the value encoded in the carry rail register state from the state value of the portion of the accumulation register, and updating the state of the portion of the accumulation register to encode the new value.

[0010] In some implementations, the method further includes: adding states of the one or more carry track registers to corresponding portions of an accumulation register; and measuring the accumulation register to determine a result of adding the one or more input binary numbers.

[0011] In some implementations, the method further includes determining whether each qubit in the one or more carry track registers is properly initialized.

[0012] In some implementations, the method further includes: measuring the accumulator register and one or more carry track registers; and removing the state of the one or more carry track registers from the state of the accumulator register by classical processing to determine the result of the piecewise addition.

[0013] In some implementations, addition operations are performed in parallel on segments of the same input binary number.

[0014] In some implementations, each qubit in the first plurality of qubits represents a corresponding bit of a first binary number stored in little-endian 2s' complement integer format, and each qubit in the corresponding carry track register represents a corresponding binary number stored in little-endian 2s' complement integer format.

[0015] In some implementations, the addition operation includes a 2s complement addition operation.

[0016] In some implementations, the addition operation includes a modular addition operation.

[0017] The subject matter described in this specification can be implemented in a specific way to realize one or more of the following advantages.

[0018] Systems implementing the presently described carry track can perform addition calculations at higher computational speeds because the carry track encodes the addition operation into multiple piecewise addition operations that can be performed in parallel.

[0019] Furthermore, a system implementing the presently described carry track can perform addition calculations with target accuracy. Normally, if the track overflows, an error may occur in the addition operation. In the presently described carry track structure, this can only be done if the carry track stores 2 m -1 (where m is the size of the carry track) and increments, and addition can only increment the track once. m There is only one deviation in the possible orbital values, so the result of the piecewise addition operation deviates from the result of the addition operation by at most 1 / 2 m Thus, increasing the carry track size reduces the bias. In addition, the presently described carry track technique can be used to perform addition on modular integers represented using a coset representation of modular integers having the following characteristics: m The r carry tracks of the deviation.

[0020] The carry track technique described so far can be applied to any quantum computation involving counting or accumulation. Quantum computations implementing the carry track described so far can therefore also achieve improved computation speeds and error rates due to the parallelization and bounded bias described above.

[0021] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 An example quantum computing system is shown.

[0023] Figure 2 is a flow chart of an example process for performing a piecewise addition to an accumulator register using one or more carry track registers.

[0024] Figure 3A An example circuit diagram for adding a carry rail register to an accumulation register is shown.

[0025] Figure 3BAn example circuit diagram for adding multiple carry rail registers to an accumulation register is shown.

[0026] Figure 4 An example circuit diagram for adding numbers to an accumulation register using parallel piecewise addition enabled by an oblivious carry track register is shown.

[0027] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0028] Overview

[0029] When performing additions, it is advantageous to know that a carry cannot occur in a particular position. For example, when many modular additions are to be performed, a known classical optimization technique is to purposefully append an additional bit (referred to herein as a carry track) to a register. This allows many additions to be performed to a register before the register must be normalized back to the [0,N) range due to risk of overflow. It is also possible to introduce a carry track in the middle of a register, allowing the two halves to work independently for a while.

[0030] In a quantum computing environment, carry tracks are difficult to implement because they cause decoherence. For example, consider a 2-bit register with a carry track at position 1, where the register is initially in the |0> state. To add 2 to the register, one can either add 1 to the register twice or add 2 to the register once. Both addition operations can be performed conditional on the auxiliary qubit q. Because 1+1=2, it is expected that the two possible addition operations will have equivalent effects and the register will not be entangled with q. However, since the carry from the bottom half (most significant part) of the register enters the track, it is possible to determine which addition operation was performed by checking (by measurement) whether the set bit is in the track or in the top half (least significant part). This causes q to be incorrectly entangled with the register. To avoid this problem, the carry track should ignore the addition operation that has been performed.

[0031] This specification describes a new carry track structure that encodes an addition operation as multiple piecewise addition operations. Based on post-processing analysis, addition operations performed using the carry track structure are indistinguishable. Therefore, the carry track structure is referred to herein as an oblivious carry track. If an attacker is given an intermediate state (between two additions) of an oblivious carry track computation, the amount of information they can infer (in addition to the amount of information they could infer from the intermediate state of the computation without the carry track) is shown to be exponentially small in the length of the track (assuming the track is initialized to a random state unknown to the attacker). This means that in the quantum case, the computation will remain consistent, so information theoretic security is maintained.

[0032] Example Hardware

[0033] Figure 1 An example quantum computing system 100 is depicted. System 100 is an example of a system implemented as quantum and classical computer programs on one or more quantum computing devices and classical computers at one or more locations in which the systems, components, and techniques described below may be implemented.

[0034] The system 100 includes a quantum computing device 102 in data communication with one or more classical processors 104. For convenience, the quantum computing device 102 and the classical processors 104 are shown as separate entities, however in some implementations, the classical processors 104 may be included in the quantum computing device 102.

[0035] The quantum computing device 102 includes components for performing quantum computing. For example, the quantum computing device 102 includes a quantum circuit 106 and a control device 108.

[0036] Quantum circuit 106 includes components for performing quantum computing, for example, components for implementing various quantum circuits and operations described in this specification. For example, a quantum circuit may include a quantum system, which includes one or more multi-level quantum subsystems, such as qubit 114. Qubit 14 is a physical qubit that can be used to perform algorithmic operations or quantum computing. The specific implementation of one or more qubits and their interactions may depend on various factors, including the type of quantum computing being performed by quantum computing device 102. For example, a qubit may include a qubit implemented by an atomic, molecular, or solid-state quantum system. In other examples, a qubit may include, but is not limited to, a superconducting qubit, such as a Gmon or Xmon qubit, or a semiconductor qubit. Further examples of multi-level quantum subsystem implementations include fluxon qubits, silicon quantum dots, or phosphorus impurity qubits. In some cases, a quantum circuit may further include one or more resonators connected to one or more superconducting qubits. In other cases, an ion trap, a photonic device, or a superconducting cavity (a state can be prepared without the need for a qubit) may be used.

[0037] In this specification, the term "quantum circuit" is used to refer to a sequence of quantum logic operations that can be applied to a qubit register to perform a corresponding calculation. Quantum circuits including different quantum logic operations, such as single qubit gates, multi-qubit gates, etc., can be constructed using quantum circuit 106. The constructed quantum circuit can be used to drive / implement using control device 108.

[0038] The type of control device 108 included in the quantum system depends on the type of qubit included in the quantum computing device. For example, in some cases, multiple qubits may be frequency-adjustable. That is, each qubit may have an associated operating frequency that can be adjusted using one or more control devices. Example operating frequencies include qubit idling frequency, qubit interaction frequency, and qubit readout frequency. Different frequencies correspond to different operations that a qubit can perform. For example, setting the operating frequency to a corresponding idling frequency may put the qubit into a state where it does not strongly interact with other qubits and it can be used to perform a single qubit operation / gate. In these examples, the control device 108 may include a device for controlling the frequency of qubits included in the quantum circuit 106, an excitation pulse generator, and a control line that couples the qubit to the excitation pulse generator. The control device can then adjust the frequency of each qubit toward or away from the quantum gate frequency of the excitation pulse on the corresponding control drive train.

[0039] The control device 108 may also include a measurement device, such as a readout resonator. The measurement results obtained by the measurement device may be provided to the classical processor 104 for processing and analysis. The measurement device directly or indirectly performs a physical measurement of the properties of the qubit, from which the state of the qubit can be inferred.

[0040] Hardware Programming: Performing Addition Using the Oblivious Carry Track

[0041] Figure 2 is a flow chart of an example process 200 for piecewise addition into an accumulation register using one or more carry track registers. For convenience, process 200 is described as being performed by a system of one or more classical or quantum computing devices located in one or more locations. For example, a system appropriately programmed according to the present specification Figure 1 A quantum computing system, such as system 100, may perform process 200. Process 200 may be performed as a subroutine of any quantum algorithm / computation involving counting or accumulation.

[0042] The accumulator register includes a first number n of qubits. Each qubit in the accumulator register represents a corresponding bit of a first binary number, so that a state of the accumulator register represents the first binary number, for example, in a little-endian 2s complement integer format. The first number of qubits may be ordered according to increasing bit importance. For example, a first (low) qubit in the accumulator register may correspond to a least significant bit of the first binary number, and a last (high) qubit in the accumulator register may correspond to a most significant bit of the first binary number.

[0043] Each carry track register includes a corresponding number of qubits. In some implementations, each carry track register can include the same number m of qubits. Each qubit in each carry track register represents a corresponding bit of a corresponding binary number, and thus the state of each carry track register represents the corresponding binary number, e.g., in a little-endian 2s complement integer format.

[0044] The system inserts one or more carry track registers into the accumulator register at corresponding predetermined qubit positions of the accumulator register (step 202). For example, the system may lengthen the size of the accumulator register (i.e., increase the total number of qubits) and then designate portions of the lengthened register for different purposes, such as an accumulator register portion and a carry track register portion. In this example, the lengthened register does not operate like a normal integer register, and during operation, the segments of the piecewise addition are added to the correct corresponding segments and carried to the appropriate tracks.

[0045] In some implementations, a predetermined number of carry track registers may be inserted at even intervals in the accumulator register. That is, for an accumulator register of length n, a carry track register of length m may be inserted into every qubit position in the accumulator register that is a multiple of s but not within the s qubit positions at the end of the accumulator register. Thus, the accumulator register will have a total of Carry track register. The track length m can be at least logarithmic in the number of carries that occur, i.e. the number of segments s times the number of additions A. In fact, the number of additions A can be polynomial in the problem size n, and the register size can also be polynomial in n. This means that m can be at least logarithmic in length with respect to n.

[0046] Figure 3A An example circuit diagram 300 for adding a carry track register to an accumulator register is shown. In the circuit diagram 300, a carry track register 302 of length m is added to an accumulator register 304 of size n at bit position p. A lower portion 306 of the accumulator register includes p qubits. An upper portion 308 of the accumulator register includes np qubits. The lower portion 306 of the accumulator register corresponds to a less significant bit of the first binary number than the upper portion 308 of the accumulator register, which corresponds to a more significant bit of the first binary number. As described below with reference to step 204 of the example process 200, each qubit in the carry track register 302 is initialized in a positive state.

[0047] Figure 3BAn example circuit diagram 350 for adding multiple carry rail registers to an accumulation register is shown. In the circuit diagram 350, three carry rail registers 352, 354, 356 are added to an accumulation register 358 of size n at equal intervals. Each carry rail register 352-356 includes s qubits. Each qubit in each carry rail register is initialized in a positive state, as described below with reference to step 204 of the example process 200.

[0048] The first carry track register 352 is added to the accumulation register 358 at bit position s. The second carry track register 354 is added at bit position 2s. The third carry track register 356 is added at bit position 3s.

[0049] After adding the three carry track registers 352-356, the accumulator register 358 is divided into a plurality of portions 360-366. Portion 360 represents the lower portion of the accumulator register, corresponding to the s least significant bits of the first binary number. Portion 362 represents a first portion that starts after the qubit position s into which the first carry track register 352 has been inserted, and ends at the qubit position before the qubit position (i.e., qubit position 2s) into which the second carry track register 354 has been inserted. Portion 364 represents a second portion that starts after the qubit position 2s into which the second carry track register 354 has been inserted, and ends at the qubit position before the position (i.e., qubit position 3s) into which the third carry track register 356 has been inserted. Portion 366 represents a third portion that starts after the qubit position 3s into which the third carry track register 356 has been inserted, and ends at the most significant bit of the first binary number. Since the third portion 366 is the last portion of the accumulator register, it will include qubits.

[0050] return Figure 2 , the system initializes each qubit of each carry track register in the normal state (step 204).

[0051] The system applies one or more subtraction operations to the accumulator register (step 206). Each subtraction operation subtracts the state of the corresponding carry track register from the portion of the accumulator register that begins at the predetermined qubit position where the corresponding initialized carry track register is inserted and ends at the qubit position before the next inserted carry track or the most significant bit of the first binary number. Subtracting the state of the corresponding carry track register from the portion of the accumulator register can include subtracting the value encoded in the track state from the state value of the portion of the accumulator register and updating the state of the portion of the accumulator register to encode the new value. This can be done by subtracting the carry track register multiplied by 2 from the entire accumulator register.k is performed by , where k is the intended qubit position. In practice, this means that the first k qubits of the accumulator register can be ignored, and it is pretended that the accumulator register starts with the qubit at position k when performing the subtraction (i.e., position k is actually position 0).

[0052] For example, Figure 3A As shown, in an implementation where a carry track register 302 is inserted into the accumulator register 304, the system applies a subtraction operation 310 to the accumulator register 304. The subtraction operation 310 subtracts the state 312 of the carry track register 302 from the high portion 308 of the accumulator register.

[0053] As another example, Figure 3B As shown, in an implementation where multiple carry rail registers 352-356 are inserted into an accumulator register 358, the system applies multiple subtraction operations 368, 372, 376 to the accumulator register 358 (where the number of subtraction operations is equal to the number of inserting carry rail registers.) A first subtraction operation 368 subtracts a state 370 of the first carry rail register 352 from a first portion 362 of the accumulator register 358. A second subtraction operation 372 subtracts a state 374 of the second carry rail register 354 from a second portion 364 of the accumulator register 358. A third subtraction operation 376 subtracts a state 378 of the third carry rail register 356 from a third portion 366 of the accumulator register 358.

[0054] Back to Figure 2 , because each qubit of each carry track register is initialized in the normal state at step 204, the state of the accumulation register after applying a number of subtraction operations to the accumulation register at step 206 is approximately an eigenvector with an eigenvalue of 1 that will implement a "normal addition" operation, i.e., adding 1 to the carry track register and subtracting 1 from the high half of the accumulation register. The deviation from the approximation is exponentially small in the length of the carry track register.

[0055] The system adds one or more input binary numbers to the accumulation register using piecewise addition (step 208). The system separates the input binary number into segments corresponding to the segments of the accumulation register between each carry track register, and performs a corresponding addition operation on each corresponding segment of the input binary number to add the segment of the input binary number to the state of the corresponding accumulation register, wherein the carry of the addition operation is added to the state of the corresponding carry track register. The addition operations of the segments of the same input binary number can be performed in parallel. In some implementations, the addition operations can be performed using Cuccaro's ripple-carry adder operation, as described in "A new quantum ripple-carry addition circuit," Cuccaro et.al., arXiv preprint quant-ph / 0410184, 2004, the disclosure of which is incorporated herein by reference in its entirety.

[0056] After step 208, the combined state of the accumulator register and the one or more carry track registers stores the result of adding the one or more input binary numbers. Figure 4 An example circuit diagram 400 is shown for adding a number k 404 to an accumulation register 402 using parallel piecewise addition by an oblivious carry track register 406. The left side of the example circuit diagram 400 shows the addition operation 404. The right side of the example circuit diagram 400 shows how the combined state of the low portion of the accumulation register and the carry track register after performing steps 202-208 of the example process 200 is increased by k mod 2. a , where a represents the bit position of the carry rail and the state of the high part of the accumulator register has been increased

[0057] To determine the result of adding one or more input binary numbers, the system can first remove the one or more carry rail registers inserted in step 202 and then measure the accumulator register (by measuring the qubits in the accumulator register) to determine the result of adding the one or more input binary numbers. Removing the one or more carry rail registers inserted in step 202 includes adding the state of the one or more carry rail registers to the corresponding segment of the accumulator register, for example, by reversing the multiple subtraction operations described in step 206. By removing the one or more carry rail registers before measuring the accumulator register, the system can determine whether each qubit in the one or more carry rail registers is correctly initialized in step 304, for example, whether the qubit is successfully initialized under normal conditions, or whether the initialization fails due to errors or adversarial grounds.

[0058] Alternatively, the system can measure the accumulator register and one or more carry rail registers and then use classical post-processing to remove the measured state of the one or more carry rail registers from the measured state of the accumulator register to determine a result of adding one or more input binary numbers.

[0059] The computational cost of performing k segment additions (terminated by a carry rail) to the accumulator register can be calculated as follows. Without loss of generality, assuming that the addition operation is performed using Cuccaro's ripple-carry adder, the measurement depth and Toffoli count of an addition to a segment is at most twice the length of the segment (where the ending segment length can be up to 2s m and the remainder of the segment can have length s + m). The k segment additions can be performed in parallel across the segments, so the total measurement depth across all k additions is between 2 · (s + m) · k and 2 · (2s + m) k, and the total Toffoli count is 2 · (n + m · r) · k.

[0060] Using the techniques described so far, an addition operation will deviate from a carry rail by at most 2 -m Furthermore, the deviation added each time is no greater than the number of orbits multiplied by the deviation introduced by a single orbit - at most r·2 -m The deviation of the entire series of additions is at most the number of additions multiplied by the deviation of one addition - at most k·r·2 -m The final state of the register can be traced at most to the encoding of the correct output

[0061] For example, consider a 4000-bit register with length 40 at bit positions 1000, 2000, and 3000. If one does a million piecewise additions of the register, the measured depth is 2080 million, the TopoLi counts are 8240 million, and the trajectory distance from the ideal output is at most 0.34%.

[0062] To perform modular addition instead of 2s complement addition, one can concatenate careless carry tracks in the coset representation of the modular integers. In terms of computational cost, this is equivalent to introducing an additional track at the end of the register. The costs are therefore very similar: the measurement depth is between 2·(s+m)·k and 2·(2s+m)·k, the Toffoli count is n+m·(r+1), and the track distance is at most

[0063] The digital and / or quantum subject matter described in this specification and appendix and the implementation of digital functional operations and quantum operations can be implemented in digital electronic circuits, suitable quantum circuits or more general quantum computing systems, in tangibly embodied digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware, including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. The term "quantum computing system" may include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptographic systems or quantum simulators. General quantum computing systems and specific quantum computers can implement or be based on different quantum computing models and architectures. For example, a quantum computing system can be based on or described by models such as quantum circuit models, one-way quantum computing, adiabatic quantum computing, complete quantum computing, simulated quantum computing, digital quantum computing or topological quantum computing.

[0064] The implementation of the digital and / or quantum subject matter described in this specification may be implemented as one or more digital and / or quantum computer programs, i.e., one or more digital and / or quantum computer program instruction modules encoded on a tangible non-transitory storage medium, executed by a data processing device or controlling its operation. The digital and / or quantum computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, one or more qubits, or a combination of one or more of them. Alternatively or in addition, the program instructions may be encoded on an artificially generated propagation signal capable of encoding digital and / or quantum information, e.g., a machine-generated electrical, optical or electromagnetic signal, which is generated to encode digital and / or quantum information for transmission to a suitable receiver device for execution by a data processing device.

[0065] The terms quantum information and quantum data refer to information or data carried, held or stored by a quantum system, wherein the smallest non-trivial system is a qubit, i.e., a system that defines a unit of quantum information. It should be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., having two or more levels. For example, such systems may include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis states are identified with a ground state and a first excited state, however it should be understood that other arrangements in which computational states are identified with higher energy excited states are also possible.

[0066] The term "data processing device" refers to digital and / or quantum data processing hardware, including various devices, equipment and machines for processing digital and / or quantum data, including, for example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, multiple digital and quantum processors or computers and combinations thereof. The device may also be or further include a dedicated logic circuit, such as an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing device designed to simulate or generate information of a specific quantum system. In particular, a quantum simulator is a special-purpose quantum computer that does not have the ability to perform general-purpose quantum computations. In addition to the hardware, the device may optionally include code that creates an execution environment for digital and / or quantum computer programs, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more thereof.

[0067] A digital computer program, which may also be referred to or described as a program, software, software application, module, software module, script or code, may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, software application, module, software module, script or code, may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and translated into a suitable quantum programming language, or may be written in a quantum programming language, such as QCL or Quipper.

[0068] A digital and / or quantum computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file containing other programs or data, such as one or more scripts stored in a markup language document, a single file dedicated to a related program, or multiple coordinated files, for example, a file storing one or more modules, subroutines, or partial codes. A digital and / or quantum computer program may be deployed to execute a data communication network on a digital or quantum computer or on multiple digital and / or quantum computers located at one site or distributed at multiple sites and interconnected by a digital and / or quantum network. A quantum data communication network is understood to be a network that can transmit quantum data using a quantum system (e.g., qubit). Typically, a digital data communication network cannot transmit quantum data, while a quantum data communication network can transmit quantum data and digital data simultaneously.

[0069] The processes and logic flows described in this specification may be performed by one or more programmable digital and / or quantum computers, where appropriate, using one or more digital and / or quantum processors to operate, execute one or more digital and / or quantum computer programs to perform functions by operating input digital and / or quantum data and generating output. The processes and logic flows may also be performed by dedicated logic circuits (e.g., FPGAs or ASICs or quantum simulators), and the apparatus may also be implemented as dedicated logic circuits, or by a combination of dedicated logic circuits or quantum simulators and one or more programmed digital and / or quantum computers.

[0070] A system of one or more digital and / or quantum computers being "configured to" perform a particular operation or action means that the system has software, firmware, hardware, or a combination thereof installed thereon that, when run, causes the system to perform the operation or action. For one or more digital and / or quantum computer programs to be configured to perform a particular operation or action means that the one or more programs include instructions that, when executed by a digital and / or quantum data processing device, cause the device to perform the operation or action. A quantum computer may receive instructions from a digital computer that, when executed by a quantum computing device, cause the device to perform the operation or action.

[0071] A digital and / or quantum computer suitable for executing a digital and / or quantum computer program may be based on a general or special purpose digital and / or quantum processor or both, or any other type of central digital and / or quantum processing unit. Typically, the central digital and / or quantum processing unit will receive instructions and digital and / or quantum data from a read-only memory, a random access memory or a quantum system suitable for transmitting quantum data (e.g. photons), or a combination thereof.

[0072] Elements of a digital and / or quantum computer include a central processing unit for completing or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and the memory may be supplemented or incorporated by a dedicated logic circuit or a quantum simulator. Typically, a digital and / or quantum computer will also include or be operatively coupled to receive digital and / or quantum data from one or more mass storage devices, or to transfer digital and / or quantum data to one or more mass storage devices, or both, and the mass storage device is used to store digital and / or quantum data, for example, a magnetic, magneto-optical disk, an optical disk, or a quantum system suitable for storing quantum information. However, a digital and / or quantum computer does not require such a device.

[0073] Digital and / or quantum computer readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memory, media and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; CD-ROM and DVD-ROM optical disks; and quantum systems, such as trapped atoms or electrons. It is understood that quantum memory is a device capable of storing quantum data for a long time with high fidelity and high efficiency, for example, light-matter interfaces for transmission and matter for storing and preserving quantum features (such as superposition or quantum coherence) of quantum data.

[0074] Control of the various systems or portions thereof described in this specification may be implemented in a digital and / or quantum computer program product that includes instructions stored on one or more non-transitory machine-readable storage media and executable on one or more digital and / or quantum processing devices. The systems or portions thereof described in this specification may each be implemented as an apparatus, method, or system that may include one or more digital and / or quantum processing devices and memory to store executable instructions for performing the operations described in this specification.

[0075] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular implementation. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although the above features may be described as working in certain combinations, or even initially claimed to be so, in some cases, one or more features from the claimed combination may be deleted from the claimed combination, and the claimed combination may be directed to a sub-combination or a variation of a sub-combination.

[0076] Similarly, although operations are described in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order or sequence shown, or that all illustrated operations be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above implementations should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated into a single software product, or packaged into multiple software products.

[0077] Particular implementations of the subject matter have been described. Other implementations are within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order shown or sequential order to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A method for determining the result of adding a plurality of input binary numbers, the method comprising: Removing one or more carry track registers from an accumulator register, wherein i) the accumulator register comprises a first plurality of qubits, each qubit in the first plurality of qubits representing a respective bit of a first binary number, ii) respective states of the portion of the accumulator register encode the plurality of input binary numbers, and iii) each of the one or more carry track registers comprises a plurality of qubits representing the respective binary numbers, the removing comprising: applying one or more addition operations to the accumulation register, wherein each of the one or more addition operations adds a state of a corresponding carry rail register to a portion of the accumulation register starting at a qubit position at which the corresponding carry rail register was inserted into the accumulation register and ending at a qubit position before a next inserted carry rail or a most significant bit of the first binary number; and The accumulator register is measured to determine the result of adding multiple input binary numbers.

2. The method according to claim 1, wherein: One or more carry track registers are respectively inserted into the accumulation register at corresponding predetermined qubit positions of the accumulation register.

3. The method according to claim 2, wherein: A predetermined number of carry track registers are inserted into the accumulation register at even intervals.

4. The method according to claim 1, further comprising: determining whether each qubit in one or more carry track registers is properly initialized in a normal state; as well as In response to determining that each qubit in the one or more carry track registers is correctly initialized in a positive state, the qubits in the accumulation register are measured to determine a result of adding the plurality of input binary numbers.

5. The method according to claim 1, wherein: adding a state of the corresponding carry rail register to a portion of the accumulation register starting at the qubit position where the corresponding carry rail register was inserted into the accumulation register and ending at the qubit position before the next inserted carry rail or the most significant bit of the first binary number, comprising: adding the value encoded in the state of the carry track register from the state value of the portion of the accumulator register; and The state of the portion of the accumulator register is updated to encode the new value.

6. The method according to claim 1, wherein: Each qubit in the first plurality of qubits represents a corresponding bit of a first binary number stored in little-endian 2s' complement integer format, and each qubit in a corresponding carry track register represents a corresponding binary number stored in little-endian 2s' complement integer format.

7. A device comprising: one or more classical computing processors; as well as Quantum computing hardware that communicates data with the one or more classical processors, wherein the quantum computing hardware includes: an accumulator register comprising a first plurality of qubits, each qubit in the first plurality of qubits representing a respective bit of a first binary number, wherein respective states of portions of the accumulator register encode the plurality of input binary numbers; one or more carry track registers inserted into the accumulator register, each of the one or more carry track registers including a corresponding plurality of qubits representing a corresponding binary number; a plurality of control devices configured to operate the first plurality of qubits and the corresponding plurality of qubits; The device is configured to perform operations including: removing one or more carry rail registers from the accumulation register, including applying one or more addition operations to the accumulation register, wherein each of the one or more addition operations adds a state of the corresponding carry rail register to a portion of the accumulation register starting at a qubit position where the corresponding carry rail register was inserted into the accumulation register and ending at a qubit position before a next inserted carry rail or a most significant bit of the first binary number; and The accumulator register is measured to determine the result of adding multiple input binary numbers.

8. The device according to claim 7, wherein: One or more carry track registers are respectively inserted into the accumulation register at corresponding predetermined qubit positions of the accumulation register.

9. The device according to claim 8, wherein: A predetermined number of carry track registers are inserted into the accumulation register at even intervals.

10. The device according to claim 7, wherein: The operation also includes: determining whether each qubit in one or more carry track registers is correctly initialized in a normal state; and In response to determining that each qubit in the one or more carry track registers is correctly initialized in a positive state, the qubits in the accumulation register are measured to determine a result of adding the plurality of input binary numbers.

11. The device according to claim 7, wherein: adding a state of the corresponding carry rail register to a portion of the accumulation register starting at the qubit position where the corresponding carry rail register was inserted into the accumulation register and ending at the qubit position before the next inserted carry rail or the most significant bit of the first binary number, comprising: adding the value encoded in the state of the carry track register from the state value of the portion of the accumulator register; and The state of the portion of the accumulator register is updated to encode the new value.

12. The device according to claim 7, wherein: Each qubit in the first plurality of qubits represents a corresponding bit of a first binary number stored in little-endian 2s' complement integer format, and each qubit in a corresponding carry track register represents a corresponding binary number stored in little-endian 2s' complement integer format.

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