Conversion method, device and storage medium based on RISC-V architecture built-in function

Abstract

The present invention discloses a conversion method, device and storage medium based on a built-in function of a RISC-V architecture. The method comprises: parsing a source code file to obtain an operator function contained therein; converting the operator function into a syntax tree, and traversing the syntax tree to obtain a child node of the syntax tree; when the child node is a loop statement node, judging whether the loop step length of the child node is the same as a preset step length; generating a second syntax tree based on a basic loop step length subtree, expanding a scalar in a code block into a vector assignment statement, and identifying it as a vector extension statement to be optimized for vector-scalar instructions; searching for the vector-scalar instruction optimization statement to be optimized from the following text; when the vector-scalar instruction optimization statement to be optimized is found, converting the vector extension assignment statement into a common assignment statement, replacing the vector instruction of the original instruction set with the vector instruction of the target instruction set according to a mapping vector instruction mapping table, and replacing the vector instruction of the target instruction set with the corresponding vector-scalar instruction.

Description

Technical Field

[0001] The present invention relates to the field of RISC-V technology, and in particular to a conversion method, device and storage medium based on a RISC-V architecture built-in function. Background Art

[0002] As an open, streamlined instruction set architecture, RISC-V architecture has the characteristics of being streamlined, modular, and scalable. It has developed rapidly in recent years and has become the third largest instruction set architecture after x86 and ARM. In order to facilitate the use of RISC-V architecture, software programs of x86 and ARM architectures need to be ported to RISC-V architecture.

[0003] As a key means to improve computing efficiency, vector instructions are closely related to the processor architecture and belong to platform-specific codes. For cross-architecture code conversion, comprehensive modifications must be made, and vector instruction migration plays an important role in code migration. Currently, there are some solutions for converting from fixed vector length instruction sets to RISC-V Vector extension instruction sets (RVV instruction sets), such as from ARMNEON instruction sets to RVV instruction sets. However, these solutions are all implemented based on fixed vector length design and cannot give full play to the advantages of variable vector length of RVV instruction sets. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a conversion method, device and storage medium based on the built-in function of the RISC-V architecture to solve the technical problem in the prior art that the advantage of the variable vector length of the RVV instruction set cannot be brought into play when converting code to the RISC-V architecture.

[0005] In a first aspect, an embodiment of the present invention provides a conversion method based on a built-in function of a RISC-V architecture, comprising:

[0006] Parse the source code file to obtain the operator functions contained therein;

[0007] Convert the operator function into an AST abstract syntax tree, and traverse the AST abstract syntax tree to obtain child nodes of the AST abstract syntax tree;

[0008] When the child node is a loop statement node, determining whether the loop step length of the child node is the same as a preset step length;

[0009] When they are the same, set the child node to the basic loop step subtree;

[0010] Generate a second AST abstract syntax tree based on the basic loop step subtree, traverse the second AST abstract syntax tree, and expand the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, and identify it as a vector extension statement to be optimized for vector-scalar instructions;

[0011] Find the corresponding vector-scalar instruction optimization statement to be optimized from the following text of the vector-scalar instruction optimization vector extension statement to be optimized;

[0012] When the vector-scalar instruction optimization statement is found, the vector-extended assignment statement is converted into an ordinary assignment statement, and the vector instructions of the original instruction set are replaced with the vector instructions of the target instruction set according to the mapping vector instruction mapping table, and the vector instructions of the target instruction set are replaced with the corresponding vector-scalar instructions.

[0013] In a second aspect, an embodiment of the present invention further provides a conversion device based on a RISC-V architecture built-in function, comprising:

[0014] A parsing module is used to parse the source code file and obtain the operator functions contained therein;

[0015] A traversal module, used to convert the operator function into an AST abstract syntax tree, and traverse the AST abstract syntax tree to obtain child nodes of the AST abstract syntax tree;

[0016] A judgment module, used for judging whether the loop step length of the sub-node is the same as the preset step length when the sub-node is a loop statement node;

[0017] Set as a module, used to set the child node to the basic loop step subtree when the same;

[0018] An identification module is used to generate a second AST abstract syntax tree based on the basic loop step subtree, traverse the second AST abstract syntax tree, and expand the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, and identify it as a vector extension statement to be optimized for vector-scalar instructions;

[0019] A search module, used for searching the corresponding vector-scalar instruction optimization statement to be performed from the following text of the vector extension statement to be optimized for the vector-scalar instruction;

[0020] The replacement module is used to convert the vector-extended assignment statement into a normal assignment statement when finding the vector-scalar instruction optimization statement to be found, replace the vector instructions of the original instruction set with the vector instructions of the target instruction set according to the mapping vector instruction mapping table, and replace the vector instructions of the target instruction set with the corresponding vector-scalar instructions.

[0021] In a third aspect, an embodiment of the present invention further provides a storage medium comprising computer executable instructions, which, when executed by a computer processor, are used to execute a conversion method based on a RISC-V architecture built-in function as provided in the above embodiment.

[0022] The conversion method, device and storage medium based on the built-in function of the RISC-V architecture provided by the embodiment of the present invention parse the source code file to obtain the operator function contained therein; convert the operator function into an AST abstract syntax tree, and traverse the AST abstract syntax tree to obtain the child node of the AST abstract syntax tree; when the child node is a loop statement node, determine whether the loop step length of the child node is the same as the preset step length; if the same, set the child node to a basic loop step length subtree; generate a second AST abstract syntax tree based on the basic loop step length subtree, traverse the second AS T abstract syntax tree, and expand the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, and identify it as a vector extension statement to be optimized by vector-scalar instruction; find the corresponding vector-scalar instruction optimization statement to be optimized from the following text of the vector extension statement to be optimized by vector-scalar instruction; when the vector-scalar instruction optimization statement to be optimized is found, the vector extension assignment statement is converted into a common assignment statement, and the vector instruction of the original instruction set is replaced by the vector instruction of the target instruction set according to the mapping vector instruction mapping table, and the vector instruction of the target instruction set is replaced by the corresponding vector-scalar instruction. By parsing the source code file, identifying the AI ​​operator function therein, extracting the optimizable code block in the AI ​​operator function, and optimizing the corresponding code with vector-scalar instructions according to the RVV characteristics, it can directly support the operation of vectors and scalars at the hardware level, without the need for additional steps to expand the scalar to a vector, simplifying the code writing process, reducing the resource occupation of the vector register, reducing the number of instructions and potential pipeline delays, and thus improving the execution efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0024] Figure 1 It is a flowchart of a conversion method based on a built-in function of a RISC-V architecture provided in Embodiment 1 of the present invention;

[0025] Figure 2 This is a schematic diagram of the conversion of vector-scalar instruction optimization statements in the conversion method based on the RISC-V architecture built-in function provided in the first embodiment of the present invention.

[0026] Figure 3 It is a flowchart of a conversion method based on a built-in function of a RISC-V architecture provided in Embodiment 2 of the present invention;

[0027] Figure 4 It is a flowchart of a conversion method based on a built-in function of a RISC-V architecture provided in Embodiment 3 of the present invention;

[0028] Figure 5 It is a structural schematic diagram of a conversion device based on a RISC-V architecture built-in function provided in a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0030] Embodiment 1

[0031] Figure 1 This is a flow chart of a conversion method based on a built-in function of the RISC-V architecture provided in the first embodiment of the present invention. This embodiment can be applied to the situation of preventing container escape and reducing security risks. The method can be executed by a conversion device based on a built-in function of the RISC-V architecture, and specifically includes the following steps:

[0032] Step 110, parse the source code file to obtain the operator function contained therein.

[0033] In this embodiment, the operator function may be: an AI operator function. Exemplarily, it may include: convolution, full connection, pooling, activation function, basic operation and other operator functions. The above functions involve vector calculations and are particularly suitable for the RVV instruction set, so as to improve the calculation efficiency by using the RVV instruction set.

[0034] Step 120: convert the operator function into an AST abstract syntax tree, and traverse the AST abstract syntax tree to obtain child nodes of the AST abstract syntax tree.

[0035] Abstract Syntax Tree (AST) is an abstract representation of the syntax structure of source code. It represents the syntax structure of a programming language in a tree form, and each node in the tree represents a structure in the source code.

[0036] In this embodiment, by converting the operator function into an AST abstract syntax tree and traversing the AST abstract syntax tree to obtain the child nodes of the AST abstract syntax tree, it is possible to intuitively and effectively manage the operator function, facilitate the subsequent conversion of its code, and prevent omissions or repeated conversions.

[0037] Step 130, when the child node is a loop statement node, determine whether the loop step of the child node is the same as the preset step. If they are the same, set the child node as the basic loop step subtree.

[0038] In this embodiment, the first-level child node of the AI ​​operator function AST abstract syntax tree can be used as the parent node, split into several subtrees, and then traversed one by one. If the node type is a loop statement node, such as ForStmt, WhileStmt. The child node can be defined as a loop statement node. The child node with the loop step length as the standard step length can be set as the basic loop step length subtree. The standard step length is set according to the vector register length and variable type of the fixed vector length instruction set. For example: if the vector register length of NEON is 128, if the variable type is float32, then stride=128 / 32=4. Wherein, stride is the basic step length.

[0039] Step 140, generate a second AST abstract syntax tree based on the basic loop step subtree, traverse the second AST abstract syntax tree, and expand the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, and identify it as a vector extension statement to be optimized for vector-scalar instructions.

[0040] The above steps are used to determine the corresponding basic loop step subtree as a child node, build a second AST abstract syntax tree, and traverse the second AST abstract syntax tree to avoid missing the corresponding nodes for post-processing. The post-processing can be to convert the code segment adapted to the vector register group into a code segment suitable for RISC-V architecture processing to give full play to the advantages of the variable vector length of the RVV instruction set. Since not all instructions in the code segment need to be converted, it is necessary to first identify the corresponding statements that can be optimized and extended. For example: a scalar is expanded to a vector assignment statement. Exemplarily, vld1q_dup_*() or vdupq_n_*() can be used to expand the scalar to a vector assignment statement, which is identified as a vector extension statement to be optimized for vector-scalar instructions.

[0041] Step 150 : searching the corresponding vector-scalar instruction optimization statement to be optimized from the context of the vector extension statement to be optimized for the vector-scalar instruction.

[0042] The corresponding vector also needs to be processed in the subsequent processing process. Therefore, it is necessary to find the vector-to-scalar instruction optimization statement corresponding to the vector from the context of the vector-to-scalar instruction optimization vector extension statement.

[0043] Step 160, when the vector-to-scalar instruction optimization statement is found, the vector-extended assignment statement is converted into a normal assignment statement, and the vector instructions of the target instruction set are used to replace the vector instructions of the original instruction set according to the mapping vector instruction mapping table, and the corresponding vector-scalar instructions are used to replace the vector instructions of the target instruction set.

[0044] Figure 2 This is a schematic diagram of the conversion of vector-scalar instruction optimization statements in the conversion method based on the RISC-V architecture built-in function provided in the first embodiment of the present invention, see Figure 2 If both the vector extension statement and the vector-scalar instruction optimization statement exist in the available vector-scalar instruction optimization code block, the vector extension assignment statement is converted into a common assignment statement, and the vector instructions of the original instruction set are replaced with the vector instructions of the target instruction set according to the mapping table, and then the vector instructions of the target instruction set are replaced with the corresponding vector-scalar instructions, generally replacing *_vv_* with *_vf_* or *_vx_*.

[0045] This embodiment parses the source code file to obtain the operator function contained therein; converts the operator function into an AST abstract syntax tree, and traverses the AST abstract syntax tree to obtain the child nodes of the AST abstract syntax tree; when the child node is a loop statement node, determines whether the loop step of the child node is the same as the preset step; when they are the same, sets the child node to a basic loop step subtree; generates a second AST abstract syntax tree based on the basic loop step subtree, traverses the second AST abstract syntax tree, and expands the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, identifying it as a vector extension statement to be optimized for vector-scalar instructions; searches for the corresponding vector-scalar instruction optimization statement to be optimized from the context of the vector extension statement to be optimized for vector-scalar instructions; when the vector-scalar instruction optimization statement to be optimized is found, converts the vector extension assignment statement into an ordinary assignment statement, replaces the vector instructions of the original instruction set with the vector instructions of the target instruction set according to the mapping vector instruction mapping table, and replaces the vector instructions of the target instruction set with the corresponding vector-scalar instructions. By parsing the source code file, identifying the AI ​​operator function therein, extracting the optimizable code blocks in the AI ​​operator function, and optimizing the corresponding code with vector-scalar instructions based on the RVV feature, it can directly support vector and scalar operations at the hardware level without the need for additional steps to expand the scalar to a vector, simplifying the code writing process, reducing the resource usage of vector registers, reducing the number of instructions and potential pipeline delays, and thus improving execution efficiency.

[0046] In a preferred implementation of this embodiment, the method may further add the following step: converting the second AST abstract syntax tree after instruction replacement into code. Using the above method, the converted code can be generated into a code file suitable for the RISC-V architecture corresponding to the source code file in the order of the original code. The original operator function code is converted into a code suitable for the RISC-V architecture. Furthermore, a subtree that does not contain any fixed vector length built-in function can be identified as an instruction set-independent code block, and the instruction set-independent code block is not processed. Using the above method, the integrity of the converted code can be guaranteed.

[0047] Embodiment 2

[0048] Figure 3 It is a flow chart of the conversion method based on the built-in function of the RISC-V architecture provided by the second embodiment of the present invention. This embodiment is optimized based on the above embodiment, and the method can also add the following steps: when judging whether the loop step is different from the preset step, judging whether the subtree loop step corresponding to the child node is an integer multiple of the preset step, when it is an integer multiple, defining the subtree corresponding to the child node as a large-stride loop code block, traversing the child nodes of the subtree corresponding to the large-stride loop code block, and when the first preset condition is met, converting the subtree corresponding to the large-stride loop code block into a plurality of corresponding basic loop step subnode subtrees, deleting the subtree corresponding to the large-stride loop code block, and using the basic loop step subtree for processing.

[0049] See also Figure 3 , the conversion method based on the built-in function of the RISC-V architecture includes:

[0050] Step 210, parse the source code file to obtain the operator function contained therein, convert the operator function into an AST abstract syntax tree, and traverse the AST abstract syntax tree to obtain child nodes of the AST abstract syntax tree.

[0051] Step 220, when the child node is a loop statement node, determine whether the loop step of the child node is the same as the preset step. If they are the same, set the child node as the basic loop step subtree.

[0052] Step 230, when judging whether the loop step is different from the preset step, judge whether the subtree loop step corresponding to the child node is an integer multiple of the preset step. When it is an integer multiple, define the subtree corresponding to the child node as a large-step loop code block, traverse the child nodes of the subtree corresponding to the large-step loop code block, and when the first preset condition is met, convert the subtree corresponding to the large-step loop code block into a plurality of corresponding basic loop step subnode subtrees, delete the subtree corresponding to the large-step loop code block, and use the basic loop step subtree for processing.

[0053] When the subtree step of the child node is greater than the basic loop step, it is necessary to determine whether the subtree loop step corresponding to the child node is an integer multiple of the preset step. If it is an integer multiple, it can be processed to form multiple basic loop step subnode subtrees. Exemplarily, the subtree corresponding to the child node is defined as a large-step loop code block, and the subnodes of the subtree corresponding to the large-step loop code block are traversed. If it meets the preset conditions, it can be converted into multiple basic loop step subnode subtrees. Exemplarily, the preset conditions may include: the tree composed of the multiple corresponding basic loop step subnode subtrees is the same as the subtree corresponding to the large-step loop code block; and the step of each basic loop step subnode subtree is the same as the preset step. Traverse the large-step loop code block subtree, take its first-level child node as a unit, ignore the variable name part in the two type nodes of VarDecl and DeclRefExpr, obtain the first-level child node set after deduplication, and record the number of occurrences of each first-level child node. By presetting the conditions, it can be ensured that there will be no omissions after the large-step loop code block is converted into multiple basic loop step sub-node sub-trees, and at the same time ensure that the step size meets the requirements of the basic loop step size. And the basic loop step sub-tree is used for processing.

[0054] In a special case, there may not be a basic loop stride subtree, but the standard stride is set according to the vector register length and variable type of the fixed vector length instruction set. Therefore, regardless of whether the code includes the basic loop stride subtree, the large-stride loop code block can still be processed in the same way as before, adding the tree consisting of the first-level child nodes of the large-stride loop code block subtree after deduplication, and deleting the large-stride loop code block.

[0055] Step 240: Generate a second AST abstract syntax tree based on the basic loop step subtree, traverse the second AST abstract syntax tree, and expand the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, and identify it as a vector expansion statement to be optimized for vector-scalar instructions.

[0056] Step 250: searching the corresponding vector-to-scalar instruction optimization statement from the context of the vector extension statement to be optimized for the vector-to-scalar instruction.

[0057] Step 260, when the vector-to-scalar instruction optimization statement is found, the vector-extended assignment statement is converted into a normal assignment statement, and the vector instructions of the target instruction set are used to replace the vector instructions of the original instruction set according to the mapping vector instruction mapping table, and the corresponding vector-scalar instructions are used to replace the vector instructions of the target instruction set.

[0058] This embodiment adds the following steps: when judging whether the loop step is different from the preset step, judging whether the subtree loop step corresponding to the child node is an integer multiple of the preset step, and when it is an integer multiple, defining the subtree corresponding to the child node as a large-step loop code block, traversing the subnodes of the subtree corresponding to the large-step loop code block, and when the first preset condition is met, converting the subtree corresponding to the large-step loop code block into a plurality of corresponding basic loop step subnode subtrees, and deleting the subtree corresponding to the large-step loop code block. Using the above method, the large-step loop code block can be processed into a plurality of basic loop step subnodes, and by limiting the preset conditions, it is ensured that no omissions occur during the conversion process. It is convenient to generate an abstract syntax tree in the later stage, and the corresponding statements that need to be converted can be converted.

[0059] In a preferred implementation of this embodiment, the method may further add the following steps: modifying the LMUL involving the vector register in the base step loop code block to a multiple of the basic loop step of the large-stride loop code block, or other values ​​that meet the hardware characteristics, and modifying the number of elements processed each time to the length of the vector length register vl, which is set by a length setting vector length statement. The characteristics of RVV can be used to modify the length of the vector register group according to the multiple of the basic loop step of the large-stride loop code block, so as to realize the flexible use of the vector register group, thereby fully demonstrating the performance advantages of RVV.

[0060] Embodiment 3

[0061] Figure 4 It is a flow chart of the conversion method based on the built-in function of the RISC-V architecture provided by the third embodiment of the present invention. This embodiment is optimized based on the above embodiment, and the method can also add the following steps: when the child node is a judgment statement node, determine whether the loop counter index in the reference step loop code block is 0. When it is not equal to 0, set the judgment statement node subtree to the tail processing code block, and the initial value of the loop counter index is determined according to the number of variables in the code, and iterate the index value according to the loop step.

[0062] See also Figure 4 , the conversion method based on the built-in function of the RISC-V architecture includes:

[0063] Step 310: parse the source code file to obtain the operator function contained therein, convert the operator function into an AST abstract syntax tree, and traverse the AST abstract syntax tree to obtain the child nodes of the AST abstract syntax tree.

[0064] Step 320, when the child node is a loop statement node, determine whether the loop step of the child node is the same as the preset step. If they are the same, set the child node as the basic loop step subtree.

[0065] Step 330, using the length judgment statement of the variable data to be processed and judging whether the loop counter index of the statement condition is equal to 0, it is judged whether there is a tail processing code block.

[0066] In this embodiment, it can be determined whether a statement, such as IfStmt, is a judgment statement node. When it is determined to be a judgment statement node, the judgment condition is then determined, and it is determined whether the loop counter index of the code block corresponding to the judgment condition is 0, wherein the initial value of the loop counter index is determined according to the number of variables in the code, and the index value is iteratively changed according to the loop step. The above-mentioned loop counter index can be used to determine whether the judgment condition includes vector instructions that can be optimized. If the index is not 0, it means that not all the variables therein have been processed, which does not meet the characteristics of vector instructions. It can be set as a tail processing code block.

[0067] Step 340, when there is a tail processing code block, the basic step size is continuously adjusted according to the length of the data to be processed of the tail processing code block to form at least one tail processing step size loop code block, and the tail processing base step size loop code block is processed until the tail processing code block is processed.

[0068] Since the length of the data to be processed in the tail processing code block is different from the previous reference step length, the step length can be adjusted by taking advantage of the variable register length to form at least one tail processing step length loop code block. In subsequent processing, the tail processing step length loop code block is used to replace the vector instructions therein with corresponding vector-scalar instructions.

[0069] Exemplarily, the vsetvl instruction can be used to flexibly adjust the length of the register, thereby determining the available step size. For example, when VLEN=128, the following statement is used to implement it: size_t vl = vsetvl_e32m2(size);

[0070] When size=9, vl=8

[0071] When size=1, vl=1. The above method can be used to form two tail processing step loop code blocks respectively, and then process them.

[0072] Step 350, generate a second AST abstract syntax tree based on the basic loop step subtree, traverse the second AST abstract syntax tree, and expand the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, and identify it as a vector extension statement to be optimized for vector-scalar instructions.

[0073] Step 360 : searching the corresponding vector-scalar instruction optimization statement to be optimized from the context of the vector extension statement to be optimized for the vector-scalar instruction.

[0074] Step 370, when the vector-to-scalar instruction optimization statement is found, the vector-extended assignment statement is converted into a normal assignment statement, and the vector instructions of the target instruction set are used to replace the vector instructions of the original instruction set according to the mapping vector instruction mapping table, and the corresponding vector-scalar instructions are used to replace the vector instructions of the target instruction set.

[0075] This embodiment adds the following steps: when the child node is a judgment statement node, determine whether the loop counter index in the reference step loop code block is 0; when it is not equal to 0, set the judgment statement node subtree as a tail processing code block; the initial value of the loop counter index is determined according to the number of variables in the code, and the index value is iteratively changed according to the loop step.

[0076] In a preferred implementation of this embodiment, the method may further add the following steps: if the tail processing code block exists, the tail processing code block is deleted, and the judgment condition of the reference step loop code block is modified to loop counter index>0. For a fixed vector length instruction set, assuming that the data that can be processed each time is 4, the judgment condition of the reference step loop is greater than or equal to 4, that is, the case of less than 4 is handled by the tail processing code block. After conversion to a variable vector length instruction set, the data processed each time can be 4 or less than 4, so there is no need for a tail processing code, but the judgment condition of the reference step loop code block must be changed from greater than or equal to 4 to greater than 0. In this way, the judgment condition of the reference step loop code block can be flexibly adjusted, and then the tail processing code block can be processed using the basic step loop code block.

[0077] Embodiment 4

[0078] Figure 5 is a schematic diagram of the structure of a conversion device based on a RISC-V architecture built-in function provided in Embodiment 3 of the present invention, see Figure 5 , the conversion device based on the built-in function of the RISC-V architecture comprises:

[0079] A parsing module 410 is used to parse the source code file to obtain the operator functions contained therein;

[0080] A traversal module 420 is used to convert the operator function into an AST abstract syntax tree, and traverse the AST abstract syntax tree to obtain child nodes of the AST abstract syntax tree;

[0081] A judging module 430, configured to judge whether the loop step length of the sub-node is the same as a preset step length when the sub-node is a loop statement node;

[0082] Set as module 440, for setting the child node to the basic loop step length subtree when the same;

[0083] An identification module 450 is used to generate a second AST abstract syntax tree based on the basic loop step subtree, traverse the second AST abstract syntax tree, and expand the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, and identify it as a vector extension statement to be optimized for vector-scalar instructions;

[0084] A search module 460, configured to search for a corresponding vector-scalar instruction optimization statement to be optimized from the context of the vector extension statement to be optimized for the vector-scalar instruction;

[0085] The replacement module 470 is used to convert the vector-extended assignment statement into a normal assignment statement when a vector-to-scalar instruction optimization statement is found, and to replace the vector instructions of the original instruction set with the vector instructions of the target instruction set according to the mapping vector instruction mapping table, and to replace the vector instructions of the target instruction set with the corresponding vector-scalar instructions.

[0086] The conversion device based on the built-in function of the RISC-V architecture provided in this embodiment parses the source code file to obtain the operator function contained therein; converts the operator function into an AST abstract syntax tree, and traverses the AST abstract syntax tree to obtain the child nodes of the AST abstract syntax tree; when the child node is a loop statement node, determines whether the loop step of the child node is the same as the preset step; when they are the same, sets the child node to the basic loop step subtree; generates a second AST abstract syntax tree based on the basic loop step subtree, traverses the second AST abstract syntax tree, and expands the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, which is identified as a vector extension statement to be optimized for vector-scalar instructions; searches for the corresponding vector-scalar instruction optimization statement to be optimized from the context of the vector extension statement to be optimized for vector-scalar instructions; when the vector-scalar instruction optimization statement to be optimized is found, converts the vector extension assignment statement into an ordinary assignment statement, replaces the vector instructions of the original instruction set with the vector instructions of the target instruction set according to the mapping vector instruction mapping table, and replaces the vector instructions of the target instruction set with the corresponding vector-scalar instructions. By parsing the source code file, identifying the AI ​​operator function therein, extracting the optimizable code blocks in the AI ​​operator function, and optimizing the corresponding code with vector-scalar instructions based on the RVV feature, it can directly support vector and scalar operations at the hardware level without the need for additional steps to expand the scalar to a vector, simplifying the code writing process, reducing the resource usage of vector registers, reducing the number of instructions and potential pipeline delays, and thus improving execution efficiency.

[0087] Based on the above embodiments, the device further includes:

[0088] The setting module is used for setting the reference step size according to the vector register length and the variable type of the fixed vector length instruction set.

[0089] Based on the above embodiments, the device further includes:

[0090] A deletion module is used to determine whether the subtree loop step corresponding to the child node is an integer multiple of the preset step when determining whether the loop step is different from the preset step. When it is an integer multiple, the subtree corresponding to the child node is defined as a large-step loop code block, and the child nodes of the subtree corresponding to the large-step loop code block are traversed. When a first preset condition is met, the subtree corresponding to the large-step loop code block is converted into a plurality of corresponding basic loop step child node subtrees, and the subtree corresponding to the large-step loop code block is deleted, and the basic loop step subtree is used for processing.

[0091] Based on the above embodiments, the device further includes:

[0092] A tail processing code block judgment module is used to judge whether there is a tail processing code block after converting the subtree corresponding to the large-step loop code block into a plurality of corresponding basic loop step subnode subtrees, using a to-be-processed variable data length judgment statement and judging whether the existence loop counter index of the statement condition is equal to 0;

[0093] The tail processing code block processing module is used to continuously adjust the basic step size according to the length of the data to be processed of the tail processing code block when there is a tail processing code block, form at least one tail processing step size loop code block, and process the tail processing base step size loop code block until the tail processing code block is processed; the initial value of the loop counter index is determined according to the number of variables in the code, and the index value is iteratively changed according to the loop step size. Based on the above embodiments, the device also includes:

[0094] A deletion module is used to modify the LMUL involving the vector register in the base step loop code block to a multiple of the basic loop step of the large step loop code block, or other values ​​that conform to the hardware characteristics, and to modify the number of elements processed each time to the length of the vector length register vl, which is set by the length setting vector length statement.

[0095] Based on the above embodiments, the first preset condition includes:

[0096] The tree composed of the plurality of corresponding basic loop step length sub-node sub-trees is the same as the sub-tree corresponding to the large-step length loop code block; and

[0097] The step size of each basic loop step sub-node sub-tree is the same as the preset step size.

[0098] Based on the above embodiments, the device further includes:

[0099] The instruction set independent code block identification module is used to identify a subtree that does not contain any fixed vector length built-in function as an instruction set independent code block, and not process the instruction set independent code block.

[0100] Based on the above embodiments, the configuration allocation module includes:

[0101] The judgment condition modification module is used to delete the tail processing code block subtree if it exists, and modify the judgment condition of the reference step loop code block to loop counter index>0.

[0102] The conversion device based on the built-in function of the RISC-V architecture provided in the embodiment of the present invention can execute the conversion method based on the built-in function of the RISC-V architecture provided in any embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method.

[0103] Embodiment 5

[0104] Embodiment 5 of the present invention further provides a storage medium comprising computer executable instructions, which, when executed by a computer processor, are used to execute a conversion method based on a RISC-V architecture built-in function as described in any of the above embodiments.

[0105] The computer storage medium of the embodiment of the present invention may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device.

[0106] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0107] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0108] Computer program code for performing the operation of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or device. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0109] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A conversion method based on a built-in function of a RISC-V architecture, characterized in that: include: Parse the source code file to obtain the operator functions contained therein; Convert the operator function into an AST abstract syntax tree, and traverse the AST abstract syntax tree to obtain child nodes of the AST abstract syntax tree; When the child node is a loop statement node, determining whether the loop step length of the child node is the same as a preset step length; When they are the same, set the child node to the basic loop step subtree; Generate a second AST abstract syntax tree based on the basic loop step subtree, traverse the second AST abstract syntax tree, and expand the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, and identify it as a vector extension statement to be optimized for vector-scalar instructions; Find the corresponding vector-scalar instruction optimization statement to be optimized from the following text of the vector-scalar instruction optimization vector extension statement to be optimized; When the vector-scalar instruction optimization statement is found, the vector-extended assignment statement is converted into an ordinary assignment statement, and the vector instructions of the original instruction set are replaced with the vector instructions of the target instruction set according to the mapping vector instruction mapping table, and the vector instructions of the target instruction set are replaced with the corresponding vector-scalar instructions.

2. The method according to claim 1, characterized in that The method further comprises: The base stride is set according to the vector register length and variable type of the fixed vector length instruction set.

3. The method according to claim 1, characterized in that The method further comprises: When determining whether the loop step is different from the preset step, determine whether the subtree loop step corresponding to the child node is an integer multiple of the preset step. When it is an integer multiple, define the subtree corresponding to the child node as a large-step loop code block, traverse the child nodes of the subtree corresponding to the large-step loop code block, and when the first preset condition is met, convert the subtree corresponding to the large-step loop code block into multiple corresponding basic loop step child node subtrees, delete the subtree corresponding to the large-step loop code block, and use the basic loop step subtree for processing.

4. The method according to claim 3, characterized in that The method further comprises: After converting the subtree corresponding to the large-step loop code block into a plurality of corresponding basic loop step subnode subtrees, using the data length judgment statement of the variable to be processed and judging whether the loop counter index of the statement condition is equal to 0 to determine whether there is a tail processing code block; When there is a tail processing code block, the basic step length is continuously adjusted according to the length of the data to be processed of the tail processing code block to form at least one tail processing step length loop code block, and the tail processing base step length loop code block is processed until the tail processing code block is processed; The initial value of the loop counter index is determined according to the number of variables in the code, and the index value is iteratively changed according to the loop step.

5. The method according to claim 3, characterized in that: The method further comprises: Modify the LMUL involving vector registers in the base stride loop code block to a multiple of the basic loop step of the large stride loop code block, or other values ​​that conform to the hardware characteristics, and modify the number of elements processed each time to the length of the vector length register vl, which is set by the length setting vector length statement.

6. The method according to claim 4, characterized in that The first preset condition includes: The tree composed of the plurality of corresponding basic loop step length sub-node sub-trees is the same as the sub-tree corresponding to the large-step length loop code block; and The step size of each basic loop step sub-node sub-tree is the same as the preset step size.

7. The method according to claim 6, characterized in that The method further comprises: A subtree that does not contain any fixed vector length built-in function is identified as an instruction set independent code block, and the instruction set independent code block is not processed.

8. The method according to claim 5, characterized in that The method further comprises: If the tail processing code block exists, the tail processing code block is deleted, and the judgment condition of the reference step loop code block is modified to loop counter index>0.

9. A conversion device based on a built-in function of a RISC-V architecture, characterized in that: include: A parsing module is used to parse the source code file and obtain the operator functions contained therein; A traversal module, used to convert the operator function into an AST abstract syntax tree, and traverse the AST abstract syntax tree to obtain child nodes of the AST abstract syntax tree; A judgment module, used for judging whether the loop step length of the sub-node is the same as the preset step length when the sub-node is a loop statement node; Set as a module, used to set the child node to the basic loop step subtree when the same; An identification module is used to generate a second AST abstract syntax tree based on the basic loop step subtree, traverse the second AST abstract syntax tree, and expand the scalar in the code block corresponding to the basic loop step subtree into a vector assignment statement, and identify it as a vector extension statement to be optimized for vector-scalar instructions; A search module, used for searching the corresponding vector-scalar instruction optimization statement to be performed from the following text of the vector extension statement to be optimized for the vector-scalar instruction; The replacement module is used to convert the vector-extended assignment statement into a normal assignment statement when finding the vector-scalar instruction optimization statement to be found, replace the vector instructions of the original instruction set with the vector instructions of the target instruction set according to the mapping vector instruction mapping table, and replace the vector instructions of the target instruction set with the corresponding vector-scalar instructions.

10. A storage medium containing computer executable instructions, characterized in that: The computer executable instructions, when executed by a computer processor, are used to execute the conversion method based on the RISC-V architecture built-in function as described in any one of claims 1 to 8.

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