Entity unit management method and storage device

Abstract

The application provides a physical unit management method and a storage device. The method comprises: determining a programming mode, a verification time point and a classification rule for a first physical unit according to a type of the first physical unit; programming the first physical unit based on the programming mode; verifying reliability of the first physical unit at the verification time point; and classifying the first physical unit according to the classification rule and a verification result of the reliability. Thus, a balance can be achieved between improving reliability of a memory module and maintaining a number of available physical units as much as possible.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a physical unit management method and storage device. Background Technology

[0002] Throughout its lifecycle, memory modules (such as flash memory modules) may experience accelerated aging of some physical blocks as usage increases. Once a physical block ages, its reliability will significantly decline (e.g., the data stored in the physical block may contain more errors).

[0003] Generally, during the manufacturing process of memory modules, manufacturers first perform read and write tests, classifying physical blocks with significantly poor reliability as bad blocks to improve the overall reliability of the memory module. After the storage device leaves the factory, with increased usage and changes in the usage environment, some physical blocks still have the risk of aging. Therefore, if physical blocks with aging risks are not detected and disabled through specific means, the overall reliability of the memory module will significantly decrease (e.g., increasing the risk of data loss). On the other hand, if physical blocks with aging risks are disabled too frequently, some still usable physical blocks may be mistakenly identified as aging physical blocks, leading to a significant decrease in the data storage capacity of the memory module.

[0004] Therefore, striking a balance between improving the reliability of memory modules and maintaining the number of available physical blocks as much as possible is a problem that urgently needs to be solved. Summary of the Invention

[0005] The present invention provides a physical cell management method and storage device that can improve the problems arising from the improper management of physical blocks with aging risks in the past, thereby achieving a balance between improving the reliability of the memory module and maintaining the number of available physical cells as much as possible.

[0006] Embodiments of the present invention provide an entity unit management method for a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of entity units, and the entity unit management method includes: determining a programming mode, a verification time point, and a classification rule for a first entity unit according to the type of a first entity unit among the plurality of entity units; programming the first entity unit based on the programming mode; verifying the reliability of the first entity unit at the verification time point; and classifying the first entity unit according to the classification rule and the verification result of the reliability.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to: determine a programming mode, a verification time point, and a classification rule for a first physical unit based on the type of a first physical unit among the plurality of physical units; program the first physical unit based on the programming mode; verify the reliability of the first physical unit at the verification time point; and classify the first physical unit according to the classification rule and the verification result of the reliability.

[0008] Based on the above, the entity cell management method and storage device provided in this embodiment of the invention can manage corresponding entity cells with different reliability levels by adopting appropriate programmatic modes, verification time points, and classification rules. This improves upon the problems arising from the improper management of entity blocks with aging risks in the past, thereby achieving a balance between improving the reliability of the memory module and maintaining the number of usable entity cells as much as possible. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram illustrating the procedural patterns, verification time points, and classification rules corresponding to different types of entity units according to embodiments of the present invention;

[0013] Figure 5 This is a flowchart illustrating an entity unit management method according to an embodiment of the present invention;

[0014] Figure 6 This is a flowchart illustrating an entity unit management method according to an embodiment of the present invention;

[0015] Figure 7 This is a flowchart illustrating an entity unit management method according to an embodiment of the present invention;

[0016] Figure 8 This is a flowchart illustrating an entity unit management method according to an embodiment of the present invention. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0019] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 via connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0020] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0021] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller.

[0022] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0023] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0027] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0028] In one embodiment, an entity unit may include one or more entity erasure units. Furthermore, an entity unit may include multiple sub-entity units. For example, a sub-entity unit may include one or more entity programming units.

[0029] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, an entity programming unit may be considered as an entity page. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0030] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0031] In one embodiment, a physical erase unit may include multiple physical programmed units. The multiple physical programmed units in a physical erase unit can be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to the multiple physical programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these physical programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0032] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1) to 301(A) and 301(A+1) to 301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1) to 301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1) to 301(B) in the idle area 32 do not store any data (e.g., valid data).

[0033] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0034] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0035] In one embodiment, the memory control circuit 23 may be configured with a plurality of logic units 302(1) to 302(C) to map physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0036] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0037] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-physical mapping table).

[0038] In one embodiment, the memory control circuit 23 can detect the type of at least one entity unit (also referred to as a first entity unit) among entity units 301(1) to 301(A) and 301(A+1) to 301(B). For example, the type of the first entity unit is related to the reliability of the first entity unit. For example, entity units of different types may have different reliability. Entity units of the same type may have the same or similar reliability.

[0039] In one embodiment, the reliability of the first entity unit may be negatively correlated with its bit error rate. That is, a higher reliability of the first entity unit indicates a lower potential bit error rate (i.e., the data read from the first entity unit may contain relatively less erroneous data). Conversely, a lower reliability of the first entity unit indicates a higher potential bit error rate (i.e., the data read from the first entity unit may contain relatively more erroneous data).

[0040] In one embodiment, the reliability of the first entity unit may be negatively correlated with the degree of use of the first entity unit. That is, a higher reliability of the first entity unit indicates that the degree of use of the first entity unit may be lower (e.g., the first entity unit is programmed, read, and / or erased relatively less often). Conversely, a lower reliability of the first entity unit indicates that the degree of use of the first entity unit may be higher (i.e., the first entity unit is programmed, read, and / or erased relatively more often).

[0041] In one embodiment, the memory control circuit 23 may add a tag to the first entity unit according to its type. This tag may reflect the type of the first entity unit. In one embodiment, the memory control circuit 23 may record the tag corresponding to the first entity unit in a management table. Alternatively, in one embodiment, the memory control circuit 23 may store the tag corresponding to the first entity unit in the first entity unit.

[0042] In one embodiment, the memory control circuit 23 can determine the programming mode, verification time point, and classification rules for the first entity unit based on its type. After determining the programming mode, verification time point, and classification rules for the first entity unit, the memory control circuit 23 can manage, use, and / or operate the first entity unit according to the programming mode, the verification time point, and the classification rules.

[0043] In one embodiment, the programmatic mode can be used to control the mode employed when performing programmatic operations on the first entity unit. The verification time point can be used to control the time point at which reliability verification is performed on the first entity unit. Furthermore, the classification rule can be used to control the rules employed when classifying (or reclassifying) the first entity unit.

[0044] In one embodiment, if the first entity unit belongs to the first type of entity unit, the memory control circuit 23 can determine that the programming mode, verification time point and classification rule for the first entity unit are a specific programming mode (also known as the first programming mode) among multiple programming modes (also known as candidate programming modes), a specific verification time point (also known as the first verification time point) among multiple verification time points (also known as candidate verification time points), and a specific classification rule (also known as the first classification rule) among multiple classification rules (also known as candidate classification rules).

[0045] In one embodiment, if the first entity unit belongs to the second type of entity unit, the memory control circuit 23 can determine that the programming mode, verification time point and classification rule for the first entity unit are a specific programming mode (also known as the second programming mode) among the plurality of candidate programming modes, a specific verification time point (also known as the second verification time point) among the plurality of candidate verification time points and a specific classification rule (also known as the second classification rule) among the plurality of candidate classification rules.

[0046] In one embodiment, if the first entity unit belongs to the third type of entity unit, the memory control circuit 23 can determine that the programming mode, verification time point and classification rule for the first entity unit are a specific programming mode (also known as the third programming mode) among the plurality of candidate programming modes, a specific verification time point (also known as the third verification time point) among the plurality of candidate verification time points and a specific classification rule (also known as the third classification rule) among the plurality of candidate classification rules.

[0047] In one embodiment, the reliability of the first type of entity unit may be higher than that of the second type of entity unit, and the reliability of the second type of entity unit may be higher than that of the third type of entity unit. In one embodiment, if the first entity unit belongs to the first type of entity unit, the second type of entity unit, or the third type of entity unit, the memory control circuit 23 may use the first entity unit to store data.

[0048] In one embodiment, the first entity unit may also belong to a fourth type of entity unit. The reliability of a third type of entity unit may be higher than that of a fourth type of entity unit. In one embodiment, the fourth type of entity unit includes damaged entity units. In one embodiment, if the first entity unit belongs to a fourth type of entity unit, the memory control circuit 23 may no longer use the first entity unit to store data. That is, in one embodiment, if the first entity unit is determined to belong to a fourth type of entity unit, the first entity unit will no longer be used.

[0049] In one embodiment, if the first entity unit belongs to a first type of entity unit, a second type of entity unit, or a third type of entity unit, the memory control circuit 23 may map at least one logic unit to the first entity unit. Subsequently, the memory control circuit 23 may access the first entity unit based on the at least one logic unit. However, in one embodiment, if the first entity unit belongs to a fourth type of entity unit, the memory control circuit 23 may not map any logic unit to the first entity unit. This prevents accidental access to the first entity unit.

[0050] In one embodiment, the plurality of candidate programming patterns may include single-level programming patterns and multi-level programming patterns. In one embodiment, the single-level programming pattern includes the SLC pattern (also known as the virtual SLC pattern). Based on the single-level programming pattern, a storage unit in an entity unit can be programmed to store p bits. For example, p can be "1". In one embodiment, the multi-level programming pattern may include the MLC pattern, TLC pattern, QLC pattern, or other types of multi-level programming patterns. Based on the multi-level programming pattern, a storage unit in an entity unit can be programmed to store q bits. For example, q can be "2", "3", "4", or other integers greater than "1".

[0051] In one embodiment, the plurality of candidate verification time points may include a first time point and a second time point. The first time point is located during the period when a regular read operation is performed on the first physical unit. For example, the first time point can refer to any time point during the period when a regular read operation is performed on the first physical unit. For example, the regular read operation may be performed according to instructions (e.g., read instructions) from the host system 11. Alternatively, the regular read operation may also be performed according to data compaction operations performed on the memory module 122. For example, the data compaction operation may include garbage collection (GC) operations, wear leveling (WL) operations, or other operations involving data movement within the memory module 122. Furthermore, the second time point is after the first physical unit is filled. For example, the second time point can refer to any time point after the first physical unit is filled. Additionally, the plurality of candidate classification rules can be used to classify different types of physical units.

[0052] In one embodiment, after determining the programming mode for the first entity unit, the memory control circuit 23 can program the first entity unit based on the programming mode. For example, if the first entity unit belongs to a first type of entity unit, the memory control circuit 23 can program the first entity unit based on the first programming mode. If the first entity unit belongs to a second type of entity unit, the memory control circuit 23 can program the first entity unit based on a second programming mode. Alternatively, if the first entity unit belongs to a third type of entity unit, the memory control circuit 23 can program the first entity unit based on a third programming mode.

[0053] In one embodiment, the first programming mode includes a single-level programming mode and a multi-level programming mode, and / or the second programming mode also includes a single-level programming mode and a multi-level programming mode. For example, the memory control circuit 23 can, as needed, determine whether to program the first entity unit belonging to the first type of entity unit or the second type of entity unit based on one of the single-level programming mode and the multi-level programming mode.

[0054] In one embodiment, the third programming mode can only be a single-level programming mode. For example, for a first entity unit belonging to the third type of entity unit, the memory control circuit 23 can program the first entity unit based on a single-level programming mode, but cannot program the first entity unit based on a multi-level programming mode. Thus, even if the reliability of the first entity unit belonging to the third type of entity unit is relatively low, there is still an opportunity to maintain the normal use of the first entity unit by strictly controlling the programming mode for the first entity unit.

[0055] In one embodiment, after determining a verification time point for the first entity unit, the memory control circuit 23 can verify the reliability of the first entity unit at that verification time point. For example, in the operation of verifying the reliability of the first entity unit, the memory control circuit 23 can read data (also referred to as first data) from the first entity unit. Then, the decoding circuit 25 decodes the first data based on at least one of a plurality of decoding modes (also referred to as candidate decoding modes). For example, the decoding circuit 25 can decode the first data based on at least one of the plurality of decoding modes according to a preset order until the first data is successfully decoded (i.e., all errors in the first data are corrected) or it is determined that the first data cannot be successfully decoded (i.e., all errors in the first data cannot be corrected). Then, the memory control circuit 23 can confirm the reliability of the first entity unit based on the decoding result of the first data.

[0056] In one embodiment, the first verification time point is a first time point, the second verification time point is a second time point, and / or the third verification time point is a second time point.

[0057] For example, for a first entity cell belonging to the first type of entity cell, the memory control circuit 23 can integrate the timing of verifying the reliability of the first entity cell (i.e., the first time point) into the regular read operation for the first entity cell, without needing to additionally verify the reliability of the first entity cell at the second time point (i.e., after the first entity cell is full).

[0058] However, for the first entity unit belonging to the second or third type of entity unit, the memory control circuit 23 needs to verify the reliability of the first entity unit after it is filled each time. Therefore, by performing additional reliability verification on the entity unit after each entity unit with relatively low reliability (i.e., the second or third type of entity unit) is filled, it can be ensured as much as possible that the current classification results for each entity unit are correct.

[0059] In one embodiment, after determining the classification rules for the first entity unit and the reliability verification results for the first entity unit, the memory control circuit 23 can classify the first entity unit according to the classification rules and the reliability verification results. It should be noted that the classification may refer to maintaining or changing the previous classification result of the first entity unit. In particular, for different types of first entity units, the memory control circuit 23 can use the most suitable classification rules to classify the first entity units.

[0060] Figure 4 This is a schematic diagram illustrating the procedural patterns, verification time points, and classification rules corresponding to different types of entity units according to embodiments of the present invention. Please refer to... Figure 4Referring to Table 41, depending on the type of the first entity unit, the memory control circuit 23 can manage, use, and / or operate the first entity unit according to a suitable programming mode, verification time point, and classification rules.

[0061] For example, for a first entity unit belonging to the first type of entity unit, the memory control circuit 23 can set the programming mode, verification time point and classification rule corresponding to the first entity unit as "SLC (i.e., single-level programming mode) / xLC (i.e., multi-level programming mode)", "T(1) (i.e., first time point)" and "R(1) (i.e., first grouping rule)" respectively.

[0062] For a first entity unit belonging to the second type of entity unit, the memory control circuit 23 can set the programming mode, verification time point and classification rule corresponding to the first entity unit as "SLC / xLC", "T(2) (i.e., the second time point)" and "R(2) (i.e., the second grouping rule)" respectively.

[0063] For a first entity unit belonging to the third type of entity unit, the memory control circuit 23 can set the programming mode, verification time point, and classification rule corresponding to the first entity unit to "SLC", "T(2)", and "R(3)" (i.e., the third grouping rule), respectively. In addition, for a first entity unit belonging to the fourth type of entity unit, the memory control circuit 23 can set the first entity unit to be no longer used.

[0064] By using the method proposed in this application, different usage strategies can be set for different types of entity units, thereby improving the stability and security of data storage. By setting different usage methods throughout the entire lifecycle of the storage device, the stability of data can be guaranteed when the storage device is nearing the end of its lifecycle.

[0065] It should be noted that, Figure 4 The management strategies for different types of entity units presented in Table 41 are merely examples and are not intended to limit the present invention. In one embodiment, the information in each field of Table 41 can be adjusted according to practical needs, and the present invention does not impose any limitations on this.

[0066] In one embodiment, when the first entity unit belongs to the first type of entity unit, the memory control circuit 23 can classify the first entity unit according to the first classification rule and the verification result of the reliability of the first entity unit at the first verification time point.

[0067] For example, if the verification result of the reliability of the first entity unit reflects that the first data was successfully decoded based on a specific decoding mode (also known as the first decoding mode) among the plurality of decoding modes, then the memory control circuit 23 can maintain the first entity unit as a first type of entity unit.

[0068] If the verification result of the reliability of the first entity unit reflects that the first data was successfully decoded based on another decoding mode (also known as the second decoding mode) among the plurality of decoding modes, then the memory control circuit 23 can classify the first entity unit as a second type of entity unit.

[0069] Furthermore, if the reliability verification result of the first entity unit reflects that the first data cannot be successfully decoded (by any decoding mode), the memory control circuit 23 may classify the first entity unit as a third type of entity unit.

[0070] It should be noted that the second decoding mode is triggered after the first decoding mode fails. For example, during the decoding process of the first data by the decoding circuit 25, the decoding circuit 25 may first decode the first data based on the first decoding mode. If the first data cannot be successfully decoded based on the first decoding mode, the second decoding mode may be triggered. Then, the decoding circuit 25 may decode the first data based on the second decoding mode. Furthermore, the error correction capability of the second decoding mode may be higher than that of the first decoding mode.

[0071] In one embodiment, the first decoding mode may include multiple decoding modes (also referred to as sub-decoding modes). For example, the multiple sub-decoding modes may include a regular decoding mode (also referred to as the first sub-decoding mode), a retry mode (also referred to as the second sub-decoding mode), and a soft bit decoding mode (also referred to as the third sub-decoding mode).

[0072] In one embodiment, the conventional decoding mode refers to the basic decoding mode in which the decoding circuit 25 initially performs a decoding operation on the first data after reading the first data from the first physical unit. The retry mode refers to an advanced decoding mode that, after determining that the first data cannot be decoded based on the conventional decoding mode, attempts to reduce erroneous bits in the read first data by adjusting the read voltage level for the first physical unit and repeatedly reading the first physical unit. The soft-bit decoding mode refers to a more advanced decoding mode that, after determining that the first data still cannot be decoded based on the retry mode, applies a higher read voltage level to the first physical unit to read additional auxiliary decoding data (also called soft bits) and adjusts some decoding parameters (e.g., the Log Likelihood Ratio (LLR)) to improve the decoding success rate.

[0073] In one embodiment, based on the first decoding mode, the decoding circuit 25 can sequentially decode the first data through the first sub-decoding mode, the second sub-decoding mode and the third sub-decoding mode until the first data is successfully decoded or it is determined that the first decoding mode cannot successfully decode the first data.

[0074] In one embodiment, the time required to decode the first data based on the first sub-decoding mode is less than the time required to decode the first data based on the second sub-decoding mode, and the time required to decode the first data based on the second sub-decoding mode is less than the time required to decode the first data based on the third sub-decoding mode. Conversely, the error correction capability of the second sub-decoding mode may be higher than that of the first sub-decoding mode, and the error correction capability of the third sub-decoding mode may be higher than that of the second sub-decoding mode.

[0075] In one embodiment, the second decoding mode may include a group decoding mode. For example, assuming the first data to be decoded is read from a first entity programmed unit in a first entity unit, in the group decoding mode, data stored in other entity programmed units in the first entity unit (or other entity units) can be used together to decode the first data. In one embodiment, the second decoding mode is also referred to as a disk array (RAID) decoding mode.

[0076] It should be noted that the first decoding mode, the various sub-decoding modes within the first decoding mode, and the second decoding mode mentioned in the foregoing embodiments are merely examples and are not intended to limit the present invention. In one embodiment, any decoding mode and any sub-decoding mode can be adjusted according to practical needs, and the present invention does not impose any limitations on them.

[0077] In one embodiment, if the first entity unit belongs to the second type of entity unit, the memory control circuit 23 can classify the first entity unit according to a second classification rule and the verification result of the reliability of the first entity unit at the second verification time point. For example, if the verification result of the reliability of the first entity unit reflects that the first data was successfully decoded based on a specific sub-decoding mode (e.g., the first sub-decoding mode) in the first decoding mode, the memory control circuit 23 can classify the first entity unit as a first type of entity unit. If the verification result of the reliability of the first entity unit reflects that the first data was successfully decoded based on another sub-decoding mode (e.g., the second sub-decoding mode) in the first decoding mode, the memory control circuit 23 can maintain the first entity unit as a second type of entity unit. Furthermore, if the verification result of the reliability of the first entity unit reflects that the first data cannot be successfully decoded (by the second sub-decoding mode or other sub-decoding modes), the memory control circuit 23 can classify the first entity unit as a third type of entity unit.

[0078] In one embodiment, if the first entity unit belongs to the third type of entity unit, the memory control circuit 23 can classify the first entity unit according to the third classification rule and the reliability verification result of the first entity unit at the third verification time point. For example, if the reliability verification result of the first entity unit reflects that the first data can be successfully decoded, the memory control circuit 23 can maintain the first entity unit as a third type of entity unit. However, if the reliability verification result of the first entity unit reflects that the first data cannot be successfully decoded, the memory control circuit 23 can classify the first entity unit as a fourth type of entity unit.

[0079] It should be noted that once the first entity unit is classified as a fourth type of entity unit, the first entity unit can no longer be used. For example, the memory control circuit 23 can lock the first entity unit that belongs to the fourth type of entity unit, making the first entity unit unusable.

[0080] In one embodiment, the memory control circuit 23 can also monitor at any point in time whether the usage level of the first physical unit meets preset conditions. If the usage level of the first physical unit meets the preset conditions, the memory control circuit 23 can classify the first physical unit into one of a second type of physical unit, a third type of physical unit, and a fourth type of physical unit, depending on the current settings and / or requirements.

[0081] In one embodiment, the memory control circuit 23 can obtain a wear assessment value corresponding to the first physical cell. This wear assessment value can reflect the usage level of the first physical cell. For example, this wear assessment value can be positively correlated with the usage level of the first physical cell. That is, the larger the wear assessment value, the higher the usage level of the first physical cell. For example, the memory control circuit 23 can determine this wear assessment value corresponding to the first physical cell based on the programming count, read count, erase count, and / or bit error rate assessment value corresponding to the first physical cell. The programming count can reflect the number of times the first physical cell has been programmed. The read count can reflect the number of times the first physical cell has been read. The erase count can reflect the number of times the first physical cell has been erased. The bit error rate assessment value can reflect the bit error rate of the first physical cell. In addition, the wear assessment value corresponding to the first physical cell can also be determined with reference to other parameters, which are not limited by the present invention.

[0082] In one embodiment, the memory control circuit 23 can compare a wear assessment value corresponding to the first physical cell with a threshold value. If the wear assessment value is greater than the threshold value, the memory control circuit 23 can determine that the usage level of the first physical cell meets a preset condition. However, if the wear assessment value is not greater than (e.g., less than or equal to) the threshold value, the memory control circuit 23 can determine that the usage level of the first physical cell does not meet the preset condition.

[0083] In one embodiment, the memory control circuit 23 can monitor whether each programming and / or erasure of the first entity unit is successful. If a programming or erasure of the first entity unit fails, the memory control circuit 23 can classify the first entity unit into one of a second type of entity unit, a third type of entity unit, or a fourth type of entity unit, depending on the current settings and / or requirements.

[0084] Figure 5 This is a flowchart illustrating an entity unit management method according to an embodiment of the present invention. Please refer to... Figure 5 In step S501, based on the type of the first entity unit, the programming mode, verification time point, and classification rules for the first entity unit are determined. In step S502, the first entity unit is programmed based on the programming mode. In step S503, at the verification time point, the reliability of the first entity unit is verified. In step S504, the first entity unit is classified according to the classification rules and the reliability verification results.

[0085] Figure 6 This is a flowchart illustrating an entity unit management method according to an embodiment of the present invention. Please refer to... Figure 6 As shown, the specific steps include the following:

[0086] In step S601, it is determined that the first entity unit belongs to the first type of entity unit.

[0087] In step S602, it is determined whether the first data can be successfully decoded based on the first decoding mode among multiple decoding modes.

[0088] If the first data can be successfully decoded based on the first decoding mode, in step S603, the first entity unit is maintained as a first type of entity unit.

[0089] If the first data cannot be successfully decoded based on the first decoding mode, in step S604, it is determined whether the first data can be successfully decoded based on the second decoding mode among the plurality of decoding modes.

[0090] If the first data can be successfully decoded based on the second decoding mode, in step S605, the first entity unit is classified as a second type of entity unit.

[0091] If the first data cannot be successfully decoded, in step S606, the first entity unit is classified as a third type of entity unit.

[0092] Figure 7 This is a flowchart illustrating an entity unit management method according to an embodiment of the present invention. Please refer to... Figure 7 As shown, the specific steps include the following:

[0093] In step S701, it is determined that the first entity unit belongs to the second type of entity unit.

[0094] In step S702, it is determined whether the first data can be successfully decoded based on the first sub-decoding mode in the first decoding mode.

[0095] If the first data can be successfully decoded based on the first sub-decoding mode, in step S703, the first entity unit is reclassified as a first type of entity unit.

[0096] If the first data cannot be successfully decoded based on the first sub-decoding mode, in step S704, it is determined whether the first data can be successfully decoded based on the second sub-decoding mode in the first decoding mode.

[0097] If the first data can be successfully decoded based on the second sub-decoding mode, in step S705, the first entity unit is maintained as the second type of entity unit.

[0098] If the first data cannot be successfully decoded, in step S706, the first entity unit is classified as a third type of entity unit.

[0099] Figure 8 This is a flowchart illustrating an entity unit management method according to an embodiment of the present invention. Please refer to... Figure 8 As shown, the specific steps include the following:

[0100] In step S801, it is determined that the first entity unit belongs to the third type of entity unit.

[0101] In step S802, it is determined whether the first data can be successfully decoded.

[0102] If the first data can be successfully decoded, in step S803, the first entity unit is maintained as a third type entity unit.

[0103] If the first data cannot be successfully decoded, in step S804, the first entity unit is classified as a fourth type of entity unit.

[0104] However, Figures 5 to 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 5 to 8 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figures 5 to 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0105] In summary, the entity cell management method and storage device provided in this invention can manage entity cells with different reliability levels by employing appropriate programming modes, verification time points, and classification rules. In particular, for entity cells with relatively low reliability (i.e., second-class and third-class entity cells), in addition to limiting them to using only higher-reliability programming modes, an additional procedure is added to verify the reliability of the entity cell after it is fully written. This improves upon the problems arising from the improper management of entity blocks with aging risks in the past, thereby achieving a balance between improving the reliability of the memory module and maintaining the number of available entity cells as much as possible.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for managing entity units, characterized in that, A storage device, wherein the storage device includes a memory module, the memory module includes a plurality of physical units, and the physical unit management method includes: Based on the type of the first entity unit among the plurality of entity units, the programmatic mode, verification time point, and classification rules for the first entity unit are determined, specifically including the following steps: If the first entity unit belongs to the first type of entity unit, the programmatic mode, the verification time point and the classification rule for the first entity unit are determined to be the first programmatic mode among multiple candidate programmatic modes, the first verification time point among multiple candidate verification time points and the first classification rule among multiple candidate classification rules, respectively. If the first entity unit belongs to the second type of entity unit, then the programmatic pattern, the verification time point, and the classification rule for the first entity unit are determined to be the second programmatic pattern among the plurality of candidate programmatic patterns, the second verification time point among the plurality of candidate verification time points, and the second classification rule among the plurality of candidate classification rules, respectively; and If the first entity unit belongs to the third type of entity unit, the programmatic mode, the verification time point and the classification rule for the first entity unit are determined to be the third programmatic mode among the multiple candidate programmatic modes, the third verification time point among the multiple candidate verification time points and the third classification rule among the multiple candidate classification rules, wherein the reliability of the first type of entity unit is higher than the reliability of the second type of entity unit, and the reliability of the second type of entity unit is higher than the reliability of the third type of entity unit. Based on the programmatic pattern, program the first entity unit; At the verification time point, the reliability of the first entity unit is verified; and The first entity unit is classified according to the classification rules and the reliability verification results.

2. The entity unit management method according to claim 1, wherein the programmatic mode includes a plurality of candidate programmatic modes, each of the candidate programmatic modes includes a single-level programmatic mode and / or a multi-level programmatic mode, the verification time point includes one of a first time point and a second time point, the first time point being located during the period of performing a regular read operation on the first entity unit, and the second time point being after the first entity unit is filled.

3. The entity unit management method according to claim 1, wherein the first programmed mode includes a single-level programmed mode and a multi-level programmed mode, the second programmed mode includes the single-level programmed mode and the multi-level programmed mode, and the third programmed mode is the single-level programmed mode.

4. The entity unit management method according to claim 1, wherein the first verification time point is a first time point, the second verification time point is a second time point, the third verification time point is the second time point, the first time point is located during the period of performing a regular read operation on the first entity unit, and the second time point is after the first entity unit is filled.

5. The entity unit management method according to claim 1, wherein the step of verifying the reliability of the first entity unit includes: Read the first data from the first entity unit; as well as The first data is decoded based on at least one of multiple decoding modes until the first data is successfully decoded or it is determined that the first data cannot be successfully decoded.

6. The entity unit management method according to claim 5, wherein when the first entity unit belongs to a first type of entity unit, the step of classifying the first entity unit according to the classification rules and the verification result of the reliability includes: If the first data is successfully decoded based on the first decoding mode among the plurality of decoding modes, the first entity unit is maintained as the first type of entity unit; If the first data is successfully decoded based on the second decoding mode among the plurality of decoding modes, the first entity unit is classified as a second type of entity unit, wherein the second decoding mode is triggered after the first decoding mode fails, and the error correction capability of the second decoding mode is higher than that of the first decoding mode; as well as If the first data cannot be successfully decoded, the first entity unit will be classified as a third type of entity unit.

7. The entity unit management method according to claim 5, wherein when the first entity unit belongs to the second type of entity unit, the step of classifying the first entity unit according to the classification rules and the verification result of the reliability includes: If the first data is successfully decoded based on the first sub-decoding mode of the first decoding mode among the plurality of decoding modes, the first entity unit is classified as a first type of entity unit; If the first data is successfully decoded based on the second sub-decoding mode in the first decoding mode, the first entity unit is maintained as the second type of entity unit, wherein the second sub-decoding mode is triggered after the first sub-decoding mode fails, and the error correction capability of the second sub-decoding mode is higher than that of the first sub-decoding mode; and If the first data cannot be successfully decoded, the first entity unit will be classified as a third type of entity unit.

8. The entity unit management method according to claim 5, wherein when the first entity unit belongs to a third type of entity unit, the step of classifying the first entity unit according to the classification rules and the verification result of the reliability includes: If the first data can be successfully decoded, the first entity unit will remain as the third type of entity unit; as well as If the first data cannot be successfully decoded, the first entity unit is classified as a fourth type of entity unit, wherein the fourth type of entity unit is no longer used.

9. The entity unit management method according to claim 1, further comprising: Monitor whether the usage level of the first entity unit meets preset conditions; Monitor whether the programming and / or erasure of the first entity unit is successful; as well as If the usage level of the first entity unit meets the preset conditions, or if the programming or erasure of the first entity unit fails, the first entity unit is classified into one of the second type of entity unit, the third type of entity unit, and the fourth type of entity unit.

10. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory module comprises multiple physical units, and the memory controller is used to: Based on the type of the first entity unit among the plurality of entity units, the programmatic mode, verification time point, and classification rules for the first entity unit are determined, specifically including the following steps: If the first entity unit belongs to the first type of entity unit, the programmatic mode, the verification time point and the classification rule for the first entity unit are determined to be the first programmatic mode among multiple candidate programmatic modes, the first verification time point among multiple candidate verification time points and the first classification rule among multiple candidate classification rules, respectively. If the first entity unit belongs to the second type of entity unit, then the programmatic pattern, the verification time point, and the classification rule for the first entity unit are determined to be the second programmatic pattern among the plurality of candidate programmatic patterns, the second verification time point among the plurality of candidate verification time points, and the second classification rule among the plurality of candidate classification rules, respectively; and If the first entity unit belongs to the third type of entity unit, the programmatic mode, the verification time point and the classification rule for the first entity unit are determined to be the third programmatic mode among the multiple candidate programmatic modes, the third verification time point among the multiple candidate verification time points and the third classification rule among the multiple candidate classification rules, wherein the reliability of the first type of entity unit is higher than the reliability of the second type of entity unit, and the reliability of the second type of entity unit is higher than the reliability of the third type of entity unit. Based on the programmatic pattern, program the first entity unit; At the verification time point, the reliability of the first entity unit is verified; and The first entity unit is classified according to the classification rules and the reliability verification results.

11. The storage device of claim 10, wherein the programming mode includes one of a single-level programming mode and a multi-level programming mode, the verification time point includes one of a first time point and a second time point, the first time point being located during the period of performing a regular read operation on the first physical unit, and the second time point being after the first physical unit is filled.

12. The storage device of claim 10, wherein the first programming mode includes a single-level programming mode and a multi-level programming mode, the second programming mode includes the single-level programming mode and the multi-level programming mode, and the third programming mode is the single-level programming mode.

13. The storage device of claim 10, wherein the first verification time point is a first time point, the second verification time point is a second time point, the third verification time point is the second time point, the first time point is located during the period of performing a normal read operation on the first physical unit, and the second time point is after the first physical unit is filled.

14. The storage device of claim 10, wherein the operation of the memory controller verifying the reliability of the first physical unit includes: Read the first data from the first entity unit; as well as The first data is decoded based on at least one of multiple decoding modes until the first data is successfully decoded or it is determined that the first data cannot be successfully decoded.

15. The storage device of claim 14, wherein when the first entity unit belongs to a first type of entity unit, the operation of the memory controller classifying the first entity unit according to the classification rule and the verification result of the reliability includes: If the first data is successfully decoded based on the first decoding mode among the plurality of decoding modes, the first entity unit is maintained as the first type of entity unit; If the first data is successfully decoded based on the second decoding mode among the plurality of decoding modes, the first entity unit is classified as a second type of entity unit, wherein the second decoding mode is triggered after the first decoding mode fails, and the error correction capability of the second decoding mode is higher than that of the first decoding mode; as well as If the first data cannot be successfully decoded, the first entity unit will be classified as a third type of entity unit.

16. The storage device of claim 14, wherein when the first entity unit belongs to a second type of entity unit, the operation of the memory controller classifying the first entity unit according to the classification rule and the verification result of the reliability includes: If the first data is successfully decoded based on the first sub-decoding mode of the first decoding mode among the plurality of decoding modes, the first entity unit is classified as a first type of entity unit; If the first data is successfully decoded based on the second sub-decoding mode in the first decoding mode, the first entity unit is maintained as the second type of entity unit, wherein the second sub-decoding mode is triggered after the first sub-decoding mode fails, and the error correction capability of the second sub-decoding mode is higher than that of the first sub-decoding mode; and If the first data cannot be successfully decoded, the first entity unit will be classified as a third type of entity unit.

17. The storage device of claim 14, wherein when the first entity unit belongs to a third type of entity unit, the operation of the memory controller classifying the first entity unit according to the classification rule and the verification result of the reliability includes: If the first data can be successfully decoded, the first entity unit will remain as the third type of entity unit; as well as If the first data cannot be successfully decoded, the first entity unit is classified as a fourth type of entity unit, wherein the fourth type of entity unit is no longer used.

18. The storage device of claim 10, wherein the memory controller is further configured to: Monitor whether the usage level of the first entity unit meets preset conditions; Monitor whether the programming and / or erasure of the first entity unit is successful; and If the usage level of the first entity unit meets the preset conditions, or if the programming or erasure of the first entity unit fails, the first entity unit is classified into one of the second, third, and fourth types of entity units.

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