Flash online loading method based on pxi

Abstract

The invention relates to a pxi-based flash online loading method. The method comprises the following steps that: an upper computer issues a transmission starting signal, the size of a writing length to be issued, a flash writing address and a flash writing command to a flash control module; the upper computer transmits binary file data to the pxi slave device in a dma mode and temporarily stores the binary file data to fifo, and when data transmission of the writing length is completed, the pxi slave device informs the upper computer of interruption; and the flash control module controls the fifo to write a binary number into the flash chip until all data in the fifo are written into the flash chip by the pxi slave device, and the pxi slave device informs the upper computer that writing is completed. According to the method, under the condition that redundant software and hardware structures are not added, software and hardware resources and cost are reduced, the requirement for device type selection is lowered, and online loading of the fpga drive file is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of human-computer interaction, and in particular to a flash online loading method based on PXI. Background Art

[0002] The pxi bus is a virtual instrument architecture that integrates the pci bus core technology and adds other technical specifications and requirements to suit the application of experiments, measurements and data acquisition. Multiple slave devices can be connected to the pxi bus. The hardware devices on the slave device use FPGA as the main control chip and can communicate with the host computer through the pxi bus. It is inevitable to frequently update the program of the FPGA master chip during the initial development or later maintenance of the slave device. The traditional JATG update method is to write the files to be solidified into the flash device through the FPGA master chip (that is, FPGA through a USB-cable box). When the pxi system is very complex and the number of slave devices that need to be updated is large, the JATG method is time-consuming and labor-intensive and requires disassembly of the architecture.

[0003] At present, the commonly used solution is to use PCI bus, host computer, and flash as carriers to realize online data loading. The host computer sends control read and write enable signals and address lines through PCI bus, and FPGA writes configuration files through SPI interface of flash. After power failure and restart, FPGA automatically retrieves configuration data from flash to realize loading. Due to the strict specifications and complex use of PCI protocol, there are two commonly used development methods: One is to use IP core to realize PCI bus control. The main way to realize IP core is to purchase verified PCI bus protocol controller from professional companies in the industry, which can be used directly in FPGA chip, but there is a problem that the cost may be too high. It processes the bus protocol inside FPGA. The advantages are higher integration and lower data transmission delay. The disadvantage is that it consumes more logic resources and has certain requirements for FPGA resources, which will bring hidden dangers to the subsequent development of other functions. Moreover, there are few FPGA products with IP cores containing PCI bus in China. The chip selection depends on the specific model of FPGA, which is not easy to select chips. Therefore, the portability of the program using this method will be very poor.

[0004] The other is to use a dedicated chip to achieve the conversion of the PCI bus protocol. The dedicated chip is provided by a third-party manufacturer and is mainly responsible for processing the PCI transmission protocol, thereby providing an easy-to-control chip local bus protocol and interface for the FPGA. The signal and timing of this local bus protocol have been greatly simplified compared to the PCI bus protocol. This method is convenient for development and saves FPGA general logic resources. The disadvantage is that the cost will be relatively higher and additional hardware resources will be occupied, which will increase the hardware PCB design area and inevitably affect the transmission delay of some signals. In the current international environment, the interruption of chip supply can easily cause the product to lose production conditions. Therefore, it is urgent to get rid of dependence on imported chips and realize state-owned independent control of products.

[0005] Since the main clock of our pxi system is 33M, we only use the protocol of part of the bus transmission under the 33M clock of pci to design the transmission of online loading data, which can solve the use of normal functions and save logic resources at the same time. In the pxi system, there are often multiple devices running at the same time. To ensure the stable operation of each device, the transmission of each configuration signal and data requires repeated application and release of the bus, which adds a lot of pressure to the scheduling of the bus. Therefore, after saving logic resources, the relatively high demand for data transmission can be increased by increasing the internal cache space to increase the transmission volume of the bus data applied once, reduce the number of bus applications, and reduce the scheduling pressure of the bus to a certain extent. Summary of the invention

[0006] The present invention aims to solve the above problems and proposes a flash online loading method based on the 33M master clock of the pxi system.

[0007] The technical solution of the present invention is: A method for online flash loading based on PXI includes a host computer, a PXI system and a PXI slave device connected in sequence; the PXI slave device has a built-in flash control module, and the flash control module controls a flash chip; the characteristic is that: the PXI slave device has a built-in PCI interface module, and the external PCI bus of the PCI interface module is connected to the PXI system; then the host computer controls the PXI system and the PXI slave device in sequence, and then controls the flash control module to realize online loading; The PCI interface module includes a transmission engine module and a configuration management module, an address decoding module, a register access module and a FIFO respectively connected to the transmission engine module; and also includes a reset management module, the reset management module is respectively connected to the configuration management module, the address decoding module, the register access module and the transmission engine module; the transmission engine module is also connected to an external PCI bus and then connected to an external PCI device; the address decoding module is also connected to the register access module; the FIFO includes an input FIFO and an output FIFO; the input FIFO and the output FIFO are both connected to the transmission engine module; The transmission engine module includes a PCI configuration space timing processing module, a PCI register read and write timing processing module and a DMA data transmission timing processing module; the PCI configuration space timing processing module is connected to the configuration management module, the PCI register read and write timing processing module is connected to the address decoding module, and one end of the DMA data transmission timing processing module is connected to the register access module and the other end is connected to the FIFO; The specific process of online loading is as follows: Flash write: The host computer sends the transmission start signal, the writing length to be sent, the flash write address and the flash write command to the flash control module of the PXI slave device; The host computer transmits binary file data to the PXI slave device in DMA mode and temporarily stores it in FIFO. When the data transmission of writing length is completed, the PXI slave device informs the host computer of interruption. The flash control module controls the fifo to write binary numbers to the flash chip until all the data in the fifo are written into the flash chip by the pxi slave device, and the pxi slave device informs the host computer that the writing is completed; Flash read: The host computer sends the transmission start signal, the reading length to be read, the flash read address and the flash read command to the flash control module of the PXI slave device; The pxi slave device reads the binary number from the flash chip and temporarily stores it in the fifo. When the length of the read data reaches the read length, the pxi slave device informs the host computer that the reading is completed. The PXI slave device transmits the binary number temporarily stored in the FIFO to the host computer in DMA mode. After the transmission is completed, the PXI slave device notifies the host computer of the completion of the transmission in an interrupt mode.

[0008] in, The host computer sends a transmission start signal, a writing length to be sent, a flash write address and a flash write command to the flash control module of the PXI slave device through the PCI register write; the host computer sends a transmission start signal, a reading length to be read, a flash read address and a flash read command to the flash control module of the PXI slave device through the PCI register write; The specific process of writing the pci register is: The host computer sends a register write command to the address decoding module through the PCI register read and write timing processing module of the transmission engine module. The address decoding module determines that the recipient is a user function module in the register access module, and the user module is a flash control module.

[0009] in, The specific process of the address decoding module determining the recipient is as follows: The address decoding module uses the highest 2 bits in the address bus to perform decoding operations; when the highest 2 bits in the address bus ≠ 2'b00, the access address of the address decoding module is mapped to the user function module in the register access module, and a corresponding enable signal is generated accordingly; The address decoding module transmits the read-write address, write data and enable signal to the register access module, and the register access module stores and identifies the read-write address and enable signal; if the host computer sends a register write command to the transmission engine module, the write data is transmitted to the user function module accordingly and used as the corresponding control signal; if it is a register read command, the feedback data of the control signal corresponding to the user function module is transmitted via the register access module to the address decoding module and then to the PCI register read-write timing processing module of the transmission engine module, and is placed on the PCI bus by the PXI slave device for reading by the host computer.

[0010] in, The host computer transmits binary file data through the DMA data transmission timing processing module of the transmission engine module and temporarily stores it in the output fifo. When the storage data size of the output fifo is consistent with the writing length, the output fifo temporary storage is completed; the flash control module reads the binary number from the flash chip and temporarily stores it in the input fifo. When the storage data size of the input fifo is consistent with the read length, the input fifo temporary storage is completed.

[0011] Also includes: The flash control module sends a write command to the flash chip through the SPI timing and controls the output fifo to write binary numbers to the flash chip; the flash control module sends a read command to the flash chip through the SPI timing and controls the reading of binary numbers from the input fifo to the host computer.

[0012] The written binary number / read binary number is in pages, and each page includes 256 bytes.

[0013] Also includes, After the flash control module writes a page of binary numbers from the output fifo to the flash chip, the flash control module reads the write completion flag in the flash chip through the SPI timing. When the write completion flag is 1, the page data is written successfully; the flash control module takes data from the output fifo and continues to write the next page to the flash chip until the writing length is reached, and all the data in the output fifo is written into the flash chip; the host computer reads the write completion flag under the corresponding address through the PCI register. When the write completion flag is 1, the host computer continues to transmit the binary file data to the output fifo through the DMA data transmission timing processing module of the transmission engine module until all the binary numbers are transmitted; The specific process of the PCI register reading is: The host computer sends a register read command to the address decoding module through the PCI register read and write timing processing module of the transmission engine module. The address decoding module determines that the recipient is a user function module in the register access module, and the user module is a flash control module.

[0014] Also includes, When the binary number read from the flash chip by the flash control module reaches the read length, all the data of the flash chip are temporarily stored in the input fifo; the host computer reads the read completion flag under the corresponding address through the pci register. When the read completion flag is 1, the host computer continues to read the binary number from the input fifo to the flash chip through the dma data transmission timing processing module of the transmission engine module until all the binary numbers are read.

[0015] Also includes, In the PXI slave device, change the flash pin that controls the flash control module from a dedicated pin to a common pin; Before writing or reading flash, the host computer sends a read flash ID command to the flash control module through register write; the host computer reads back the flash ID received by the flash control module through register read to detect whether the flash is online; before executing the flash write operation when the flash is online, the host computer sends an erase command to the flash control module through register write, and the host computer reads back the erase result through register read; after the erase is completed, the flash write starts.

[0016] The writing length and reading length should be integer multiples of a flash page in the flash control module, and if they are insufficient, they should be filled with 0.

[0017] The technical effects of the present invention are: The present invention reduces software and hardware resources and costs without adding redundant software and hardware structures, reduces the requirements for device selection, realizes online loading of FPGA driver files, improves the convenience of loading driver files, and the PCI interface module is fully independently developed, which is applicable to any FPGA product that can provide a PCI hardware interface specification, and the code portability is very high; Through close cooperation with the host computer during the PCI multi-byte burst transmission process, the transmission rate is high, and the saving of logical resources can increase the FIFO cache before flash writing and after reading, ensuring the stable transmission of online downloaded file data, reducing the bus call rate of multiple devices under the PXI system, and increasing the stability of the bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural block diagram of the PCI interface module of the present invention. DETAILED DESCRIPTION

[0019] Example 1 A method for online flash loading based on PXI includes a host computer, a PXI system and a PXI slave device connected in sequence; the PXI slave device has a built-in flash control module, and the flash control module controls a flash chip; the characteristic is that: the PXI slave device has a built-in PCI interface module, and the external PCI bus of the PCI interface module is connected to the PXI system; then the host computer controls the PXI system and the PXI slave device in sequence, and then controls the flash control module to realize online loading; The PCI interface module includes a transmission engine module and a configuration management module, an address decoding module, a register access module and a FIFO respectively connected to the transmission engine module; and also includes a reset management module, the reset management module is respectively connected to the configuration management module, the address decoding module, the register access module and the transmission engine module; the transmission engine module is also connected to an external PCI bus and then connected to an external PCI device; the address decoding module is also connected to the register access module; the FIFO includes an input FIFO and an output FIFO; the input FIFO and the output FIFO are both connected to the transmission engine module; The transmission engine module includes a PCI configuration space timing processing module, a PCI register read and write timing processing module and a DMA data transmission timing processing module; the PCI configuration space timing processing module is connected to the configuration management module, the PCI register read and write timing processing module is connected to the address decoding module, and one end of the DMA data transmission timing processing module is connected to the register access module and the other end is connected to the FIFO; The specific process of online loading is as follows: Flash write: The host computer sends the transmission start signal, the writing length to be sent, the flash write address and the flash write command to the flash control module of the PXI slave device; The host computer transmits binary file data to the PXI slave device in DMA mode and temporarily stores it in FIFO. When the data transmission of writing length is completed, the PXI slave device informs the host computer of interruption. The flash control module controls the fifo to write binary numbers to the flash chip until all the data in the fifo are written into the flash chip by the pxi slave device, and the pxi slave device informs the host computer that the writing is completed; Flash read: The host computer sends the transmission start signal, the reading length to be read, the flash read address and the flash read command to the flash control module of the PXI slave device; The pxi slave device reads the binary number from the flash chip and temporarily stores it in the fifo. When the length of the read data reaches the read length, the pxi slave device informs the host computer that the reading is completed. The PXI slave device transmits the binary number temporarily stored in the FIFO to the host computer in DMA mode. After the transmission is completed, the PXI slave device notifies the host computer of the completion of the transmission in an interrupt mode.

[0020] Example 2 - Flash write On the basis of Example 1, it also includes: The host computer sends a transmission start signal, a writing length to be sent, a flash write address and a flash write command to the flash control module of the pxi slave device through the pci register write; Among them, the specific process of writing the pci register is: The host computer issues a register write command to the address decoding module through the PCI register read and write timing processing module of the transmission engine module, and the address decoding module determines that the recipient is a user function module in the register access module, and the user module is a flash control module; The specific process of the address decoding module determining the recipient is as follows: The address decoding module uses the highest 2 bits in the address bus to perform decoding operations; when the highest 2 bits in the address bus ≠ 2'b00, the access address of the address decoding module is mapped to the user function module in the register access module, and a corresponding enable signal is generated accordingly; The address decoding module transmits the write address, write data and write enable to the register access module, the register access module stores and identifies the write address and write enable, and transmits the write data to the user function module as a corresponding control signal; The host computer transmits the binary file data through the DMA data transmission timing processing module of the transmission engine module and temporarily stores it in the output fifo. The flash control module sends a write command to the flash chip through the SPI timing and controls the output fifo to write binary numbers to the flash chip. After the flash control module writes a page of binary numbers from the output fifo to the flash chip, the flash control module reads the write completion flag in the flash chip through the SPI timing. When the write completion flag is 1, the page data is written successfully; the flash control module takes data from the output fifo and continues to write the next page to the flash chip until the writing length is reached, and all the data in the output fifo is written into the flash chip; the host computer reads the write completion flag under the corresponding address through the PCI register. When the write completion flag is 1, the host computer continues to transmit the binary file data to the output fifo through the DMA data transmission timing processing module of the transmission engine module until all the binary numbers are transmitted; Among them, the specific process of the PCI register reading is: The host computer sends a register read command to the address decoding module through the PCI register read and write timing processing module of the transmission engine module. The address decoding module determines that the recipient is a user function module in the register access module, and the user module is a flash control module.

[0021] Example 3 - Flash Read On the basis of Example 1, it also includes: The host computer sends the transmission start signal, the reading length to be read, the flash read address and the flash read command to the flash control module of the PXI slave device through the PCI register write; Among them, the specific process of writing the pci register is: The host computer issues a register write command to the address decoding module through the PCI register read and write timing processing module of the transmission engine module, and the address decoding module determines that the recipient is a user function module in the register access module, and the user module is a flash control module; The specific process of the address decoding module determining the recipient is as follows: The address decoding module uses the highest 2 bits in the address bus to perform decoding operations; when the highest 2 bits in the address bus ≠ 2'b00, the access address of the address decoding module is mapped to the user function module in the register access module, and a corresponding enable signal is generated accordingly; The address decoding module transmits the read address and the read enable to the register access module, and the register access module stores and identifies the read address and the read enable; The feedback data of the control signal corresponding to the user function module is placed on the PCI bus by the PXI slave device through the register access module to the address decoding module and then to the PCI register read-write timing processing module of the transmission engine module for the host computer to read; The flash control module reads the binary number from the flash chip and temporarily stores it in the input fifo. When the storage data size of the input fifo is consistent with the read length, the input fifo temporary storage is completed. The binary number is read in pages, and each page includes 256 bytes. When the binary number read from the flash chip by the flash control module reaches the read length, all the data of the flash chip are temporarily stored in the input fifo; the host computer reads the read completion flag under the corresponding address through the pci register. When the read completion flag is 1, the host computer continues to read the binary number from the input fifo to the flash chip through the dma data transmission timing processing module of the transmission engine module until all the binary numbers are read.

[0022] Example 4 On the basis of Example 1, it also includes: The writing length and reading length should be integer multiples of a flash page in the flash control module, and if they are insufficient, they should be filled with 0.

[0023] Here are some examples: The size of data to be sent or read back by the host computer should be an integer multiple of a flash page, and the insufficient data should be padded with 0. For example, the size of a binary bin file of a flash configuration that needs to be burned is 2322718 bytes = 9073*256+30, that is, the host computer must add 256-30=226 bits of 0 at the end of the write data sent, and the binary file read back also has 226 0s at the end. The writing length and reading length of the host computer written and read through the PCI bus at one time are integer multiples of 256 and are determined by the size of the memory area currently applied in the DDR of the CPU and the depth of the fifo in the FPGA on the acquisition card. The depth of the fifo is determined by the usage of the FPGA resources in the acquisition board. Currently, the fifo depth is set to 2048 and the bit width is set to 8 bits, that is, 2048 bytes can be stored at a time. From the previous calculation, we can get 9074 / 2048=4...882. In this way, 4+1=5 times are needed to write or read all of them. The writing length and reading length of the first four times are 2048, and the last time is 882.

Claims

1. A method for online flash loading based on PXI, comprising a host computer, a PXI system and a PXI slave device connected in sequence; the PXI slave device has a built-in flash control module, and the flash control module controls a flash chip; characterized in that: The pxi slave device has a built-in pci interface module, and the external pci bus of the pci interface module is connected to the pxi system; then the host computer sequentially controls the pxi system and the pxi slave device and then controls the flash control module to realize online loading; The PCI interface module includes a transmission engine module and a configuration management module, an address decoding module, a register access module and a FIFO respectively connected to the transmission engine module; and also includes a reset management module, the reset management module is respectively connected to the configuration management module, the address decoding module, the register access module and the transmission engine module; the transmission engine module is also connected to an external PCI bus and then connected to an external PCI device; the address decoding module is also connected to the register access module; the FIFO includes an input FIFO and an output FIFO; the input FIFO and the output FIFO are both connected to the transmission engine module; The transmission engine module includes a PCI configuration space timing processing module, a PCI register read and write timing processing module and a DMA data transmission timing processing module; the PCI configuration space timing processing module is connected to the configuration management module, the PCI register read and write timing processing module is connected to the address decoding module, and one end of the DMA data transmission timing processing module is connected to the register access module and the other end is connected to the FIFO; The specific process of online loading is as follows: Flash write: The host computer sends the transmission start signal, the writing length to be sent, the flash write address and the flash write command to the flash control module of the PXI slave device; The host computer transmits binary file data to the PXI slave device in DMA mode and temporarily stores it in FIFO. When the data transmission of the writing length is completed, the PXI slave device informs the host computer of the interrupt; The flash control module controls the fifo to write binary numbers to the flash chip until all the data in the fifo are written into the flash chip by the pxi slave device, and the pxi slave device informs the host computer that the writing is completed; Flash read: The host computer sends the transmission start signal, the reading length to be read, the flash read address and the flash read command to the flash control module of the PXI slave device; The pxi slave device reads the binary number from the flash chip and temporarily stores it in the fifo. When the length of the read data reaches readlength, the pxi slave device informs the host computer that the reading is completed. The PXI slave device transmits the binary number temporarily stored in the FIFO to the host computer in DMA mode. After the transmission is completed, the PXI slave device notifies the host computer of the completion of the transmission in an interrupt mode.

2. The method for online flash loading based on PXI according to claim 1, characterized in that: The host computer sends a transmission start signal, a writing length to be sent, a flash write address and a flash write command to the flash control module of the pxi slave device through the pci register write; The host computer sends the transmission start signal, the reading length to be read, the flash read address and the flash read command to the flash control module of the PXI slave device through the PCI register write; The specific process of writing the pci register is: The host computer sends a register write command to the address decoding module through the PCI register read and write timing processing module of the transmission engine module. The address decoding module determines that the recipient is a user function module in the register access module, and the user module is a flash control module.

3. The method for online flash loading based on PXI according to claim 2, characterized in that: The specific process of the address decoding module determining the recipient is as follows: The address decoding module uses the highest 2 bits in the address bus to perform decoding operations; when the highest 2 bits in the address bus ≠ 2'b00, the access address of the address decoding module is mapped to the user function module in the register access module, and a corresponding enable signal is generated accordingly; The address decoding module transmits the read / write address, write data and enable signal to the register access module, which stores and identifies the read / write address and enable signal. If the host computer issues a register write command to the transmission engine module, the write data is transmitted to the user function module as the corresponding control signal. If it is a register read command, the feedback data of the control signal corresponding to the user function module is sent via the register access module to the address decoding module and then to the PCI register read and write timing processing module of the transmission engine module, and is placed on the PCI bus by the PXI slave device for reading by the host computer.

4. The method for online flash loading based on PXI according to claim 3 is characterized in that: The host computer transmits binary file data through the DMA data transmission timing processing module of the transmission engine module and temporarily stores it in the output fifo. When the storage data size of the output fifo is consistent with the writing length, the output fifo temporary storage is completed; the flash control module reads the binary number from the flash chip and temporarily stores it in the input fifo. When the storage data size of the input fifo is consistent with the read length, the input fifo temporary storage is completed.

5. The method for online flash loading based on PXI according to claim 4 is characterized in that: Also includes: The flash control module sends a write command to the flash chip through the SPI timing and controls the output fifo to write binary numbers to the flash chip; The flash control module sends a read command to the flash chip through the SPI timing and controls the reading of binary numbers from the input fifo to the host computer.

6. The method for online flash loading based on PXI according to claim 5, characterized in that: The written binary number / read binary number is in pages, and each page includes 256 bytes.

7. The method for online flash loading based on PXI according to claim 6, characterized in that: It also includes that after the flash control module writes a page of binary numbers from the output fifo to the flash chip, the flash control module reads the write completion flag in the flash chip through the SPI timing, and when the write completion flag is 1, that is, when the page data is written successfully; the flash control module takes data from the output fifo and continues to write the next page to the flash chip until the writing length is reached, and all the data in the output fifo is written into the flash chip; the host computer reads the write completion flag under the corresponding address through the PCI register, and when the write completion flag is 1, the host computer continues to transmit the binary file data to the output fifo through the DMA data transmission timing processing module of the transmission engine module until all the binary numbers are transmitted; The specific process of the PCI register reading is: The host computer sends a register read command to the address decoding module through the PCI register read and write timing processing module of the transmission engine module. The address decoding module determines that the recipient is a user function module in the register access module, and the user module is a flash control module.

8. The method for online flash loading based on PXI according to claim 7, characterized in that: It also includes that the binary number read from the flash chip by the flash control module reaches the read length, and all the data of the flash chip is temporarily stored in the input fifo; the host computer reads the read completion flag under the corresponding address through the pci register. When the read completion flag is 1, the host computer continues to read the binary number from the input fifo to the flash chip through the dma data transmission timing processing module of the transmission engine module until all the binary numbers are read.

9. The method for online flash loading based on PXI according to claim 8, characterized in that: It also includes, in the pxi slave device, changing the flash pin controlling the flash control module from a dedicated pin to a common pin; Before writing or reading flash, the host computer sends a read flash ID command to the flash control module through register write; the host computer reads back the flash ID received by the flash control module through register read to detect whether the flash is online; before executing the flash write operation when the flash is online, the host computer sends an erase command to the flash control module through register write, and the host computer reads back the erase result through register read; after the erase is completed, the flash write starts.

10. The method for online flash loading based on PXI according to claim 9, characterized in that: Also includes: The writing length and reading length should be integer multiples of a flash page in the flash control module, and if they are insufficient, they should be filled with 0.

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