Processing method and device for register permutation level design
By module division and comprehensive processing of the RTL design of ASIC design, accurate netlists and bitstream files are generated, which solves the problem of waste of resources and timing convergence after modification of RTL design in the traditional verification process, and improves design efficiency and stability .
Patent Information
- Application Number
- CN202411117845.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-14
- Publication Date
- 2024-12-24
AI Technical Summary
After the RTL design modification, the traditional ASIC design prototype verification process requires recompilation, segmentation and system routing of the entire design, resulting in high version iteration time cost, and the comprehensive implementation of FPGA timing convergence is difficult, which is difficult to meet the timing requirements.
By dividing the RTL design modules, generating target modules and comprehensive processing, forming netlists, segmenting and layout and routing, and generating bitstream files, ensuring that the segmentation stage has accurate mapping relationships and timing information, reducing subsequent timing repair needs.
It improves the processing efficiency and timing convergence capability of RTL design, reduces version iteration time, and enhances the stability and reliability of the design.
Smart Images
Figure CN119180241A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a processing method, device, electronic equipment and storage medium for register replacement level design. Background Art
[0002] With the continuous development and iteration of integrated circuit technology, its functions and structures are becoming more and more complex. Traditional front-end verification methods can no longer fully guarantee the effectiveness of ASIC (Application Specific Integrated Circuit) design and meet the needs of collaborative development of corresponding driver software. In this context, the emergence of FPGA (Field Programmable Gate Array) prototype verification platform provides a way to solve the above problems. The platform is designed to equivalently simulate the hardware environment of ASIC design, help ASIC designers improve the stability of the design, and provide a real physical platform for software developers.
[0003] At present, the scale of ASIC design is becoming larger and more complex. Single-chip FPGA can no longer meet the resource requirements of prototype verification. Therefore, the "HAPS prototype verification platform", a product serving multi-chip FPGA verification platform technology, came into being. It can provide ASIC / SOC (System on Chip) designers with a high-performance, high-capacity FPGA-based prototype verification platform, providing designers with more convenience and improving development efficiency.
[0004] In the traditional method, for the prototype verification of large-scale chips, the specific processing flow is as follows: Figure 1 As shown:
[0005] Step 1: Input RTL design. The design source file can be the same as the ASIC source file or modified and replaced from the ASIC source file.
[0006] Step 2: Pre-test. Add RTL debug test.
[0007] Step 3: Compile. In this stage, the input files will be verified and the design will be compiled. Usually, the unified compilation mode is used to compile the RTL in the VCS.
[0008] Step 4: Pre-segmentation. Read in the constraint files Timing Constraints (FDC) and Target System Spec (TTS). The .fdc file is the timing constraint file, and the .tss file is the HAPS platform configuration file, such as clock source, cable connection, external daughter board type and location. Run resource assessment to prepare for segmentation by properly handling issues such as direct-through, duplicate outputs, unconnected or unloaded top-level input ports. This step takes a long time.
[0009] Step 5: Partition. Read in the constraint files Target System Spec (TSS) and Partition Constraints (PCF). The .pcf file sets the partition constraints, such as pin location, cell allocation, and partition strategy control. Partitioning is an iterative process, in which the results will be continuously improved until they meet the requirements, such as no Unrouted (unable to route) and Cut Clock (cross clock).
[0010] Step 6: System routing. Perform system routing between each FPGA. At this stage, the tool assigns the network between FPGAs to the HAPS board routing and performs time domain multiplexing as needed.
[0011] Step 7: System generation: Generate relevant files at the single FPGA system level according to the partitioning scheme.
[0012] Step 8: Synthesis, layout, and routing. For Single FPGAs, map the logic design to a specific FPGA chip, generate a netlist file corresponding to the design, and complete the layout and routing of each FPGA.
[0013] Step 9: Generate bitstream file and related configuration files.
[0014] However, the above process has the following problems:
[0015] 1) The processing object of the compilation stage is the entire RTL design. If the RTL design needs to be modified, no matter how large the scope of the change is, the subsequent steps need to be run based on the entire RTL design. When running to the pre-segmentation, segmentation, system wiring and generation stages, it is often necessary to continue trying until the results meet the requirements. This increases the time cost of version iteration and reduces the efficiency of version production.
[0016] 2) In the traditional process, FPGA synthesis is implemented at the end. At this time, the partitioning scheme has been determined, but the specific logic mapping relationship still needs to be obtained through synthesis. Therefore, the partitioning scheme at this time does not have accurate mapping relationships and timing information, and its feasibility is inevitably lacking. This increases the difficulty of FPGA timing convergence, and manual timing repair is required in the later stage. If the timing convergence cannot be met, it may even be necessary to re-segment. Summary of the invention
[0017] In view of the above problems, embodiments of the present invention are proposed to provide a register permutation level design processing method, device, electronic device and storage medium that overcome the above problems or at least partially solve the above problems.
[0018] In a first aspect, an embodiment of the present invention discloses a method for processing register permutation level design, the method comprising:
[0019] In response to a processing instruction for a register permutation level RTL design to be processed, partitioning the RTL design to obtain at least one target module;
[0020] Performing comprehensive processing on each of the target modules to obtain a first netlist corresponding to each of the target modules;
[0021] Combining the first netlists to obtain a top-level netlist;
[0022] Segmenting the top-level netlist to obtain at least one second netlist;
[0023] Performing layout and routing on each of the second netlists, and generating at least one corresponding bitstream file;
[0024] A configuration file corresponding to the RTL design is generated based on each bitstream file.
[0025] Optionally, dividing the RTL design to obtain at least one target module includes:
[0026] Filtering all modules in the RTL design to determine at least one first candidate module having a clock domain;
[0027] Divide each of the first candidate modules according to the type of the clock domain to obtain at least one second candidate module and at least one third candidate module; wherein the type of the clock domain of the second candidate module is a simultaneous clock domain, and the type of the clock domain of the third candidate module is a cross-clock domain;
[0028] Divide each of the second candidate modules based on the clock frequency to obtain at least one fourth candidate module, at least one fifth candidate module and at least one sixth candidate module; wherein the highest clock frequency of the fourth candidate module is less than a highest clock frequency threshold and not less than two-thirds of the highest clock frequency threshold, the highest clock frequency of the fifth candidate module is less than two-thirds of the highest clock frequency threshold and not less than one-third of the highest clock frequency threshold, and the highest clock frequency of the sixth candidate module is less than one-third of the highest clock frequency threshold;
[0029] The fourth candidate modules are divided based on the reuse rate to obtain at least one seventh candidate module and at least one eighth candidate module, and the fifth candidate modules are divided to obtain at least one ninth candidate module and at least one tenth candidate module, and the sixth candidate modules are divided to obtain at least one eleventh candidate module and at least one twelfth candidate module; wherein the reuse rates of the seventh candidate module, the ninth candidate module and the eleventh candidate module exceed the reuse rate threshold, and the reuse rates of the eighth candidate module, the tenth candidate module and the twelfth candidate module do not exceed the reuse rate threshold;
[0030] Based on the data flow, each of the seventh candidate modules, each of the eighth candidate modules, each of the ninth candidate modules, each of the tenth candidate modules, each of the eleventh candidate modules and each of the twelfth candidate modules are divided respectively to obtain at least one first target module.
[0031] Optionally, also include:
[0032] The third candidate modules are divided based on the reuse rate to obtain at least one thirteenth candidate module and at least one fourteenth candidate module; wherein the reuse rate of the thirteenth candidate module exceeds the reuse rate threshold, and the reuse rate of the fourteenth candidate module does not exceed the reuse rate threshold;
[0033] The thirteenth candidate modules and the fourteenth candidate modules are divided based on the data stream to obtain at least one second target module.
[0034] Optionally, combining the first netlists to obtain a top-level netlist includes:
[0035] Creating a blank netlist and setting the blank netlist as the top layer;
[0036] Based on the hierarchical structure of each of the first netlists, each of the first netlists is filled into the blank netlist to obtain a top-level netlist.
[0037] Optionally, the dividing the top-level netlist to obtain at least one second netlist includes:
[0038] The top-level netlist is segmented according to the characteristics of each field programmable gate array FPGA to obtain at least one second netlist; wherein the number of the FPGAs is the same as the number of the second netlists, any one of the second netlists includes at least one of the first netlists, and any two of the second netlists do not include the same first netlist.
[0039] Optionally, also include:
[0040] Obtaining a modification instruction for any one of the target modules;
[0041] If the modification instruction is used to modify the data interaction interface of any one of the target modules, the processing instruction is triggered and jumps to the processing instruction in response to the register replacement level RTL design to be processed, and the RTL design is divided to obtain the step of obtaining at least one target module.
[0042] Optionally, also include:
[0043] If the modification instruction is not used to modify the data interaction interface of any one of the target modules, performing comprehensive processing on the any one of the target modules to obtain a third netlist;
[0044] The top-level netlist is updated by using the third netlist to obtain an updated top-level netlist, and the process jumps to the step of segmenting the top-level netlist to obtain at least one second netlist for the updated top-level netlist.
[0045] In a second aspect, an embodiment of the present invention discloses a processing device for register permutation level design, the device comprising:
[0046] A partitioning module, configured to partition the register replacement level RTL design to be processed in response to a processing instruction for the RTL design to be processed, to obtain at least one target module;
[0047] A synthesis module, used for performing synthesis processing on each of the target modules to obtain a first netlist corresponding to each of the target modules;
[0048] A combination module, used for combining the first netlists to obtain a top-level netlist;
[0049] A segmentation module, used for segmenting the top-level netlist to obtain at least one second netlist;
[0050] An implementation module, used for performing layout and routing on each of the second netlists;
[0051] The generation module is used to generate at least one corresponding bit stream file, and generate a configuration file corresponding to the RTL design based on each bit stream file.
[0052] In a third aspect, the present invention further discloses an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the processing method of the register permutation level design as described above are implemented.
[0053] In a fourth aspect, the present invention further discloses a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the processing method for register permutation level design as described above.
[0054] The embodiments of the present invention include the following advantages:
[0055] In response to the processing instruction for the register replacement level RTL design to be processed, the RTL design is divided to obtain at least one target module; each of the target modules is subjected to comprehensive processing to obtain a first netlist corresponding to each of the target modules; each of the first netlists is combined to obtain a top-level netlist; the top-level netlist is segmented to obtain at least one second netlist; each of the second netlists is laid out and wired, and at least one corresponding bitstream file is generated; and a configuration file corresponding to the RTL design is generated based on each bitstream file. In the above manner, before the segmentation stage, a netlist has been generated with relatively accurate mapping relationships and timing information, so that when the new netlist is subsequently segmented, the segmentation result is more in line with the actual situation, which is beneficial to the subsequent timing convergence.
[0056] Moreover, segmenting the top-level netlist according to the characteristics of the FPGA not only makes the segmentation results more in line with the actual situation and is beneficial to the subsequent timing convergence, but also no longer strictly follows the pre-segmentation-segmentation process in the traditional method, but directly runs the segmentation, thereby improving processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0057] Figure 1 This is a flow chart of the prototype verification process for larger-scale chips in the traditional method;
[0058] Figure 2 is a flowchart of a processing method for register replacement level design provided by an embodiment of the present invention;
[0059] Figure 3 It is a schematic diagram of module division of RTL design provided by an embodiment of the present invention;
[0060] Figure 4is a schematic diagram of a top-level netlist and its segmentation provided by an embodiment of the present invention;
[0061] Figure 5 It is a schematic diagram of the processing flow of RTL design provided by an embodiment of the present invention;
[0062] Figure 6 is a flowchart of another method for processing register replacement level design provided by an embodiment of the present invention;
[0063] Figure 7 is a structural block diagram of an electronic device provided by an embodiment of the present invention;
[0064] Figure 8 It is a structural block diagram of a computer-readable storage medium provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0065] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0066] like Figure 2 , shows a flowchart of a method for processing register permutation level design provided by an embodiment of the present invention, which can be applied to an application, platform or system capable of processing RTL design. The method may include the following steps:
[0067] Step 201 : In response to a processing instruction for a register permutation level RTL design to be processed, partition the RTL design to obtain at least one target module.
[0068] Since the complete RTL design includes multiple modules, after obtaining the RTL design to be processed, the RTL design can be divided to determine the modules (for the convenience of description, recorded as "target modules"). When dividing the RTL design, the division can be performed according to a certain attribute of the module. However, since some modules do not have this attribute, when dividing the RTL design, there is no need to process these modules, and the modules with this attribute in the RTL design can be divided.
[0069] In an embodiment of the present invention, dividing the RTL design to obtain at least one target module includes:
[0070] Filtering all modules in the RTL design to determine at least one first candidate module having a clock domain;
[0071] Divide each of the first candidate modules according to the type of the clock domain to obtain at least one second candidate module and at least one third candidate module; wherein the type of the clock domain of the second candidate module is a simultaneous clock domain, and the type of the clock domain of the third candidate module is a cross-clock domain;
[0072] Divide each of the second candidate modules based on the clock frequency to obtain at least one fourth candidate module, at least one fifth candidate module and at least one sixth candidate module; wherein the highest clock frequency of the fourth candidate module is less than a highest clock frequency threshold and not less than two-thirds of the highest clock frequency threshold, the highest clock frequency of the fifth candidate module is less than two-thirds of the highest clock frequency threshold and not less than one-third of the highest clock frequency threshold, and the highest clock frequency of the sixth candidate module is less than one-third of the highest clock frequency threshold;
[0073] The fourth candidate modules are divided based on the reuse rate to obtain at least one seventh candidate module and at least one eighth candidate module, and the fifth candidate modules are divided to obtain at least one ninth candidate module and at least one tenth candidate module, and the sixth candidate modules are divided to obtain at least one eleventh candidate module and at least one twelfth candidate module; wherein the reuse rates of the seventh candidate module, the ninth candidate module and the eleventh candidate module exceed the reuse rate threshold, and the reuse rates of the eighth candidate module, the tenth candidate module and the twelfth candidate module do not exceed the reuse rate threshold;
[0074] Based on the data flow, each of the seventh candidate modules, each of the eighth candidate modules, each of the ninth candidate modules, each of the tenth candidate modules, each of the eleventh candidate modules and each of the twelfth candidate modules are divided respectively to obtain at least one first target module.
[0075] Specifically, when dividing the RTL design, each module in the RTL design may be filtered first, and modules without clock domains may be filtered out to obtain at least one module with a clock domain (referred to as a "first candidate module").
[0076] The types of clock domains include simultaneous clock domains and cross-clock domains, so each first candidate module can be divided into at least one module of the simultaneous clock domain type (recorded as a "second candidate module") and at least one module of the cross-clock domain type (recorded as a "third candidate module").
[0077] In the simultaneous clock domain, the clock frequency can be divided into three categories: high frequency, medium frequency and low frequency. Therefore, for each second candidate module, it can be divided into a high frequency module (recorded as "fourth candidate module"), a medium frequency module (recorded as "fifth candidate module") and a low frequency module (recorded as "sixth candidate module"). Among them, the highest clock frequency of the high frequency module is less than the highest clock frequency threshold, and not less than two-thirds of the highest clock frequency threshold, the highest clock frequency of the medium frequency module is less than two-thirds of the highest clock frequency threshold, and not less than one-third of the highest clock frequency threshold, and the highest clock frequency of the low frequency module is less than one-third of the highest clock frequency threshold.
[0078] It should be noted that, in addition to the above-mentioned values, other values may be used for the specific values of high frequency, medium frequency and low frequency divided according to the clock frequency. In practical applications, they can be adjusted according to actual needs, and the embodiments of the present invention do not limit this.
[0079] Because some modules have single and clear functions, simple interfaces and configurable parameters, the reuse rate of these modules is high. Similarly, because some modules are configured for a certain dedicated interface or function, the reuse rate is low and even cannot be reused. Therefore, the fourth candidate module can be divided according to the reuse rate to obtain at least one module with a higher reuse rate (recorded as "the seventh candidate module") and at least one module with a lower reuse rate (recorded as "the eighth candidate module"), the fifth candidate module can be divided to obtain at least one module with a higher reuse rate (recorded as "the ninth candidate module") and at least one module with a lower reuse rate (recorded as "the tenth candidate module"), and the sixth candidate module can be divided to obtain at least one module with a higher reuse rate (recorded as "the eleventh candidate module") and at least one module with a lower reuse rate (recorded as "the twelfth candidate module"). Wherein, the reuse rate of the module with a higher reuse rate exceeds the reuse rate threshold, and the reuse rate of the module with a lower reuse rate does not exceed the reuse rate threshold.
[0080] Finally, the seventh candidate modules are divided according to the data flow to obtain the final division result, for example, the input module, the output module, the control module and the storage module are obtained by division. Similarly, the eighth candidate modules, the ninth candidate modules, the tenth candidate modules, the eleventh candidate modules and the twelfth candidate modules are divided to obtain the final division result, that is, the modules after division (recorded as "first target modules").
[0081] In an embodiment of the present invention, it also includes:
[0082] The third candidate modules are divided based on the reuse rate to obtain at least one thirteenth candidate module and at least one fourteenth candidate module; wherein the reuse rate of the thirteenth candidate module exceeds the reuse rate threshold, and the reuse rate of the fourteenth candidate module does not exceed the reuse rate threshold;
[0083] The thirteenth candidate modules and the fourteenth candidate modules are divided based on the data stream to obtain at least one second target module.
[0084] Specifically, since the cross-clock domain can use set_false or set_clock_groups constraints to completely ignore the timing analysis of the cross-clock domain path, or use set_max_delay-datapath_only for partial analysis, it is not necessary to consider dividing according to the clock frequency under the cross-clock domain. Therefore, for each third candidate module, it can be divided according to the reuse rate to obtain at least one module with a high reuse rate (recorded as the "thirteenth candidate module") and at least one module with a low reuse rate (recorded as the "fourteenth candidate module"). Among them, the reuse rate of the module with a higher reuse rate exceeds the reuse rate threshold, and the reuse rate of the module with a lower reuse rate does not exceed the reuse rate threshold.
[0085] Then, each thirteenth candidate module and each fourteenth candidate module are divided according to the data flow to obtain a final division result, that is, each module after division (recorded as a “second target module”).
[0086] For ease of understanding, combined Figure 3 An example is given to illustrate the module division of RTL design. Figure 3 The schematic diagram of module division of RTL design is shown. Specifically, for the complete RTL design, the modules without clock domains (not shown in the figure) are filtered out to obtain at least one module with clock domains, and then each module is divided according to the type of clock domain to obtain at least one module with the same clock domain and at least one module across clock domains.
[0087] Each module in the simultaneous clock domain is divided according to the clock frequency to obtain at least one high-frequency module, at least one medium-frequency module and at least one low-frequency module.
[0088] Each high-frequency module is divided according to the reuse rate to obtain at least one module with a high reuse rate and at least one module with a low reuse rate.
[0089] For each high-reuse rate module, division is performed according to the data flow to obtain at least one input module, at least one output module, at least one control module and at least one storage module.
[0090] Similarly, the division of other modules can be completed. In this way, before the RTL design is integrated, the RTL design is divided into multiple modules. When the RTL design is subsequently updated, the module can be updated, which not only improves the reuse rate of the module, but also reduces the time required to update the RTL design and improves the processing efficiency.
[0091] Step 202, performing comprehensive processing on each of the target modules to obtain a first netlist corresponding to each of the target modules.
[0092] After obtaining each target module (including the "first target module" and the "second target module"), each target module can be synthesized to obtain the netlist corresponding to each target module (referred to as the "first netlist"). For example, after the RTL design is divided, the target modules RTL1, RTL2, RTL3 and RTL4 are obtained, and RTL1, RTL2, RTL3 and RTL4 are synthesized to obtain the corresponding netlists Netlist1, Netlist2, Netlist3 and Netlist4, that is, RTL1 corresponds to Netlist1, RTL2 corresponds to Netlist2, RTL3 corresponds to Netlist3, and RTL4 corresponds to Netlist4.
[0093] Step 203: combine the first netlists to obtain a top-level netlist.
[0094] After obtaining each first netlist, each first netlist can be combined according to the hierarchical structure of each first netlist to obtain a top-level netlist. Since each first netlist is obtained by comprehensive processing of each target module, the hierarchical structure of each first netlist is also the hierarchical structure of each target module.
[0095] In the embodiment of the present invention, the combining of the first netlists to obtain a top-level netlist includes:
[0096] Creating a blank netlist and setting the blank netlist as the top layer;
[0097] Based on the hierarchical structure of each of the first netlists, each of the first netlists is filled into the blank netlist to obtain a top-level netlist.
[0098] Specifically, after obtaining each first netlist, a blank netlist can be created according to the number of first netlists, and the blank netlist can be set as the top layer, and then each first netlist is filled into the blank netlist according to the corresponding hierarchical structure, so as to obtain the top layer netlist. In this way, each first netlist is recombined through the hierarchical structure of each first netlist to generate a new netlist, and the new netlist has a more accurate mapping relationship and timing information, so that when the new netlist is subsequently segmented, the segmentation result is more in line with the actual situation, which is beneficial to the subsequent timing convergence.
[0099] Step 204: segment the top-level netlist to obtain at least one second netlist.
[0100] After obtaining the top-level netlist, the top-level netlist can be segmented to obtain at least one netlist (referred to as the "second netlist"). During segmentation, segmentation can be performed based on the characteristics of the currently used FPGA (Field Programmable Gate Array), for example, segmentation can be performed based on the number and model of the currently used FPGA. Of course, in actual applications, the specific characteristics required for segmentation can be set according to actual needs, and the embodiment of the present invention does not limit this.
[0101] In an embodiment of the present invention, the step of segmenting the top-level netlist to obtain at least one second netlist includes:
[0102] The top-level netlist is segmented according to the characteristics of each field programmable gate array FPGA to obtain at least one second netlist; wherein the number of the FPGAs is the same as the number of the second netlists, any one of the second netlists includes at least one of the first netlists, and any two of the second netlists do not include the same first netlist.
[0103] Specifically, when the top-level netlist is segmented, it can be segmented according to the characteristics of each FPGA to obtain a second netlist corresponding to each FPGA, that is, the number of FPGAs is the same as the number of second netlists. Moreover, since multiple first netlists may correspond to the characteristics of the same FPGA, a second netlist may include multiple first netlists, and any two second netlists do not include the same first netlist.
[0104] For example, after the top-level netlist is divided according to the characteristics of FPGA 1, FPGA 2, FPGA 3, and FPGA 4, the second netlists Netlist a, Netlist b, Netlist c, and Netlist d are obtained. FPGA 1 corresponds to Netlist a, FPGA 2 corresponds to Netlist b, FPGA 3 corresponds to Netlist c, and FPGA 4 corresponds to Netlist d. FPGA 1 has more block RAMs, and the Netlist 1 area in the top-level netlist also uses more block RAMs. Therefore, the Netlist 1 area can be divided into Netlist a together with other areas in the top-level netlist that match the characteristics of FPGA 1, corresponding to FPGA 1; FPGA 2 integrates specific high-speed transceivers, and the Netlist 2 area in the top-level netlist also uses high-speed interfaces. Therefore, the Netlist 2 area can be divided into Netlist b together with other areas in the top-level netlist that match the characteristics of FPGA 2, corresponding to FPGA 2.
[0105] For ease of understanding, combined Figure 4 An example of the top-level netlist and its partitioning is given. Figure 4 The schematic diagram of the top-level netlist and its segmentation is shown. Specifically, the top-level netlist includes the first netlists such as "N in1", "N mem2", "N con2", "N 1", "N n", ..., "N in7", "N 12", "N out2", "N mem1", "N out5", "N 3", and "N GTX". During segmentation, "N mem1" and "N in7" are segmented to obtain Netlist a, corresponding to FPGA 1; "Nout5" and "N GTX" are segmented to obtain Netlist b, corresponding to FPGA 2; "N in1" and "N 12" are segmented to obtain Netlist c, corresponding to FPGA 3; "N n" and "N mem2" are segmented to obtain Netlist d, corresponding to FPGA 4; "N 3" and "N out2" are segmented to obtain Netlist n, corresponding to FPGA n.
[0106] Through the above method, the top-level netlist is divided into multiple second netlists according to the characteristics of the FPGA, which not only makes the result of the division more in line with the actual situation and is beneficial to the subsequent timing convergence, but also no longer strictly follows the pre-division-division process in the traditional method, but directly runs the division, thereby improving processing efficiency.
[0107] Step 205 , performing layout and routing on each of the second netlists, and generating at least one corresponding bitstream file.
[0108] After obtaining each second netlist, each second netlist can be placed and routed to complete FPGA implementation, and then a bitstream file corresponding to each FPGA is generated.
[0109] Step 206: Generate a configuration file corresponding to the RTL design based on each bitstream file.
[0110] After obtaining each bitstream file, each bitstream file can be used to generate a configuration file corresponding to the RTL design.
[0111] For ease of understanding, combined Figure 5 The complete processing of RTL design is illustrated by example. Figure 5 The processing flow diagram of RTL design is shown. Specifically, the complete RTL design is divided to obtain various target modules: RTL 1 (Module 1), RTL 2 (Module 2), RTL input1 (Module input1), RTL input2 (Module input2), RTLmemory1 (Module memory1), RTL memory2 (Module memory2), ..., RTL n (Module n).
[0112] Then each target module is synthesized to obtain each netlist: Netlist 1, Netlist 2, Netlistinput1, Netlist input2, Netlist memory1, Netlist memory2, ..., Netlist n.
[0113] The netlists are combined to obtain the top-netlist Top-Netlist, and then the top-netlist is divided to obtain the netlists: Netlist a (corresponding to FPGA a), Netlist b (corresponding to FPGA b), Netlist c (corresponding to FPGA c), ..., Netlist n (corresponding to FPGA n).
[0114] Perform layout and routing on each netlist and generate corresponding bitstream files: a.bit, b.bit, c.bit, ..., n.bit. Generate configuration files corresponding to the RTL design based on each bitstream file.
[0115] In an embodiment of the present invention, in response to a processing instruction for a register replacement level RTL design to be processed, the RTL design is divided to obtain at least one target module; each of the target modules is subjected to comprehensive processing to obtain a first netlist corresponding to each of the target modules; each of the first netlists is combined to obtain a top-level netlist; the top-level netlist is segmented to obtain at least one second netlist; each of the second netlists is laid out and routed, and at least one corresponding bitstream file is generated; and a configuration file corresponding to the RTL design is generated based on each bitstream file. In the above manner, before the segmentation stage, a netlist has been generated with relatively accurate mapping relationships and timing information, so that when the new netlist is subsequently segmented, the segmentation result is more in line with the actual situation, which is beneficial to the subsequent timing convergence.
[0116] Moreover, segmenting the top-level netlist according to the characteristics of the FPGA not only makes the segmentation results more in line with the actual situation and is beneficial to the subsequent timing convergence, but also no longer strictly follows the pre-segmentation-segmentation process in the traditional method, but directly runs the segmentation, thereby improving processing efficiency.
[0117] like Figure 6 , shows a flowchart of another method for processing register permutation level design provided by an embodiment of the present invention, which can be applied to an application, platform or system capable of processing RTL design. The method may include the following steps:
[0118] Step 601, in response to a processing instruction for a register permutation level RTL design to be processed, partitioning the RTL design to obtain at least one target module;
[0119] Step 602, performing comprehensive processing on each of the target modules to obtain a first netlist corresponding to each of the target modules;
[0120] Step 603, combining the first netlists to obtain a top-level netlist;
[0121] Step 604, segmenting the top-level netlist to obtain at least one second netlist;
[0122] Step 605, performing layout and routing on each of the second netlists, and generating at least one corresponding bitstream file;
[0123] Step 606: Generate a configuration file corresponding to the RTL design based on each bitstream file.
[0124] Among them, steps 601 to 606 are substantially the same as steps 101 to 106, and will not be described here for avoiding repetition.
[0125] Step 607, obtaining a modification instruction for any one of the target modules;
[0126] Step 608, if the modification instruction is used to modify the data interaction interface of any one of the target modules, the processing instruction is triggered, and the process jumps to the processing instruction in response to the register replacement level RTL design to be processed, and the RTL design is divided to obtain at least one target module.
[0127] Specifically, when a modification instruction for any one of all target modules is obtained, if the modification instruction is used to modify the data interaction interface in the any one of the target modules, it means that the entire RTL design needs to be reprocessed. Therefore, the processing instruction in step 601 can be triggered, and the process jumps to step 601 to reprocess the entire RTL design.
[0128] Step 609, if the modification instruction is not used to modify the data interaction interface of any one of the target modules, then perform comprehensive processing on the any one of the target modules to obtain a third netlist;
[0129] Step 610: Use the third netlist to update the top-level netlist to obtain an updated top-level netlist, and jump to the step of segmenting the top-level netlist to obtain at least one second netlist for the updated top-level netlist.
[0130] Specifically, if the modification instruction is not used to modify the data interaction interface in any one of the target modules, that is, to modify the parameters other than the data interaction interface, then it means that there is no need to reprocess the entire RTL design, and only the any one of the target modules needs to be reprocessed, and other target modules do not need to be modified. Therefore, the any one of the target modules is modified to obtain the modified target module, and the modified target module is synthesized to obtain the corresponding netlist (recorded as the "third netlist").
[0131] Then, the third netlist is used to update the top netlist, that is, the third netlist is combined with the other second netlists to obtain an updated top netlist. For the updated top netlist, the process jumps to step 604 to continue.
[0132] In an embodiment of the present invention, after obtaining the modification instruction, it can be determined whether the entire RTL design needs to be reprocessed. If reprocessing is not required, then the target module corresponding to the modification instruction is modified, and other target modules can be reused, which not only reduces resource consumption but also greatly improves modification efficiency.
[0133] The present invention also provides a processing device for register permutation level design, the device comprising:
[0134] A partitioning module, configured to partition the register replacement level RTL design to be processed in response to a processing instruction for the RTL design to be processed, to obtain at least one target module;
[0135] A synthesis module, used for performing synthesis processing on each of the target modules to obtain a first netlist corresponding to each of the target modules;
[0136] A combination module, used for combining the first netlists to obtain a top-level netlist;
[0137] A segmentation module, used for segmenting the top-level netlist to obtain at least one second netlist;
[0138] An implementation module, used for performing layout and routing on each of the second netlists;
[0139] The generation module is used to generate at least one corresponding bit stream file, and generate a configuration file corresponding to the RTL design based on each bit stream file.
[0140] In the embodiment of the present invention, the division module is specifically used to:
[0141] Filtering all modules in the RTL design to determine at least one first candidate module having a clock domain;
[0142] Divide each of the first candidate modules according to the type of the clock domain to obtain at least one second candidate module and at least one third candidate module; wherein the type of the clock domain of the second candidate module is a simultaneous clock domain, and the type of the clock domain of the third candidate module is a cross-clock domain;
[0143] Divide each of the second candidate modules based on the clock frequency to obtain at least one fourth candidate module, at least one fifth candidate module and at least one sixth candidate module; wherein the highest clock frequency of the fourth candidate module is less than a highest clock frequency threshold and not less than two-thirds of the highest clock frequency threshold, the highest clock frequency of the fifth candidate module is less than two-thirds of the highest clock frequency threshold and not less than one-third of the highest clock frequency threshold, and the highest clock frequency of the sixth candidate module is less than one-third of the highest clock frequency threshold;
[0144] The fourth candidate modules are divided based on the reuse rate to obtain at least one seventh candidate module and at least one eighth candidate module, and the fifth candidate modules are divided to obtain at least one ninth candidate module and at least one tenth candidate module, and the sixth candidate modules are divided to obtain at least one eleventh candidate module and at least one twelfth candidate module; wherein the reuse rates of the seventh candidate module, the ninth candidate module and the eleventh candidate module exceed the reuse rate threshold, and the reuse rates of the eighth candidate module, the tenth candidate module and the twelfth candidate module do not exceed the reuse rate threshold;
[0145] Based on the data flow, each of the seventh candidate modules, each of the eighth candidate modules, each of the ninth candidate modules, each of the tenth candidate modules, each of the eleventh candidate modules and each of the twelfth candidate modules are divided respectively to obtain at least one first target module.
[0146] In the embodiment of the present invention, the division module is further used for:
[0147] The third candidate modules are divided based on the reuse rate to obtain at least one thirteenth candidate module and at least one fourteenth candidate module; wherein the reuse rate of the thirteenth candidate module exceeds the reuse rate threshold, and the reuse rate of the fourteenth candidate module does not exceed the reuse rate threshold;
[0148] The thirteenth candidate modules and the fourteenth candidate modules are divided based on the data stream to obtain at least one second target module.
[0149] In the embodiment of the present invention, the combination module is specifically used for:
[0150] Creating a blank netlist and setting the blank netlist as the top layer;
[0151] Based on the hierarchical structure of each of the first netlists, each of the first netlists is filled into the blank netlist to obtain a top-level netlist.
[0152] In the embodiment of the present invention, the segmentation module is specifically used for:
[0153] The top-level netlist is segmented according to the characteristics of each field programmable gate array FPGA to obtain at least one second netlist; wherein the number of the FPGAs is the same as the number of the second netlists, any one of the second netlists includes at least one of the first netlists, and any two of the second netlists do not include the same first netlist.
[0154] In an embodiment of the present invention, it also includes:
[0155] An acquisition module, used for acquiring a modification instruction for any one of the target modules;
[0156] A trigger module is used to trigger the processing instruction and call the partitioning module if the modification instruction is used to modify the data interaction interface of any one of the target modules.
[0157] In an embodiment of the present invention, it also includes:
[0158] The synthesis module is further configured to perform synthesis processing on any one of the target modules to obtain a third netlist if the modification instruction is not used to modify the data interaction interface of any one of the target modules;
[0159] An updating module is used to update the top-level netlist by using the third netlist to obtain an updated top-level netlist, and to call the segmentation module for the updated top-level netlist.
[0160] like Figure 7 , showing a structural block diagram of an electronic device 70 provided in an embodiment of the present invention, including:
[0161] A processor 701, a memory 702, and a computer program 7021 stored in the memory 702 and capable of running on the processor 701. When the computer program 7021 is executed by the processor 701, each process of the processing method embodiment of the above-mentioned register replacement level design is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0162] like Figure 8 , shows a structural block diagram of a computer-readable storage medium 80 provided in an embodiment of the present invention. A computer program 801 is stored on the computer-readable storage medium 80. When the computer program 801 is executed by the processor, each process of the processing method embodiment of the above-mentioned register replacement level design is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0163] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0164] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
[0165] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0166] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0167] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0168] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0169] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.
[0170] The above is a detailed introduction to the processing method, device, electronic device and storage medium for register replacement level design provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A method for processing register permutation level design, characterized in that: The method comprises: In response to a processing instruction for a register permutation level RTL design to be processed, partitioning the RTL design to obtain at least one target module; Performing comprehensive processing on each of the target modules to obtain a first netlist corresponding to each of the target modules; combining each of the first netlists to obtain a top-level netlist; Segmenting the top-level netlist to obtain at least one second netlist; Performing layout and routing on each of the second netlists, and generating at least one corresponding bitstream file; A configuration file corresponding to the RTL design is generated based on each bitstream file.
2. The register permutation level design processing method according to claim 1, characterized in that: The step of dividing the RTL design to obtain at least one target module includes: Filtering all modules in the RTL design to determine at least one first candidate module having a clock domain; Divide each of the first candidate modules according to the type of the clock domain to obtain at least one second candidate module and at least one third candidate module; wherein the type of the clock domain of the second candidate module is a simultaneous clock domain, and the type of the clock domain of the third candidate module is a cross-clock domain; Divide each of the second candidate modules based on the clock frequency to obtain at least one fourth candidate module, at least one fifth candidate module and at least one sixth candidate module; wherein the highest clock frequency of the fourth candidate module is less than a highest clock frequency threshold and not less than two-thirds of the highest clock frequency threshold, the highest clock frequency of the fifth candidate module is less than two-thirds of the highest clock frequency threshold and not less than one-third of the highest clock frequency threshold, and the highest clock frequency of the sixth candidate module is less than one-third of the highest clock frequency threshold; The fourth candidate modules are divided based on the reuse rate to obtain at least one seventh candidate module and at least one eighth candidate module, and the fifth candidate modules are divided to obtain at least one ninth candidate module and at least one tenth candidate module, and the sixth candidate modules are divided to obtain at least one eleventh candidate module and at least one twelfth candidate module; wherein the reuse rates of the seventh candidate module, the ninth candidate module and the eleventh candidate module exceed the reuse rate threshold, and the reuse rates of the eighth candidate module, the tenth candidate module and the twelfth candidate module do not exceed the reuse rate threshold; Based on the data flow, each of the seventh candidate modules, each of the eighth candidate modules, each of the ninth candidate modules, each of the tenth candidate modules, each of the eleventh candidate modules and each of the twelfth candidate modules are divided respectively to obtain at least one first target module.
3. The register permutation level design processing method according to claim 2, characterized in that: Also includes: The third candidate modules are divided based on the reuse rate to obtain at least one thirteenth candidate module and at least one fourteenth candidate module; wherein the reuse rate of the thirteenth candidate module exceeds the reuse rate threshold, and the reuse rate of the fourteenth candidate module does not exceed the reuse rate threshold; The thirteenth candidate modules and the fourteenth candidate modules are divided based on the data stream to obtain at least one second target module.
4. The register permutation level design processing method according to claim 1, characterized in that: The combining of the first netlists to obtain a top-level netlist includes: Creating a blank netlist and setting the blank netlist as the top layer; Based on the hierarchical structure of each of the first netlists, each of the first netlists is filled into the blank netlist to obtain a top-level netlist.
5. The method for processing register permutation level design according to claim 1, characterized in that: The step of segmenting the top-level netlist to obtain at least one second netlist includes: The top-level netlist is segmented according to the characteristics of each field programmable gate array FPGA to obtain at least one second netlist; wherein the number of the FPGAs is the same as the number of the second netlists, any one of the second netlists includes at least one of the first netlists, and any two of the second netlists do not include the same first netlist.
6. The register permutation level design processing method according to claim 1, characterized in that: Also includes: Obtaining a modification instruction for any one of the target modules; If the modification instruction is used to modify the data interaction interface of any one of the target modules, the processing instruction is triggered and jumps to the processing instruction in response to the register replacement level RTL design to be processed, and the RTL design is divided to obtain the step of obtaining at least one target module.
7. The method for processing register permutation level design according to claim 6, characterized in that: Also includes: If the modification instruction is not used to modify the data interaction interface of any one of the target modules, performing comprehensive processing on the any one of the target modules to obtain a third netlist; The top-level netlist is updated by using the third netlist to obtain an updated top-level netlist, and the process jumps to the step of segmenting the top-level netlist to obtain at least one second netlist for the updated top-level netlist.
8. A processing device for register permutation level design, characterized in that: The device comprises: A partitioning module, configured to partition the register replacement level RTL design to be processed in response to a processing instruction for the RTL design to be processed, to obtain at least one target module; A synthesis module, used for performing synthesis processing on each of the target modules to obtain a first netlist corresponding to each of the target modules; A combination module, used for combining the first netlists to obtain a top-level netlist; A segmentation module, used for segmenting the top-level netlist to obtain at least one second netlist; An implementation module, used for performing layout and routing on each of the second netlists; The generation module is used to generate at least one corresponding bit stream file, and generate a configuration file corresponding to the RTL design based on each bit stream file.
9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the processing method for register permutation level design according to any one of claims 1 to 7 are implemented.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the processing method for register permutation level design according to any one of claims 1 to 7 are implemented.