Display panel and display device

Abstract

The present invention proposes a display panel and a display device, wherein the display panel includes a first substrate, the first substrate includes a display area and a non-display area surrounding the display area, the periphery of the non-display area is provided with a first circular routing, a second circular routing and a third circular routing which are arranged in sequence from the outside to the inside, a first electric field in a first direction and a second electric field in a second direction are alternately established between the first circular routing and the second circular routing, a third electric field in a second direction and a fourth electric field in the first direction are alternately established between the third circular routing and the second circular routing, the electric field strength of the first electric field is not less than the electric field strength of the third electric field, and the electric field strength of the second electric field is greater than the electric field strength of the fourth electric field, and the process of repeatedly adsorbing and discharging electric charges entering the first substrate from the outside is continuously realized, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area, thereby enhancing the electrostatic protection capability and reliability of the display panel.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and in particular relates to a display panel and a display device. Background Art

[0002] Display panels such as OLED and LCD usually use glass as a substrate, and a corresponding display area is set on the substrate. The display area is provided with pixel units composed of thin film transistors, and the pixel units display corresponding image information according to driving signals.

[0003] The generation of static electricity is inevitable during the production and use process. The charge generated by static electricity can damage the thin-film transistor devices and circuits of the panel, thereby reducing the display level of the display and affecting the production yield.

[0004] The existing electrostatic protection measures for display panels are mainly to conduct the charge accumulated on the substrate by attaching a conductive film material on the inner side of the substrate, but it cannot completely prevent external static electricity from entering the display panel, causing the external static electricity to affect the internal circuit. In order to block external static electricity, the usual method is to increase the distance between the outermost trace and the cutting edge of the substrate to reduce the external static electricity entering the outermost trace. However, this method cannot completely prevent external static electricity from entering the interior of the substrate, causing static electricity to affect the internal circuit, and the reliability of electrostatic protection is low. Summary of the invention

[0005] The object of the present invention is to provide a display panel, aiming to solve the problem of low reliability of traditional electrostatic protection methods.

[0006] A first aspect of an embodiment of the present invention provides a display panel, comprising:

[0007] A first substrate, the first substrate comprising a display area and a non-display area surrounding the display area, wherein a first circular routing line, a second circular routing line and a third circular routing line are arranged in sequence from the outside to the inside at the periphery of the non-display area;

[0008] The first looped routing, the second looped routing and the third looped routing are connected to a signal source circuit and receive a clock signal, a first electric field in a first direction and a second electric field in a second direction are alternately established between the first looped routing and the second looped routing, a third electric field in the second direction and a fourth electric field in the first direction are alternately established between the third looped routing and the second looped routing, the first direction is a direction from the non-display area toward the display area, and the first direction and the second direction are opposite in direction;

[0009] At the same time, the direction of the electric field between the first circular routing and the second circular routing is opposite to the direction of the electric field between the third circular routing and the second circular routing, the electric field strength of the first electric field is not less than the electric field strength of the third electric field, and the electric field strength of the second electric field is greater than the electric field strength of the fourth electric field.

[0010] Optionally, the signal source circuit outputs a first clock signal and a second clock signal with opposite polarities and equal amplitudes, the first ring wiring and the third ring wiring are used to receive the first clock signal, and the second ring wiring is used to receive the second clock signal;

[0011] The first spacing is smaller than the second spacing, the first spacing is the spacing between the first circular routing and the second circular routing, and the second spacing is the spacing between the second circular routing and the third circular routing.

[0012] Optionally, the signal source circuit outputs a first clock signal, a second clock signal and a third clock signal, the first ring wiring is used to receive the first clock signal, the second ring wiring is used to receive the second clock signal, the third ring wiring is used to receive the third clock signal, the first clock signal and the third clock signal have the same polarity, and the first clock signal and the second clock signal have opposite polarities;

[0013] The voltage of the high level signal of the first clock signal is not less than the voltage of the high level signal of the third clock signal, and the voltage of the low level signal of the first clock signal is less than the voltage of the low level signal of the third clock signal.

[0014] Optionally, the signal source circuit outputs a first clock signal and a second clock signal with opposite polarities and equal amplitudes;

[0015] The display panel further includes:

[0016] A clock conversion circuit, wherein the clock conversion circuit is arranged in the non-display area, and the clock conversion circuit is respectively connected to the first ring wiring, the second ring wiring, the third ring wiring and the signal source circuit;

[0017] The clock conversion circuit is used to convert the first clock signal and the second clock signal into a third clock signal, a fourth clock signal and a fifth clock signal, the first ring line is used to receive the third clock signal, the second ring line is used to receive the fourth clock signal, the third ring line is used to receive the fifth clock signal, the third clock signal and the fifth clock signal have the same polarity, and the third clock signal and the fourth clock signal have opposite polarity;

[0018] The voltage of the high level signal of the third clock signal is not less than the voltage of the high level signal of the fifth clock signal, and the voltage of the low level signal of the third clock signal is less than the voltage of the low level signal of the fifth clock signal.

[0019] Optionally, the clock conversion circuit includes a first clock signal terminal, a second clock signal terminal, a first electronic switch tube and a second electronic switch tube;

[0020] The first end of the first electronic switch tube and the first clock signal end are respectively connected to the first ring wiring, the first clock signal end is also connected to the control end of the first electronic switch tube, the second end of the first electronic switch tube is connected to the third ring wiring, and the first clock signal end is used to input the first clock signal;

[0021] The first end of the second electronic switch tube is used to input the first voltage signal, the control end of the second electronic switch tube is respectively connected to the second clock signal end and the second ring wiring, the second end of the second electronic switch tube is connected to the third ring wiring, and the second clock signal end is used to input the second clock signal;

[0022] The voltage of the low level signal of the first clock signal is lower than the voltage of the first voltage signal.

[0023] Optionally, the clock conversion circuit includes a first clock signal terminal, a second clock signal terminal, a first electronic switch tube, a second electronic switch tube and a first potential shift circuit;

[0024] The first end of the first electronic switch tube and the first clock signal end are respectively connected to the first ring wiring, the first clock signal end is also respectively connected to the control end of the first electronic switch tube and the input end of the first potential shift circuit, and the first clock signal end is used to input the first clock signal;

[0025] The first end of the second electronic switch tube is connected to the output end of the first potential shift circuit, the control end and the second clock signal end of the second electronic switch tube are respectively connected to the second ring wiring, the second end of the second electronic switch tube is connected to the third ring wiring, and the second clock signal end is used to input the second clock signal;

[0026] The first potential shift circuit is used to perform potential shift on the input first clock signal and output it as a sixth clock signal, the voltage of the high-level signal of the sixth clock signal is greater than the voltage of the high-level signal of the first clock signal, and the voltage of the low-level signal of the sixth clock signal is greater than the voltage of the low-level signal of the first clock signal.

[0027] Optionally, the clock conversion circuit includes a first clock signal terminal, a second clock signal terminal, a first resistor, a third electronic switch tube and a fourth electronic switch tube;

[0028] The first clock signal end is respectively connected to the third ring wiring, the first end of the first resistor and the first end of the third electronic switch tube, the second end of the first resistor is connected to the control end of the third electronic switch tube, the second end of the third electronic switch tube is connected to the first ring wiring, and the first clock signal end is used to input the first clock signal;

[0029] The first end of the fourth electronic switch tube is used to input the second voltage signal, the second end of the fourth electronic switch tube is connected to the first ring line, the control end of the fourth electronic switch tube and the second ring line are respectively connected to the second clock signal end, and the second clock signal end is used to input the second clock signal;

[0030] The voltage of the low level signal of the first clock signal is greater than the voltage of the second voltage signal.

[0031] Optionally, the clock conversion circuit includes a first clock signal terminal, a second clock signal terminal, a first resistor, a third electronic switch tube, a fourth electronic switch tube and a second potential shift circuit;

[0032] The first clock signal end is respectively connected to the third ring wiring, the first end of the first resistor, the first end of the third electronic switch tube and the input end of the second potential shift circuit, the second end of the first resistor is connected to the control end of the third electronic switch tube, the second end of the third electronic switch tube is connected to the first ring wiring, and the first clock signal end is used to input the first clock signal;

[0033] The first end of the fourth electronic switch tube is connected to the output end of the second potential shift circuit, the second end of the fourth electronic switch tube is connected to the first ring wiring, the control end of the fourth electronic switch tube is respectively connected to the second ring wiring and the second clock signal end, and the second clock signal end is used to input the second clock signal;

[0034] The second potential shift circuit is used to perform potential shift on the input first clock signal and output it as a seventh clock signal, the voltage of the high-level signal of the seventh clock signal is lower than the voltage of the high-level signal of the first clock signal, and the voltage of the low-level signal of the seventh clock signal is lower than the voltage of the low-level signal of the first clock signal.

[0035] Optionally, the signal source circuit is arranged in the non-display area.

[0036] A second aspect of an embodiment of the present invention provides a display device, comprising a display panel driving circuit and the display panel as described above, wherein the display panel driving circuit is connected to the display panel.

[0037] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned display panel includes a first substrate, the first substrate includes a display area and a non-display area surrounding the display area, the periphery of the non-display area is provided with a first circular routing, a second circular routing and a third circular routing which are arranged in sequence from the outside to the inside, a first electric field in the first direction and a second electric field in the second direction are alternately established between the first circular routing and the second circular routing, a third electric field in the second direction and a fourth electric field in the first direction are alternately established between the third circular routing and the second circular routing, the electric field strength of the first electric field is not less than the electric field strength of the third electric field, and the electric field strength of the second electric field is greater than the electric field strength of the fourth electric field, and the process of repeatedly adsorbing and discharging charges entering the first substrate from the outside is continuously realized, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area, thereby enhancing the electrostatic protection capability and reliability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0039] Figure 1 A schematic diagram of the structure of a display device provided in Embodiment 1 of the present invention;

[0040] Figure 2 A schematic diagram of a first structure of a display panel provided in Embodiment 1 of the present invention;

[0041] Figure 3 A second structural schematic diagram of a display panel provided in the first embodiment of the present invention;

[0042] Figure 4 A waveform diagram of a clock signal provided in Embodiment 1 of the present invention;

[0043] Figure 5 A schematic diagram of electric field distribution of the first electric field and the third electric field provided in Embodiment 1 of the present invention;

[0044] Figure 6 A schematic diagram of electric field distribution of the second electric field and the fourth electric field provided in Embodiment 1 of the present invention;

[0045] Figure 7A schematic diagram of the structure of a display panel provided in Embodiment 2 of the present invention;

[0046] Figure 8 A schematic diagram of electric field distribution of the first electric field and the third electric field provided in Embodiment 2 of the present invention;

[0047] Fig. 9 A schematic diagram of electric field distribution of the second electric field and the fourth electric field provided in Embodiment 2 of the present invention;

[0048] Fig.10 A schematic diagram of electric field distribution of the second electric field and the fourth electric field provided in Embodiment 3 of the present invention;

[0049] Fig.11 A waveform diagram of a clock signal provided in Embodiment 3 of the present invention;

[0050] Fig.12 A schematic diagram of the structure of a display panel provided in Embodiment 3 of the present invention;

[0051] Fig.13 A schematic diagram of a waveform of a clock signal provided in Embodiment 4 of the present invention;

[0052] Fig.14 A schematic diagram of the structure of a display panel provided in Embodiment 5 of the present invention;

[0053] Fig.15 A schematic diagram of the structure of a display panel provided in Embodiment 6 of the present invention;

[0054] Fig.16 A schematic diagram of the structure of a display panel provided in Embodiment 7 of the present invention;

[0055] Fig.17 This is a schematic diagram of the structure of a display panel provided in Embodiment 8 of the present invention.

[0056] Among them, the reference numerals in the figures are:

[0057] 100, display panel; 200, driving circuit of display panel; 1, first substrate; 2, signal source circuit; 3, clock conversion circuit; 31, first potential shift circuit; 32, second potential shift circuit; 11, display area; 12, non-display area; 121, first loop wiring; 122, second loop wiring; 123, third loop wiring;

[0058] T1, first electronic switch tube; T2, second electronic switch tube; T3, third electronic switch tube; T4, fourth electronic switch tube; R1, first resistor; IN1, first clock signal terminal; IN2, second clock signal terminal;

[0059] CLK1, a first clock signal; CLK2, a second clock signal; CLK3, a third clock signal; CLK4, a fourth clock signal; CLK5, a fifth clock signal; CLK6, a sixth clock signal; CLK7, a seventh clock signal; VGH1, a high level signal of the first clock signal; VGL1, a low level signal of the first clock signal; VGH2, a high level signal of the second clock signal; VGL2, a low level signal of the second clock signal; VGH3, a high level signal of the third clock signal; VGL3, a low level signal of the third clock signal; VGH4, a high level signal of the fourth clock signal; VGL4, a low level signal of the fourth clock signal; VGH5, a high level signal of the fifth clock signal; VGL5, a low level signal of the fifth clock signal;

[0060] X1, first direction; X2, second direction; S1, first spacing; S2, second spacing; E1, electric field strength of the first electric field; E2, electric field strength of the second electric field; E3, electric field strength of the third electric field; E4, electric field strength of the fourth electric field. DETAILED DESCRIPTION

[0061] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0062] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0063] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0064] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0065] Embodiment 1

[0066] A first aspect of an embodiment of the present invention provides a display panel 100. The display panel 100 may be an OLED display panel, an LCD display panel, etc. Figure 1 As shown, the display panel 100 is also connected to a display panel driving circuit 200 to form a display device. The display panel driving circuit 200 is used to output data signals and row scanning signals to the display panel 100 to turn on the display panel 100 row by row and display corresponding image information.

[0067] The display panel 100 includes a first substrate 1 and a second substrate arranged opposite to each other. The first substrate 1 includes a display area 11 and a non-display area 12 surrounding the display area 11. The display area 11 is provided with pixel units, data lines and scan lines arranged in an array. The pixel units are connected to the data lines and the scan lines respectively.

[0068] When the display panel 100 is an OLED display panel, the pixel unit on the first substrate 1 is composed of a light-emitting diode and a pixel driving circuit. The pixel driving circuit is composed of multiple thin-film transistors and capacitors. The pixel driving circuit outputs a driving power supply under the drive of a row scanning signal and a data signal to control the light-emitting diode to light up and display the corresponding image information. The second substrate is packaged with the first substrate 1 by means of frame glue or the like.

[0069] When it is an LCD display panel, the display panel 100 also includes a liquid crystal layer arranged between a first substrate 1 and a second substrate. The first substrate 1 is an array substrate, and the second substrate is a color filter substrate. The pixel unit on the first substrate 1 is composed of a thin film transistor, and a color filter and a common electrode layer are arranged on the second substrate. The pixel unit on the first substrate 1 receives a row scan signal of a corresponding row and a data signal of a corresponding column, and outputs a data signal of corresponding polarity and magnitude under the control of the row scan signal. The data signal and the common electrode voltage of the common electrode layer establish a driving voltage and control the liquid crystal deflection of the liquid crystal layer. A backlight module is also arranged at the corresponding position of the display panel 100. The backlight module provides a backlight source, thereby combining the liquid crystal layer and the color filter of the display panel 100 to display the corresponding image information.

[0070] The driving circuit 200 of the display panel may be disposed outside or inside the display panel 100 and transmits driving signals to the pixel units inside the display panel 100 . The driving signals include row scanning signals, data signals, clock signals, etc.

[0071] The first substrate 1 and the second substrate may be made of light-transmitting materials. In an optional embodiment, the first substrate 1 and the second substrate are glass substrates.

[0072] In order to prevent electrostatic charges from entering the display panel 100, in this embodiment, Figure 2As shown, the periphery of the non-display area 12 of the display panel 100 is provided with a first circular wiring 121, a second circular wiring 122 and a third circular wiring 123 which are arranged sequentially from the outside to the inside;

[0073] The first loop wiring 121, the second loop wiring 122 and the third loop wiring 123 are connected to the signal source circuit 2 and receive the clock signal. A first electric field in the first direction X1 and a second electric field in the second direction X2 are alternately established between the first loop wiring 121 and the second loop wiring 122. A third electric field in the second direction X2 and a fourth electric field in the first direction X1 are alternately established between the third loop wiring 123 and the second loop wiring 122. The first direction X1 is the direction from the non-display area 12 to the display area 11. The first direction X1 and the second direction X2 are opposite in direction.

[0074] At the same time, the direction of the electric field between the first circular routing 121 and the second circular routing 122 is opposite to the direction of the electric field between the third circular routing 123 and the second circular routing 122, the electric field strength E1 of the first electric field is not less than the electric field strength E3 of the third electric field, and the electric field strength E2 of the second electric field is greater than the electric field strength E4 of the fourth electric field.

[0075] In this embodiment, the signal source circuit 2 is used to provide a clock signal for the three ring wirings. The signal source circuit 2 can be shared with a circuit for outputting a clock signal in the driving circuit 200 of the display panel, or can be an additional circuit for outputting a clock signal, such as Figure 2 and Figure 3 As shown, the signal source circuit 2 may be disposed on the first substrate 1 or outside the first substrate 1 .

[0076] In order to reduce the electrostatic charge from directly entering the interior of the first substrate 1 through the signal source circuit 2, in an optional embodiment, the signal source circuit 2 is arranged in the non-display area 12, and is directly connected to the first ring wiring 121, the second ring wiring 122 and the third ring wiring 123, and provides clock signals for the three ring wirings respectively.

[0077] The timing of the clock signals on each ring line is the same, and at the same time, the level polarity of the clock signals on the first ring line 121 and the third ring line 123 is the same, and the level polarity of the clock signals on the first ring line 121 and the second ring line 122 is opposite, for example Figure 4As shown, it is assumed that the first ring line 121 and the third ring line 123 receive the first clock signal CLK1, and the second ring line 122 receives the second clock signal CLK2, that is, when the clock signal on the first ring line 121 is at a high level, the clock signal on the second ring line 122 is at a low level, and the clock signal on the third ring line 123 is at a high level. When the clock signal on the first ring line 121 switches to a low level, the clock signal on the second ring line 122 switches to a high level at the same time, and the clock signal on the third ring line 123 switches to a low level at the same time.

[0078] In the first time period t1, the clock signal on the first loop line 121 is at a high level, the clock signal on the second loop line 122 is at a low level, and the clock signal on the third loop line 123 is at a high level. Figure 5 As shown, a first electric field in a first direction X1 is established between the first circular routing 121 and the second circular routing 122, and a third electric field in a second direction X2 is established between the third circular routing 123 and the second circular routing 122. The first direction X1 is the direction from the non-display area 12 to the display area 11, and the second direction X2 is the direction from the display area 11 to the non-display area 12.

[0079] When the electrostatic charge enters the first substrate 1, the positive charge is subjected to the electric field force in the same direction as the electric field line, and the negative charge is subjected to the electric field force in the opposite direction to the electric field line. Under the action of the first electric field, the negative charge is subjected to the electric field force in the second direction X2 and is blocked outside the first substrate 1, and the positive charge is subjected to the electric field force in the second direction X2 and is adsorbed on the second circular wiring 122 along the direction of the electric field line. At this time, the positive charge with a certain initial velocity may escape from the first electric field by crossing the second circular wiring 122 under the action of the first electric field, and enter the display area 11 of the first substrate 1. At this time, the third electric field established between the third circular wiring 123 and the second circular wiring 122 will give a third electric field to the positive charge in the direction of the first electric field. The electric field force in the second direction X2 causes the positive charges entering the first substrate 1 to be adsorbed on the second circular wiring 122. Since a small number of positive charges may enter the display area 11 of the first substrate 1, and the speed of this part of the positive charges will gradually decrease, and in order to avoid the electric field strength E3 of the third electric field being too strong, which will cause the negative charges to be adsorbed into the display area 11 of the first substrate 1, the electric field strength E3 of the third electric field can be equal to the electric field strength E1 of the first electric field or less than the electric field strength E1 of the first electric field. The third electric field can drive the positive charges to move along the second direction X2 and be adsorbed on the second circular wiring 122. At the same time, no additional negative charges will be adsorbed into the display area 11, thereby improving the charge shielding effect.

[0080] If the operation continues in the above manner, too much positive charge will accumulate on the second loop line 122, which will cause electrostatic discharge. Therefore, it is necessary to change the polarity of the loop line to release or discharge the positive charge. Therefore, in the second time period t2, the clock signal of the loop line changes, that is, the clock signal on the first loop line 121 is switched to a low level, the clock signal on the second loop line 122 is switched to a high level, and the clock signal on the third loop line 123 is switched to a low level. Figure 6 As shown, a second electric field in a second direction X2 is established between the first circular routing 121 and the second circular routing 122, and a fourth electric field in a first direction X1 is established between the third circular routing 123 and the second circular routing 122. The negative charges entering the glass from the outside begin to gather on the second circular routing 122 under the action of the second electric field, and the positive charges accumulated on the second circular routing 122 in the first time period t1 begin to be released to the outside under the action of the second electric field.

[0081] When the electric field strength E2 of the second electric field is equal to the electric field strength E4 of the fourth electric field, the positive charges located in the middle of the second circular routing 122 in the first time period t1 are subjected to the same electric field force and will continue to stay on the second circular routing 122. The positive charges located on the second circular routing 122 close to the first circular routing 121 will be discharged to the outside under the action of the second electric field, and the positive charges located on the second circular routing 122 close to the third circular routing 123 will enter the display area 11 under the action of the fourth electric field, resulting in the problem of charge accumulation and charge entering the display area 11.

[0082] To this end, in the second time period t2, the electric field strength E2 of the second electric field is greater than the electric field strength E4 of the fourth electric field, and the positive charge is subjected to a greater electric field force in the second direction X2. Therefore, the positive charge accumulated on the second circular wiring 122 in the first time period t1 will be discharged to the outside under the action of the second electric field. At the same time, under the action of the second electric field and the fourth electric field, the negative charge enters and gathers on the second circular wiring 122, and the negative charge is discharged by the first electric field and the third electric field established again in the next time period. The first time period t1 and the second time period t2 are a complete cycle, and the above actions are repeated in subsequent cycles, thereby continuously realizing the process of repeated adsorption and discharge of charges entering the first substrate 1 from the outside, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area 11, thereby enhancing the electrostatic protection capability and reliability of the display panel 100.

[0083] The clock signals on the first circular line 121 and the third circular line 123 may be the same or different, and the spacing between the circular lines may be equal or unequal, which is selected and set accordingly according to the electric field strength requirement.

[0084] Embodiment 2

[0085] In an alternative embodiment, if Figure 4 As shown, the signal source circuit 2 outputs a first clock signal CLK1 and a second clock signal CLK2 with opposite polarities and equal amplitudes, the first ring line 121 and the third ring line 123 are used to receive the first clock signal CLK1, and the second ring line 122 is used to receive the second clock signal CLK2;

[0086] Among them, Figure 7 As shown, the first spacing S1 is smaller than the second spacing S2. The first spacing S1 is the spacing between the first circular wiring 121 and the second circular wiring 122. The second spacing S2 is the spacing between the second circular wiring 122 and the third circular wiring 123.

[0087] It can be understood that the electric field strength is positively correlated with the voltage difference between the circular traces, and negatively correlated with the spacing between the circular traces, that is, when the spacing between the circular traces remains unchanged, the greater the voltage difference between the circular traces, the stronger the electric field strength, the greater the electric field force, the smaller the voltage difference between the circular traces, the weaker the electric field strength, and the smaller the electric field force; and when the voltage difference between the circular traces remains unchanged, the smaller the spacing between the circular traces, the stronger the electric field strength, the greater the electric field force, the larger the spacing between the circular traces, the weaker the electric field strength, and the smaller the electric field force.

[0088] Therefore, in order to reduce signal switching and circuit settings, simplify the control method and reduce design costs, in this embodiment, the electric field strength and electric field force between the circular lines are changed by changing the spacing between the circular lines.

[0089] In the first time period t1, the first clock signal CLK1 on the first loop line 121 and the third loop line 123 is at a high level, and the second clock signal CLK2 on the second loop line 122 is at a low level. Figure 8 As shown, a first electric field in a first direction X1 is established between the first circular routing 121 and the second circular routing 122, and a third electric field in a second direction X2 is established between the third circular routing 123 and the second circular routing 122. Since the first spacing S1 is smaller than the second spacing S2, the electric field strength E1 of the first electric field is greater than the electric field strength E3 of the third electric field.

[0090] When electrostatic charges enter the first substrate 1, positive charges are subjected to an electric field force in the same direction as the electric field lines, and negative charges are subjected to an electric field force in the opposite direction to the electric field lines. Under the action of the first electric field, negative charges are subjected to the electric field force in the second direction X2 and are blocked outside the first substrate 1, and positive charges are subjected to the electric field force in the second direction X2 and are adsorbed on the second circular wiring 122 along the direction of the electric field lines. The third electric field established between the third circular wiring 123 and the second circular wiring 122 will exert an electric field force in the second direction X2 on some positive charges, so that the positive charges entering the first substrate 1 are adsorbed on the second circular wiring 122. The electric field strength E3 of the third electric field is less than the electric field strength E1 of the first electric field. The third electric field can drive the positive charges to move along the second direction X2 and be adsorbed on the second circular wiring 122, and at the same time, no additional negative charges will be adsorbed into the display area 11, thereby improving the charge shielding effect.

[0091] In the second time period t2, the first clock signal CLK1 on the first loop line 121 and the third loop line 123 is switched to a low level, and the second clock signal CLK2 on the second loop line 122 is switched to a high level. Fig. 9 As shown, a second electric field in the second direction X2 is established between the first circular line 121 and the second circular line 122, and a fourth electric field in the first direction X1 is established between the third circular line 123 and the second circular line 122. The negative charges entering the glass from the outside begin to gather on the second circular line 122 under the action of the second electric field, and the positive charges accumulated on the second circular line 122 in the first time period t1 begin to be released to the outside under the action of the second electric field. Since the first spacing S1 is smaller than the second spacing S2, the electric field strength E2 of the second electric field is greater than the electric field strength E4 of the fourth electric field, and the positive charges are subjected to a greater electric field force in the second direction X2, so the first The positive charges accumulated on the second circular wiring 122 in time period t1 will be discharged to the outside under the action of the second electric field. At the same time, under the action of the second electric field and the fourth electric field, negative charges enter and accumulate on the second circular wiring 122. The negative charges are discharged by the first electric field and the third electric field established again in the next time period. The first time period t1 and the second time period t2 are a complete cycle, and the subsequent cycles repeat the above actions, thereby continuously realizing the process of repeated adsorption and discharge of charges entering the first substrate 1 from the outside, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area 11, thereby enhancing the electrostatic protection capability and reliability of the display panel 100.

[0092] Embodiment 3

[0093] In another alternative embodiment, if Fig.10As shown, the signal source circuit 2 outputs a first clock signal CLK1, a second clock signal CLK2 and a third clock signal CLK3, the first ring wiring 121 is used to receive the first clock signal CLK1, the second ring wiring 122 is used to receive the second clock signal CLK2, and the third ring wiring 123 is used to receive the third clock signal CLK3. The polarity of the first clock signal CLK1 is the same as that of the third clock signal CLK3, and the polarity of the first clock signal CLK1 is opposite to that of the second clock signal CLK2;

[0094] like Fig.11 As shown, the voltage of the high level signal VGH1 of the first clock signal CLK1 is not less than the voltage of the high level signal VGH3 of the third clock signal CLK3, and the voltage of the low level signal VGL1 of the first clock signal CLK1 is less than the voltage of the low level signal VGL3 of the third clock signal CLK3.

[0095] In this embodiment, the signal source circuit 2 directly outputs three different clock signals to the three ring lines respectively, and changes the electric field intensity and electric field force between the ring lines by changing the voltage difference between the ring lines.

[0096] In the first time period t1, the first clock signal CLK1 on the first circular routing 121 and the third clock signal CLK3 on the third circular routing 123 are at a high level, and the second clock signal CLK2 on the second circular routing 122 is at a low level. A first electric field in a first direction X1 is established between the first circular routing 121 and the second circular routing 122, and a third electric field in a second direction X2 is established between the third circular routing 123 and the second circular routing 122. Since the voltage of the high level signal VGH1 of the first clock signal CLK1 is not less than the voltage of the high level signal VGH3 of the third clock signal CLK3, a first voltage difference between the voltage of the high level signal VGH1 of the first clock signal CLK1 and the voltage of the low level signal VGL2 of the second clock signal CLK2 is not less than the third voltage difference between the voltage of the high level signal VGH3 of the third clock signal CLK3 and the voltage of the low level signal of the second clock, and the electric field strength E1 of the first electric field is greater than or equal to the electric field strength E3 of the third electric field.

[0097] When the electrostatic charge enters the first substrate 1, the positive charge is subjected to the electric field force in the same direction as the electric field line, and the negative charge is subjected to the electric field force in the opposite direction to the electric field line. Under the action of the first electric field, the negative charge is subjected to the electric field force in the second direction X2 and is blocked outside the first substrate 1, and the positive charge is subjected to the electric field force in the second direction X2 and is adsorbed on the second circular wiring 122 along the direction of the electric field line. The third electric field established between the third circular wiring 123 and the second circular wiring 122 will exert an electric field force in the second direction X2 on some positive charges, so that the positive charges entering the first substrate 1 are adsorbed on the second circular wiring 122. The electric field strength E3 of the third electric field can be equal to the electric field strength E1 of the first electric field or less than the electric field strength E1 of the first electric field. The third electric field can drive the positive charge to move along the second direction X2 and be adsorbed on the second circular wiring 122, and at the same time, it will not additionally adsorb negative charges into the display area 11, thereby improving the charge shielding effect.

[0098] In the second time period t2, the first clock signal CLK1 on the first circular line 121 and the third clock signal CLK3 on the third circular line 123 are switched to a low level, and the second clock signal CLK2 on the second circular line 122 is switched to a high level. A second electric field in the second direction X2 is established between the first circular line 121 and the second circular line 122, and a fourth electric field in the first direction X1 is established between the third circular line 123 and the second circular line 122. The negative charges entering the glass from the outside begin to gather on the second circular line 122 under the action of the second electric field, and the positive charges accumulated on the second circular line 122 in the first time period t1 begin to be released to the outside under the action of the second electric field. Since the voltage of the low level signal VGL1 of the first clock signal CLK1 is less than the voltage of the low level signal VGL3 of the third clock signal CLK3, the voltage of the high level signal of the second circular line 122 is equal to the voltage of the low level signal of the first clock signal CLK1. The second voltage difference of the voltage of VGL1 is greater than the fourth voltage difference between the voltage of the high-level signal of the second ring wiring 122 and the voltage of the low-level signal VGL3 of the third clock signal CLK3. The electric field strength E2 of the second electric field is greater than the electric field strength E4 of the fourth electric field. The positive charge is subjected to a greater electric field force in the second direction X2. Therefore, the positive charge accumulated on the second ring wiring 122 in the first time period t1 will be discharged to the outside under the action of the second electric field. At the same time, under the action of the second electric field and the fourth electric field, negative charges enter and gather on the second ring wiring 122. The negative charges are discharged by the first electric field and the third electric field established again in the next time period. The first time period t1 and the second time period t2 are a complete cycle. The above actions are repeated in subsequent cycles, thereby continuously realizing the process of repeated adsorption and discharge of charges entering the first substrate 1 from the outside, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area 11, thereby enhancing the electrostatic protection capability and reliability of the display panel 100.

[0099] Embodiment 4

[0100] In another alternative embodiment, if Fig.12 As shown, the signal source circuit 2 outputs a first clock signal CLK1 and a second clock signal CLK2 with opposite polarities and equal amplitudes;

[0101] The display panel 100 further includes:

[0102] A clock conversion circuit 3, which is disposed in the non-display area 12, and is respectively connected to the first ring wiring 121, the second ring wiring 122, the third ring wiring 123 and the signal source circuit 2;

[0103] The clock conversion circuit 3 is used to convert the first clock signal CLK1 and the second clock signal CLK2 into a third clock signal CLK3, a fourth clock signal CLK4 and a fifth clock signal CLK5. The first ring line 121 is used to receive the third clock signal CLK3, the second ring line 122 is used to receive the fourth clock signal CLK4, and the third ring line 123 is used to receive the fifth clock signal CLK5. Fig.13 As shown, the third clock signal CLK3 and the fifth clock signal CLK5 have the same polarity, and the third clock signal CLK3 and the fourth clock signal CLK4 have opposite polarities;

[0104] The voltage of the high level signal VGH3 of the third clock signal CLK3 is not less than the voltage of the high level signal VGH5 of the fifth clock signal CLK5 , and the voltage of the low level signal VGL3 of the third clock signal CLK3 is less than the voltage of the low level signal VGL5 of the fifth clock signal CLK5 .

[0105] In this embodiment, compared with the third embodiment, the signal source circuit 2 outputs two clock signals in the same manner as the second embodiment, without the need to additionally set up another signal output terminal. By additionally setting up a clock conversion circuit 3, the first clock signal CLK1 and the second clock signal CLK2 are converted to generate a third clock signal CLK3, a fourth clock signal CLK4 and a fifth clock signal CLK5.

[0106] In the first time period t1, the fifth clock signal CLK5 of the first circular routing 121 and the fifth clock signal CLK5 on the third circular routing 123 are at a high level, and the fourth clock signal CLK4 on the second circular routing 122 is at a low level. A first electric field in a first direction X1 is established between the first circular routing 121 and the second circular routing 122, and a third electric field in a second direction X2 is established between the third circular routing 123 and the second circular routing 122. Since the voltage of the high-level signal VGH3 of the third clock signal CLK3 is not less than the voltage of the high-level signal VGH5 of the fifth clock signal CLK5, a first voltage difference between the voltage of the high-level signal VGH3 of the third clock signal CLK3 and the voltage of the low-level signal VGL4 of the fourth clock signal CLK4 is not less than the third voltage difference between the voltage of the high-level signal VGH5 of the fifth clock signal CLK5 and the voltage of the low-level signal of the second clock, and the electric field strength E1 of the first electric field is greater than or equal to the electric field strength E3 of the third electric field.

[0107] When the electrostatic charge enters the first substrate 1, the positive charge is subjected to the electric field force in the same direction as the electric field line, and the negative charge is subjected to the electric field force in the opposite direction to the electric field line. Under the action of the first electric field, the negative charge is subjected to the electric field force in the second direction X2 and is blocked outside the first substrate 1, and the positive charge is subjected to the electric field force in the second direction X2 and is adsorbed on the second circular wiring 122 along the direction of the electric field line. The third electric field established between the third circular wiring 123 and the second circular wiring 122 will exert an electric field force in the second direction X2 on some positive charges, so that the positive charges entering the first substrate 1 are adsorbed on the second circular wiring 122. The electric field strength E3 of the third electric field can be equal to the electric field strength E1 of the first electric field or less than the electric field strength E1 of the first electric field. The third electric field can drive the positive charge to move along the second direction X2 and be adsorbed on the second circular wiring 122, and at the same time, it will not additionally adsorb negative charges into the display area 11, thereby improving the charge shielding effect.

[0108] In the second time period t2, the third clock signal CLK3 of the first circular line 121 and the fifth clock signal CLK5 on the third circular line 123 are switched to a low level, and the fourth clock signal CLK4 on the second circular line 122 is switched to a high level. A second electric field in the second direction X2 is established between the first circular line 121 and the second circular line 122, and a fourth electric field in the first direction X1 is established between the third circular line 123 and the second circular line 122. The negative charges entering the glass from the outside begin to gather on the second circular line 122 under the action of the second electric field, and the positive charges accumulated on the second circular line 122 in the first time period t1 begin to be released to the outside under the action of the second electric field. Since the voltage of the low level signal VGL3 of the third clock signal CLK3 is less than the voltage of the low level signal VGL5 of the fifth clock signal CLK5, the voltage of the high level signal of the second circular line 122 is equal to the low level signal VGL5 of the third clock signal CLK3. The second voltage difference of the voltage of GL3 is greater than the fourth voltage difference between the voltage of the high-level signal of the second ring wiring 122 and the voltage of the low-level signal VGL5 of the fifth clock signal CLK5. The electric field strength E2 of the second electric field is greater than the electric field strength E4 of the fourth electric field. The positive charge is subjected to a greater electric field force in the second direction X2. Therefore, the positive charge accumulated on the second ring wiring 122 in the first time period t1 will be discharged to the outside under the action of the second electric field. At the same time, under the action of the second electric field and the fourth electric field, negative charges enter and gather on the second ring wiring 122. The negative charges are discharged by the first electric field and the third electric field established again in the next time period. The first time period t1 and the second time period t2 are a complete cycle. The above actions are repeated in subsequent cycles, thereby continuously realizing the process of repeated adsorption and discharge of charges entering the first substrate 1 from the outside, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area 11, thereby enhancing the electrostatic protection capability and reliability of the display panel 100.

[0109] The clock conversion circuit 3 may adopt a signal splitting circuit, a switch switching circuit, etc., and the specific structure is not limited.

[0110] Embodiment 5

[0111] Based on the fourth embodiment, in an optional embodiment, as Fig.14 As shown, the clock conversion circuit 3 includes a first clock signal terminal IN1, a second clock signal terminal IN1, a first electronic switch tube T1 and a second electronic switch tube T2;

[0112] The first end of the first electronic switch tube T1 and the first clock signal end IN1 are respectively connected to the first ring wiring 121, the first clock signal end IN1 is also connected to the control end of the first electronic switch tube T1, the second end of the first electronic switch tube T1 is connected to the third ring wiring 123, and the first clock signal end IN1 is used to input the first clock signal CLK1;

[0113] The first end of the second electronic switch tube T2 is used to input the first voltage signal, the control end of the second electronic switch tube T2 is respectively connected to the second clock signal end IN2 and the second ring line 122, the second end of the second electronic switch tube T2 is connected to the third ring line 123, and the second clock signal end IN2 is used to input the second clock signal CLK2;

[0114] The voltage of the low level signal VGL1 of the first clock signal CLK1 is lower than the voltage of the first voltage signal V1 .

[0115] In this embodiment, in the first time period t1, when the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the first electronic switch tube T1 is turned on and the second electronic switch tube T2 is turned off, and the high level of the first clock signal CLK1 is output to the first ring wiring 121 and the third ring wiring 123, the high level signal of the first clock signal CLK1 constitutes the high level of the third clock signal CLK3 and the fifth clock signal CLK5, the low level signal of the second clock signal CLK2 is output to the second ring wiring 122, and the low level signal of the second clock signal CLK2 constitutes the low level of the fourth clock signal CLK4.

[0116] A first electric field in a first direction X1 is established between the first circular routing 121 and the second circular routing 122, and a third electric field in a second direction X2 is established between the third circular routing 123 and the second circular routing 122. Since the voltage of the high-level signal VGH3 of the third clock signal CLK3 and the voltage of the high-level signal VGH5 of the fifth clock signal CLK5 are both the voltage of the high-level signal VGH1 of the first clock signal CLK1, the first voltage difference is equal to the third voltage difference, and the electric field strength E1 of the first electric field is equal to the electric field strength E3 of the third electric field.

[0117] When the electrostatic charge enters the first substrate 1, the positive charge is subjected to the electric field force in the same direction as the electric field line, and the negative charge is subjected to the electric field force in the opposite direction to the electric field line. Under the action of the first electric field, the negative charge is subjected to the electric field force in the second direction X2 and is blocked outside the first substrate 1, and the positive charge is subjected to the electric field force in the second direction X2 and is adsorbed on the second circular wiring 122 along the direction of the electric field line. The third electric field established between the third circular wiring 123 and the second circular wiring 122 will exert an electric field force in the second direction X2 on some positive charges, so that the positive charges entering the first substrate 1 are adsorbed on the second circular wiring 122. The electric field strength E3 of the third electric field is equal to the electric field strength E1 of the first electric field. The third electric field can drive the positive charge to move along the second direction X2 and be adsorbed on the second circular wiring 122. At the same time, it will not additionally adsorb negative charges into the display area 11, thereby improving the charge shielding effect.

[0118] In the second time period t2, the first clock signal CLK1 switches to a low level, the second clock signal CLK2 switches to a high level, the first electronic switch tube T1 is turned off, and the second electronic switch tube T2 is turned on. The low level signal of the first clock signal CLK1 is output to the first ring wiring 121, the high level signal of the second clock signal CLK2 is output to the second ring wiring 122, and the first voltage signal V1 is output to the third ring wiring 123. The low level signal of the first clock signal CLK1 constitutes the low level signal VGL3 of the third clock signal CLK3, the high level signal of the second clock signal CLK2 constitutes the high level signal VGH4 of the fourth clock signal CLK4, and the first voltage signal V1 constitutes the low level signal VGL5 of the fifth clock signal CLK5.

[0119] A second electric field in the second direction X2 is established between the first circular line 121 and the second circular line 122, and a fourth electric field in the first direction X1 is established between the third circular line 123 and the second circular line 122. The negative charges entering the glass from the outside begin to gather on the second circular line 122 under the action of the second electric field, and the positive charges accumulated on the second circular line 122 in the first time period t1 begin to be released to the outside under the action of the second electric field. Since the voltage of the low-level signal VGL1 of the first clock signal CLK1 is less than the voltage of the first voltage signal V1, the second voltage difference is greater than the fourth voltage difference, and the electric field strength E2 of the second electric field is greater than the electric field strength E4 of the fourth electric field. The positive charges are affected by The electric field force in the second direction X2 is stronger, so the positive charges accumulated on the second circular wiring 122 in the first time period t1 will be discharged to the outside under the action of the second electric field. At the same time, under the action of the second electric field and the fourth electric field, negative charges enter and gather on the second circular wiring 122, and the negative charges are discharged by the first electric field and the third electric field established again in the next time period. The first time period t1 and the second time period t2 are a complete cycle, and the subsequent cycles repeat the above actions, thereby continuously realizing the process of repeated adsorption and discharge of charges entering the first substrate 1 from the outside, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area 11, thereby enhancing the electrostatic protection capability and reliability of the display panel 100.

[0120] Among them, the voltage of the first voltage signal V1 is greater than the voltage of the low level signal VGL1 of the first clock signal CLK1. According to the size of the low level signal of the first clock signal CLK1, the size of the voltage of the first voltage signal V1 can be set according to demand. In an optional embodiment, the voltage of the first voltage signal V1 is zero.

[0121] The first voltage signal V1 can be provided by another power supply module, or by the signal source circuit 2. The specific method is not limited. In an optional embodiment, in order to reduce the structural design of the power supply module and reduce the design cost, the first end of the second electronic switch tube T2 is grounded and connected to a ground signal with a zero voltage.

[0122] The first electronic switch tube T1 and the second electronic switch tube T2 are turned on at a high level and turned off at a low level. Corresponding types of switching devices may be used, such as NMOS tubes, NPN transistors, etc. In order to simplify the structure of the display panel 100, in an optional embodiment, the first electronic switch tube T1 and the second electronic switch tube T2 are N-channel thin film transistors.

[0123] Embodiment 6

[0124] Based on the fourth embodiment, in another optional embodiment, as Fig.15 As shown, the clock conversion circuit 3 includes a first clock signal terminal IN1, a second clock signal terminal IN2, a first electronic switch tube T1, a second electronic switch tube T2 and a first potential shift circuit 31;

[0125] The first end of the first electronic switch tube T1 and the first clock signal end IN1 are respectively connected to the first ring wiring 121, and the first clock signal end IN1 is also respectively connected to the control end of the first electronic switch tube T1 and the input end of the first potential shift circuit 31, and the first clock signal end IN1 is used to input the first clock signal CLK1;

[0126] The first end of the second electronic switch tube T2 is connected to the output end of the first potential shift circuit 31, the control end and the second clock signal end IN2 of the second electronic switch tube T2 are respectively connected to the second ring wiring 122, the second end of the second electronic switch tube T2 is connected to the third ring wiring 123, and the second clock signal end IN2 is used to input the second clock signal CLK2;

[0127] The first potential shift circuit 31 is used for performing potential shift on the input first clock signal CLK1 and outputting it as a sixth clock signal CLK6, wherein the voltage of the high level signal of the sixth clock signal CLK6 is greater than the voltage of the high level signal VGH1 of the first clock signal CLK1, and the voltage of the low level signal of the sixth clock signal CLK6 is greater than the voltage of the low level signal VGL1 of the first clock signal CLK1.

[0128] In this embodiment, the first potential shift circuit 31 is used to achieve an overall upward shift of the first clock signal CLK1, so that the voltage of the high-level signal of the output sixth clock signal CLK6 is greater than the voltage of the high-level signal VGH1 of the first clock signal CLK1, and the voltage of the low-level signal of the sixth clock signal CLK6 is greater than the voltage of the low-level signal VGL1 of the first clock signal CLK1. There is no need to additionally set up a power supply module for providing the first voltage signal V1, thereby simplifying the design cost.

[0129] In the first time period t1, when the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the first electronic switch tube T1 is turned on and the second electronic switch tube T2 is turned off, and the high level of the first clock signal CLK1 is output to the first ring wiring 121 and the third ring wiring 123, the high level signal of the first clock signal CLK1 constitutes the high level of the third clock signal CLK3 and the fifth clock signal CLK5, the low level signal of the second clock signal CLK2 is output to the second ring wiring 122, and the low level signal of the second clock signal CLK2 constitutes the low level of the fourth clock signal CLK4.

[0130] When the electrostatic charge enters the first substrate 1, the positive charge is subjected to the electric field force in the same direction as the electric field line, and the negative charge is subjected to the electric field force in the opposite direction to the electric field line. Under the action of the first electric field, the negative charge is subjected to the electric field force in the second direction X2 and is blocked outside the first substrate 1, and the positive charge is subjected to the electric field force in the second direction X2 and is adsorbed on the second circular wiring 122 along the direction of the electric field line. The third electric field established between the third circular wiring 123 and the second circular wiring 122 will exert an electric field force in the second direction X2 on some positive charges, so that the positive charges entering the first substrate 1 are adsorbed on the second circular wiring 122. The electric field strength E3 of the third electric field is equal to the electric field strength E1 of the first electric field. The third electric field can drive the positive charge to move along the second direction X2 and be adsorbed on the second circular wiring 122. At the same time, it will not additionally adsorb negative charges into the display area 11, thereby improving the charge shielding effect.

[0131] In the second time period t2, the first clock signal CLK1 switches to a low level, the second clock signal CLK2 switches to a high level, the first electronic switch tube T1 is turned off, and the second electronic switch tube T2 is turned on. The low level signal of the first clock signal CLK1 is output to the first ring wiring 121, and the high level signal of the second clock signal CLK2 is output to the second ring wiring 122. The low level signal of the sixth clock signal CLK6 output by the first potential shift circuit 31 is output to the third ring wiring 123. The low level signal of the first clock signal CLK1 constitutes the low level signal VGL3 of the third clock signal CLK3, the high level signal of the second clock signal CLK2 constitutes the high level signal VGH4 of the fourth clock signal CLK4, and the low level signal of the sixth clock signal CLK6 constitutes the low level signal VGL5 of the fifth clock signal CLK5.

[0132] A second electric field in the second direction X2 is established between the first circular line 121 and the second circular line 122, and a fourth electric field in the first direction X1 is established between the third circular line 123 and the second circular line 122. Negative charges entering the glass from the outside begin to gather on the second circular line 122 under the action of the second electric field, and positive charges accumulated on the second circular line 122 in the first time period t1 begin to be released to the outside under the action of the second electric field. Since the voltage of the low-level signal VGL1 of the first clock signal CLK1 is less than the voltage of the low-level signal of the sixth clock signal CLK6, the second voltage difference is greater than the fourth voltage difference, and the electric field strength E2 of the second electric field is greater than the electric field strength E4 of the fourth electric field. The positive charges are subjected to a greater electric field force in the second direction X2, so the positive charges accumulated on the second circular wiring 122 in the first time period t1 will be discharged to the outside under the action of the second electric field. At the same time, under the action of the second electric field and the fourth electric field, negative charges enter and gather on the second circular wiring 122, and the negative charges are discharged by the first electric field and the third electric field established again in the next time period. The first time period t1 and the second time period t2 are a complete cycle, and the subsequent cycles repeat the above actions, thereby continuously realizing the process of repeated adsorption and discharge of charges entering the first substrate 1 from the outside, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area 11, thereby enhancing the electrostatic protection capability and reliability of the display panel 100.

[0133] The first electronic switch tube T1 and the second electronic switch tube T2 are turned on at a high level and turned off at a low level. Corresponding types of switching devices may be used, such as NMOS tubes, NPN transistors, etc. In order to simplify the structure of the display panel 100, in an optional embodiment, the first electronic switch tube T1 and the second electronic switch tube T2 are N-channel thin film transistors.

[0134] The first level shift circuit may adopt a potential boosting chip, a switch switching circuit or the like, and the specific structure is not limited.

[0135] Embodiment 7

[0136] Based on the fourth embodiment, in another optional embodiment, as Fig.16 As shown, the clock conversion circuit 3 includes a first clock signal terminal IN1, a second clock signal terminal IN2, a first resistor R1, a third electronic switch tube T3 and a fourth electronic switch tube T4;

[0137] The first clock signal terminal IN1 is respectively connected to the third ring wiring 123, the first end of the first resistor R1 and the first end of the third electronic switch tube T3, the second end of the first resistor R1 is connected to the control end of the third electronic switch tube T3, the second end of the third electronic switch tube T3 is connected to the first ring wiring 121, and the first clock signal terminal IN1 is used to input the first clock signal CLK1;

[0138] The first end of the fourth electronic switch tube T4 is used to input the second voltage signal, the second end of the fourth electronic switch tube T4 is connected to the first ring wiring 121, the control end of the fourth electronic switch tube T4 and the second ring wiring 122 are respectively connected to the second clock signal end IN2, and the second clock signal end IN2 is used to input the second clock signal CLK2;

[0139] The voltage of the low level signal VGL1 of the first clock signal CLK1 is greater than the voltage of the second voltage signal V2 .

[0140] In this embodiment, in the first time period t1, when the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the fourth electronic switch tube T4 is turned on, and the fourth electronic switch tube T4 is turned off. The high level of the first clock signal CLK1 is output to the first ring wiring 121 and the third ring wiring 123, and the high level signal of the first clock signal CLK1 constitutes the high level of the third clock signal CLK3 and the fifth clock signal CLK5. The low level signal of the second clock signal CLK2 is output to the second ring wiring 122, and the low level signal of the second clock signal CLK2 constitutes the low level of the fourth clock signal CLK4.

[0141] A first electric field in a first direction X1 is established between the first circular routing 121 and the second circular routing 122, and a third electric field in a second direction X2 is established between the third circular routing 123 and the second circular routing 122. Since the voltage of the high-level signal VGH3 of the third clock signal CLK3 and the voltage of the high-level signal VGH5 of the fifth clock signal CLK5 are both the voltage of the high-level signal VGH1 of the first clock signal CLK1, the first voltage difference is equal to the third voltage difference, and the electric field strength E1 of the first electric field is equal to the electric field strength E3 of the third electric field.

[0142] When the electrostatic charge enters the first substrate 1, the positive charge is subjected to the electric field force in the same direction as the electric field line, and the negative charge is subjected to the electric field force in the opposite direction to the electric field line. Under the action of the first electric field, the negative charge is subjected to the electric field force in the second direction X2 and is blocked outside the first substrate 1, and the positive charge is subjected to the electric field force in the second direction X2 and is adsorbed on the second circular wiring 122 along the direction of the electric field line. The third electric field established between the third circular wiring 123 and the second circular wiring 122 will exert an electric field force in the second direction X2 on some positive charges, so that the positive charges entering the first substrate 1 are adsorbed on the second circular wiring 122. The electric field strength E3 of the third electric field is equal to the electric field strength E1 of the first electric field. The third electric field can drive the positive charge to move along the second direction X2 and be adsorbed on the second circular wiring 122. At the same time, it will not additionally adsorb negative charges into the display area 11, thereby improving the charge shielding effect.

[0143] In the second time period t2, the first clock signal CLK1 switches to a low level, the second clock signal CLK2 switches to a high level, the third electronic switch tube T3 is turned off, and the fourth electronic switch tube T4 is turned on. The low level signal of the first clock signal CLK1 is output to the third ring line 123, the high level signal of the second clock signal CLK2 is output to the second ring line 122, and the second voltage signal V2 is output to the first ring line 121. The low level signal of the first clock signal CLK1 constitutes the low level signal VGL5 of the fifth clock signal CLK5, the high level signal of the second clock signal CLK2 constitutes the high level signal VGH4 of the fourth clock signal CLK4, and the second voltage signal V2 constitutes the low level signal VGL3 of the third clock signal CLK3.

[0144] A second electric field in the second direction X2 is established between the first circular line 121 and the second circular line 122, and a fourth electric field in the first direction X1 is established between the third circular line 123 and the second circular line 122. The negative charges entering the glass from the outside begin to gather on the second circular line 122 under the action of the second electric field, and the positive charges accumulated on the second circular line 122 in the first time period t1 begin to be released to the outside under the action of the second electric field. Since the voltage of the second voltage signal V2 is less than the voltage of the low level signal VGL1 of the first clock signal CLK1, the second voltage difference is greater than the fourth voltage difference, and the electric field strength E2 of the second electric field is greater than the electric field strength E4 of the fourth electric field, and the positive charges are affected. The electric field force in the second direction X2 is stronger, so the positive charges accumulated on the second circular wiring 122 in the first time period t1 will be discharged to the outside under the action of the second electric field. At the same time, under the action of the second electric field and the fourth electric field, negative charges enter and gather on the second circular wiring 122, and the negative charges are discharged by the first electric field and the third electric field established again in the next time period. The first time period t1 and the second time period t2 are a complete cycle, and the subsequent cycles repeat the above actions, thereby continuously realizing the process of repeated adsorption and discharge of charges entering the first substrate 1 from the outside, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area 11, thereby enhancing the electrostatic protection capability and reliability of the display panel 100.

[0145] Among them, the voltage of the second voltage signal V2 is smaller than the voltage of the low level signal VGL1 of the first clock signal CLK1. According to the size of the low level signal of the first clock signal CLK1, the size of the voltage of the second voltage signal V2 can be set according to demand. In an optional embodiment, the voltage of the first voltage signal V1 is a negative voltage.

[0146] The third electronic switch tube T3 and the fourth electronic switch tube T4 are turned on at a high level and turned off at a low level, and corresponding types of switching devices may be used, such as NMOS tubes, NPN transistors, etc. In order to simplify the structure of the display panel 100, in an optional embodiment, the third electronic switch tube T3 and the fourth electronic switch tube T4 are N-channel thin film transistors.

[0147] Embodiment 8

[0148] Based on the fourth embodiment, in another optional embodiment, as Fig.17 As shown, the clock conversion circuit includes a first clock signal terminal IN1, a second clock signal terminal IN2, a first resistor R1, a third electronic switch tube T3, a fourth electronic switch tube T4 and a second potential shift circuit 32;

[0149] The first clock signal terminal IN1 is respectively connected to the third ring wiring 123, the first end of the first resistor R1, the first end of the third electronic switch tube T3 and the input end of the second potential shift circuit 32, the second end of the first resistor R1 is connected to the control end of the third electronic switch tube T3, the second end of the third electronic switch tube T3 is connected to the first ring wiring 121, and the first clock signal terminal IN1 is used to input the first clock signal CLK1;

[0150] A first end of the fourth electronic switch tube T4 is connected to the output end of the second potential shift circuit 32, a second end of the fourth electronic switch tube T4 is connected to the first ring wiring 121, a control end of the fourth electronic switch tube T4 is respectively connected to the second ring wiring 122 and the second clock signal end IN2, and the second clock signal end IN2 is used to input the second clock signal CLK2;

[0151] The second potential shift circuit 32 is used for performing potential shift on the input first clock signal CLK1 and outputting it as a seventh clock signal CLK7, wherein the voltage of the high level signal of the seventh clock signal CLK7 is lower than the voltage of the high level signal VGH1 of the first clock signal CLK1, and the voltage of the low level signal of the seventh clock signal CLK7 is lower than the voltage of the low level signal VGL1 of the first clock signal CLK1.

[0152] In this embodiment, the first potential shift circuit 31 is used to achieve an overall downward shift of the first clock signal CLK1, so that the voltage of the high-level signal of the output seventh clock signal CLK7 is less than the voltage of the high-level signal VGH1 of the first clock signal CLK1, and the voltage of the low-level signal of the seventh clock signal CLK7 is less than the voltage of the low-level signal VGL1 of the first clock signal CLK1. There is no need to additionally set up a power supply module for providing the first voltage signal V1, thereby simplifying the design cost.

[0153] In the first time period t1, when the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the third electronic switch tube T3 is turned on and the fourth electronic switch tube T4 is turned off, and the high level of the first clock signal CLK1 is output to the first ring wiring 121 and the third ring wiring 123, the high level signal of the first clock signal CLK1 constitutes the high level of the third clock signal CLK3 and the fifth clock signal CLK5, the low level signal of the second clock signal CLK2 is output to the second ring wiring 122, and the low level signal of the second clock signal CLK2 constitutes the low level of the fourth clock signal CLK4.

[0154] When the electrostatic charge enters the first substrate 1, the positive charge is subjected to the electric field force in the same direction as the electric field line, and the negative charge is subjected to the electric field force in the opposite direction to the electric field line. Under the action of the first electric field, the negative charge is subjected to the electric field force in the second direction X2 and is blocked outside the first substrate 1, and the positive charge is subjected to the electric field force in the second direction X2 and is adsorbed on the second circular wiring 122 along the direction of the electric field line. The third electric field established between the third circular wiring 123 and the second circular wiring 122 will exert an electric field force in the second direction X2 on some positive charges, so that the positive charges entering the first substrate 1 are adsorbed on the second circular wiring 122. The electric field strength E3 of the third electric field is equal to the electric field strength E1 of the first electric field. The third electric field can drive the positive charge to move along the second direction X2 and be adsorbed on the second circular wiring 122. At the same time, it will not additionally adsorb negative charges into the display area 11, thereby improving the charge shielding effect.

[0155] In the second time period t2, the first clock signal CLK1 switches to a low level, the second clock signal CLK2 switches to a high level, the third electronic switch tube T3 is turned off, and the fourth electronic switch tube T4 is turned on. The low level signal of the first clock signal CLK1 is output to the third ring wiring 123, the high level signal of the second clock signal CLK2 is output to the second ring wiring 122, and the low level signal of the seventh clock signal CLK7 output by the second potential shift circuit 32 is output to the first ring wiring 121. The low level signal of the first clock signal CLK1 constitutes the low level signal VGL5 of the fifth clock signal CLK5, the high level signal of the second clock signal CLK2 constitutes the high level signal VGH4 of the fourth clock signal CLK4, and the low level signal of the seventh clock signal CLK7 constitutes the low level signal VGL3 of the third clock signal CLK3.

[0156] A second electric field in the second direction X2 is established between the first circular line 121 and the second circular line 122, and a fourth electric field in the first direction X1 is established between the third circular line 123 and the second circular line 122. Negative charges entering the glass from the outside begin to gather on the second circular line 122 under the action of the second electric field, and positive charges accumulated on the second circular line 122 in the first time period t1 begin to be released to the outside under the action of the second electric field. Since the voltage of the low-level signal VGL1 of the first clock signal CLK1 is greater than the voltage of the low-level signal of the seventh clock signal CLK7, the second voltage difference is greater than the fourth voltage difference, and the electric field strength E2 of the second electric field is greater than the electric field strength E4 of the fourth electric field. The positive charges are subjected to a greater electric field force in the second direction X2, so the positive charges accumulated on the second circular wiring 122 in the first time period t1 will be discharged to the outside under the action of the second electric field. At the same time, under the action of the second electric field and the fourth electric field, negative charges enter and gather on the second circular wiring 122, and the negative charges are discharged by the first electric field and the third electric field established again in the next time period. The first time period t1 and the second time period t2 are a complete cycle, and the subsequent cycles repeat the above actions, thereby continuously realizing the process of repeated adsorption and discharge of charges entering the first substrate 1 from the outside, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area 11, thereby enhancing the electrostatic protection capability and reliability of the display panel 100.

[0157] The third electronic switch tube T3 and the fourth electronic switch tube T4 are turned on at a high level and turned off at a low level, and corresponding types of switching devices may be used, such as NMOS tubes, NPN transistors, etc. In order to simplify the structure of the display panel 100, in an optional embodiment, the third electronic switch tube T3 and the fourth electronic switch tube T4 are N-channel thin film transistors.

[0158] The second level shift circuit may adopt a potential pull-down chip, a switch switching circuit or the like, and the specific structure is not limited.

[0159] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the display panel 100 includes a first substrate 1, the first substrate 1 includes a display area 11 and a non-display area 12 surrounding the display area 11, the periphery of the non-display area 12 is provided with a first circular routing 121, a second circular routing 122 and a third circular routing 123 which are arranged in sequence from the outside to the inside, a first electric field in the first direction X1 and a second electric field in the second direction X2 are alternately established between the first circular routing 121 and the second circular routing 122, a third electric field in the second direction X2 and a fourth electric field in the first direction X1 are alternately established between the third circular routing 123 and the second circular routing 122, an electric field strength E1 of the first electric field is not less than an electric field strength E3 of the third electric field, and an electric field strength E2 of the second electric field is greater than an electric field strength E4 of the fourth electric field, and a process of repeatedly adsorbing and discharging charges entering the first substrate 1 from the outside is continuously realized, thereby realizing electrostatic protection and blocking electrostatic charges from entering the display area 11, thereby enhancing the electrostatic protection capability and reliability of the display panel 100.

[0160] The present invention further provides a display device, which includes a display panel drive circuit 200 and a display panel 100. The specific structure of the display panel 100 refers to the above embodiment. Since the present display device adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. The display panel drive circuit 200 is connected to the display panel 100.

[0161] The display panel 100 may be an OLED display panel, an LCD display panel, etc. Figure 1 As shown, the display panel 100 is also connected to a display panel driving circuit 200 to form a display device. The display panel driving circuit 200 is used to output data signals and row scanning signals to the display panel 100 to turn on the display panel 100 row by row and display corresponding image information.

[0162] The driving circuit 200 of the display panel may be disposed outside or inside the display panel 100 and transmits driving signals to the pixel units inside the display panel 100 . The driving signals include row scanning signals, data signals, clock signals, etc.

[0163] The driving circuit 200 of the display panel may include a gate driving circuit, a source driving circuit, a timing controller and other structures. The specific structure is not limited. According to the type of different display panels 100, the display device may also select and set a backlight source and other structures accordingly.

[0164] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A first substrate, the first substrate comprising a display area and a non-display area surrounding the display area, wherein a first circular routing line, a second circular routing line and a third circular routing line are arranged in sequence from the outside to the inside at the periphery of the non-display area; The first looped routing, the second looped routing and the third looped routing are connected to a signal source circuit and receive a clock signal, a first electric field in a first direction and a second electric field in a second direction are alternately established between the first looped routing and the second looped routing, a third electric field in the second direction and a fourth electric field in the first direction are alternately established between the third looped routing and the second looped routing, the first direction is a direction from the non-display area toward the display area, and the first direction and the second direction are opposite in direction; At the same time, the direction of the electric field between the first circular routing and the second circular routing is opposite to the direction of the electric field between the third circular routing and the second circular routing, the electric field strength of the first electric field is not less than the electric field strength of the third electric field, and the electric field strength of the second electric field is greater than the electric field strength of the fourth electric field.

2. The display panel according to claim 1, wherein: The signal source circuit outputs a first clock signal and a second clock signal with opposite polarities and equal amplitudes, the first loop wiring and the third loop wiring are used to receive the first clock signal, and the second loop wiring is used to receive the second clock signal; The first spacing is smaller than the second spacing, the first spacing is the spacing between the first circular routing and the second circular routing, and the second spacing is the spacing between the second circular routing and the third circular routing.

3. The display panel according to claim 1, wherein: The signal source circuit outputs a first clock signal, a second clock signal and a third clock signal, the first ring line is used to receive the first clock signal, the second ring line is used to receive the second clock signal, and the third ring line is used to receive the third clock signal, the first clock signal and the third clock signal have the same polarity, and the first clock signal and the second clock signal have opposite polarities; The voltage of the high level signal of the first clock signal is not less than the voltage of the high level signal of the third clock signal, and the voltage of the low level signal of the first clock signal is less than the voltage of the low level signal of the third clock signal.

4. The display panel according to claim 1, wherein: The signal source circuit outputs a first clock signal and a second clock signal with opposite polarities and equal amplitudes; The display panel further includes: A clock conversion circuit, wherein the clock conversion circuit is arranged in the non-display area, and the clock conversion circuit is respectively connected to the first ring wiring, the second ring wiring, the third ring wiring and the signal source circuit; The clock conversion circuit is used to convert the first clock signal and the second clock signal into a third clock signal, a fourth clock signal and a fifth clock signal, the first ring line is used to receive the third clock signal, the second ring line is used to receive the fourth clock signal, the third ring line is used to receive the fifth clock signal, the third clock signal and the fifth clock signal have the same polarity, and the third clock signal and the fourth clock signal have opposite polarity; The voltage of the high level signal of the third clock signal is not less than the voltage of the high level signal of the fifth clock signal, and the voltage of the low level signal of the third clock signal is less than the voltage of the low level signal of the fifth clock signal.

5. The display panel according to claim 4, wherein: The clock conversion circuit comprises a first clock signal terminal, a second clock signal terminal, a first electronic switch tube and a second electronic switch tube; The first end of the first electronic switch tube and the first clock signal end are respectively connected to the first ring wiring, the first clock signal end is also connected to the control end of the first electronic switch tube, the second end of the first electronic switch tube is connected to the third ring wiring, and the first clock signal end is used to input the first clock signal; The first end of the second electronic switch tube is used to input the first voltage signal, the control end of the second electronic switch tube is respectively connected to the second clock signal end and the second ring wiring, the second end of the second electronic switch tube is connected to the third ring wiring, and the second clock signal end is used to input the second clock signal; The voltage of the low level signal of the first clock signal is lower than the voltage of the first voltage signal.

6. The display panel according to claim 4, wherein: The clock conversion circuit comprises a first clock signal terminal, a second clock signal terminal, a first electronic switch tube, a second electronic switch tube and a first potential shift circuit; The first end of the first electronic switch tube and the first clock signal end are respectively connected to the first ring wiring, the first clock signal end is also respectively connected to the control end of the first electronic switch tube and the input end of the first potential shift circuit, and the first clock signal end is used to input the first clock signal; The first end of the second electronic switch tube is connected to the output end of the first potential shift circuit, the control end and the second clock signal end of the second electronic switch tube are respectively connected to the second ring wiring, the second end of the second electronic switch tube is connected to the third ring wiring, and the second clock signal end is used to input the second clock signal; The first potential shift circuit is used to perform potential shift on the input first clock signal and output it as a sixth clock signal, the voltage of the high-level signal of the sixth clock signal is greater than the voltage of the high-level signal of the first clock signal, and the voltage of the low-level signal of the sixth clock signal is greater than the voltage of the low-level signal of the first clock signal.

7. The display panel according to claim 4, wherein: The clock conversion circuit comprises a first clock signal terminal, a second clock signal terminal, a first resistor, a third electronic switch tube and a fourth electronic switch tube; The first clock signal end is respectively connected to the third ring wiring, the first end of the first resistor and the first end of the third electronic switch tube, the second end of the first resistor is connected to the control end of the third electronic switch tube, the second end of the third electronic switch tube is connected to the first ring wiring, and the first clock signal end is used to input the first clock signal; The first end of the fourth electronic switch tube is used to input the second voltage signal, the second end of the fourth electronic switch tube is connected to the first ring line, the control end of the fourth electronic switch tube and the second ring line are respectively connected to the second clock signal end, and the second clock signal end is used to input the second clock signal; The voltage of the low level signal of the first clock signal is greater than the voltage of the second voltage signal.

8. The display panel according to claim 4, wherein: The clock conversion circuit includes a first clock signal terminal, a second clock signal terminal, a first resistor, a third electronic switch tube, a fourth electronic switch tube and a second potential shift circuit; The first clock signal end is respectively connected to the third ring wiring, the first end of the first resistor, the first end of the third electronic switch tube and the input end of the second potential shift circuit, the second end of the first resistor is connected to the control end of the third electronic switch tube, the second end of the third electronic switch tube is connected to the first ring wiring, and the first clock signal end is used to input the first clock signal; The first end of the fourth electronic switch tube is connected to the output end of the second potential shift circuit, the second end of the fourth electronic switch tube is connected to the first ring wiring, the control end of the fourth electronic switch tube is respectively connected to the second ring wiring and the second clock signal end, and the second clock signal end is used to input the second clock signal; The second potential shift circuit is used to perform potential shift on the input first clock signal and output it as a seventh clock signal, the voltage of the high-level signal of the seventh clock signal is lower than the voltage of the high-level signal of the first clock signal, and the voltage of the low-level signal of the seventh clock signal is lower than the voltage of the low-level signal of the first clock signal.

9. The display panel according to claim 1, wherein: The signal source circuit is arranged in the non-display area.

10. A display device, characterized in that: The invention comprises a display panel driving circuit and a display panel as claimed in any one of claims 1 to 9, wherein the display panel driving circuit is connected to the display panel.

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