Integrated circuit and method for data storage

Abstract

An integrated circuit and a method for data storage. The integrated circuit includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary chip select signal via a primary chip select (CS) line connected to the primary memory die. The secondary memory die is coupled to a bus that does not include the primary chip select line, and to a secondary chip select line carrying a secondary chip select signal provided by the primary memory die. The primary memory die is configured to: receive a command via the bus when the primary chip select signal is active; in response to identifying that the command is sent to the primary memory die, executing the command within the primary memory die; and in response to identifying that the command is addressed to the secondary memory die, causing the secondary memory die to execute the command by transmitting the primary chip select signal on the secondary chip select line.

Description

Technical Field

[0001] Embodiments described herein relate generally to secure data storage, and more particularly, to methods and systems for secure storage in multi-die packages. Background Art

[0002] Various systems store data in storage devices that include multiple memory dies stacked in a common package.

[0003] The use of memory die stacked in a common package is a known technology. For example, U.S. Patent 9,245,590 describes that any number of Serial Peripheral Interface (SPI) flash memory die can be stacked and packaged to achieve any one or combination of various capabilities, such as low bit cost, high density storage, code shadowing of RAM, and fast random access to "execute in place" applications, while maintaining the advantages of the SPI interface. When manufacturing the device, each stacked die is assigned a unique identifier or "die ID" relative to the other stacked dies in the package. During normal operation, the unique die ID is used for die selection commands to enable any stacked die to respond to subsequent commands on the SPI interface, while preventing other stacked dies in the package from responding to subsequent commands, but is used for certain "common" commands that include die selection commands to support parallel operations by stacked dies.

[0004] As another example, U.S. Pat. No. 11,194,726 describes methods, systems, and devices for stacking memory dies and combining access operations. The device may include multiple memory dies. One die may be configured as a master device and another die may be configured as a slave device. The master device may communicate with a host device. The slave device may be coupled to the master device. The device may include a first die (e.g., a master device) and a second die (e.g., a slave device). The first die may be coupled to the host device and configured to output a data set in response to a read command. The first die may supply a first subset of data and obtain a second subset of data from the second die. Summary of the invention

[0005] Embodiments described herein provide an integrated circuit (IC) comprising a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary chip select (CS) line connected to the primary memory die. The secondary memory die is coupled to a bus that does not include a primary CS line and is coupled to a secondary CS line that carries a secondary CS signal provided by the primary memory die. The primary memory die is configured to: receive a command via the bus when the primary CS signal is active; execute the command within the primary memory die in response to recognizing that the command is addressed to the primary memory die; and cause the secondary memory die to execute the command by transmitting the primary CS signal as a secondary CS signal on the secondary CS line in response to recognizing that the command is addressed to the secondary memory die.

[0006] In some embodiments, the primary memory die includes a local memory selectable by a local valid signal carried on a local valid line, and the primary memory die is configured to execute a command by: (i) transmitting a primary CS signal as a local valid signal on the local valid line; (ii) deactivating a secondary CS signal provided to the secondary memory die. In other embodiments, the IC includes another secondary die coupled to a bus that does not include a primary CS line and to another secondary CS line carrying another secondary CS signal provided by the primary memory die, and the primary die is configured to cause the other secondary die to execute a command by: (i) transmitting the primary CS signal as another secondary CS signal on the another secondary CS line; (ii) deactivating the secondary CS signal provided to the secondary die; (iii) deactivating a local valid signal provided to the local memory of the primary die. In yet other embodiments, the primary memory die and the secondary memory die have respective first and second different memory types, each memory type selected from a list comprising at least: (i) a NAND flash memory type; or (ii) a NOR flash memory type.

[0007] In an embodiment, the primary memory die and the secondary memory die support respective first and second different access protocols, and the primary memory die is configured to present the second access protocol of the secondary memory die to a host coupled to the bus. In another embodiment, the primary memory die is configured to: in response to receiving a die select command specifying a selected memory die between the primary memory die and the secondary memory die, cause the selected memory die to execute one or more commands received after the die select command. In yet another embodiment, the primary memory die and the secondary memory die are mapped to different respective address sub-ranges of a common address space, and the primary memory die is configured to recognize an address parameter in a received command, and, depending on the address range to which the address parameter belongs, execute the received command by the primary memory die or by the secondary memory die.

[0008] In some embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls the second CS signal to block access to the secondary memory die for all incoming commands. In other embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls the second CS signal to allow access to the secondary memory die for a partial subset of commands supported by the secondary memory die. In still other embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls the second CS signal to allow full access to the secondary memory die for all commands supported by the secondary memory die, while only selectively executing commands that modify the access mode.

[0009] In an embodiment, the primary memory die is configured to locally store boot code for a host coupled to the bus and manage secure access to the stored boot code. In another embodiment, the primary memory die is configured to act as a root of trust (RoT) for an underlying system including the IC for securing storage operations sent to the secondary memory die.

[0010] According to embodiments described herein, there is further provided a method for data storage, the method comprising: in an integrated circuit (IC), the integrated circuit comprising: a primary memory die coupled to a bus providing a primary chip select (CS) signal via a primary CS line connected to the primary memory die; and a secondary memory die coupled to the bus not including the primary CS line and coupled to a secondary CS line carrying a secondary CS signal provided by the primary memory die; receiving a command via the bus by the primary memory die when the primary CS signal is active. In response to recognizing that the command is addressed to the primary memory die, executing the command within the primary memory die, and in response to recognizing that the command is addressed to the secondary memory die, causing the secondary memory die to execute the command by transmitting the primary CS signal as the secondary CS signal on the secondary CS line. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 shows a block diagram of a computer system including multiple memory dies stacked within a common package according to embodiments described herein;

[0012] Figure 2 A flow chart illustrating a method for executing commands in a multi-die storage device according to embodiments described herein;

[0013] Figure 3 A timing diagram illustrating signals generated during execution of a read command in a multi-die memory device according to embodiments described herein.

[0014] Description of Figure Numbers

[0015] 20: Computer systems;

[0016] 24: host;

[0017] 28: Integrated circuit / storage device;

[0018] 32: bus;

[0019] 40: primary memory die;

[0020] 42: local storage;

[0021] 46: CS logic;

[0022] 50: secondary memory die;

[0023] 54: memory;

[0024] 100, 104, 108, 112: steps;

[0025] 150: Operation code parameters;

[0026] 154: address parameter;

[0027] 158: primary CS signal;

[0028] 162: Time instance;

[0029] A0: lowest address bit;

[0030] A31: highest address bit;

[0031] LSb: least significant bit;

[0032] MSb: Most significant bit. DETAILED DESCRIPTION

[0033] Embodiments described herein provide improved methods and systems for managing secure access to multiple memory dies stacked in a common package. In the disclosed embodiments, one memory die controls access to other memory dies by controlling its corresponding chip select (CS) input. The disclosed embodiments are applicable to different types of memory dies having different corresponding command sets and / or supporting different access protocols.

[0034] In various systems, a host is coupled to a storage device including multiple memory dies via a bus. The bus typically includes one or more input / output (IO) lines for carrying opcodes, addresses, and data, as well as a CS signal that becomes active during commands.

[0035] Each memory die has a CS input that, when active, selects that memory die for executing a command. A memory die can complete execution of a supported command while its CS input is active for the entire command duration, and will typically abandon command execution if the CS input becomes inactive before execution is complete. A memory die typically ignores unsupported commands, even when its CS input is active for the entire command duration.

[0036] Various architectures can be used to access individual memory dies within a package. For example, the entire bus signal including the bus CS signal can be coupled in parallel to all memory dies. This type of technology is used by Winbond to , and is implemented in Winbond's W25M product family. When a command is sent over the bus, all memory die initially receive the command, and each memory die independently decides whether to execute the command or abort the command. This parallel bus approach typically requires that the memory dies will be of the same memory type and share common rules for deciding whether to execute or abort a command, and is therefore not suitable when different types of memory dies are mixed within a package.

[0037] In another approach, the host bus may be coupled to a mediation controller that terminates the host bus and generates separate bus signals to the different memory dies, including respective CS signals. The host may communicate with each memory die only indirectly via the controller. This approach is typically highly complex and expensive because the controller handles multiple complete buses for respective memory dies.

[0038] In the disclosed embodiment, the bus is coupled in parallel to multiple memory dies, excluding a CS signal connected to only one of the memory dies (referred to herein as the "primary memory die"). The primary memory die controls access to the other memory dies (also referred to herein as the "secondary dies") by providing a separate CS signal to each secondary die.

[0039] Consider an integrated circuit (IC) including one primary memory die and one or more secondary memory die. The primary memory die is coupled to a bus providing a primary chip select (CS) signal via a primary CS line connected only to the primary memory die. The secondary memory die is coupled to a bus that does not include a primary CS line and is coupled to a respective secondary CS line carrying a respective secondary CS signal provided by the primary memory die. When the primary CS signal is active, the primary memory die receives a command via the bus and, in response to recognizing that the command is addressed to the primary memory die, executes the command within the primary memory die. Otherwise, in response to recognizing that the command is addressed to the secondary memory die, the primary memory die causes a given secondary memory die to execute the command by transmitting the primary CS signal as a secondary CS signal on a secondary CS line of the given secondary memory die.

[0040] For clarity, some embodiments described below refer to packages containing a primary memory die and a single secondary die. However, the disclosed technology is similarly applicable to packages containing multiple secondary memory dies.

[0041] In some embodiments, the primary memory die includes local memory selectable by a local "valid signal" carried on a local "valid line", and the primary memory die executes a command by: (i) transmitting the primary CS signal as the local valid signal on the local valid line; and (ii) deactivating the secondary CS signal provided to the secondary memory die.

[0042] In other embodiments, the IC includes another secondary die coupled to a bus that does not include a primary CS line and coupled to another secondary CS line that carries another secondary CS signal provided by the primary memory die. In these embodiments, the primary die causes the other secondary die to execute a command by: (i) transmitting the primary CS signal as another secondary CS signal on another secondary CS line; (ii) deactivating the secondary CS signal provided to the secondary die; and (iii) deactivating a local valid signal provided to a local memory of the primary die.

[0043] In the disclosed architecture, at least some of the primary memory dies and the secondary memory dies may have different respective memory types, each memory type selected from a list including at least: (i) a NAND flash type; and (ii) a NOR flash type.

[0044] In an embodiment, the primary memory die and the secondary memory die support respective first and second different access protocols, and the primary memory die presents the second access protocol of the secondary memory die to a host coupled to the bus.

[0045] The primary memory die may select a target memory die for executing the received command (or one or more subsequent commands) using any suitable method (eg, based on a dedicated die select command or based on address information included in the command).

[0046] In some embodiments, the primary die may operate in one of three access modes, namely, a "Standalone" mode, a "Restricted-Access" mode, and a "Full-Access" mode. In the Standalone mode, the primary memory die controls the second CS signal to block access to the secondary memory die for all incoming commands. In the Restricted-Access mode, the primary memory die controls the second CS signal to allow access to the secondary memory die for a partial subset of the corresponding commands supported by the secondary memory die. In the Full-Access mode, the primary memory die controls the second CS signal to allow full access to the secondary memory die for all commands supported by the secondary memory die, while only selectively executing (by the primary memory die) commands that modify the access mode.

[0047] The disclosed architecture can be used, for example, for secure booting. In such example embodiments, the primary memory die locally stores boot code for a host coupled to a bus, and manages secure access to the stored boot code, such as when storing, updating, and uploading the boot code.

[0048] In an embodiment, the primary memory die acts as a root of trust (RoT) for the underlying system including the IC for securing storage operations to the secondary memory die. For example, the primary memory die can provide write protection and various cryptographic services such as encryption and data authentication to the secondary memory die.

[0049] In the disclosed technology, the primary memory die controls access to the secondary memory die by controlling its corresponding CS input. The disclosed architecture and related embodiments produce low complexity, low power consumption, and fast access to the secondary memory die. In addition, memory dies of different storage technologies are supported, such as mixing flash NOR dies with flash NAND dies in the same package. Since the primary die manages each command die selection, the memory dies do not need to follow common rules and / or otherwise cooperate with each other for selecting a target die, which produces a simplified and flexible implementation.

[0050] Reference Figure 1 , computer system 20 includes a host 24 coupled to an integrated circuit (IC) 28 via a bus 32 (also referred to as a link or interface), which in this example implements a storage device. Bus 32 includes a plurality (e.g., 'n') of input / output (IO) lines, a clock line denoted as "CLK", and a chip select (CS) line denoted as "CS-0". Bus 32 may include, for example, a serial peripheral interface (SPI). Alternatively, other suitable bus types may be used, such as extended SPI, extended SPI (xSPI), and inter-integrated circuit (IC) bus. 2 C) bus.

[0051] In computer system 20, host 24 typically communicates commands with storage device 28 via bus 32. Communication may include sending opcodes, sending addresses, and sending and / or receiving data.

[0052] The computer system 20 may be used in various applications, such as Internet of Things (IoT) devices, automotive applications, PC / server Basic Input-Output System (BIOS), industrial controllers, etc.

[0053] The storage device 28 includes a memory die 40, denoted as "die-0," which includes a local memory 42 and a CS logic 46. The memory die 40 is also referred to herein as a "primary memory die" or simply a "primary die." The storage device 28 also includes one or more memory dies 50, each of which includes a memory 54. The memory die 50 is denoted as "die-m," where 'm' represents an integer greater than 0. The memory die 50 is also referred to herein as a "secondary memory die" or simply a "secondary die."

[0054] The primary die and each secondary die have a CS input that, when active, selects the corresponding memory die. Note that selecting a memory die means gaining access to the internal memory of the memory die. Figure 1 , storage device 28 includes two secondary dies, indicated as Die-1 and Die-2, but in alternative embodiments, the storage device may include a single secondary die or more than two secondary dies.

[0055] exist Figure 1 In the architecture of , the CLK line and IO line of bus 32 are connected in parallel between the host 24 and each of the primary die and the secondary die. In contrast, the CS-0 line of bus 32 (also referred to herein as the "primary CS line") is connected between the host and the CS input of the primary die, but is not connected to the CS input of the secondary die. The memory select line (also referred to herein as the "valid line") is connected between the CS logic and the local memory 42. The CS lines, denoted "CS-1" and "CS-2" (also referred to herein as the "secondary CS lines"), are connected between the CS logic and the CS input of the corresponding secondary die. The architecture described above allows CS logic 46 to control access to its local memory (42) as well as the secondary die (50) and its memory (54).

[0056] In the following description, the CS signal carried on the primary CS line is also referred to herein as the “primary CS signal,” the CS signal carried on the secondary CS line is also referred to herein as the “secondary CS signal,” and the memory select signal carried on the valid line is also referred to herein as the “valid signal.” As will be described below, the CS logic controls the valid signal for accessing the local memory 42 of the primary die, and controls the secondary CS signal for accessing the secondary die.

[0057] The local memory 42 of the primary die 40 and the memory 54 of the secondary die 50 may include any suitable type of memory. In the present example, the local memory 42 for die-0 includes a NOR flash memory device, while the memory 54 for die-1 and die-2 includes a NAND flash memory device. However, in other embodiments, any other suitable combination of memory types may also be used. For example, the local memory 42 of the primary die and the memory 54 of all secondary dies may have the same memory type. As another example, two (or more than two) memories 54 of a secondary die may have different corresponding memory types. Although in the context of the present invention, the main memory types used are NOR die and NAND die, this is not mandatory, and other suitable memory types (volatile or non-volatile) may also be used.

[0058] When the host 24 sends a command via the bus, the primary die controls the valid and secondary signals so that the command is initially received by the primary die and all secondary die, while the primary CS signal (sent on the CS-0 line) is active. As the command progresses (e.g., after receiving an opcode parameter), the CS logic determines the target die to which the command is sent, and controls the valid and secondary CS signals so that the command will be executed by the target die and abandoned by all other memory die.

[0059] The method for determining the target die will be described in detail below.

[0060] Execution of commands in a multi-die storage device

[0061] Reference Figure 2 , the method will be described as consisting of Figure 1 For example, when all memory dies in the storage device support the same command set and command format, Figure 2 The method is applicable.

[0062] The method begins at a command receive step 100 where die-0 receives a command from host 24 via bus 32. The command is carried on bus IO line using bus CLK signal. Furthermore, it is assumed that the primary CS signal carried on the primary CS line (CS-0) is active during the command.

[0063] In response to the primary CS signal, the CS logic 46 of die-0 initially selects the local memory 42 and all secondary dies 50 (die-1 and die-2 in this example). To this end, the CS logic transmits the primary CS signal as a valid signal on the internal valid line and transmits the primary CS signal as a secondary CS signal on the secondary CS lines of the secondary dies. Thus, the local memory 42 of die-0 and the memory 54 of the secondary dies receive at least the opcode parameters of the command, and thus, if selected as the target die, each of the primary die and the secondary die is ready to execute the command.

[0064] At die selection step 104, the CS logic of die-0 determines the target die to which the command is sent. Die-0 may determine the target die based on information carried in an opcode parameter and / or an address parameter (if available) in the current or previous command, for example.

[0065] When Die-0 is selected as the target die at step 104, the method proceeds to primary die execution step 108. Otherwise, Die-1 or Die-2 is the target die, and the method proceeds to secondary die execution step 112.

[0066] At step 108, die-0 executes the command via CS logic that: (i) propagates the (active) primary CS signal as a valid signal on the local valid line of local memory 42; and (ii) deactivates the secondary CS signals of all secondary dies (die-1 and die-2 in this example). Since the secondary die is deselected, the secondary die aborts execution of the command.

[0067] At step 112, die-0 causes the target die (in this example, die-1 or die-2) to execute the command through CS logic that performs the following operations: (i) transmits the primary CS signal as a secondary CS signal on the secondary CS line of the target die; (ii) deactivates the secondary CS signals of the other secondary dies; and (iii) deactivates the local valid signal of die-0. Any suitable method can be used to perform the deactivation of the valid signal or the secondary CS signal, such as using a logic OR gate when the signal is low active, or using a logic AND gate when the signal is high active.

[0068] After each of steps 108 and 112, the method loops back to step 100 to receive subsequent commands.

[0069] Figure 2The method is given by way of example, and other suitable methods may also be used. For example, when the command includes only an opcode command (eg, a configuration command), the primary die may control the valid signal and the secondary CS signal to enable multiple memory dies to execute the command in parallel with each other.

[0070] Reference Figure 3 , will target host 24, for example, using Figure 2 A timing diagram is described for a system (eg, 20) that executes a read command in a method.

[0071] In this example, bus 32 includes an SPI having an IO0 line for sending commands to memory device 28 and an IO1 line for receiving data from the memory device. As shown in the figure, the command has an 8-bit opcode parameter 150 sent starting with the Most Significant bit (MSb) and ending with the Least Significant bit (LSb). The opcode parameter is followed by a 32-bit address parameter 154 sent starting with the highest address bit (A31) and ending with the lowest address bit (A0). In response to the read command, the memory device sends Byte-0...Byte-m of the data read from the target die back to the host via the IO1 line.

[0072] The primary CS signal 158 sent from the host via the primary CS line (CS-0) of the bus becomes active during the command. Figure 3 In the example of , the primary CS signal becomes active (eg, changes from high to low in this example) just before the start of the MSb of the opcode, and remains active until the memory device completes sending the mth data byte via the IO1 line.

[0073] exist Figure 3 In the example of FIG. 1 , assume that Die-0 determines the target die based on some upper address bits of the address parameter at time instance 162. The timing diagram depicts the valid signal and the secondary CS signal when (i) the target die is the primary die Die-0 (170) and (ii) the target die is the secondary die Die-2 (174).

[0074] When the primary CS 158 signal becomes active, the CS logic first transmits the primary CS signal as a valid signal on the valid line of die-0, and transmits it as a secondary signal on the secondary CS lines of both die-1 and die-2. This enables all memory dies to receive at least part of the opcode parameters and address parameters.

[0075] When die-0 is the target die, the CS logic continues to transmit the primary CS signal as a valid signal on the valid line. In addition, the CS logic causes die-1 and die-2 to abandon the command by deactivating the secondary CS signal of the secondary die. When die-2 (for example) is the target die, the CS logic causes die-2 to execute the command by transmitting the primary CS signal as a secondary signal on the secondary CS line of die-2. The CS logic also causes die-1 and die-0 to abandon the command by deactivating the secondary CS signal of die-1 and the valid signal of die-0, respectively.

[0076] Figure 3 The timing diagrams shown in and described above are referenced by way of example. Other suitable timing diagrams may be used in alternative embodiments. For example, in some embodiments, the bus width operating mode may be quad or octal, and therefore additional IO lines may be added. In this case, multiple bits of the command will be transmitted per clock cycle. Although Figure 3 32-bit address parameters are shown, but other address lengths such as 24-bit addresses may also be used. As another example, although Figure 3 The timing diagram in depicts a low-activity CS signal, but in alternative embodiments, a high-activity CS signal may also be used.

[0077] After receiving a command by storage device 28, the primary die determines (e.g., using CS logic 46) which of the memory dies within the storage device will execute the command. The memory die selected for executing a given command is referred to herein as the "target die" for the given command. The target die may be one of the primary die or the secondary die. In general, a command sequence may contain commands addressed to the same memory die or to two or more different memory dies. In the disclosed embodiment, primary die 40 (die-0) handles the selection of a single target die for each command.

[0078] The primary die may determine the target die for a given command in a variety of ways, as will be described below. In one embodiment, a respective die identifier is pre-assigned to each of the memory dies, and the primary die selects the target die in response to receiving a dedicated die select command that specifies the identifier of the target die. The dedicated command may specify the die identifier, for example, within the opcode parameter or in a separate parameter following the opcode parameter. The die select command is processed by the primary die, but is not part of the command set supported by the secondary die, and is therefore ignored by the secondary die.

[0079] In an embodiment, in response to a die select command, the primary die controls the valid signal and the secondary CS signal so that subsequent commands will be executed by the target die (and typically not by other die). The primary die continues to monitor for subsequently received commands, even when the target die is the secondary die, and upon receiving another die select command, reselects the target die accordingly.

[0080] Some commands, such as read, program, and erase commands, contain address parameters. For such commands, the primary die may determine the target die based on the address parameters. In this method, the primary die and the secondary die are mapped into a common address space that is partitioned into a plurality of address sub-ranges, wherein each of the memory dies is mapped into a respective address sub-range of the address space. In some embodiments, upon receiving a command with an address parameter, the primary die determines the target die based on at least a portion of the address parameter (e.g., the most significant (MS) byte of the address) by identifying the address sub-range to which the address parameter belongs. The address-based target die selection as described above is applicable, but not limited to, to storage devices in which all memory dies share the same command set and command format.

[0081] As mentioned above Figure 1 As described in , a storage device may include memory dies of various memory types that comply with different command sets, different command formats, and / or different access protocols, such as when NOR and NAND flash memory devices are mixed within the same storage device. In such embodiments, a host accessing a target die needs to use commands from a command set supported by the corresponding target die. Alternatively or in addition, a primary die may present to the host an access protocol used by a secondary die having a memory type different from the memory type of the primary die. This allows the host to communicate with all memory dies using a common access protocol.

[0082] Consider, for example, a read operation performed in a storage device 28, where the primary die is a NOR flash device and the secondary die is a NAND flash device. A read (or write) command for a NOR flash device typically carries a full address parameter (e.g., a 24-bit or 32-bit memory address) for direct access. In contrast, a read operation applied to a NAND flash device is typically indirect and includes a "page load" command followed by one or more "page read" commands. Within the target NAND device, a page load command loads a page from memory into a local read buffer (not shown) of the target NAND device. A page may contain several kilobytes of data (e.g., 4 kilobytes or any other suitable size). A page read command reads the data loaded by the previous page load command from the read buffer. A page load command typically carries only the 16 most significant bits of the address parameter (e.g., A31 ... A16), while a page read command typically carries only the 16 least significant bits of the address parameter (e.g., A15 ... A0). In this example, the primary die selects the given target die when the portion of the address carried in the page load command is within the sub-range assigned to the given target die.

[0083] The page load command is usually executed by all secondary NAND dies. After determining the NAND target die, the primary die controls the valid signal and the secondary CS signal so that subsequent page read commands are only executed by the target NAND die and abandoned by the primary die and other secondary dies. In addition, the primary die monitors subsequent commands received via the bus and, upon detecting a subsequent page load command, reselects a target die based on the address parameters carried in the subsequent page load command.

[0084] When two or more memory dies have different corresponding storage sizes, various address mappings can be used. Consider, for example, a storage device that includes a 128-megabit primary NOR die and one or more 1-gigabit secondary NAND dies. This architecture is suitable, for example, for storing relatively small boot codes in a NOR device and using the secondary NAND die to extend the entire storage space.

[0085] In one such embodiment, the primary die may be mapped to an address sub-range beyond the address sub-range assigned to the secondary NAND die. For example, in the case of a single 1 Gigabit secondary NAND die, the NAND die is mapped to the address sub-range 0000 0000h-07FF FFFFh, and the 128 Mbit primary NOR die is mapped to the address range 0800_0000h-08FF_FFFFh.

[0086] In another embodiment, the address sub-range assigned to the primary NOR die overlaps the address range assigned to the secondary NAND die. For example, a 128-megabit primary NOR die is mapped to an address sub-range given by 0000_0000h-00FF_FFFFh, and a single 1-gigabit secondary NAND die is mapped to an address sub-range given by 0100_0000h-07FF_FFFFh. In this case, the lower 128-megabit addresses of the secondary die are inaccessible.

[0087] In some embodiments, the primary die NOR presents the access protocol of the secondary die NAND to the host. To this end, the primary die NOR implements the page load and page read commands of the NAND die so that a host with a NAND flash controller can access the primary die NOR and the secondary die NAND using the same command set and format (at least for read operations). In these embodiments, the local memory of the primary die NOR appears to the host as a NAND device, and thus software executed by the host can access memory in the storage device when accessing a monolithic (single die) NAND flash device. In some embodiments, before accessing either the primary die or the secondary NAND die in NAND format, it is required that the host loads a suitable driver designed to access NAND memory, for example, from the storage device.

[0088] Certain commands may be too short to allow the primary die enough time to determine the target die based on the address parameters. For example, a block erase command for a NAND device issued in xSPI octal dual transfer rate (DTR) bus mode (also known as "8d-8d-8d" mode - meaning that the command, address, and data are transferred as 8-bit wide DTR) requires one clock cycle for the opcode followed by an additional clock cycle for the address. In this case, the secondary die may undesirably execute the erase command before the primary die determines the target die based on the address parameters (in response to the opcode and address parameters). In some embodiments, to avoid such erroneous command execution, the primary die limits the use of the address-based target selection method to selected commands (e.g., to read operations only), and blocks commands that may result in erroneous execution (e.g., erase operations and program operations).

[0089] Note that unlike erase and program commands, in a read command the die continues to process the command after receiving the address, prepares a response, and then begins transmitting the response back to the host, which may leave enough time for a die other than the target die to terminate the command.

[0090] In some embodiments, commands that modify the content stored in the storage device, such as program commands and erase commands, are preceded by a write enable command. The primary die monitors the commands received via the bus, and when a write enable command (or other qualifying condition) is detected when the target die is one of the secondary die, the primary die blocks further access to the secondary die, for example, until the following system reset, or depending on a predefined flow implemented within the primary die. The primary die thus blocks any command sequence that begins with a write enable command and is followed by a program or erase command, which means that the secondary die is essentially write protected. The primary die thus manages the write protection of the secondary die, even when the secondary die itself does not support an inherent write protection mechanism.

[0091] In some embodiments, the primary die supports security functions that can be used to provide write protection (and other security features) to the secondary die, even when the secondary die does not support inherent security functions. For example, the primary die can execute a security command protected by, for example, a signature, password, and / or other user authentication mechanism to gain access to the secondary die.

[0092] In some embodiments, the primary die supports an access mode selectable from a plurality of predefined modes. In an example embodiment, the primary die supports triple access modes, including (i) "standalone mode", (ii) "restricted access" mode, and (iii) "full access" mode. In an embodiment, the primary die 40 switches among the access modes by controlling the host 24.

[0093] In standalone mode, the primary die allows access only to its local memory and blocks access to any of the secondary dies. This mode is useful, for example, in systems where the host boots from the primary die (e.g., a NOR flash device). In standalone mode, the primary die selects itself as the target die for all incoming commands, and therefore the target die does not need to be determined on the fly.

[0094] After the boot process is complete, the primary die may be switched to a restricted access mode in which the primary die (e.g., NOR) allows access (e.g., read access) to the secondary die (e.g., NAND) for certain commands containing address parameters. In the restricted access mode, the primary die may present the secondary die's access protocol to the host, as described above.

[0095] In full access mode, the primary die allows access to the secondary die for all supported commands. This mode can be used to program, erase, and / or configure the secondary die. In full access mode, the primary die monitors received commands and responds only to storage commands that modify the access mode to restricted access mode or standalone mode.

[0096] In some embodiments, the standalone mode acts as the default access mode after a reset. In such embodiments, in response to a reset event, the primary die automatically begins operating in standalone mode, allowing the host to boot from the primary die (e.g., NOR). At a later appropriate time, such as after the boot is complete, the host loads firmware (Firmware, FW) code containing a driver for accessing the NAND die from a storage device and switches to a restricted access or full access mode. In other embodiments, after a reset, the restricted access mode or full access mode may serve as the default mode. In this case, after a reset, the primary die begins operating in a restricted access mode or a full access mode. For example, this embodiment is useful when the host boots from a secondary die instead of a primary die.

[0097] In an example embodiment, the primary die includes a security device stacked in the same package as one or more secondary dies. In such embodiments, the primary die acts as a root of trust (RoT) for the system. The storage device may rely on the security functions of the primary die to store, protect, and update the boot code stored in the primary die.

[0098] The above embodiments are given by way of example, and other suitable embodiments may also be used. For example, although some of the above embodiments refer to a storage device comprising a NOR primary die and one or more NAND secondary dies, this architecture is not mandatory, and in other embodiments, other suitable combinations of NOR, NAND and / or other memory types may also be used.

[0099] The configuration of computer system 20 (including host 24, storage device 28 and its components, such as primary die 40, local memory 42 and CS logic 46, and secondary die 50 and its memory 54) is an example configuration shown only for conceptual clarity. Any other suitable computer, host and memory die configuration may be used in alternative embodiments.

[0100] The different subunits of the storage device 28 may be implemented using suitable hardware, such as in one or more Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs), using software, using hardware, or using a combination of hardware and software elements.

[0101] The storage device 28 may include one or more general purpose processors programmed with software to perform the functions described herein. The software may be downloaded to the processor in electronic form, via a network or from a host, for example, or it may alternatively or additionally be provided and / or stored on non-transitory tangible media (e.g., magnetic, optical or electronic memory).

[0102] It should be understood that the embodiments described above are cited by way of example, and the present invention is not limited to what has been specifically shown and described above. In fact, the scope includes both combinations and sub-combinations of the various features described above, as well as variations and modifications of the present invention that will occur to a person skilled in the art after reading the foregoing description and that are not disclosed in the prior art. Except for the definition of any term in these incorporated documents that conflicts with the definition explicitly or implicitly described in this specification, only the definition in this specification should be considered, and the documents incorporated by reference in this patent application are considered to be an integral part of the application.

Claims

1. An integrated circuit, comprising: a primary memory die coupled to a bus providing a primary chip select signal via a primary chip select line connected to the primary memory die; as well as a secondary memory die coupled to the bus not including the primary chip select line and to a secondary chip select line carrying a secondary chip select signal provided by the primary memory die, wherein the primary memory die is configured as: receiving a command via the bus when the primary chip select signal is active; in response to identifying that the command is addressed to the primary memory die, executing the command within the primary memory die; as well as In response to identifying that the command is addressed to the secondary memory die, causing the secondary memory die to execute the command by transmitting the primary chip select signal as the secondary chip select signal on the secondary chip select line.

2. An integrated circuit according to claim 1, wherein the primary memory die includes a local memory capable of being selected by a local valid signal carried on a local valid line, and wherein the primary memory die is configured to execute the command by: i. transmitting the primary chip select signal as the local valid signal on the local valid line; and ii. deactivating the secondary chip select signal provided to the secondary memory die.

3. An integrated circuit according to claim 2, wherein the integrated circuit includes another secondary die, which is coupled to the bus that does not include the primary chip select line and is coupled to another secondary chip select line carrying another secondary chip select signal provided by the primary memory die, and wherein the primary die is configured to cause the other secondary die to execute the command by: i. transmitting the primary chip select signal as the other secondary chip select signal on the other secondary chip select line; ii. deactivating the secondary chip select signal provided to the secondary die; and iii. deactivating the local valid signal provided to the local memory of the primary die.

4. An integrated circuit according to claim 1, wherein the primary memory die and the secondary memory die have corresponding first different memory types and second different memory types, each memory type is selected from a list including at least the following: i. NAND flash memory type; and ii. OR non-flash memory type.

5. The integrated circuit of claim 1 , wherein the primary memory die and the secondary memory die support respective first and second different access protocols, and wherein the primary memory die is configured to present the second access protocol of the secondary memory die to a host coupled to the bus.

6. The integrated circuit of claim 1 , wherein the primary memory die is configured to, in response to receiving a die select command specifying a selected memory die between the primary memory die and the secondary memory die, cause the selected memory die to execute one or more commands received after the die select command.

7. An integrated circuit according to claim 1, wherein the primary memory die and the secondary memory die are mapped to different corresponding address sub-ranges of a common address space, and wherein the primary memory die is configured to recognize an address parameter in the received command and, depending on the address range to which the address parameter belongs, execute the received command by the primary memory die or by the secondary memory die.

8. The integrated circuit of claim 1, wherein the primary memory die is configured to operate according to an access mode in which the primary memory die controls a second chip select signal to block access to the secondary memory die for all incoming commands.

9. An integrated circuit according to claim 1, wherein the primary memory die is configured to operate according to an access mode in which the primary memory die controls a second chip select signal to allow access to the secondary memory die for a partial subset of the commands supported by the secondary memory die.

10. An integrated circuit according to claim 1, wherein the primary memory die is configured to operate according to an access mode, in which the primary memory die controls a second chip select signal to allow full access to the secondary memory die for all commands supported by the secondary memory die, while only selectively executing commands that modify the access mode.

11. The integrated circuit of claim 1, wherein the primary memory die is configured to locally store boot code for a host coupled to the bus and to manage secure access to the stored boot code.

12. The integrated circuit of claim 1, wherein the primary memory die is configured to serve as a root of trust for an underlying system including the integrated circuit for securing memory operations directed to the secondary memory die.

13. A method for data storage, comprising: In an integrated circuit, the integrated circuit includes: a primary memory die coupled to a bus providing a primary chip select signal via a primary chip select line connected to the primary memory die; and a secondary memory die coupled to the bus not including the primary chip select line and coupled to a secondary chip select line carrying a secondary chip select signal provided by the primary memory die, receiving a command via the bus by the primary memory die when the primary chip select signal is active; In response to identifying that the command is addressed to the primary memory die, executing the command within the primary memory die; and In response to identifying that the command is addressed to the secondary memory die, causing the secondary memory die to execute the command by transmitting the primary chip select signal as the secondary chip select signal on the secondary chip select line.

14. A method for data storage according to claim 13, wherein the primary memory die includes a local memory capable of being selected by a local valid signal carried on a local valid line, and wherein executing the command within the primary memory die includes executing the command by: i. transmitting the primary chip select signal as the local valid signal on the local valid line; and ii. deactivating the secondary chip select signal provided to the secondary memory die.

15. A method for data storage according to claim 14, wherein the integrated circuit includes another secondary die, the other secondary die is coupled to the bus that does not include the primary chip select line and is coupled to another secondary chip select line carrying another secondary chip select signal provided by the primary memory die, and the method includes causing the other secondary die to execute the command by: i. transmitting the primary chip select signal as the other secondary chip select signal on the other secondary chip select line; ii. deactivating the secondary chip select signal provided to the secondary die; and iii. deactivating the local valid signal provided to the local memory of the primary die.

16. A method for data storage according to claim 13, wherein the primary memory die and the secondary memory die have corresponding first different memory types and second different memory types, each memory type is selected from a list including at least the following: i. NAND flash memory type; and ii. OR non-flash memory type.

17. A method for data storage according to claim 13, wherein the primary memory die and the secondary memory die support respective first different access protocols and second different access protocols, and the method includes presenting, by the primary die, the second access protocol of the secondary memory die to a host coupled to the bus.

18. The method for data storage of claim 13, wherein in response to receiving a die select command specifying a selected memory die between the primary memory die and the secondary memory die, causing the selected memory die to execute one or more commands received after the die select command.

19. A method for data storage according to claim 13, wherein the primary memory die and the secondary memory die are mapped to different corresponding address sub-ranges of a common address space, and the method includes identifying an address parameter in the received command and, depending on the address range to which the address parameter belongs, executing the received command by the primary memory die or by the secondary memory die.

20. A method for data storage as claimed in claim 13 and including operating according to an access mode in which the primary memory die controls a second chip select signal to block access to the secondary memory die for all incoming commands.

21. A method for data storage as described in claim 13, and including operating according to an access mode in which the primary memory die controls a second chip select signal to allow access to the secondary memory die for a partial subset of the commands supported by the secondary memory die.

22. A method for data storage according to claim 13, and including operating according to an access mode, in which the primary memory die controls a second chip select signal to allow full access to the secondary memory die for all commands supported by the secondary memory die, while only selectively executing commands that modify the access mode.

23. A method for data storage as claimed in claim 13 and including locally storing boot code for a host coupled to the bus and managing secure access to the stored boot code.

24. The method for data storage of claim 13, wherein and including acting, by the primary memory die, as a root of trust for an underlying system including the integrated circuit for securing storage operations directed to the secondary memory die.

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