Receiver and semiconductor memory device including same

Abstract

The invention provides a receiver and a semiconductor memory device. The receiver comprises a decision feedback equalizer. Comprising a cascade arrangement of a first stage having a first plurality of adders therein and a second stage having a second plurality of adders therein is configured to (i) generate a compensated data signal by adding a current value of a data signal to a plurality of feedback signals in response to a plurality of selection signals, (ii) generate a compensated data signal by adding a current value of the data signal to a plurality of frequency-divided strobe signals in response to a plurality of frequency-divided strobe signals in response to a plurality of frequency-divided strobe signals. Generating a sampled signal comprising a decision value by sampling bits of the compensated data signal, and (iii) generating a feedback signal in response to the plurality of weights, the sampled signal, and at least one delayed version of the sampled signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0080194, filed on June 22, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] Example embodiments relate generally to semiconductor integrated circuits, and more particularly, to a receiver capable of ensuring a sufficient timing margin and a semiconductor memory device including the receiver. Background Art

[0004] Semiconductor memory devices can generally be divided into two categories according to whether they retain stored data when disconnected from a power source. These categories include volatile memory devices, which lose stored data when disconnected from a power source, and nonvolatile memory devices, which retain stored data when disconnected from a power source. Volatile memory devices can perform read and write operations at high speed, while the contents stored therein may be lost when power is turned off. Nonvolatile memory devices can retain the contents stored therein even when power is turned off, which means that they can be used to store data that must be retained regardless of whether they are powered on or not.

[0005] Recently, as the performance of semiconductor memory devices has improved, a higher communication speed (or interface speed) is required between a memory controller and the semiconductor memory device. The requirement for a higher communication speed may affect the performance of a receiver within the semiconductor memory device. Summary of the invention

[0006] Some example embodiments provide an integrated circuit receiver capable of reducing power consumption and improving operation speed while supporting higher data communication speeds.

[0007] Some example embodiments provide an integrated circuit device having therein a receiver capable of operating with reduced power consumption while supporting higher operating speeds enabling higher data communication speeds.

[0008] According to an example embodiment, a receiver includes a decision feedback equalizer and may further include a deserializer and a control circuit. The decision feedback equalizer includes a first stage and a second stage, and the first stage and the second stage include a plurality of adders connected in cascade. The decision feedback equalizer is configured to generate a compensation data signal by adding a current value of a data signal to a plurality of feedback signals in response to a plurality of selection signals, and to generate a sampling signal including a decision value by sampling bits of the compensation data signal in response to a frequency division selection signal. In some embodiments, the decision feedback equalizer also generates a feedback signal based on a combination of a weight and a sampling signal corresponding to a previous value of the data signal, and also provides a first portion of the feedback signal to the second stage, and provides a second portion of the feedback signal to the first stage.

[0009] According to another embodiment, a semiconductor memory device includes a receiver and a control logic circuit. The receiver is connected to a memory controller through a channel and generates output data based on a data signal received from the channel. The control logic circuit controls the receiver. The receiver includes a decision feedback equalizer, a deserializer, and a control circuit. The decision feedback equalizer includes a first stage and a second stage, and the first stage and the second stage include a plurality of adders connected in cascade. The decision feedback equalizer is configured to generate a compensation data signal by adding a current value of a data signal and a feedback signal based on a plurality of selection signals, and to generate a sampling signal including a decision value by sampling a bit of the compensation data signal based on a frequency division selection signal. The equalizer is also configured to generate a feedback signal based on a weight and a sampling signal corresponding to a previous value of the data signal. In addition, a first portion of the feedback signal is provided to the second stage, and a second portion of the feedback signal is provided to the first stage.

[0010] According to another example embodiment, a receiver includes a decision feedback equalizer, a deserializer, and a control circuit. The decision feedback equalizer includes a first stage and a second stage, the first stage and the second stage include a plurality of adders connected in cascade, and the decision feedback equalizer is configured to: (i) generate a compensation data signal by adding a current value of a data signal to a feedback signal based on a plurality of selection signals, (ii) generate a sampling signal including a decision value by sampling bits of the compensation data signal based on a frequency division selection signal, (iii) generate a feedback signal based on a weight and a sampling signal corresponding to a previous value of the data signal, and (iv) provide a first portion of the feedback signal to the second stage and provide a second portion of the feedback signal to the first stage. The deserializer may also generate output data by deserializing the sampling signal. In some embodiments, the control circuit may generate a plurality of selection signals and provide the plurality of selection signals to the decision feedback equalizer. The decision feedback equalizer may generate a first internal data signal and a second internal data signal by adding a data signal to a second portion of the feedback signal using a time division scheme based on the plurality of selection signals, and generate a compensation data signal by adding a combination of the first internal data signal, the second internal data signal, and the first portion of the feedback signal.

[0011] Therefore, the decision feedback equalizer of the receiver according to the example embodiment includes a plurality of adders, which are cascade-connected and divided into a first stage and a second stage. The equalizer provides a first part of the feedback signal to the second stage, and provides a second part of the feedback signal to the first stage. Advantageously, the critical path and the non-critical path are separated from each other, and the decision feedback equalizer can operate at a high speed. In addition, the adder in the second stage generates bits of the compensation data signal in response to a plurality of selection signals by operating using a time division scheme, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a block diagram illustrating a memory system according to example embodiments.

[0014] Figure 2 and Figure 3 It is shown Figure 1 A block diagram of an example of a memory system.

[0015] Figure 4 is a block diagram illustrating an example of a memory controller included in a memory system according to example embodiments.

[0016] Figure 5 is a diagram showing a method of including Figure 1 A block diagram of an example of a semiconductor memory device in a memory system.

[0017] Figure 6 Show Figure 5 An example of a first memory bank array in a semiconductor memory device.

[0018] Fig. 7A is a block diagram illustrating an example of a receiver according to an example embodiment.

[0019] Figure 7B is a diagram showing a method according to an example embodiment Fig. 7A A circuit diagram of an example of a decision feedback equalizer in a receiver.

[0020] Fig. 8A According to an example embodiment, Figure 7B The first part of the decision feedback equalizer.

[0021] Figure 8B According to an example embodiment, Figure 7B The second part of the decision feedback equalizer.

[0022] Fig.9A It is shown 7A to 8B 0 is a timing diagram of an example of a data signal, a selection signal, and a frequency division selection signal.

[0023] Fig. 9B It is shown 7A to 8B 0014 is a timing diagram of an example of a data signal, a selection signal, and a compensation data signal in FIG.

[0024] Fig. 10A Is input to Fig. 7A Eye diagram of the data signal of the decision feedback equalizer.

[0025] Fig. 10B Shown from Figure 7B Eye diagrams of compensated data signals output by the third adder and the fourth adder in FIG.

[0026] Fig.11A According to an example embodiment, Figure 7B The first part of the decision feedback equalizer.

[0027] Fig. 11B According to an example embodiment, Figure 7B The second part of the decision feedback equalizer.

[0028] Fig.12 shows that during the third time interval when the first selection signal is deactivated Fig. 8A The third and fourth nodes and Fig.11A The voltage levels of the third node and the fourth node.

[0029] Fig.13is a block diagram illustrating an example of a receiver according to an example embodiment.

[0030] Fig.14 is a block diagram illustrating a receiver according to an example embodiment.

[0031] Fig.15A and Fig. 15B is a diagram for describing a data signal generated based on a multi-level signaling scheme according to example embodiments.

[0032] Fig.16 is a diagram showing a method according to an example embodiment Fig.14 A block diagram of an example of a receiver.

[0033] Fig.17 is a diagram showing a method according to an example embodiment Fig.16 A block diagram of an example of an output circuit in a receiver.

[0034] Fig.18 is a block diagram illustrating a semiconductor memory device according to example embodiments.

[0035] Fig.19 is a configuration diagram illustrating a semiconductor package including a stacked memory device according to example embodiments.

[0036] Fig. 20 is a block diagram illustrating a communication system according to an example embodiment. DETAILED DESCRIPTION

[0037] Various example embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. In this application, the same reference numerals represent the same elements.

[0038] Figure 1 is a block diagram illustrating a memory system according to an example embodiment. Figure 1 , the memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 may also include a plurality of signal lines 30 electrically connecting the memory controller 100 with the semiconductor memory device 200. The semiconductor memory device 200 may be controlled by the memory controller 100. For example, based on a request from a host (not shown), the memory controller 100 may store data (e.g., write data or program data) in the semiconductor memory device 200, or may retrieve data (e.g., read data or read out data) from the semiconductor memory device 200.

[0039] The plurality of signal lines 30 may include, for example, command lines, address lines, and data input / output (I / O) lines. The memory controller 100 may transmit a command CMD and an address ADDR to the semiconductor memory device 200 via the command line and the address line, and may exchange a data signal DS with the semiconductor memory device 200 via the data I / O line. Although not shown, the plurality of signal lines 30 may further include a data strobe signal line configured to transmit a data strobe signal DQS and a clock line configured to transmit a clock signal CK.

[0040] In some example embodiments, at least a portion or all of the signal lines 30 may be referred to as channels. The term "channel" used herein may refer to a signal line including a data I / O line for transmitting a data signal DS. However, example embodiments are not limited thereto, and the channel may further include a command line for transmitting a command CMD and / or an address line for transmitting an address ADDR.

[0041] Figure 2 and Figure 3 It is shown Figure 1 A block diagram of an example of a memory system. Figure 2 and Figure 3 , the memory system 11 includes a memory controller 101, a semiconductor memory device 201, and a plurality of channels 31a, 31b, and 31c. As shown, the memory controller 101 may include a plurality of transmitters 25a, 25b, and 25c, a plurality of receivers 27a, 27b, and 27c, and a plurality of data I / O pads 29a, 29b, and 29c. In addition, the semiconductor memory device 201 may include a plurality of transmitters 45a, 45b, and 45c, a plurality of receivers 47a, 47b, and 47c, and a plurality of data I / O pads 49a, 49b, and 49c.

[0042] Each of the plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c may generate a data signal. Each of the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c may receive a data signal. The plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c and the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c may transmit and receive data signals through the plurality of channels 31a, 31b, and 31c. Furthermore, each of the plurality of data I / O pads 29a, 29b, 29c, 49a, 49b, and 49c may be connected to a corresponding one of the plurality of transmitters 25a, 25b, 25c, 45a, 45b, and 45c and a corresponding one of the plurality of receivers 27a, 27b, 27c, 47a, 47b, and 47c. As shown, a plurality of channels 31 a , 31 b , and 31 c may electrically connect the memory controller 101 with the semiconductor memory device 201 .

[0043] As shown, each of the plurality of channels 31a, 31b, and 31c can be connected to a corresponding one of the plurality of transmitters 25a, 25b, and 25c and a corresponding one of the plurality of receivers 27a, 27b, and 27c through a corresponding one of the plurality of data I / O pads 29a, 29b, and 29c. In addition, each of the plurality of channels 31a, 31b, and 31c can be connected to a corresponding one of the plurality of transmitters 45a, 45b, and 45c and a corresponding one of the plurality of receivers 47a, 47b, and 47c through a corresponding one of the plurality of data I / O pads 49a, 49b, and 49c. Data signals can be transmitted through each of the plurality of channels 31a, 31b, and 31c.

[0044] Figure 2 1 shows an operation of transmitting data from the memory controller 101 to the semiconductor memory device 201. For example, the transmitter 25a may generate an output data signal DS11 based on the input data DAT11, the output data signal DS11 may be transmitted from the memory controller 101 to the semiconductor memory device 201 through the channel 31a, and the receiver 47a may receive the output data signal DS11 to obtain data ODAT11 corresponding to the input data DAT11. Similarly, the transmitter 25b may generate an output data signal DS21 based on the input data DAT21, the output data signal DS21 may be transmitted to the semiconductor memory device 201 through the channel 31b, and the receiver 47b may receive the output data signal DS21 to obtain data ODAT21 corresponding to the input data DAT21. The transmitter 25c may generate an output data signal DSN1 based on the input data DATN1, the output data signal DSN1 may be transmitted to the semiconductor memory device 201 through the channel 31c, and the receiver 47c may receive the output data signal DSN1 to obtain data ODATN1 corresponding to the input data DATN1. In some embodiments, the input data DAT11 , DAT21 , and DATN1 may be write data to be written into the semiconductor memory device 201 .

[0045] Figure 31 shows an operation of transmitting data from the semiconductor memory device 201 to the memory controller 101. For example, the transmitter 45a may generate an output data signal DS12 based on the input data DAT12, the output data signal DS12 may be transmitted from the semiconductor memory device 201 to the memory controller 101 through the channel 31a, and the receiver 27a may receive the output data signal DS12 to obtain data ODAT12 corresponding to the input data DAT12. Similarly, the transmitter 45b may generate an output data signal DS22 based on the input data DAT22, the output data signal DS22 may be transmitted to the memory controller 101 through the channel 31b, and the receiver 27b may receive the output data signal DS22 to obtain data ODAT22 corresponding to the input data DAT22. The transmitter 45c may generate an output data signal DSN2 based on the input data DATN2, the output data signal DSN2 may be transmitted to the memory controller 101 through the channel 31c, and the receiver 27c may receive the output data signal DSN2 to obtain data ODATN2 corresponding to the input data DATN2. In some embodiments, the input data DAT12 , DAT22 , and DATN2 may be read data retrieved from the semiconductor memory device 201 in response to a read command issued by the memory controller 101 .

[0046] Figure 4 is a block diagram illustrating an example of a memory controller included in a memory system according to example embodiments. Figure 4 , the memory controller 100 may include at least one processor 110, a buffer memory 120, a host interface 130, an error correction code (ECC) engine 140, and a memory interface 150. The processor 110 may control the operation of the memory controller 100 in response to a command and / or request received from an external host (not shown) via the host interface 130. For example, the processor 110 may control various components by adopting firmware in order to operate a semiconductor memory device such as Figure 1 1 . In addition, the buffer memory 120 may store instructions and data executed and processed by the processor 110. As will be appreciated by those skilled in the art, the buffer memory 120 may be implemented as a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a cache memory, etc.

[0047] The host interface 130 may provide a physical connection between the host and the memory controller 100. The host interface 130 may provide an interface corresponding to a bus format of the host for communication between the host and the memory controller 100. The ECC engine 140 for error correction may perform coding modulation using a Bose-Chaudhuri-Hocquenghem (BCH) code, a low-density parity-check (LDPC) code, a turbo code, a Reed-Solomon code, a convolutional code, a recursive systematic code (RSC), a trellis coded modulation (TCM), a block coded modulation (BCM), etc., or may perform ECC encoding and ECC decoding using the above codes or other error correction codes.

[0048] The memory interface 150 may exchange data with the semiconductor memory device 200. The memory interface 150 may transmit commands and addresses to the semiconductor memory device 200, and may transmit data to the semiconductor memory device 200 or receive data read from the semiconductor memory device 200. Figure 4 1, but the memory interface 150 may include a Figure 2 The transmitter 25a of the transmitter generating the data signal according to the example embodiment and the receiver (eg, Figure 2 Receiver 27a).

[0049] Figure 5 is a diagram showing a method of including Figure 1 A block diagram of an example of a semiconductor memory device in a memory system of FIG. Figure 5 , the semiconductor memory device 200 may include a control logic circuit 210, an address register 220, a clock buffer 225, a bank control logic 230, a refresh counter 245, a row address (RA) multiplexer (MUX) 240, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a memory cell array 310, a sense amplifier unit 285, an I / O gating circuit 290, an ECC engine 320, an on-die termination (ODT) circuit 297, and a data I / O buffer 295. As described above, the semiconductor memory device 200 may be a volatile memory device such as a dynamic random access memory (DRAM) device that supports a refresh operation to maintain the integrity of stored data.

[0050] The memory cell array 310 may include first to eighth memory bank arrays 310a to 380h. The row decoder 260 may include first to eighth row decoders 260a to 260h respectively coupled to the first to eighth memory bank arrays 310a to 380h, the column decoder 270 may include first to eighth column decoders 270a to 270h respectively coupled to the first to eighth memory bank arrays 310a to 380h, and the sense amplifier unit 285 may include first to eighth sense amplifiers 285a to 285h respectively coupled to the first to eighth memory bank arrays 310a to 380h.

[0051] The first to eighth memory bank arrays 310a to 380h, the first to eighth row decoders 260a to 260h, the first to eighth column decoders 270a to 270h, and the first to eighth sense amplifiers 285a to 285h may form the first to eighth memory banks. Each of the first to eighth memory bank arrays 310a to 380h may include a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

[0052] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250. The clock buffer 225 may receive a clock signal CK, may generate an internal clock signal ICK by buffering the clock signal CK, and may provide the internal clock signal ICK to a circuit component that processes a command CMD and an address ADDR.

[0053] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. One row decoder corresponding to the bank address BANK_ADDR among the first to eighth row decoders 260a to 260h is activated in response to the bank control signal, and one column decoder corresponding to the bank address BANK_ADDR among the first to eighth column decoders 270a to 270h is activated in response to the bank control signal.

[0054] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220, and may receive the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first row decoder 260a to the eighth row decoder 260h. The refresh counter 245 may sequentially increase or decrease the refresh row address REF_ADDR under the control of the control logic circuit 210.

[0055] One row decoder activated by the memory control logic 230 among the first row decoder 260a to the eighth row decoder 260h may decode the row address RA output from the row address multiplexer 240, and may activate the word line corresponding to the row address RA. For example, the activated row decoder may apply a word line drive voltage to the word line corresponding to the row address. The column address latch 250 may receive the column address COL_ADDR from the address register 220, and may temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, the column address latch 250 may generate a column address COL_ADDR' incremented from the received column address COL_ADDR. The column address latch 250 applies the temporarily stored or generated column address COL_ADDR' to the first column decoder 270a to the eighth column decoder 270h.

[0056] An activated one of the first to eighth column decoders 270a to 270h may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit 290. The I / O gating circuit 290 may include a circuit for gating input / output data, and may also include input data masking logic, a read data latch for storing data output from the first to eighth bank arrays 310a to 380h, and a write driver for writing data into the first to eighth bank arrays 310a to 380h.

[0057] The codeword CW read from one of the first to eighth memory bank arrays 310a to 380h may be read by a sense amplifier coupled to one of the memory bank arrays from which data is to be read and may be stored in the read data latch. After the ECC engine 320 performs ECC decoding on the codeword CW, the codeword CW stored in the read data latch may be provided to the memory controller 100 via the data I / O buffer 295.

[0058] The data DQ to be written into one of the first to eighth memory arrays 310 a to 380 h is provided from the data I / O buffer 295 to the ECC engine 320, the ECC engine 320 may perform ECC encoding on the data DQ to generate parity bits, the ECC engine 320 may provide the data DQ and the parity bits to the I / O gating circuit 290, and the I / O gating circuit 290 may write the data DQ and the parity bits into a sub-page in the one memory array through a write driver.

[0059] The data I / O buffer 295 may convert the data signal DS received from the memory controller 100 into data DQ, and may provide the data DQ to the ECC engine 320 in a write operation of the semiconductor memory device 200. The data I / O buffer 295 may convert the data DQ into a data signal DS, and may provide the data signal DS to the memory controller 100 in a read operation of the semiconductor memory device 200. The data I / O buffer 295 may transmit / receive the data signal DS through the data I / O pad 299, and may transmit / receive the data strobe signal DQS through the strobe pad 298.

[0060] The data I / O buffer 295 may include a transmitter and a receiver. The receiver may include a decision feedback equalizer. The decision feedback equalizer may include a first stage and a second stage, the first stage and the second stage include a plurality of adders connected in cascade, may generate a compensation data signal by adding a current value of the data signal to a feedback signal based on a plurality of selection signals, may generate a sampling signal including a decision value by sampling bits of the compensation data signal based on a frequency division selection signal, may generate a feedback signal based on a weight and a sampling signal corresponding to a previous value of the data signal, may provide a first portion of the feedback signal to the second stage, and may provide a second portion of the feedback signal to the first stage.

[0061] The ECC engine 320 may perform ECC encoding and ECC decoding on the data DQ according to the control of the control logic circuit 210. In addition, the control logic circuit 210 may control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 may generate a control signal for the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes the command CMD received from the memory controller 100 and a mode register 212 that sets the operation mode of the semiconductor memory device 200. For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The command decoder 211 (i.e., the control logic circuit 210) may generate a first control signal CTL1 for controlling the I / O gating circuit 290, a second control signal CTL2 for controlling the ECC engine 320, and a third control signal CTL3 for controlling a receiver in the data I / O buffer 295 by decoding the command CMD.

[0062] The ODT circuit 297 may be connected to the data I / O pad 299 and the data I / O buffer 295. When the ODT circuit 297 is enabled, the ODT circuit 297 may perform an ODT operation. When the ODT operation is performed, the signal integrity of any transmitted or received signal may be enhanced by preventing signal reflection due to impedance matching.

[0063] Although the semiconductor memory device included in the memory system according to the example embodiments is described based on DRAM, the semiconductor memory device according to the example embodiments may be any volatile memory device and / or any nonvolatile memory device, for example, a flash memory, a phase random access memory (PRAM), a resistance random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc.

[0064] Figure 6 Show Figure 5 An example of a first memory bank array in a semiconductor memory device. Figure 6, the first memory bank array 310a may include a plurality of word lines WL0 to WLm-1 (m is a natural number greater than 2), a plurality of bit lines BTL0 to BTLn-1 (n is a natural number greater than 2), and a plurality of memory cells MC disposed at intersections between the word lines WL0 to WLm-1 and the bit lines BTL0 to BTLn-1. Each of the memory cells MC includes a cell transistor coupled to each of the word lines WL0 to WLm-1 and each of the bit lines BTL0 to BTLn-1 and a cell capacitor coupled to the cell transistor. Each of the memory cells MC may have a DRAM cell structure. Each of the word lines WL0 to WLm-1 extends in a first direction DR1, and each of the bit lines BTL0 to BTLn-1 extends in a second direction DR2 intersecting the first direction DR1. Word lines WL0 to WLm-1 coupled to the plurality of memory cells MC may be referred to as rows of the first bank array 310a, and bit lines BTL0 to BTLn-1 coupled to the plurality of memory cells MC may be referred to as columns of the first bank array 310a.

[0065] Fig. 7A 4 is a block diagram showing an example of a receiver 400 according to an example embodiment. Fig. 7A , the receiver 400 may include a buffer 410, a decision feedback equalizer 420, a deserializer 490, a frequency divider 480, and a control circuit 500. The buffer 410 may receive a data signal DS, and may generate a buffered data signal BDS by comparing the received data signal DS with a reference voltage VREF. The buffer 410 may include a positive input terminal for receiving the data signal DS, a negative input terminal for receiving the reference voltage VREF, and an output terminal for providing the buffered data signal BDS. In an alternative embodiment, the receiver 400 may not include the buffer 410. When the receiver 400 does not include the buffer 410, the decision feedback equalizer 420 may directly receive the data signal DS.

[0066] The decision feedback equalizer 420 may include a multi-stage adder circuit 430, a sampling circuit 440, and a feedback circuit (FC) 450. The multi-stage adder circuit 430 may include a first stage 430a and a second stage 430b connected in cascade. The decision feedback equalizer 420 including a plurality of adding devices (i.e., "adders") connected in cascade may collectively generate a compensation data signal CDS1 based on a plurality of selection signals SELI, SELIB, SELQ, and SELQB by adding a current value of a data signal DS and feedback signals FS11, FS12, FS13, and FS14 in a time division scheme, and may generate a sampling signal SDS including a decision value by sampling bits of the compensation data signal CDS1 based on a divided selection signal DQS_2N. 1, feedback signals FS11, FS12, FS13, and FS14 may be generated based on the weights WC1, WC2, WC3, and WC4 and the sampling signal SDS1 corresponding to the previous value of the data signal DS, a first portion FS11 of the feedback signals FS11, FS12, FS13, and FS14 may be provided to the second stage 430b, and a second portion FS12, FS13, and FS14 of the feedback signals FS11, FS12, FS13, and FS14 may be provided to the first stage 430a.

[0067] In addition, the first stage 430a may generate a first internal data signal IDS1 and a second internal data signal IDS2 based on the data signal DS and the second parts FS12, FS13 and FS14 of the feedback signals FS11, FS12, FS13 and FS14. The second stage 430b may generate a compensation data signal CDS1 based on the first internal data signal IDS1, the second internal data signal IDS2 and the first part FS11 of the feedback signals FS11, FS12, FS13 and FS14.

[0068] The sampling circuit 440 may generate bits of a sampling signal SDS1 by sampling bits of the compensation data signal CDS1 based on the frequency division strobe signal DQS_2N, and may provide the sampling signal SDS1 to the deserializer 490. The sampling signal SDS1 may include a decision value associated with the data signal DS.

[0069] In addition, the feedback circuit 450 may generate feedback signals FS11, FS12, FS13, and FS14 by multiplying the sampling signal SDS1 and the delayed sampling signal by weights WC1, WC2, WC3, and WC4, respectively, and may provide the feedback signal FS11 to the second stage 430b, and may provide the feedback signals FS12, FS13, and FS14 to the first stage 430a. The delayed sampling signal may be obtained by sequentially delaying the sampling signal SDS1.

[0070] The deserializer 490 can generate deserialized data DQ by deserializing the sampling signal SDS1. The deserialized data DQ can be referred to as output data. The frequency divider 480 can generate a first frequency division selection signal DQS_2N_0, a second frequency division selection signal DQS_2N_90, a third frequency division selection signal DQS_2N_180, and a fourth frequency division selection signal DQS_2N_270 with a phase difference of 90 degrees from each other based on the data selection signal DQS including the first selection signal DQS0 and the second selection signal DQS180 with a phase difference of 180 degrees, and can provide the frequency division selection signal DQS_2N including the first frequency division selection signal DQS_2N_0, the second frequency division selection signal DQS_2N_90, the third frequency division selection signal DQS_2N_180, and the fourth frequency division selection signal DQS_2N_270 to the decision feedback equalizer 420.

[0071] The control circuit 500 may generate a plurality of selection signals SELI, SELIB, SELQ, and SELQB, and may provide the plurality of selection signals SELI, SELIB, SELQ, and SELQB to the second stage 430b of the decision feedback equalizer 420. The control circuit 500 may generate weights WC1, WC2, WC3, and WC4, and may provide the weights WC1, WC2, WC3, and WC4 to the feedback circuit 450 of the decision feedback equalizer 420.

[0072] As described above, within the decision feedback equalizer 420, the adder is divided into a first stage 430a and a second stage 430b connected in cascade, and the feedback circuit 450 provides the feedback signal FS11 to the second stage 430b, and provides the feedback signals FS12, FS13, and FS14 to the first stage 430a. Based on this configuration, the critical path and the non-critical path are separated from each other, so that the decision feedback equalizer 420 can operate at a high speed. In addition, the adder in the second stage 430b generates bits of the compensation data signal CDS1 by operating based on a time division scheme in response to a plurality of selection signals SELI, SELIB, SELQ, and SELQB, and thus power consumption can be reduced. In addition, the decision feedback equalizer 420 may include a cascade arrangement of a first stage (e.g., the first stage 430a) having at least one summing circuit therein and a second stage (e.g., the second stage 430b) having a plurality of summing circuits therein. The decision feedback equalizer 420 can generate a compensation data signal CDS1 in response to at least one selection signal (e.g., at least one of SELI, SELIB, SELQ, and SELQB) by adding properties of the data signal DS to at least one feedback signal (e.g., at least one of FS11, FS12, FS13, and FS14), can generate a sampling signal SDS1 in response to a plurality of frequency division selection signals DQS_2N by sampling bits of the compensation data signal CDS1, and can generate at least one feedback signal in response to at least one weight (e.g., at least one of WC1, WC2, WC3, and WC4), the sampling signal SDS1, and at least one delayed version of the sampling signal.

[0073] Figure 7B It shows that Fig. 7A A circuit diagram of an example embodiment of a decision feedback equalizer 420 for use within a receiver of FIG. Figure 7B , a plurality of selection signals SELI, SELQ, SELIB, and SELQB are referred to as first, second, third, and fourth selection signals, respectively, and feedback signals FS11, FS12, FS13, and FS14 are referred to as first, second, third, and fourth feedback signals. The first stage 430a may include a first adder 431 and a second adder 432, and the second stage 430b may include a third adder 433, a fourth adder 434, a fifth adder 435, and a sixth adder 436. As described above, these "adders" may operate as adding devices having a plurality of inputs configured to receive respective signals to be added.

[0074] The first adder 431 (within the first stage 430a) may generate a first internal data signal IDS1 by adding the data signal DS to the second feedback signal FS12, the third feedback signal FS13, and the fourth feedback signal FS14. The second adder 432 (within the first stage 430a) may generate a second internal data signal IDS2 by adding the data signal DS to the second feedback signal FS12, the third feedback signal FS13, and the fourth feedback signal FS14. Based on the configuration shown, the first internal data signal IDS1 and the second internal data signal IDS2 will be equivalent signals.

[0075] During the first time interval, the third adder 433 (within the second stage 430b) may generate a first bit CDS11 of the compensation data signal CDS1 by adding the first internal data signal IDS1 to the first feedback signal FS11 in response to the first selection signal SELI. Conversely, during a third time interval that does not overlap with the first time interval, the fourth adder 434 (within the second stage 430b) may generate a second bit CDS12 of the compensation data signal CDS1 by adding the first internal data signal IDS1 to the first feedback signal FS11 in response to the third selection signal SELIB. In the illustrated embodiment, the first selection signal SELI and the third selection signal SELIB may be complementary signals.

[0076] During the second time interval, the fifth adder 435 (within the second stage 430b) may generate the third bit CDS13 of the compensation data signal CDS1 by adding the second internal data signal IDS2 to the first feedback signal FS11 in response to the second selection signal SELQ. Conversely, during a fourth time interval that does not overlap with the second time interval, the sixth adder 436 may generate the fourth bit CDS14 of the compensation data signal CDS1 by adding the second internal data signal IDS2 to the first feedback signal FS11 in response to the fourth selection signal SELQB. In the illustrated embodiment, the second selection signal SELQ and the fourth selection signal SELQB may be complementary signals.

[0077] Still refer to Figure 7B, the sampling circuit 440 may include a first slicer 441, a second slicer 442, a third slicer 443, and a fourth slicer 444. As shown in the figure, the first slicer 441 may generate a first bit SDS11 of the sampling signal SDS1 by sampling the first bit CDS11 of the compensation data signal CDS1 based on the first frequency division selection signal DQS_2N_0. The second slicer 442 may generate a second bit SDS12 of the sampling signal SDS1 by sampling the second bit CDS12 of the compensation data signal CDS1 based on the third frequency division selection signal DQS_2N_180 (which is 180° out of phase with the first frequency division selection signal DQS_2N_0).

[0078] The third limiter 443 may generate the third bit SDS13 of the sampling signal SDS1 by sampling the third bit CDS13 of the compensation data signal CDS1 based on the second frequency division selection signal DQS_2N_90 (which is 90° out of phase with respect to the first frequency division selection signal DQS_2N_0). Finally, the fourth limiter 444 may generate the fourth bit SDS14 of the sampling signal SDS1 by sampling the fourth bit CDS14 of the compensation data signal CDS1 based on the fourth frequency division selection signal DQS_2N_270 (which is 270° out of phase with respect to the first frequency division selection signal DQS_2N_0).

[0079] Next, the feedback circuit 450 may include a first tap 451, a second tap 452, a third tap 453, a fourth tap 454, a first delay element (DE) 456, a second delay element 457, and a third delay element 458. The first tap 451 may generate a first feedback signal FS11 by multiplying the sampling signal SDS1 by the first weight WC1, and may provide the first feedback signal FS11 to the third adder 433 to the sixth adder 436.

[0080] The first delay element 456 may output a first delayed sampling signal SDS1_D1 by delaying the sampling signal SDS1. The second tap 452 may generate a second feedback signal FS12 by multiplying the first delayed sampling signal SDS1_D1 by the second weight WC2, and may provide the second feedback signal FS12 to the first adder 431 and the second adder 432. Similarly, the second delay element 457 may output a second delayed sampling signal SDS1_D2 by further delaying the first delayed sampling signal SDS1_D1. The third tap 453 may generate a third feedback signal FS13 by multiplying the second delayed sampling signal SDS1_D2 by the third weight WC3, and may provide the third feedback signal FS13 to the first adder 431 and the second adder 432. Finally, the third delay element 458 may output a third delayed sampling signal SDS1_D3 by further delaying the second delayed sampling signal SDS1_D2. The fourth tap 454 may generate a fourth feedback signal FS14 by multiplying the third delayed sampling signal SDS1_D3 by the fourth weight WC4 , and may provide the fourth feedback signal FS14 to the first adder 431 and the second adder 432 .

[0081] Fig. 8A According to an example embodiment, Figure 7B The first part 420aa of the decision feedback equalizer 420 includes a first adder 431, a third adder 433, a fourth adder 434, and a load circuit 460aa. As shown, the load circuit 460aa may include a first resistor R11, a second resistor R12, a third resistor R13, and a fourth resistor R14 connected in parallel to the power supply voltage VDDQ.

[0082] The first adder 431 may include a pair of n-channel metal oxide semiconductor (NMOS) transistors 431a and 431b and a current source 431c electrically coupled to the source terminals of the NMOS transistors 431a and 431b. As shown, the NMOS transistor 431a may be coupled between the first node N11 and the seventh node N17, and may have a gate for receiving the data signal DS. On the contrary, the NMOS transistor 431b may be coupled between the second node N12 and the seventh node N17, and may have a gate for receiving the inverted data signal DSB. The current source 431c may be coupled between the seventh node N17 and the ground voltage VSSQ, and may provide a constant "pull-down" current to the seventh node N17. In addition, the second tap 452, the third tap 453, and the fourth tap 454 may be connected to the first node N11 and the second node N12.

[0083] The third adder 433 may include a first NMOS transistor 433a and a second NMOS transistor 433b. The first NMOS transistor 433a may be coupled to the first adder 431 at a first node N11, may be coupled to the first resistor R11 and the first tap 451 at a third node N13, and may have a gate receiving a first selection signal SELI. The second NMOS transistor 433b may be coupled to the first adder 431 at a second node N12, may be coupled to the second resistor R12 and the first tap 451 at a fourth node N14, and may have a gate receiving the first selection signal SELI.

[0084] During the first time interval when the first selection signal SELI is activated, the first NMOS transistor 433a and the second NMOS transistor 433b may connect the first node N11 and the second node N12 to the third node N13 and the fourth node N14, respectively. The first limiter 441 may have input terminals connected to the third node N13 and the fourth node N14, and may output a first bit SDS11 of the sampling signal SDS1 by sampling a voltage level of the third node N13 and a voltage level of the fourth node N14 based on the first frequency-divided selection signal DQS_2N_0.

[0085] The fourth adder 434 may include a third NMOS transistor 434a and a fourth NMOS transistor 434b. The third NMOS transistor 434a may be coupled to the first adder 431 at the second node N12, may be coupled to the fourth resistor R14 and the first tap 451 at the fifth node N15, and may have a gate receiving the third selection signal SELIB. The fourth NMOS transistor 434b may be coupled to the first adder 431 at the first node N11, may be coupled to the third resistor R13 and the first tap 451 at the sixth node N16, and may have a gate receiving the third selection signal SELIB.

[0086] During the third time interval when the third selection signal SELIB is activated, the third NMOS transistor 434a and the fourth NMOS transistor 434b may connect the second node N12 and the first node N11 to the fifth node N15 and the sixth node N16, respectively. The second limiter 442 may have input terminals connected to the sixth node N16 and the fifth node N15, and may output the second bit SDS12 of the sampling signal SDS1 by sampling the voltage levels of the sixth node N16 and the fifth node N15 based on the third frequency-divided selection signal DQS_2N_180.

[0087] Although not wishing to be bound by any theory of operation, the first time constant τ1 of the first node N11 can be expressed as (C11+C12) / gm, where gm represents the conductivity of the first node N11, C11 represents the capacitance of the first adder 431, and C12 represents the capacitance of the second tap 452, the third tap 453, and the fourth tap 454. Similarly, the second time constant τ2 of the fourth node N14 can be expressed as (R)×(C21+C22+C23), where R represents the resistance of the second resistor R12, C21 represents the capacitance of the second NMOS transistor 433b, C22 represents the capacitance of the first tap 451, and C23 represents the capacitance of the first limiter 441. Because the second time constant τ2 is associated with the capacitance of the first tap 451 rather than the capacitance of the first to fourth taps 451, 452, 453 and 454, the value of the second time constant τ2 can be reduced and the decision feedback equalizer 420aa can advantageously operate at a higher speed.

[0088] Figure 8B Show Figure 7B The second part 420ab of the decision feedback equalizer 420 may include a second adder 432, a fifth adder 435, a sixth adder 436, and a load circuit 460ab. As shown, the load circuit 460ab may include a first resistor R21, a second resistor R22, a third resistor R23, and a fourth resistor R24 ​​connected in parallel to the power supply voltage VDDQ.

[0089] The second adder 432 may include NMOS transistors 432a and 432b and a "pull-down" current source 432c. The NMOS transistor 432a may be coupled between the first node N21 and the seventh node N27, and may have a gate for receiving the data signal DS. The NMOS transistor 432b may be coupled between the second node N22 and the seventh node N27, and may have a gate for receiving the inverted data signal DSB. The current source 432c may be coupled between the seventh node N27 and the ground voltage VSSQ, and may provide a constant "pull-down" current to the seventh node N27. The second tap 452, the third tap 453, and the fourth tap 454 may be connected to the first node N21 and the second node N22.

[0090] The fifth adder 435 may include a first NMOS transistor 435a and a second NMOS transistor 435b. The first NMOS transistor 435a may be coupled to the second adder 432 at a first node N21, may be coupled to the first resistor R21 and the first tap 451 at a third node N23, and may have a gate receiving a second selection signal SELQ. The second NMOS transistor 435b may be coupled to the second adder 432 at a second node N22, may be coupled to the second resistor R22 and the first tap 451 at a fourth node N24, and may have a gate receiving a second selection signal SELQ.

[0091] During the second time interval in which the second selection signal SELQ is activated, the first NMOS transistor 435a and the second NMOS transistor 435b may connect the first node N21 and the second node N22 to the third node N23 and the fourth node N24, respectively. In addition, the third limiter 443 may be connected to the third node N23 and the fourth node N24, and may output the third bit SDS13 of the sampling signal SDS1 by sampling the voltage level of the third node N23 and the voltage level of the fourth node N24 based on the second frequency-divided selection signal DQS_2N_90.

[0092] The sixth adder 436 may include a third NMOS transistor 436a and a fourth NMOS transistor 436b. The third NMOS transistor 436a may be coupled to the second adder 432 at the second node N22, may be coupled to the fourth resistor R24 ​​and the first tap 451 at the fifth node N25, and may have a gate receiving a fourth selection signal SELQB. The fourth NMOS transistor 436b may be coupled to the second adder 432 at the first node N21, may be coupled to the third resistor R23 and the first tap 451 at the sixth node N26, and may have a gate receiving a fourth selection signal SELQB.

[0093] During a fourth time interval when the fourth selection signal SEQIB is activated, the third NMOS transistor 436a and the fourth NMOS transistor 436b may connect the second node N22 and the first node N21 to the fifth node N25 and the sixth node N26, respectively. The fourth limiter 444 may be connected to the sixth node N26 and the fifth node N25, and may output a fourth bit SDS14 of the sampling signal SDS1 by sampling the voltage levels of the sixth node N26 and the fifth node N25 based on the fourth frequency-divided selection signal DQS_2N_270.

[0094] As mentioned above Fig. 8A and Figure 8BAs described, each of the first adder 431 , the third adder 433 , and the fourth adder 434 is configured symmetrically with a corresponding one of the second adder 432 , the fifth adder 435 , and the sixth adder 436 .

[0095] Fig.9A It is shown 7A to 8B The timing diagram of the data signal, selection signal and frequency division selection signal in the example. 7A to 9A : (i) during the first time interval when the first selection signal SELI is activated (i.e., valid), the first limiter 441 may sample the first bit D0 of the data signal DS at the rising edge of the first frequency division selection signal DQS_2N_0 (i.e., when DQS_2N_0 becomes valid), (ii) during the third time interval when the third selection signal SELIB is valid, the second limiter 442 may sample the third bit D2 of the data signal DS at the rising edge of the third frequency division selection signal DQS_2N_180, (iii) during the second time interval when the second selection signal SELQ is valid, the third limiter 443 may sample the second bit D1 of the data signal DS at the rising edge of the second frequency division selection signal DQS_2N_90, and (iv) during the fourth time interval when the fourth selection signal SELQB is valid, the fourth limiter 444 may sample the fourth bit D3 of the data signal DS at the rising edge of the fourth frequency division selection signal DQS_2N_270.

[0096] Fig. 9B It is shown 7A to 8B The timing diagram of the data signal, the selection signal and the compensation data signal in FIG. 7A to 8B and Fig. 9B : (i) during the first time interval when the first selection signal SELI is activated, the third adder 433 can output the first bit CDS11 of the compensation data signal CDS1, (ii) during the third time interval when the third selection signal SELIB is activated, the fourth adder 434 can output the second bit CDS12 of the compensation data signal CDS1, (iii) during the second time interval when the second selection signal SELQ is activated, the fifth adder 435 can output the third bit CDS13 of the compensation data signal CDS1, and (iv) during the fourth time interval when the fourth selection signal SELQB is activated, the sixth adder 436 can output the fourth bit CDS14 of the compensation data signal CDS1.

[0097] Fig. 10A Shows input to Fig. 7A The eye diagram of the data signal of the decision feedback equalizer, Fig. 10B Shown from Figure 7B The eye diagram of the compensated data signal output by the third adder and the fourth adder in FIG. Fig. 10B A value obtained by subtracting a second bit CSD12 of the compensation data signal CDS1 output from the fourth adder 434 from a first bit CSD11 of the compensation data signal CDS1 output from the third adder 433 is shown.

[0098] Reference Fig. 10A and Fig. 10B The eye diagram of the data signal DS having the first eye width EW1 and the first eye height EH1 is output as an eye diagram of the compensated data signal having the second eye width EW2 and the second eye height EH2. According to some embodiments, the second eye width EW2 is greater than the first eye width EW1, and the second eye height EH2 is greater than the first eye height EH1.

[0099] Fig.11A According to an example embodiment, Figure 7B The first part of the decision feedback equalizer. Fig.11A , the first part of the decision feedback equalizer 420ba may include a first adder 431, a third adder 433, a fourth adder 434 and a load circuit 460ba. As shown in the figure, Fig.11A The decision feedback equalizer 420ba and Fig. 8A The decision feedback equalizer 420aa is different from the decision feedback equalizer 420ba in that the decision feedback equalizer 420ba includes a load circuit 460ba instead of the load circuit 460aa, and the description of Fig. 8A Duplicate description.

[0100] The load circuit 460ba may include a first p-channel metal oxide semiconductor (PMOS) transistor 461, a second PMOS transistor 462, a third PMOS transistor 463, and a fourth PMOS transistor 464 connected in parallel to the power supply voltage VDDQ. As shown, the first PMOS transistor 461 may be coupled between the power supply voltage VDDQ and the third node N13, and may have a gate receiving the third selection signal SELIB. The second PMOS transistor 462 may be coupled between the power supply voltage VDDQ and the fourth node N14, and may have a gate receiving the third selection signal SELIB.

[0101] The third PMOS transistor 463 may be coupled between the power supply voltage VDDQ and the fifth node N15 and may have a gate receiving the first selection signal SELI. The fourth PMOS transistor 464 may be coupled between the power supply voltage VDDQ and the sixth node N16 and may have a gate receiving the first selection signal SELI.

[0102] During the first time interval when the third selection signal SELIB is deactivated, the first PMOS transistor 461 and the second PMOS transistor 462 may respectively provide a current based on the power supply voltage VDDQ to the third node N13 and the fourth node N14, and during the third time interval when the third selection signal SELIB is activated, the voltage level of the third node N13 and the voltage level of the fourth node N14 may be maintained.

[0103] During the third time interval when the first selection signal SELI is deactivated, the third PMOS transistor 463 and the fourth PMOS transistor 464 may respectively provide a current based on the power supply voltage VDDQ to the fifth node N15 and the sixth node N16, and during the first time interval when the first selection signal SELI is activated, the voltage level of the fifth node N15 and the voltage level of the sixth node N16 may be maintained.

[0104] Fig. 11B According to an example embodiment, Figure 7B The second part of the decision feedback equalizer. Fig. 11B , the second part of the decision feedback equalizer 420bb may include a second adder 432, a fifth adder 435, a sixth adder 436 and a load circuit 460bb. Fig. 11B The decision feedback equalizer 420bb and Figure 8B The decision feedback equalizer 420ab is different in that the decision feedback equalizer 420bb includes a load circuit 460bb instead of the load circuit 460ab, and the description of Figure 8B Duplicate description.

[0105] The load circuit 460bb may include a first PMOS transistor 465, a second PMOS transistor 466, a third PMOS transistor 467, and a fourth PMOS transistor 468 connected in parallel to the power supply voltage VDDQ. As shown, the first PMOS transistor 465 may be coupled between the power supply voltage VDDQ and the third node N23, and may have a gate receiving the fourth selection signal SELQB. The second PMOS transistor 466 may be coupled between the power supply voltage VDDQ and the fourth node N24, and may have a gate receiving the fourth selection signal SELQB. Similarly, the third PMOS transistor 467 may be coupled between the power supply voltage VDDQ and the fifth node N25, and may have a gate receiving the second selection signal SELQ. The fourth PMOS transistor 468 may be coupled between the power supply voltage VDDQ and the sixth node N26, and may have a gate receiving the second selection signal SELQ.

[0106] During the second time interval when the fourth selection signal SELQB is deactivated, the first PMOS transistor 465 and the second PMOS transistor 466 may respectively supply a current based on the power supply voltage VDDQ to the third node N23 and the fourth node N24, and during the fourth time interval when the fourth selection signal SELQB is activated, the voltage level of the third node N23 and the voltage level of the fourth node N24 may be maintained. In addition, during the fourth time interval when the second selection signal SELQ is deactivated, the third PMOS transistor 467 and the fourth PMOS transistor 468 may respectively supply a current based on the power supply voltage VDDQ to the fifth node N25 and the sixth node N26, and during the second time interval when the second selection signal SELQ is activated, the voltage level of the fifth node N25 and the voltage level of the sixth node N26 may be maintained.

[0107] Fig.12 shows that during the third time interval when the first selection signal is deactivated, Fig. 8A The third and fourth nodes and Fig.11A The voltage levels of the third node and the fourth node. Fig. 8A , Fig.11A and Fig.12 ,when Fig. 8A When the third node N13 and the fourth node N14 are coupled to the resistors R11 and R12, respectively, as indicated by reference numeral 471, during the third time interval when the first selection signal SELI is deactivated, the voltage level of the third node N13 and the voltage level of the fourth node N14 increase to the level of the power supply voltage VDDQ. Fig.11A When the third node N13 and the fourth node N14 are coupled to the PMOS transistors 461 and 462, respectively, as indicated by reference numeral 473, during a third time interval in which the first selection signal SELI is deactivated, voltage levels of the third node N23 and the fourth node N24 are maintained at a fixed level.

[0108] Fig.13 is a block diagram illustrating another example of a receiver according to an example embodiment. Fig.13 , the receiver 600 may include a buffer 605, a decision feedback equalizer 610, a deserializer 690, a frequency divider 680, and a control circuit 685. The buffer 605 may receive a data signal DS, and may generate a buffered data signal BDS by comparing the received data signal DS with a reference voltage VREF. The buffer 605 may include a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal being used to receive the data signal DS, the negative input terminal being used to receive the reference voltage VREF, and the output terminal being used to provide the buffered data signal BDS.

[0109] In an example embodiment, the receiver 600 may not include the buffer 605. When the receiver 600 does not include the buffer 605, the decision feedback equalizer 610 may directly receive the data signal DS. The decision feedback equalizer 610 may include a multi-stage adder circuit 615, a sampling circuit 640, and a feedback circuit 650.

[0110] The multi-stage adder circuit 615 may include a first stage 620 and a second stage 630 connected in cascade. The first stage 620 may generate a first internal data signal IDS21 and a second internal data signal IDS22 based on the data signal DS and the second part FS22, ..., FS2M of the feedback signals FS21, FS22, ..., FS2M. Here, M is a natural number greater than four (4). For example, in some embodiments, M may be eight (8). The second stage 630 may generate a compensation data signal CDS2 based on the first internal data signal IDS21, the second internal data signal IDS22 and the first part FS21 of the feedback signals FS21, FS22, ..., FS2M.

[0111] Specifically, the first stage 620 may include a first adder 621 and a second adder 622, and the second stage 630 may include a plurality of adders 631, 632, ..., 63M. The first adder 621 may generate a first internal data signal IDS21 by adding the data signal DS to the feedback signals FS22, ..., FS2M, and may provide the first internal data signal IDS21 to the upper half of the plurality of adders 631, 632, ..., 63M. The second adder 622 may generate a second internal data signal IDS22 by adding the data signal DS to the feedback signals FS22, ..., FS2M, and may provide the second internal data signal IDS22 to the lower half of the plurality of adders 631, 632, ..., 63M.

[0112] The upper part of multiple adders 631, 632, ..., 63M can generate the upper part of bits CDS21, CDS22, ..., CDS2M of the compensation data signal CDS2 by adding the first internal data signal IDS21 and the feedback signal FS21 based on the first part of the selection signal SEL21, ..., SEL2M, and the lower part of multiple adders 631, 632, ..., 63M can generate the lower part of bits CDS21, CDS22, ..., CDS2M of the compensation data signal CDS2 by adding the second internal data signal IDS22 and the feedback signal FS21 based on the second part of the selection signal SEL21, ..., SEL2M.

[0113] The sampling circuit 640 may generate bits SDS21, SDS22, ..., SDS2M of the sampling signal SDS2 by sampling bits CDS21, CDS22, ..., CDS2M of the compensation data signal CDS2 based on the frequency division selection signals DQS_N1, ..., DQS_NM, and may provide the sampling signal SDS2 to the deserializer 690. The sampling circuit 640 may include a plurality of limiters 641, 642, ..., 64M. Each of the plurality of limiters 641, 642, ..., 64M may generate a corresponding one of the bits SDS21, SDS22, ..., SDS2M of the sampling signal SDS2 by sampling a corresponding one of the bits CDS21, CDS22, ..., CDS2M of the compensation data signal CDS2 based on a corresponding one of the frequency division selection signals DQS_N1 to DQS_NM having a predetermined phase difference.

[0114] The feedback circuit 650 may generate feedback signals FS21, FS22, ..., FS2M by multiplying the sampling signal SDS2 and the delayed sampling signal by weights WC21 to WC2M, respectively, may provide the feedback signal FS21 to the second stage 630, and may provide the feedback signals FS22, ..., FS2M to the first stage 620. The delayed sampling signal may be obtained by sequentially delaying the sampling signal SDS2.

[0115] The feedback circuit 650 may include a plurality of taps 651, 652, ..., 65M and a plurality of delay components 661, ..., 66M-1. The plurality of delay components 661, ..., 66M-1 may generate delayed sampling signals SDS_D1, ..., SDS2_DM-1 by sequentially delaying the sampling signal SDS2. Each of the plurality of taps 651, 652, ..., 65M may generate a corresponding one of the feedback signals FS21, FS22, ..., FS2M by multiplying a corresponding one of the sampling signal SDS2 and the delayed sampling signal SDS_D1, ..., SDS2_DM-1 with a corresponding one of the weights WC21 to WC2M.

[0116] The deserializer 690 may generate deserialized data DQ by deserializing the sampling signal SDS1. The deserialized data DQ may be referred to as output data.

[0117] The frequency divider 680 may generate divided frequency strobe signals DQS_N1 to DQS_NM having a regular phase difference by dividing the data strobe signal DQS, and provide the divided frequency strobe signals DQS_N1 to DQS_NM to the sampling circuit 640 .

[0118] The control circuit 685 may generate a plurality of selection signals SEL21 to SEL2M and may provide the plurality of selection signals SEL21 to SEL2M to the second stage 630 of the decision feedback equalizer 620. The control circuit 685 may generate weights WC21 to WC2M and may provide the weights WC21 to WC2M to the feedback circuit 650 of the decision feedback equalizer 610.

[0119] Therefore, in the decision feedback equalizer 610, the adder is divided into a first stage 620 and a second stage 630 connected in cascade, and the feedback circuit 650 provides a feedback signal FS21 to the second stage 630, and provides a feedback signal FS22, ..., FS2M to the first stage 620. Therefore, the critical path and the non-critical path are separated from each other, and the decision feedback equalizer 610 operates at a high speed. In addition, the adder in the second stage 630 generates bits of the compensation data signal CDS2 by operating based on a time division scheme in response to a plurality of selection signals SEL21 to SEL2M, thereby reducing power consumption.

[0120] Fig.14 is a block diagram illustrating a receiver according to an example embodiment. Fig.14 , the receiver 1000 may include a compensation circuit 1100, a sampling circuit 1200, an output circuit 1300, and a control circuit 1400. The receiver 1000 may also include a data input pad (or pin) 1010, and may receive a data signal MLDS as a multi-level signal having three or more voltage levels, and generate output data ODAT as multi-bit data including two or more bits based on the data signal MLDS. For example, the multi-level signal may have one of three or more voltage levels different from each other during one unit interval (UI), and the multi-bit data may include two or more bits different from each other. The receiver 1000 may be included in various communication systems and / or signal transmission systems, and may be included in, for example, a semiconductor memory device and / or a memory system.

[0121] The compensation circuit 1100 can generate a plurality of data signals (or intermediate data signals) MIDS and a plurality of reference voltages VREFS by compensating for inter-symbol interference (ISI) on the data signal MLDS as a multi-level signal. Each of the plurality of reference voltages VREFS includes a plurality of compensation reference levels. The sampling circuit 1200 can generate a plurality of sampling signals SAM based on the plurality of data signals MIDS and the plurality of reference voltages VREFS. Each of the plurality of sampling signals SAM includes a plurality of decision values.

[0122] In some example embodiments, the compensation circuit 1100 and the sampling circuit 1200 may form a decision feedback equalizer (DFE) and may be implemented in a loop expansion structure. Fig.16The detailed construction of the compensation circuit 1100 and the sampling circuit 1200 is described. In some example embodiments, the compensation circuit 1100 may generate multiple compensation reference levels by performing an equalization technique on multiple reference levels. For example, the compensation circuit 1100 may perform post-mark elimination based on decision feedback equalization, and may be referred to as a post-mark elimination circuit. Multiple reference levels may be used to sense or detect the voltage level of a multi-level signal. When equalization is performed on multiple reference levels, multiple compensation reference levels may be generated by adjusting or controlling the increase and / or decrease direction of the multiple reference levels and the amount of change of the multiple reference levels. For example, the sampling circuit 1200 may perform a decision (or determination) based on the output of the compensation circuit 1100, and may be referred to as a decision circuit or a limiter circuit.

[0123] The output circuit 1300 may generate output data ODAT as multi-bit data based on a plurality of sampling signals SAM, and may select a current value of the output data ODAT based on a previous value of the output data ODAT. For example, the output circuit 1300 may be used to determine or determine an output in a loop unrolling structure. Fig.17 The detailed configuration of the output circuit 1300 is described.

[0124] The control circuit 1400 may generate a selection signal SEL and a frequency division selection signal DQS_N, and may provide the selection signal SEL and the frequency division selection signal DQS_N to the sampling circuit 1200. The data input pad 1010 may be connected to the compensation circuit 1100 and may receive the data signal MLDS. For example, the pad may be a contact pad or a contact pin, but example embodiments are not limited thereto.

[0125] The data signal MLDS is received based on a multi-level signaling scheme. The multi-level signaling scheme can be used as a means to compress the bandwidth required to send data at a given bit rate. In a simple binary scheme, two single symbols (usually two voltage levels) can be used to represent "1" and "0", and therefore the symbol rate can be equal to the bit rate. In contrast, the principle of the multi-level signaling scheme can be to use a table of a larger alphabet m symbols to represent data so that each symbol can represent more than one data bit. As a result, the number of symbols that need to be sent can be less than the number of bits (e.g., the symbol rate can be less than the bit rate), and therefore the bandwidth can be compressed.

[0126] In other words, a multi-level signaling scheme can be used to increase the data transmission (or delivery) rate without increasing the frequency of data transmission and / or the transmission power of the transmitted data. An example of one type of multi-level signaling scheme can be a pulse amplitude modulation (PAM) scheme, in which a unique symbol of a multi-level signal can represent multiple data bits. The number of possible pulse amplitudes in a digital PAM scheme can be a power of two. For example, in a 4-level PAM (e.g., in PAM4), there can be 22 possible discrete pulse amplitudes, there can be 2 in 8-level PAM (e.g., in PAM8) 3 possible discrete pulse amplitudes, and in 16-level PAM (e.g., in PAM16) there can be 2 4 However, example embodiments are not limited thereto, and example embodiments may be applied or used for a K-level PAM (eg, PAM(K)) having K possible pulse amplitudes, where K is a natural number greater than or equal to 3.

[0127] In a general data I / O interface, a data signal is sent to a receiver through a channel. Recently, with the increase of data rate, interference signals caused by channel influence may increase, and therefore the characteristics and / or quality of the received signal may deteriorate or deteriorate. In order to solve this problem or improve signal integrity (SI), equalization techniques have been used to restore or recover the received signal by eliminating or compensating for interference signals. One of the various equalization techniques is decision feedback equalization. In decision feedback equalization, signal integrity can be improved by eliminating interference signals (e.g., by eliminating the post-mark causing inter-symbol interference), however, since the current data is compensated after determining the signal compensation amount according to the result of the previous data of the decision, there may be feedback delay. In order to reduce feedback delay, decision feedback equalization using a loop expansion structure has been studied. In the loop expansion structure, output candidates can be generated by pre-calculating compensation signals based on all possible results of the decision value, and then one of the output candidates can be selected as the final output value.

[0128] Fig.15A and Fig. 15B is a diagram for describing a data signal generated based on a multi-level signaling scheme according to an example embodiment. Specifically, Fig.15A 1 shows an ideal eye diagram of a data signal (eg, a PAM4 signal) generated based on a 4-level scheme (eg, a PAM4 scheme) as an example of a multi-level signaling scheme (eg, a PAM scheme), and Fig. 15B By simplifying Fig.15A An ideal eye diagram is shown in the figure.

[0129] Reference Fig.15A, eye diagrams can be used to indicate the quality of signals in high-speed transmission. For example, an eye diagram may represent four symbols of a signal (e.g., "00", "01", "10", and "11"), and each of the four symbols may be represented by a corresponding one of different voltage levels (e.g., voltage amplitudes) VL11, VL21, VL31, and VL41. Eye diagrams can be used to provide a healthy visual indication of signal integrity and may indicate the noise margin of a data signal. For example, when using Gray code, voltage levels VL11, VL21, VL31, and VL41 may be mapped to "00", "01", "11", and "10", respectively.

[0130] To generate an eye diagram, an oscilloscope or other computing device may sample a digital signal according to a sampling period SP (e.g., a unit interval or a bit period). The sampling period SP may be defined by a clock associated with the transmission of the measurement signal. The oscilloscope or other computing device may measure the voltage level of the signal during the sampling period SP to form a plurality of traces TRC. Various characteristics associated with the measured signal may be determined by superimposing the plurality of traces TRC.

[0131] The eye diagram can be used to identify multiple characteristics of the communication signal, such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. For example, the width W of the eye in the eye diagram can be used to indicate the timing synchronization of the measured signal or the jitter effect of the measured signal. For example, the eye diagram can indicate the eye opening OP, which represents the peak-to-peak voltage difference between various voltage levels VL11, VL21, VL31, and VL41. The eye diagram opening OP can be related to the voltage margin between different voltage levels VL11, VL21, VL31, and VL41 used to distinguish the measured signal. For example, the eye diagram can be used to identify the rise time RT and / or the fall time FT of the transition from the first amplitude to the second amplitude. The rise time RT or the fall time FT can indicate the time required to transition from one voltage level to another voltage level, and can be related or associated with the rising edge and the falling edge, respectively. For example, the eye diagram can be used to identify the amount of jitter JT in the measured signal. Jitter JT can refer to the timing error caused by the misalignment of the rise time and the fall time.

[0132] Reference Fig. 15B , showing different first voltage levels VL11, second voltage levels VL21, third voltage levels VL31, and fourth voltage levels VL41 of the data signal as the PAM4 signal, and showing different first reference levels VREF_H, second reference levels VREF_M, and third reference levels VREF_L for sensing or detecting the levels of the data signal. For example, the number of reference levels may be one less than the number of voltage levels of the data signal.

[0133] The first voltage level VL11, which is the lowest voltage level among the voltage levels VL11 to VL41, may be lower than the second voltage level VL21, the second voltage level VL21 may be lower than the third voltage level VL31, and the third voltage level VL31 may be lower than the fourth voltage level VL41, which is the highest voltage level among the voltage levels VL11 to VL41. In addition, the first reference level VREF_H may be a level between the third voltage level VL31 and the fourth voltage level VL41, the second reference level VREF_M may be a level between the second voltage level VL21 and the third voltage level VL31, and the third reference level VREF_L may be a level between the first voltage level VL11 and the second voltage level VL21. The voltage level (e.g., sign) of the data signal may be decided or determined based on the result of comparing the data signal with the reference levels VREF_H, VREF_M, and VREF_L.

[0134] Fig.16 is a diagram showing a method according to an example embodiment Fig.14 A block diagram of an example of a receiver is shown in FIG. Fig.16 , the receiver 1002 may include a compensation circuit 1102, a sampling circuit 1202, an output circuit 1302, and a control circuit 1400. The receiver 1002 may also include a data input pad 1010, a first buffer 1020, and a second buffer 1030. The data input pad 1010 may receive a data signal MLDS1 having one of a first voltage level VL11, a second voltage level VL21, a third voltage level VL31, and a fourth voltage level VL41 during one UI.

[0135] The compensation circuit 1102 may include a first post-mark canceller 1110 , a second post-mark canceller 1120 , a third post-mark canceller 1130 , and a fourth post-mark canceller 1140 .

[0136] The first post-mark eliminator 1110 may generate a first data signal MIDS1 and a first reference voltage VREF1 based on a previous value DATA_PRE of the output data ODAT1 being "10" (e.g., corresponding to the fourth voltage level VL41). The second post-mark eliminator 1120 may generate a second data signal MIDS2 and a second reference voltage VREF2 based on a previous value DATA_PRE of the output data ODAT1 being "11" (e.g., corresponding to the third voltage level VL31). The third post-mark eliminator 1130 may generate a third data signal MIDS3 and a third reference voltage VREF3 based on a previous value DATA_PRE of the output data ODAT1 being "01" (e.g., corresponding to the second voltage level VL21). The fourth post-mark eliminator 1140 may generate a fourth data signal MIDS4 and a fourth reference voltage VREF4 based on a previous value DATA_PRE of the output data ODAT1 being "00" (e.g., corresponding to the first voltage level VL11). For example, each post-mark eliminator may include a feedback filter having an n-tap structure, where n is a natural number.

[0137] The first reference voltage VREF1 may include a first compensation reference level VREF_H1, a second compensation reference level VREF_M1, and a third compensation reference level VREF_L1. The second reference voltage VREF2 may include a fourth compensation reference level VREF_H2, a fifth compensation reference level VREF_M2, and a sixth compensation reference level VREF_L2. The third reference voltage VREF3 may include a seventh compensation reference level VREF_H3, an eighth compensation reference level VREF_M3, and a ninth compensation reference level VREF_L3. The fourth reference voltage VREF4 may include a tenth compensation reference level VREF_H4, an eleventh compensation reference level VREF_M4, and a twelfth compensation reference level VREF_L4. Each of the first compensation reference level VREF_H1, the fourth compensation reference level VREF_H2, the seventh compensation reference level VREF_H3, and the tenth compensation reference level VREF_H4 may correspond to the first reference level VREF_H, and may be generated by increasing or decreasing the first reference level VREF_H by a specific level based on equalization. Similarly, each of the second compensation reference level VREF_M1, the fifth compensation reference level VREF_M2, the eighth compensation reference level VREF_M3, and the eleventh compensation reference level VREF_M4 may correspond to the second reference level VREF_M, and may be generated by increasing or decreasing the second reference level VREF_M by a specific level based on equalization. Each of the third compensation reference level VREF_L1, the sixth compensation reference level VREF_L2, the ninth compensation reference level VREF_L3, and the twelfth compensation reference level VREF_L4 may correspond to the third reference level VREF_L, and may be generated by increasing or decreasing the third reference level VREF_L by a specific level based on equalization.

[0138] In some example embodiments, the data signals MIDS1 to MIDS4 may be substantially identical to each other. In other example embodiments, the first data signal MIDS1 and the first reference voltage VREF1 may be provided as a pair of differential signals, another data signal and a corresponding reference voltage may also be provided as a pair of differential signals, and thus the data signals MIDS1 to MIDS4 may be different from each other.

[0139] The sampling circuit 1202 may include a first limiter circuit 1210, a second limiter circuit 1220, a third limiter circuit 1230, and a fourth limiter circuit 1240. The first limiter circuit 1210 may generate a first sampling signal SAM1 by comparing the first data signal MIDS1 with the first compensation reference level VREF_H1, the second compensation reference level VREF_M1, and the third compensation reference level VREF_L1. The second limiter circuit 1220 may generate a second sampling signal SAM2 by comparing the second data signal MIDS2 with the fourth compensation reference level VREF_H2, the fifth compensation reference level VREF_M2, and the sixth compensation reference level VREF_L2. The third limiter circuit 1230 may generate a third sampling signal SAM3 by comparing the third data signal MIDS3 with the seventh compensation reference level VREF_H3, the eighth compensation reference level VREF_M3, and the ninth compensation reference level VREF_L3. The fourth limiter circuit 1240 may generate a fourth sampling signal SAM4 by comparing the fourth data signal MIDS4 with the tenth compensation reference level VREF_H4 , the eleventh compensation reference level VREF_M4 , and the twelfth compensation reference level VREF_L4 .

[0140] The first sampling signal SAM1 may include a first decision value VOH1, a second decision value VOM1, and a third decision value VOL1. The second sampling signal SAM2 may include a fourth decision value VOH2, a fifth decision value VOM2, and a sixth decision value VOL2. The third sampling signal SAM3 may include a seventh decision value VOH3, an eighth decision value VOM3, and a ninth decision value VOL3. The fourth sampling signal SAM4 may include a tenth decision value VOH4, an eleventh decision value VOM4, and a twelfth decision value VOL4. Each of the first decision value VOH1, the fourth decision value VOH2, the seventh decision value VOH3, and the tenth decision value VOH4 may represent a decision result obtained by comparing the data signal MLDS1 with a corresponding one of the first reference levels equalized by the compensation circuit 1102. Similarly, each of the second decision value VOM1, the fifth decision value VOM2, the eighth decision value VOM3, and the eleventh decision value VOM4 may represent a decision result obtained by comparing the data signal MLDS1 with a corresponding one of the second reference levels equalized by the compensation circuit 1102. Each of the third decision value VOL1 , the sixth decision value VOL2 , the ninth decision value VOL3 , and the twelfth decision value VOL4 may represent a decision result obtained by comparing the data signal MLDS1 with a corresponding one of the third reference levels equalized by the compensation circuit 1102 .

[0141] The output circuit 1302 may generate output data ODAT1 including a first bit MSB1 and a second bit LSB1 based on the first to twelfth decision values ​​VOH1 to VOH4, VOM1 to VOM4, and VOL1 to VOL4. The first bit MSB1 and the second bit LSB1 may be the most significant bit (MSB) and the least significant bit (LSB) of the output data ODAT1, respectively. For example, when the output data ODAT1 is "10", the first bit MSB1 may be "1" and the second bit LSB1 may be "0".

[0142] The first buffer 1020 may buffer the data signal MLDS1 and may provide the buffered data signal to the first and fourth post-mark erasers 1110 and 1140. The second buffer 1030 may buffer the data signal MLDS1 and may provide the buffered data signal to the second and third post-mark erasers 1120 and 1130.

[0143] The control circuit 1400 may generate a selection signal SEL and a frequency division selection signal DQS_N, and may provide the selection signal SEL and the frequency division selection signal DQS_N to the sampling circuit 1202 .

[0144] As described above, receiver 1002 may be implemented in a loop unrolling structure such that compensation circuit 1102 and sampling circuit 1202 pre-calculate all possible decision results and generate output candidates based on all possible decision results, and output circuit 1302 selects one of the output candidates as the final output value.

[0145] In some example embodiments, as will be referred to Fig.17 As described above, the output circuit 1302 may select or determine the output value of the loop unrolling structure based on the first bit MSB1 and the second bit LSB1. In this example, the number of multiplexers and flip-flops may be reduced, and the load at the input terminal observed by the buffer may be reduced.

[0146] Fig.17 is a diagram showing a method according to an example embodiment Fig.16 A block diagram of an example of an output circuit in a receiver. Fig.17 The output circuit 1302a may include a first decoder 1312, a second decoder 1314, a third decoder 1316, a fourth decoder 1318, a first multiplexer 1322, and a second multiplexer 1324. The output circuit 1302a may also include flip-flops (FFs) 1332 and 1334, each of which operates based on a data strobe signal DQS.

[0147] The first decoder 1312 may generate a first MSB MSB_10 and a first LSB LSB_10 based on the first decision value VOH1, the second decision value VOM1, and the third decision value VOL1. The second decoder 1314 may generate a second MSB MSB_11 and a second LSB LSB_11 based on the fourth decision value VOH2, the fifth decision value VOM2, and the sixth decision value VOL2. The third decoder 1316 may generate a third MSB MSB_01 and a third LSB LSB_01 based on the seventh decision value VOH3, the eighth decision value VOM3, and the ninth decision value VOL3. The fourth decoder 1318 may generate a fourth MSB MSB_00 and a first LSB LSB_00 based on the tenth decision value VOH4, the eleventh decision value VOM4, and the twelfth decision value VOL4.

[0148] The first multiplexer 1322 may output a first bit (e.g., MSB) MSB1 of the output data ODAT1 by selecting one of the first MSB MSB_10, the second MSB MSB_11, the third MSB MSB_01, and the fourth MSB MSB_00. The second multiplexer 1324 may output a second bit (e.g., LSB) LSB1 of the output data ODAT1 by selecting one of the first LSB LSB_10, the second LSB LSB_11, the third LSB LSB_01, and the fourth LSB LSB_00. The first bit MSB1 and the second bit LSB1 of the output data ODAT1 may be synchronized with the data strobe signal DQS through the flip-flops 1332 and 1334.

[0149] Fig.18 is a block diagram illustrating a semiconductor memory device according to an example embodiment. Fig.18 , the semiconductor memory device 700 may include at least one buffer die 710 and a plurality of memory dies 720 - 1 to 720 - p (p is a natural number equal to or greater than 3) that provide soft error analysis and correction functions in a stacked chip structure.

[0150] A plurality of memory dies 720-1 to 720-p are stacked on the buffer die 710, and data is transmitted through a plurality of through silicon vias (TSV) lines. At least one of the memory dies 720-1 to 720-p may include a unit core 721 for storing data and a unit core ECC engine 723 for generating transmission parity bits (i.e., transmission parity data) based on transmission data to be sent to at least one buffer die 710. The unit core 721 may include a plurality of memory cells having a DRAM cell structure.

[0151] The buffer die 710 may include a via ECC engine 712, which, when a transmission error is detected from the transmission data received through the TSV line, uses the transmission parity bits to correct the transmission error and generates error-corrected data. The buffer die 710 may also include a receiver 713 and a transmitter 714. The receiver 713 may use Fig. 7A Receiver 400.

[0152] The semiconductor memory device 700 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals via TSV lines. TSV lines may also be referred to as “through electrodes.” The unit core ECC engine 723 may perform error correction on data output from the memory die 720 - p before transmitting the transmission data.

[0153] A transmission error occurring at the transmission data may be caused by noise occurring at the TSV line. Data failures due to noise occurring at the TSV line can be distinguished from data failures due to erroneous operation of the memory die, so they can be regarded as soft data failures (or soft errors). Soft data failures may be generated due to transmission failures on the transmission path and can be detected and remedied by ECC operations.

[0154] Through the above description, the data TSV line group 732 formed at one memory die 720-p may include TSV lines L1, L2 to Lp, and the parity TSV line group 734 may include TSV lines L10 to Lq. The TSV lines L1, L2 to Lp of the data TSV line group 732 and the parity TSV lines L10 to Lq of the parity TSV line group 734 may be connected to micro bumps MCB, which are correspondingly formed between the memory dies 720-1 to 720-p. At least one of the memory dies 720-1 to 720-p may include a DRAM cell, each of which includes at least one access transistor and one storage capacitor.

[0155] The semiconductor memory device 700 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host through the data bus B10. The buffer die 710 may be connected to the memory controller through the data bus B10. The unit core ECC engine 723 may output the transmission parity bit and the transmission data through the parity TSV line group 734 and the data TSV line group 732, respectively. The output transmission data may be data corrected by the unit core ECC engine 723.

[0156] The via ECC engine 712 may determine whether a transmission error occurs at the transmission data received through the data TSV line group 732 based on the transmission parity bits received through the parity TSV line group 734. When a transmission error is detected, the via ECC engine 712 may correct the transmission error on the transmission data using the transmission parity bits. When the transmission error is uncorrectable, the via ECC engine 712 may output information indicating that an uncorrectable data error has occurred.

[0157] Fig.19 is a diagram showing a configuration of a semiconductor package including a stacked memory device according to example embodiments. Fig.19 , the semiconductor package 900 may include one or more stacked memory devices 910 and a graphics processing unit (GPU) 920 .

[0158] The stacked memory device 910 and the GPU 920 may be mounted on an interposer 930, and the interposer 930 on which the stacked memory device 910 and the GPU 920 are mounted may be mounted on a package substrate 940, and the package substrate 940 is mounted on solder balls 950. The GPU 920 may correspond to a semiconductor device that can perform a memory control function, and, for example, the GPU 920 may be implemented as an application processor (AP). The GPU 920 may include a memory controller MCT 925.

[0159] The stacked memory device 910 may be implemented in various forms, and the stacked memory device 910 may be a memory device in the form of a high bandwidth memory (HBM) in which a plurality of layers are stacked. Therefore, the stacked memory device 910 may include a buffer die and a plurality of memory dies, and the buffer die may include the above-mentioned receiver.

[0160] A plurality of stacked memory devices 910 may be mounted on the interposer 930, and the GPU 920 may communicate with the plurality of stacked memory devices 910. For example, each of the stacked memory device 910 and the GPU 920 may include a physical region, and communication may be performed between the stacked memory device 910 and the GPU 920 via the physical region. Meanwhile, when the stacked memory device 910 includes a direct access region, a test signal may be provided to the stacked memory device 910 through a conductive device (e.g., a solder ball 950) mounted below the package substrate 940 and the direct access region.

[0161] Fig. 20 is a block diagram illustrating a communication system according to an example embodiment. Fig. 20 , the communication system 1500 includes a first communication device 1510 , a second communication device 1530 and a channel 1550 .

[0162] The first communication device 1510 includes a first transmitter 1511 and a first receiver 1512. The second communication device 1530 includes a second transmitter 1531 and a second receiver 1532. The first transmitter 1511 and the first receiver 1512 are connected to the second transmitter 1531 and the second receiver 1532 through a channel 1550. In some example embodiments, each of the first communication device 1510 and the second communication device 1530 may include a plurality of transmitters and a plurality of receivers, and the communication system 1500 may include a plurality of channels for connecting the plurality of transmitters and the plurality of receivers.

[0163] Receivers 1512 and 1532 may be receivers according to example embodiments and may include a decision feedback equalizer. The decision feedback equalizer includes an adder, the adder is divided into a first stage and a second stage connected in cascade, and the second stage adder operates based on a time division scheme in response to a plurality of selection signals, thereby reducing power consumption.

[0164] The present invention can be applied to various devices and systems including memory devices and memory systems. For example, the present invention can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0165] The above is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

Claims

1. A receiver, comprising: A decision feedback equalizer comprising a cascade arrangement of a first stage having a first plurality of adders therein and a second stage having a second plurality of adders therein, the decision feedback equalizer being configured to: generating a compensated data signal by adding a current value of the data signal to a plurality of feedback signals in response to the plurality of selection signals; generating a sampling signal including a decision value by sampling bits of the compensation data signal in response to a plurality of frequency-divided strobe signals; generating the plurality of feedback signals in response to a plurality of weights, the sampled signal, and at least one delayed version of the sampled signal; as well as A first portion of the plurality of feedback signals is provided to the second stage, and a second portion of the plurality of feedback signals is provided to the first stage.

2. The receiver of claim 1, further comprising: a deserializer configured to generate output data by deserializing the sampled signal; as well as a control circuit configured to generate the plurality of selection signals; wherein the first stage is configured to generate a first internal data signal and a second internal data signal in response to the data signal and the second portion of the plurality of feedback signals; wherein the second stage is configured to generate the compensation data signal in response to the first internal data signal, the second internal data signal and the first portion of the plurality of feedback signals; and Wherein, the decision feedback equalizer further includes: a sampling circuit configured to generate bits of the sampling signal by sampling bits of the compensation data signal in response to the plurality of frequency-divided strobe signals; and A feedback circuit is configured to generate the plurality of feedback signals by multiplying the sampled signal and a delayed version of the sampled signal by corresponding weights of the plurality of weights, respectively.

3. The receiver as claimed in claim 2, in, The multiple feedback signals include a first feedback signal, a second feedback signal, a third feedback signal and a fourth feedback signal; The plurality of selection signals include a first selection signal, a second selection signal, a third selection signal and a fourth selection signal, and the first selection signal, the second selection signal, the third selection signal and the fourth selection signal are staggered by 90°, 180° and 270° respectively relative to the other selection signals; Wherein, the first stage includes a first adder and a second adder; wherein the second stage includes a third adder, a fourth adder, a fifth adder and a sixth adder; and Wherein, each of the first adder, the third adder and the fourth adder is symmetrically configured with a corresponding one of the second adder, the fifth adder and the sixth adder.

4. The receiver as claimed in claim 3, in, The first adder is configured to generate the first internal data signal by adding the data signal and the second to fourth feedback signals; and The second adder is configured to generate the second internal data signal by adding the data signal and the second to fourth feedback signals.

5. The receiver according to claim 3, in, The third adder is configured to generate a first bit of the compensation data signal by adding the first internal data signal to the first feedback signal in response to the first selection signal during a first time interval; wherein the fourth adder is configured to generate a second bit of the compensation data signal by adding the first internal data signal to the first feedback signal in response to the third selection signal during a third time interval that does not overlap with the first time interval; wherein the fifth adder is configured to generate a third bit of the compensation data signal by adding the second internal data signal to the first feedback signal in response to the second selection signal during a second time interval; and The sixth adder is configured to generate a fourth bit of the compensation data signal by adding the second internal data signal to the first feedback signal in response to the fourth selection signal during a fourth time interval that does not overlap with the second time interval.

6. The receiver of claim 5, wherein: The decision feedback equalizer also includes: a load circuit including a first resistor, a second resistor, a third resistor, and a fourth resistor, each of the first resistor, the second resistor, the third resistor, and the fourth resistor being connected to a power supply voltage; Wherein, the third adder comprises: a first n-channel metal oxide semiconductor transistor coupled to the first adder at a first node, coupled to the first resistor and a first tap generating the first feedback signal at a third node, and having a gate receiving the first selection signal; and a second n-channel metal oxide semiconductor transistor coupled to the first adder at a second node, coupled to the second resistor and the first tap at a fourth node, and having a gate receiving the first selection signal; and Wherein, the fourth adder comprises: a third n-channel metal oxide semiconductor transistor coupled to the first adder at the second node, coupled to the third resistor and the first tap at a fifth node, and having a gate receiving the third selection signal; and A fourth n-channel metal oxide semiconductor transistor is coupled to the first adder at the first node, coupled to the fourth resistor and the first tap at a sixth node, and has a gate receiving the third selection signal.

7. The receiver of claim 6, wherein: The first and second n-channel metal oxide semiconductor transistors are configured to connect the first and second nodes to the third and fourth nodes, respectively, during the first time interval when the first selection signal is activated.

8. The receiver of claim 6, wherein: The third and fourth n-channel metal oxide semiconductor transistors are configured to connect the second and first nodes to the fifth and sixth nodes, respectively, during the third time interval in which the third selection signal is activated.

9. The receiver of claim 5, wherein: The decision feedback equalizer also includes: a load circuit including a first p-channel metal oxide semiconductor transistor, a second p-channel metal oxide semiconductor transistor, a third p-channel metal oxide semiconductor transistor, and a fourth p-channel metal oxide semiconductor transistor connected to a power supply voltage; Wherein, the third adder comprises: a first n-channel metal oxide semiconductor transistor coupled to the first adder at a first node, coupled to the first p-channel metal oxide semiconductor transistor and a first tap generating the first feedback signal at a third node, and having a gate receiving the first selection signal; and a second n-channel metal oxide semiconductor transistor coupled to the first adder at a second node, coupled to the second p-channel metal oxide semiconductor transistor and the first tap at a fourth node, and having a gate receiving the first selection signal; Wherein, the fourth adder comprises: a third n-channel MOS transistor coupled to the first adder at the second node, coupled to the third p-channel MOS transistor and the first tap at a fifth node, and having a gate receiving the third selection signal; and a fourth n-channel metal oxide semiconductor transistor coupled to the first adder at the first node, coupled to the fourth p-channel metal oxide semiconductor transistor and the first tap at a sixth node, and having a gate receiving the third selection signal; and The gate of the first p-channel metal oxide semiconductor transistor and the gate of the second p-channel metal oxide semiconductor transistor receive the third selection signal, and the gate of the third p-channel metal oxide semiconductor transistor and the gate of the fourth p-channel metal oxide semiconductor transistor receive the first selection signal.

10. The receiver of claim 9, wherein: During the first time interval in which the first selection signal is activated, the first n-channel metal oxide semiconductor transistor and the second n-channel metal oxide semiconductor transistor are configured to connect the first node and the second node to the third node and the fourth node, respectively, and each of the first p-channel metal oxide semiconductor transistor and the second p-channel metal oxide semiconductor transistor supplies a current based on the power supply voltage to a corresponding one of the third node and the fourth node.

11. The receiver of claim 9, wherein: During the third time interval in which the third selection signal is activated, the first n-channel metal oxide semiconductor transistor and the second n-channel metal oxide semiconductor transistor are configured to maintain voltage levels of the third node and the fourth node, respectively.

12. The receiver of claim 9, wherein: During the third time interval in which the third selection signal is activated, the third n-channel metal oxide semiconductor transistor and the fourth n-channel metal oxide semiconductor transistor are configured to connect the second node and the first node to the fifth node and the sixth node, respectively, and each of the third p-channel metal oxide semiconductor transistor and the fourth p-channel metal oxide semiconductor transistor supplies a current based on the power supply voltage to a corresponding one of the fifth node and the sixth node.

13. The receiver of claim 9, wherein: During the first time interval in which the first selection signal is activated, the third p-channel metal oxide semiconductor transistor and the fourth p-channel metal oxide semiconductor transistor are configured to maintain voltage levels of the fifth node and the sixth node, respectively.

14. The receiver according to claim 3, in, The frequency division gating signal comprises a first frequency division gating signal, a second frequency division gating signal, a third frequency division gating signal and a fourth frequency division gating signal, wherein the first frequency division gating signal, the second frequency division gating signal, the third frequency division gating signal and the fourth frequency division gating signal are staggered by 90°, 180° and 270° respectively relative to other gating signals; Wherein, the sampling circuit comprises: a first limiter configured to generate a first bit of the sampled signal by sampling a first bit of the compensation data signal in response to the first frequency-divided selection signal; a second limiter configured to generate a second bit of the sampled signal by sampling a second bit of the compensation data signal in response to the third frequency-divided selection signal; a third limiter configured to generate a third bit of the sampled signal by sampling a third bit of the compensated data signal in response to the second frequency-divided selection signal; and A fourth limiter is configured to generate a fourth bit of the sampled signal by sampling a fourth bit of the compensation data signal in response to the fourth frequency-divided gate signal.

15. The receiver according to claim 3, in, The control circuit is further configured to generate the plurality of weights including a first weight, a second weight, a third weight, and a fourth weight; as well as Wherein, the feedback circuit comprises: a first tap configured to generate the first feedback signal by multiplying the sampled signal by the first weight, and provide the first feedback signal to the third adder to the sixth adder; a first delay element configured to output a first delayed sampling signal by delaying the sampling signal; a second tap configured to generate the second feedback signal by multiplying the first delayed sampled signal by the second weight, and provide the second feedback signal to the first adder and the second adder; a second delay element configured to output a second delayed sampling signal by delaying the first delayed sampling signal; a third tap configured to generate the third feedback signal by multiplying the second delayed sampled signal by the third weight, and provide the third feedback signal to the first adder and the second adder; a third delay element configured to output a third delayed sampling signal by delaying the second delayed sampling signal; and a fourth tap configured to generate the fourth feedback signal by multiplying the third delayed sampled signal by the fourth weight, and provide the fourth feedback signal to the first adder and the second adder.

16. The receiver of claim 1, further comprising: A frequency divider is configured to generate a first frequency division selection signal, a second frequency division selection signal, a third frequency division selection signal and a fourth frequency division selection signal having a phase difference of 90 degrees relative to each other based on a data selection signal including a first selection signal and a second selection signal having a phase difference of 180 degrees relative to each other.

17. A semiconductor memory device comprising: a receiver connected to the memory controller via a channel, the receiver being configured to generate output data based on a data signal received from the channel; as well as a control logic circuit configured to control the receiver; The receiver includes a decision feedback equalizer, the decision feedback equalizer includes a first stage and a second stage, the first stage and the second stage include a plurality of adders connected in cascade, and the decision feedback equalizer is configured as follows: generating a compensated data signal by adding a current value of the data signal to a feedback signal based on a plurality of selection signals; generating a sampling signal including a decision value by sampling bits of the compensation data signal based on the frequency-divided selection signal; generating the feedback signal based on a weight and the sampled signal corresponding to a previous value of the data signal; providing a first portion of the feedback signal to the second stage; and providing a second portion of the feedback signal to the first stage; a deserializer configured to generate the output data by deserializing the sampled signal; and A control circuit is configured to generate the plurality of selection signals and provide the plurality of selection signals to the decision feedback equalizer.

18. The semiconductor memory device according to claim 17, further comprising: a memory cell array comprising a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, the memory cell array being configured to store the output data; and Wherein, the decision feedback equalizer comprises: a multi-stage adder circuit having the first stage and the second stage, the first stage being configured to generate a first internal data signal and a second internal data signal based on the data signal and the second portion of the feedback signal, and the second stage being configured to generate the compensation data signal based on the first internal data signal, the second internal data signal and the first portion of the feedback signal; a sampling circuit configured to generate bits of the sampling signal by sampling bits of the compensation data in response to the frequency-divided strobe signal; and A feedback circuit is configured to generate the feedback signal by multiplying the sampling signal and the delayed sampling signal by corresponding weights in the weights, wherein the delayed sampling signal is obtained by delaying the sampling signal by a corresponding delay amount.

19. The semiconductor memory device according to claim 17, wherein: The data signal is a multi-level signal having one voltage level among three or more voltage levels different from each other.

20. A receiver, comprising: A decision feedback equalizer comprising a first stage and a second stage, wherein the first stage and the second stage comprise a plurality of adders connected in cascade, the decision feedback equalizer being configured as follows: generating a compensated data signal by adding a current value of the data signal to the feedback signal based on the plurality of selection signals; generating a sampling signal including a decision value by sampling bits of the compensation data signal based on the frequency-divided selection signal; generating the feedback signal based on a weight and the sampled signal corresponding to a previous value of the data signal; providing a first portion of the feedback signal to the second stage; as well as providing a second portion of the feedback signal to the first stage; a deserializer configured to generate output data by deserializing the sampled signal; as well as a control circuit configured to generate the plurality of selection signals and provide the plurality of selection signals to the decision feedback equalizer, Wherein, the decision feedback equalizer is configured as: generating a first internal data signal and a second internal data signal by adding the data signal to the second portion of the feedback signal; as well as The compensation data signal is generated by adding the first internal data signal, the second internal data signal, and the first portion of the feedback signal in a time division scheme based on the plurality of selection signals.

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