Memory refreshing method, memory controller, storage system and computing equipment

Abstract

The invention provides a memory refreshing method, a memory controller, a storage system and computing equipment, the method is applied to the memory controller, the memory controller comprises a counter, and the counter is used for counting delayed refreshing commands; the method comprises the steps that under the condition that the memory controller is switched to a low-power-consumption working mode, the memory controller sends a first number of refresh commands to a memory, and the first number is not smaller than the number of delayed refresh commands counted by the counter; under the condition that the memory controller sends the first number of refresh commands, the memory controller sends refresh commands to a memory according to a set frequency; wherein the frequency of sending the first number of refresh commands by the memory controller is greater than the set frequency. By adopting the method, the system power consumption caused by the refreshing operation of the scheduling memory can be reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory refresh method, a memory controller, a storage system and a computing device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is the most common system memory. In order to maintain data, DRAM uses capacitors for storage, but it can only keep data for a short time, so it must be refreshed every once in a while. If the storage unit is not refreshed, the stored information will be lost. In order to ensure that data is not lost, the memory controller must continuously send refresh commands to DRAM. During this process, the refresh command and the read / write access request to the memory may occupy the command bus at the same time. In this case, the refresh command needs to be scheduled. For example, when the refresh command conflicts with the read / write access request, the refresh command will be delayed for a period of time before being sent.

[0003] As the size and speed of DRAM devices increase, the refresh operation on the DRAM and the scheduling operation of the refresh command become more and more frequent, and the resulting system power consumption also increases significantly. Summary of the invention

[0004] Based on the above technical problems, the present application proposes a memory refresh method, a memory controller, a storage system and a computing device, which can reduce the system power consumption caused by scheduling refresh operations.

[0005] The first aspect of the present application proposes a memory refresh method, characterized in that it is applied to a memory controller, and the memory controller includes a counter for counting delayed refresh commands; the method includes: when the memory controller switches to a low-power working mode, the memory controller sends a first number of refresh commands to the memory, and the first number is not less than the number of delayed refresh commands counted by the counter; when the memory controller has sent the first number of refresh commands, the memory controller sends refresh commands to the memory at a set frequency; wherein the frequency at which the memory controller sends the first number of refresh commands is greater than the set frequency.

[0006] The second aspect of the present application proposes a memory controller, which includes a counter for counting delayed refresh commands; the memory controller includes: a refresh module, which is used to send a first number of refresh commands to the memory when the memory controller switches to a low-power working mode, and the first number is not less than the number of delayed refresh commands counted by the counter; after sending the first number of refresh commands, sending refresh commands to the memory at a set frequency; wherein the frequency at which the refresh module sends the first number of refresh commands is greater than the set frequency.

[0007] A third aspect of the present application provides a storage system, including a memory controller and a memory connected to the memory controller, wherein the memory controller is configured to implement the above-mentioned memory refresh method.

[0008] A fourth aspect of the present application provides a computing device, comprising the above-mentioned storage system.

[0009] Based on any one of the first to fourth aspects above, the memory refresh method proposed in the present application reissues the delayed refresh command to the memory at a higher frequency when the memory controller switches to the low-power working mode, and after the refresh command reissue is completed, the refresh command sending frequency is adjusted to a lower frequency. The above scheme reissues the refresh command when the memory controller is in an idle state and enters the low-power working mode, which can reduce the system power consumption of the reissued refresh command. At the same time, the above scheme quickly completes the refresh command reissue at a higher frequency when the memory controller enters the low-power working mode, and then reduces the refresh command sending frequency to the normal frequency, which can avoid the increase in system power consumption due to maintaining a high refresh frequency for a long time in the low-power working mode.

[0010] In some implementations, the method further includes: predicting the duration of the next idle cycle of the memory controller based on the historical idle cycle distribution of the memory controller; the idle cycle is a working cycle in which there is no read or write access request to the memory; when it is determined that the duration of the next idle cycle of the memory controller is greater than a set duration threshold, when the memory controller enters the next idle cycle, switching the working mode of the memory controller to a low power working mode. Based on this implementation, by predicting the next idle cycle of the memory controller through the historical idle cycle distribution, the idle cycle duration of the memory controller can be predicted in advance, so that the memory controller can be controlled to switch to a low power working mode in a timely manner, which is conducive to reducing system power consumption.

[0011] In some implementations, when the memory controller switches to a low power mode, the memory controller sends a first number of refresh commands to the memory, including: when the memory controller switches to a low power mode, the memory controller sends a first number of refresh commands to the memory at a first frequency, the first frequency being greater than the set frequency. Based on this implementation, by adjusting the refresh command sending frequency of the memory controller, the refresh command resending operation can be implemented more efficiently and conveniently.

[0012] In some implementations, when the memory controller switches to the low power mode, the memory controller sends a first number of refresh commands to the memory, including: when the memory controller switches to the low power mode, the memory controller continuously sends the first number of refresh commands to the memory. Based on this implementation, the memory controller continuously reissues the refresh commands after entering the low power mode, which can improve the efficiency of reissuing the refresh commands.

[0013] In some implementations, the first number is not less than the number of delayed refresh commands and is not greater than the maximum number of refresh commands allowed to be scheduled. Based on this implementation, limiting the number of refresh commands sent by the memory controller can make the memory refresh operation meet system requirements and avoid sending too many refresh commands to affect the normal operation of the system.

[0014] In some implementations, the method further includes: when the number of delayed refresh commands counted by the counter is not less than the maximum number of refresh commands allowed to be scheduled, the memory controller sends a refresh command to the memory at the set frequency. Based on this implementation, when there are too many delayed refresh commands, the refresh command is forced to be sent at the set frequency, which can avoid memory data loss due to excessive delay of the refresh command.

[0015] In some implementations, the method further includes: in the process of the memory controller sending a refresh command to the memory at a set frequency, based on the historical idle cycle distribution of the memory controller, predicting the duration of the next idle cycle of the memory controller; the idle cycle is a working cycle in which there is no read or write request to the memory; when it is determined that the duration of the next idle cycle of the memory controller is not greater than the set duration threshold, when the memory controller is in the next idle cycle, the memory controller sends an insert refresh command; wherein the insert refresh command is a refresh command sent between two adjacent refresh commands sent by the memory controller to the memory at a set frequency. Based on this implementation, the memory controller inserts the sending of a refresh command in the refresh command sending cycle while sending the refresh command at the set frequency, so that the delayed refresh command can be reissued while the refresh command is sent normally, thereby improving the efficiency of refreshing command sending. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0017] Figure 1 A schematic diagram of the structure of a storage system provided in an embodiment of the present application.

[0018] Figure 2 A flowchart of a memory refresh method provided in an embodiment of the present application.

[0019] Figure 3 A timing diagram of sending a refresh command provided in an embodiment of the present application.

[0020] Figure 4 Another timing diagram for sending a refresh command provided in an embodiment of the present application.

[0021] Figure 5 A schematic diagram of the structure of another storage system provided in an embodiment of the present application.

[0022] Figure 6 A flowchart of another memory refresh method provided in an embodiment of the present application.

[0023] Figure 7 Another timing diagram for sending a refresh command provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solution of the embodiment of the present application is applicable to a memory refresh application scenario, specifically, to an application scenario of refreshing a dynamic random access memory (DRAM).

[0025] Dynamic Random Access Memory (DRAM) is the most common system memory. In order to maintain data, DRAM uses capacitors for storage, but it can only keep data for a short time, so it must be refreshed every once in a while. If the memory is not refreshed, the stored information will be lost. In order to ensure that data is not lost, the memory controller must continuously send refresh commands to DRAM. During this process, the refresh command and the read / write access request to the memory may occupy the command bus at the same time. In this case, the refresh command needs to be scheduled. For example, when the refresh command conflicts with the read / write access request, the refresh command will be delayed for a period of time before being sent.

[0026] Figure 1 A schematic diagram of a DRAM-based storage system is shown, which includes a memory controller and a memory. The memory is DRAM. The memory controller includes a command queue and a refresh module. The command queue is used to store read and write access requests to the memory. When there are read and write access requests in the command queue, the memory controller takes the read and write access requests from the command queue and sends them to the memory. The refresh module is used to trigger a refresh operation and issue a refresh command to the memory.

[0027] The memory controller is connected to the memory via a command bus. Therefore, when the memory controller sends a read / write access request and a refresh command to the memory at the same time, the read / write access request and the refresh command will occupy the command bus at the same time.

[0028] Normally, when a read / write access request conflicts with a refresh command, in order to ensure system smoothness, the refresh command will be delayed, and the read / write access request will be sent to the memory via the command bus first. For delayed refresh commands, they will be scheduled to be sent at a time node that does not conflict with the access request, thereby reissuing the delayed refresh command. This can solve the problem of conflicts between read / write access requests and refresh commands, and ensure timely refresh of the memory, avoiding data loss due to long-term non-refresh.

[0029] As the size and speed of DRAM devices increase, the refresh operation on the DRAM becomes more frequent, which in turn causes the scheduling operation of the refresh command to become more frequent, and the resulting system power consumption also increases significantly.

[0030] In response to the above technical problems, the present application proposes a memory refresh method, which reissues the delayed refresh command when the memory controller is in an idle cycle and enters a low-power working mode, and in the process of reissuing the refresh command, also optimizes and controls the refresh command sending frequency, thereby reducing the system power consumption caused by sending the refresh command.

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] The embodiment of the present application first proposes a memory refresh method, which is applied to a memory controller. In the memory controller that executes the memory refresh method proposed in the embodiment of the present application, a counter is provided for counting the number of delayed refresh commands. The counter can be provided in the refresh module of the memory controller, or it can be provided outside the refresh module. The counter has a reference value. When a read-write access request conflicts with a refresh command and the control refresh command is delayed, the value of the counter is increased by 1, indicating that the number of delayed refresh commands increases by 1. It can be understood that the difference between the count value of the counter and the reference value is the number of delayed refresh commands recorded by the counter. When the refresh command is reissued, the count value of the counter is reduced by 1 accordingly, so that the count value of the counter is synchronized with the actual number of delayed refresh commands.

[0033] See also Figure 2 As shown, the memory refresh method proposed in the embodiment of the present application includes:

[0034] S101. When the memory controller switches to a low power consumption working mode, the memory controller sends a first number of refresh commands to the memory.

[0035] Specifically, when there are no read or write access requests in the command queue of the memory controller, and no read or write access requests are received after a certain period of waiting, the memory controller confirms that it has entered an idle cycle, that is, it has entered a working cycle in which there are no read or write access requests to the memory. In order to reduce system power consumption, the memory controller switches to a low-power working mode at this time.

[0036] From the moment when the memory controller switches to the low power consumption working mode, the memory controller starts to send refresh commands to the memory to reissue the delayed refresh commands.

[0037] In this embodiment, when the memory controller enters the low power working mode, the memory controller sends a first number of refresh commands to the memory, and the first number is not less than the number of delayed refresh commands counted by the counter. That is, when the memory controller enters the low power working mode, the memory controller reissues the delayed refresh commands to the memory.

[0038] In addition, when the idle cycle of the memory controller is long enough, the memory controller can not only reissue the delayed refresh command after entering the low-power working mode, but also send the subsequent refresh command to be sent in advance, that is, the refresh command to be sent after the memory controller ends the low-power working mode and enters the normal working mode is sent in advance. In this way, the number of refresh commands sent by the memory controller after the low-power working mode is ended and the normal working mode is entered can be reduced, thereby avoiding the situation where the read and write access requests sent by the memory controller in the normal working mode conflict with the refresh command. In addition, since the number of refresh commands sent in the normal working mode is reduced, the system power consumption caused by sending the refresh command can also be reduced.

[0039] In this case, the first number of refresh commands sent by the memory controller is greater than the number of delayed refresh commands counted by the counter.

[0040] In another embodiment, it is disclosed that the first number of refresh commands sent by the memory controller is not less than the number of delayed refresh commands recorded by the counter and is not greater than the maximum number of refresh commands allowed to be scheduled.

[0041] The maximum number of refresh commands allowed to be scheduled refers to the maximum number of refresh commands allowed to be delayed or sent in advance. The maximum number can be flexibly set according to the performance of the storage system or according to the protocol requirements. Usually, the maximum number is 8 or less. Figure 1 In the storage system shown, a maximum of 8 refresh commands can be sent late or 8 refresh commands can be sent in advance.

[0042] Based on the above maximum number restriction, the first number of refresh commands sent by the memory controller may be greater than the number of delayed refresh commands, but cannot exceed the above maximum number of refresh commands allowed to be scheduled.

[0043] For example, when the number of delayed refresh commands is greater than or equal to the maximum number of refresh commands allowed to be scheduled, the first number of refresh commands sent by the memory controller is equal to the maximum number of refresh commands allowed to be scheduled. After the memory controller sends the maximum number of refresh commands, even if there are delayed refresh commands that have not been reissued, the memory controller stops sending the first number of refresh commands to the memory and switches to sending refresh commands at a normal frequency.

[0044] When the number of delayed refresh commands is less than the maximum number of refresh commands allowed to be scheduled, the memory controller sends a first number of refresh commands to the memory, and the first number may be equal to the number of delayed refresh commands, or may be greater than the number of delayed refresh commands, but the maximum number may not exceed the maximum number of refresh commands allowed to be scheduled. When the first number is greater than the number of delayed refresh commands, the memory controller sends some refresh commands in advance within the maximum number of refresh commands allowed to be scheduled on the basis of reissuing the delayed refresh commands, so that the number of refresh commands sent can be reduced in the subsequent normal sending of refresh commands, thereby effectively reducing the probability of conflicts between read and write access requests and refresh commands, and because these refresh commands have been sent in advance, they will not delay the refresh operation of the memory.

[0045] In some embodiments, the memory controller sends a first number of refresh commands to the memory. Specifically, when the memory controller switches to a low power operating mode, the memory controller sends a first number of refresh commands to the memory at a first frequency, wherein the first frequency is greater than the set frequency.

[0046] Specifically, Figure 3 As shown, when the memory controller enters the idle cycle and switches to the low power operation mode, it first sends a refresh command at a first frequency, that is, it sends a refresh command at a shorter time interval (tREFI / 2). After the memory controller sends a first number of refresh commands at the first frequency, it sends a refresh command at a set frequency, that is, it sends a refresh command at a longer time interval (tREFI).

[0047] In this embodiment, after entering the low power working mode, the memory controller first completes the sending of a first number of refresh commands at a higher frequency, that is, completes the reissuance of delayed refresh commands. After sending the first number of refresh commands, the memory controller switches the sending frequency of the refresh commands to the set frequency, that is, reduces the sending frequency of the refresh commands. At this time, it can avoid the increase in power consumption in the low power working mode due to long-term high-frequency sending of refresh commands.

[0048] Among them, if the memory controller exits the low power operation mode before the memory controller completes sending the first number of refresh commands at the first frequency, the memory controller immediately adjusts the refresh command sending frequency from the first frequency to the set frequency to avoid affecting the normal operation of the memory controller due to the high frequency of sending refresh commands.

[0049] In other embodiments, the memory controller sends the first number of refresh commands to the memory, and the memory controller may continuously send the first number of refresh commands to the memory when the memory controller switches to a low power consumption operation mode.

[0050] Specifically, Figure 4 As shown, when the memory controller enters the idle cycle and switches to the low power mode, it first continuously sends a first number of refresh commands to the memory. That is, after the memory controller sends a refresh command, it immediately sends the next refresh command, and there may be no waiting time in between. After sending the first number of refresh commands in the above manner, the memory controller switches to sending refresh commands at a set frequency.

[0051] In this embodiment, after entering the low power working mode, the memory controller first continuously sends a first number of refresh commands to the memory, that is, it centrally executes the reissue of delayed refresh commands, and after sending the first number of refresh commands, the memory controller switches to sending refresh commands at a set frequency, which can avoid the increase of power consumption in the low power working mode due to the centralized and continuous sending of refresh commands.

[0052] S102: When the memory controller has sent the first number of refresh commands, the memory controller sends refresh commands to the memory at a set frequency.

[0053] Specifically, sending the refresh command to the memory at a set frequency refers to sending the refresh command to the memory at a preset refresh period tREFI, that is, sending a refresh command to the memory every tREFI.

[0054] In the embodiment of the present application, the frequency at which the memory controller sends the first number of refresh commands is greater than the above-mentioned set frequency. That is, the memory controller executes step S101 to send the first number of refresh commands to the memory, which is to quickly and centrally send the first number of refresh commands to the memory at a faster frequency. At this time, the time interval between adjacent refresh commands in the first number of refresh commands is less than the refresh period tREFI.

[0055] When the memory controller has sent the first number of refresh commands, the memory controller switches to a working mode of sending refresh commands at a set frequency, and sends a refresh command to the memory every tREFI.

[0056] After completing sending of the first number of refresh commands at a higher frequency, the memory controller is adjusted to periodically send refresh commands to the memory at a lower frequency, thereby avoiding increased power consumption caused by sending refresh commands at a higher frequency for a long time.

[0057] From the above introduction, it can be seen that the memory refresh method proposed in the embodiment of the present application reissues the delayed refresh command to the memory at a higher frequency when the memory controller switches to the low-power working mode, and after the refresh command reissue is completed, the refresh command sending frequency is adjusted to a lower frequency. The above scheme reissues the refresh command when the memory controller is in an idle state and enters the low-power working mode, which can reduce the system power consumption of the reissued refresh command. At the same time, the above scheme quickly completes the refresh command reissue at a higher frequency when the memory controller enters the low-power working mode, and then reduces the refresh command sending frequency to the normal frequency, which can avoid the increase of system power consumption due to maintaining a high refresh frequency for a long time in the low-power working mode.

[0058] In some embodiments, see Figure 5 As shown, a prediction module, an arbitration module and a register are also provided in the memory controller.

[0059] The prediction module is used to predict the idle cycle of the memory controller based on the historical idle cycle distribution of the memory controller.

[0060] The idle cycle mentioned above refers to a working cycle in which there is no read or write access request to the memory, that is, a working cycle in which the memory controller does not perform any read or write access operation on the memory.

[0061] In the embodiment of the present application, based on a preset duration threshold, the space cycle of the memory controller is divided into a long idle cycle and a short idle cycle. When the duration of the idle cycle of the memory controller is not less than the duration threshold, the idle cycle is determined to be a long idle cycle, and when the duration of the idle cycle of the memory controller is less than the duration threshold, the idle cycle is determined to be a short idle cycle.

[0062] Alternatively, based on a preset first duration threshold and a second duration threshold (the first duration threshold is less than the second duration threshold), the idle cycle of the memory controller is divided into a long idle cycle, a medium idle cycle and a short idle cycle. When the duration of the idle cycle of the memory controller is less than the first duration threshold, the idle cycle is determined to be a short idle cycle; when the duration of the idle cycle of the memory controller is not less than the first duration threshold and less than the second duration threshold, the idle cycle is determined to be a medium idle cycle; when the duration of the idle cycle of the memory controller is not less than the second duration threshold, the idle cycle is determined to be a long idle cycle.

[0063] The prediction module can record the idle cycles in the historical operation process of the memory controller, such as recording the time and duration of each historical idle cycle, and predict the time and duration of the next idle cycle based on the time and duration of the historical idle cycle.

[0064] Exemplarily, the above prediction module can be implemented by a neural network model, which extracts the regularity of the occurrence of idle cycles by learning the time and duration of historical idle cycles, and can then predict the time and duration of the next idle cycle. When training the neural network model, the time and duration of historical idle cycles are used as training samples, and the time and duration of the next idle cycle of the historical idle cycle are used as training labels, and the neural network model is trained to predict idle cycles.

[0065] The arbitration module is used to make decisions on the working mode and refresh mode of the memory controller based on the time and duration of the idle cycle predicted by the prediction module, the number of read and write access requests in the command queue, and the number of delayed refresh commands counted by the refresh module.

[0066] The above-mentioned register includes a refresh mode register, and the arbitration module can adjust the refresh mode by adjusting the value of the refresh mode register in the register. For example, the arbitration module changes the refresh frequency by adjusting the value of the refresh mode register in the register, so that the refresh module sends a refresh command to the memory according to the refresh frequency in the refresh mode register.

[0067] In this embodiment, see Figure 6 As shown, the above memory refresh method also includes:

[0068] S1001. Predicting the duration of the next idle cycle of the memory controller based on the historical idle cycle distribution of the memory controller.

[0069] Specifically, the prediction module predicts the time and duration of the next idle cycle of the memory controller based on the historical idle cycle distribution of the memory controller, such as the time and duration of the historical idle cycles.

[0070] S1002: When it is determined that the duration of the next idle cycle of the memory controller is greater than a set duration threshold, when the memory controller enters the next idle cycle, switch the working mode of the memory controller to a low power consumption working mode.

[0071] Specifically, when the prediction module predicts that the next idle cycle of the memory controller is a long idle cycle, that is, it is predicted that the duration of the next idle cycle is greater than the set duration threshold, when the memory controller enters the next idle cycle, the arbitration module decides that the memory controller will switch the working mode to the low power working mode.

[0072] In some embodiments, it is disclosed that due to errors in the prediction of the prediction module, such as the prediction of the start time and duration of the next idle cycle may be inaccurate, errors may occur if the memory controller is triggered to enter the next idle cycle in full accordance with the start time of the next idle cycle predicted by the prediction module.

[0073] In order to prevent the memory controller from entering an idle cycle or switching to a low-power working mode at an incorrect time node, in this embodiment, the prediction result of the next idle cycle obtained by the prediction module is used as auxiliary information to enable the memory controller to decide whether to switch to the low-power working mode.

[0074] When the duration of the memory controller entering the idle state exceeds the set first idle duration threshold, it is considered that the memory controller has entered the next idle cycle. At this time, combined with the prediction result of the prediction module, it is further determined whether to switch to the low-power working mode. If the prediction module predicts that the duration of the next idle cycle of the memory controller is greater than the set duration threshold, the memory controller switches to the low-power working mode.

[0075] In other embodiments, when the duration of the memory controller entering the idle state exceeds the set second idle duration threshold, it can be determined that it has entered a long idle cycle, and the memory controller switches to a low-power mode of operation. The second idle duration threshold is greater than the first idle duration threshold. In other words, the memory controller may not rely on the prediction result of the prediction module to decide whether to switch to a low-power mode of operation. In this case, as long as the duration of the memory controller entering the idle state exceeds the second idle duration threshold and is still in the idle state, the memory controller can determine that it has entered a long idle cycle, and the operating mode can be switched to a low-power mode of operation.

[0076] The next idle cycle is predicted based on the historical idle cycle distribution of the memory controller, and the working mode of the memory controller is switched based on the prediction result of the next idle cycle. This can identify the idle cycle of the memory controller more timely and accurately, and when it is confirmed that the memory controller enters a long idle cycle, the memory controller is switched to a low-power working mode in time, thereby reducing energy consumption.

[0077] In another embodiment, it is disclosed that when the number of delayed refresh commands recorded by the counter is not less than the maximum number of refresh commands allowed to be scheduled, the memory controller sends refresh commands to the memory at a set frequency.

[0078] For example, assuming that the maximum number of refresh commands allowed to be scheduled is 8, when the number of delayed refresh commands recorded by the counter is greater than or equal to 8, it means that the number of delayed refresh commands has reached the limit of the number of refresh commands that can be scheduled. At this time, if a new refresh command is delayed, it cannot be reissued, which will cause the refresh of the memory to be delayed and may cause data loss. Therefore, in this case, the memory controller must send refresh commands to the memory at a set frequency. In this process, when a refresh command conflicts with a memory read / write access request, the memory controller gives priority to sending the refresh command and blocks the read / write access request. Until the number of delayed refresh commands recorded by the counter is less than the maximum number of refresh commands allowed to be scheduled, when the refresh command sent by the memory controller conflicts with the read / write access request, the refresh command can be delayed and the read / write access request can be sent first.

[0079] Exemplarily, when the number of delayed refresh commands recorded by the counter is not less than the maximum number of refresh commands allowed to be scheduled, the memory controller sends a refresh command to the memory at a set frequency. During this process, the memory controller can also perform a reissue operation on the delayed refresh command, such as during the cycle of sending the refresh command, or when the memory controller has no read-write access request to send, the memory controller can perform a reissue operation on the refresh command. Each time the memory controller reissues a refresh command, the counter decrements its count result by 1. Based on the above operation, when the number of delayed refresh commands recorded by the counter is less than the maximum number of refresh commands allowed to be scheduled, if the refresh command sent by the memory controller conflicts with the read-write access request, the refresh command can be delayed and the read-write access request can be sent first.

[0080] In another embodiment, it is also disclosed that, in the process of the memory controller sending a refresh command to the memory at a set frequency, the duration of the next idle cycle of the memory controller is predicted based on the historical idle cycle distribution of the memory controller.

[0081] When it is determined that the duration of the next idle cycle of the memory controller is not greater than a set duration threshold, the memory controller sends an insertion refresh command when the memory controller is in the next idle cycle.

[0082] The inserted refresh command is a refresh command sent between two adjacent refresh commands sent by the memory controller to the memory at a set frequency.

[0083] Specifically, under normal circumstances, the memory controller sends a refresh command to the memory at a set frequency, such as sending a refresh command to the memory at a period of tREFI, so as to meet the requirement of regularly refreshing the memory. In this process, the prediction module in the memory controller predicts the duration of the next idle cycle of the memory controller based on the historical idle cycle distribution of the memory controller.

[0084] If the memory controller predicts that the duration of its next idle cycle is not greater than the set duration threshold, it means that the next idle cycle is a short idle cycle. At this time, when the memory controller enters the next idle cycle, the memory controller sends an insert refresh command, that is, the arbitration module of the memory controller decides that the refresh module sends an insert refresh command to the memory.

[0085] like Figure 7 As shown, in the process of the memory controller periodically sending refresh commands to the memory at a set frequency, an inserted refresh command is sent within the cycle of sending the refresh command, that is, a refresh command is sent between two adjacent refresh commands sent, thereby realizing the re-issuance of the delayed refresh command.

[0086] In some embodiments, the number of inserted refresh commands sent by the memory controller does not exceed the maximum number of refresh commands allowed to be scheduled. Also, the number of refresh commands sent by the memory controller in one cycle does not exceed the maximum number of refresh commands allowed to be sent in one cycle.

[0087] In other embodiments, during the process of sending the insert refresh command, the memory controller detects in real time whether it needs to send a read / write access request to the memory, that is, detects whether the command queue for storing the read / write access request is empty. If the memory controller does not need to send a read / write access request, such as the command queue is empty, the memory controller can send the insert refresh command, otherwise the memory controller does not send the insert refresh command, so as to avoid increasing the probability of a conflict between the refresh command and the read / write access request due to sending the insert refresh command.

[0088] For example, before sending an insert refresh command each time, the memory controller first checks whether the command queue is empty. When the command queue is confirmed to be empty, the memory controller sends an insert refresh command. When the command queue is confirmed to be not empty, the memory controller cancels sending the insert refresh command, and can continue to send refresh commands at the set frequency.

[0089] In other embodiments, during the process of the memory controller sending the insert refresh command, the working mode of the memory controller is also monitored. When the memory controller enters the low power working mode, it stops sending the insert refresh command and keeps sending the refresh command at the set frequency, thereby avoiding increasing the energy consumption of the memory controller in the low power working mode due to sending the insert refresh command.

[0090] The above embodiments introduce refresh command sending strategies under different circumstances. In practical applications, the refresh command sending strategies introduced in the above embodiments can be applied in combination. For example, when the number of delayed refresh commands counted by the counter is not less than the maximum number of refresh commands allowed to be scheduled, the memory controller sends refresh commands to the memory at a set frequency. In this process, the memory controller predicts the duration of the next idle cycle of the memory controller based on the historical idle cycle distribution. When it is determined that the duration of the next idle cycle is not greater than the set duration threshold, when the memory controller is in the next idle cycle, the memory controller continues to send refresh commands at the set frequency while also sending an insert refresh command.

[0091] Alternatively, when the number of delayed refresh commands counted by the counter is not less than the maximum number of refresh commands allowed to be scheduled, the memory controller sends refresh commands to the memory at a set frequency. In this process, the memory controller predicts the duration of the next idle cycle of the memory controller based on the historical idle cycle distribution. When it is determined that the duration of the next idle cycle of the memory controller is greater than the set duration threshold, when the memory controller enters the next idle cycle, the working mode of the memory controller is switched to a low-power working mode. After switching to the low-power working mode, the memory controller sends a first number of refresh commands to the memory, and the first number is not less than the number of delayed refresh commands counted by the counter; after the memory controller sends the first number of refresh commands, the memory controller resumes sending refresh commands to the memory at the set frequency.

[0092] The specific execution process of the refresh command sending solution obtained by combining different refresh command sending strategies can be found in the introduction of the above embodiment, which will not be repeated here.

[0093] Another embodiment of the present application further provides a memory controller, which includes a counter for counting delayed refresh commands. The memory controller includes a refresh module for sending a first number of refresh commands to the memory when the memory controller switches to a low-power operation mode, wherein the first number is not less than the number of delayed refresh commands counted by the counter; after sending the first number of refresh commands, sending refresh commands to the memory at a set frequency;

[0094] The refresh module sends the first number of refresh commands at a frequency greater than the set frequency.

[0095] In some implementations, the memory controller further includes:

[0096] A prediction module, configured to predict the duration of a next idle cycle of the memory controller based on the historical idle cycle distribution of the memory controller; the idle cycle is a working cycle in which there is no read or write access request to the memory;

[0097] A decision module is used to switch the working mode of the memory controller to a low power consumption working mode when the memory controller enters the next idle cycle if it is determined that the duration of the next idle cycle of the memory controller is greater than a set duration threshold.

[0098] In some implementations, the refresh module sends a first number of refresh commands to the memory when the memory controller switches to the low power consumption working mode, including:

[0099] When the memory controller switches to a low power consumption working mode, a first number of refresh commands are sent to the memory at a first frequency, where the first frequency is greater than the set frequency.

[0100] In some implementations, the refresh module sends a first number of refresh commands to the memory when the memory controller switches to the low power consumption working mode, including:

[0101] When the memory controller switches to a low power consumption working mode, a first number of refresh commands are continuously sent to the memory.

[0102] In some implementations, the first number is no less than the number of refresh commands that are delayed and no greater than a maximum number of refresh commands allowed to be scheduled.

[0103] In some implementations, the refresh module is further configured to:

[0104] When the number of delayed refresh commands counted by the counter is not less than the maximum number of refresh commands allowed to be scheduled, refresh commands are sent to the memory at the set frequency.

[0105] In some implementations, the memory controller further includes:

[0106] A prediction module, configured to predict the duration of the next idle cycle of the memory controller based on the historical idle cycle distribution of the memory controller during the process of the memory controller sending a refresh command to the memory at a set frequency; the idle cycle is a working cycle in which there is no read or write request to the memory;

[0107] The refresh module is further configured to send an insert refresh command when the memory controller is in the next idle cycle if it is determined that the duration of the next idle cycle of the memory controller is not greater than a set duration threshold;

[0108] The inserted refresh command is a refresh command sent between two adjacent refresh commands sent to the memory at a set frequency.

[0109] The memory controller provided in this embodiment belongs to the same application concept as the memory refresh method provided in the above embodiments of this application, and can execute the memory refresh method provided in any of the above embodiments of this application, and has the corresponding functional modules and beneficial effects of the execution method. For the technical details not fully described in this embodiment, please refer to the specific processing content of the memory refresh method provided in the above embodiments of this application, and will not be repeated here.

[0110] Another embodiment of the present application further provides a storage system, which includes a memory controller and a memory connected to the memory controller, and the memory controller is configured to execute the memory refresh method described in any of the above embodiments.

[0111] In addition, another embodiment of the present application further provides a computing device, which includes the above-mentioned storage system.

[0112] Since the above-mentioned storage system and computing device can implement the memory refresh method described in any of the above-mentioned embodiments, the above-mentioned storage system and computing device belong to the same application concept as the memory refresh method provided in the above-mentioned embodiments of the present application, and can execute the memory refresh method provided in any of the above-mentioned embodiments of the present application, and have the corresponding functional modules and beneficial effects of the execution method. For the technical details not described in detail in this embodiment, please refer to the specific processing content of the memory refresh method provided in the above-mentioned embodiments of the present application, and will not be repeated here.

[0113] For the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0114] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0115] The steps in the methods of each embodiment of the present application can be adjusted in order, combined and deleted according to actual needs, and the technical features recorded in each embodiment can be replaced or combined.

[0116] The modules and sub-modules in the devices and terminals of the various embodiments of the present application can be combined, divided and deleted according to actual needs.

[0117] In the several embodiments provided in the present application, it should be understood that the disclosed terminals, devices and methods can be implemented in other ways. For example, the terminal embodiments described above are only schematic, for example, the division of modules or submodules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple submodules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0118] The modules or submodules described as separate components may or may not be physically separated, and the components of the modules or submodules may or may not be physical modules or submodules, that is, they may be located in one place, or they may be distributed on multiple network modules or submodules. Some or all of the modules or submodules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] In addition, each functional module or submodule in each embodiment of the present application may be integrated into one processing module, or each module or submodule may exist physically separately, or two or more modules or submodules may be integrated into one module. The above-mentioned integrated modules or submodules may be implemented in the form of hardware or in the form of software functional modules or submodules.

[0120] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0121] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly by hardware, software units executed by a processor, or a combination of the two. The software units may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0122] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0123] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory refresh method, characterized in that: Applied to a memory controller, the memory controller includes a counter for counting delayed refresh commands; the method includes: When the memory controller switches to the low power consumption working mode, the memory controller sends a first number of refresh commands to the memory, where the first number is not less than the number of delayed refresh commands counted by the counter; When the memory controller has sent the first number of refresh commands, the memory controller sends refresh commands to the memory at a set frequency; The memory controller sends the first number of refresh commands at a frequency greater than the set frequency.

2. The method according to claim 1, characterized in that The method further comprises: Based on the historical idle cycle distribution of the memory controller, the duration of the next idle cycle of the memory controller is predicted; the idle cycle is a working cycle in which there is no read or write access request to the memory; When it is determined that the duration of the next idle cycle of the memory controller is greater than a set duration threshold, the working mode of the memory controller is switched to a low power consumption working mode when the memory controller enters the next idle cycle.

3. The method according to claim 1, characterized in that When the memory controller switches to a low power consumption working mode, the memory controller sends a first number of refresh commands to the memory, including: When the memory controller switches to the low power consumption working mode, the memory controller sends a first number of refresh commands to the memory at a first frequency, and the first frequency is greater than the set frequency.

4. The method according to claim 1, characterized in that When the memory controller switches to a low power consumption working mode, the memory controller sends a first number of refresh commands to the memory, including: When the memory controller switches to a low power consumption working mode, the memory controller continuously sends a first number of refresh commands to the memory.

5. The method according to any one of claims 1 to 4, characterized in that: The first number is not less than the number of refresh commands that are delayed and not greater than the maximum number of refresh commands that are allowed to be scheduled.

6. The method according to any one of claims 1 to 4, characterized in that The method further comprises: When the number of delayed refresh commands counted by the counter is not less than the maximum number of refresh commands allowed to be scheduled, the memory controller sends refresh commands to the memory at the set frequency.

7. The method according to any one of claims 1 to 4, characterized in that The method further comprises: In the process of the memory controller sending a refresh command to the memory at a set frequency, based on the historical idle cycle distribution of the memory controller, the duration of the next idle cycle of the memory controller is predicted; the idle cycle is a working cycle in which there is no read or write request to the memory; In a case where it is determined that the duration of the next idle cycle of the memory controller is not greater than a set duration threshold, the memory controller sends an insert refresh command when the memory controller is in the next idle cycle; The inserted refresh command is a refresh command sent between two adjacent refresh commands sent by the memory controller to the memory at a set frequency.

8. A memory controller, characterized in that: The memory controller includes a counter for counting delayed refresh commands; The memory controller comprises: A refresh module, configured to send a first number of refresh commands to the memory when the memory controller switches to a low power consumption working mode, wherein the first number is not less than the number of delayed refresh commands counted by the counter; and send refresh commands to the memory at a set frequency after sending the first number of refresh commands; The refresh module sends the first number of refresh commands at a frequency greater than the set frequency.

9. A storage system, characterized in that: It comprises a memory controller and a memory connected to the memory controller, wherein the memory controller is configured to implement the memory refresh method according to any one of claims 1 to 7.

10. A computing device, characterized in that Comprising the storage system as claimed in claim 9.

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