Chip packaging method, chip packaging structure and electronic equipment
By first making the rewiring layer and flipping the chip in the chip packaging method, the problem of chip offset during the rewiring layer is solved, the chip accuracy and integration are improved, and chip scrapping and production costs are reduced.
Patent Information
- Application Number
- CN202411218523.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2024-12-24
AI Technical Summary
In the prior art, chips are offset due to mismatch in thermal expansion coefficients or mechanical impact during the production of rewiring layer, which affects the accuracy of the patch and the product yield is not high.
In the chip packaging method, firstly, the first heavy wiring layer is made, and the first chip and the second chip are flipped on the corresponding connectors respectively to prevent offsets in the subsequent process, and at the same time, the signal transmission path is shortened, so that the chip can be made The packaging structure is more compact and the integration is improved.
By making the rewiring layer and flip chip in advance, the chip accuracy is improved, chip scrapping caused by poor rewiring layer is reduced, production costs are reduced, and the reliability and integration of chip packaging are enhanced.
Smart Images
Figure CN119181649A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a chip packaging method, a chip packaging structure and an electronic device. Background Art
[0002] In semiconductor technology, packaging is an important part of the production and processing of semiconductor integrated circuit chips. It can not only place, fix, seal and protect the chips, but also enhance the electrical and thermal performance. At the same time, it can also realize the transmission of data and signals between the internal and external circuits of the chip.
[0003] In the prior art, the chip is usually mounted on the substrate through temporary bonding glue, and then the redistribution layer is made. During the process of making the redistribution layer, the chip temporarily mounted on the substrate may shift due to thermal expansion coefficient mismatch or mechanical impact, thereby affecting the mounting accuracy and the product yield is low. Summary of the invention
[0004] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a chip packaging method, a chip packaging structure and an electronic device.
[0005] In a first aspect, an embodiment of the present application provides a chip packaging method, the preparation method comprising:
[0006] Providing a first carrier board, and manufacturing a first redistribution layer on one side of the first carrier board, wherein the first redistribution layer comprises a first side and a second side opposite to each other, the second side of the redistribution layer contacts the first carrier board, and the first redistribution layer further comprises a first connecting portion located on the first side and a second connecting portion located on the second side;
[0007] Manufacturing a first chip layer on a first side of the first redistribution layer, wherein the first chip layer includes at least one first chip, and pins of the first chip are electrically connected to the first redistribution layer through the first connection portion;
[0008] The first carrier board is removed, and a second chip layer is manufactured on the second side of the first redistribution layer. The second chip layer includes at least one second chip, and the pins of the second chip are electrically connected to the first redistribution layer through the second connection portion.
[0009] In a possible implementation manner, the step of manufacturing the first chip layer on the first side of the first redistribution layer includes:
[0010] Placing at least one first chip on a side of the first redistribution layer away from the first carrier, and welding the first chip to the first connection portion so that an electrode of the first chip is electrically connected to the first redistribution layer;
[0011] A first plastic encapsulation layer is formed on the peripheral side of the first chip, and through-hole leads are made on the first plastic encapsulation layer to penetrate the first plastic encapsulation layer, so as to obtain the first chip layer, wherein the through-hole leads are electrically connected to the first redistribution layer, and the orthographic projection of the first plastic encapsulation layer on the first redistribution layer does not overlap with the orthographic projection of the first chip on the first redistribution layer.
[0012] In a possible implementation, the step of forming a first plastic encapsulation layer on the peripheral side of the first chip and making through-hole leads penetrating the first plastic encapsulation layer on the first plastic encapsulation layer to obtain the first chip layer includes:
[0013] Performing a plastic encapsulation process on the first redistribution layer after the first chip is welded, so as to obtain a plastic encapsulation layer that embeds the first chip;
[0014] Grinding the plastic encapsulation layer that embeds the first chip until the first chip is exposed to obtain a first plastic encapsulation layer, wherein the orthographic projection of the first plastic encapsulation layer on the first redistribution layer does not overlap with the orthographic projection of the first chip on the first redistribution layer to obtain the first plastic encapsulation layer;
[0015] Performing patterning on the first plastic encapsulation layer to form a wiring through hole penetrating the first plastic encapsulation layer;
[0016] Metal deposition is performed on the first redistribution layer after the routing through hole is formed, and through-hole leads are formed in the routing through hole to obtain the first chip layer, wherein the through-hole leads are electrically connected to the first redistribution layer.
[0017] In a possible implementation, the step of removing the first carrier board and manufacturing the second chip layer on the second side of the first redistribution layer includes:
[0018] Removing the first carrier board, and transferring the first redistribution layer on which the first chip layer is manufactured to a second carrier board, wherein a side of the first chip layer away from the first redistribution layer contacts the second carrier board;
[0019] placing at least one second chip on the second side of the first redistribution layer, and soldering the second chip to the second connection portion;
[0020] A second plastic packaging layer is formed on the peripheral side of the second chip to obtain the second chip layer.
[0021] In a possible implementation, after the step of manufacturing a second plastic encapsulation layer on the peripheral side of the second chip to obtain the second chip layer, the method further includes:
[0022] The second carrier is removed, and the first redistribution layer on which the second chip layer is made is transferred to a third carrier, wherein a side of the second chip layer away from the redistribution is in contact with the third carrier;
[0023] A second redistribution layer is fabricated on a side of the first chip layer away from the third carrier board, wherein the second redistribution layer is electrically connected to the through-hole leads;
[0024] A ball placement process is performed on a side of the second redistribution layer away from the third carrier board to obtain a conductive ball electrically connected to the second redistribution layer. The conductive ball is electrically connected to the first redistribution layer through the second redistribution layer and the through-hole lead.
[0025] In a second aspect, an embodiment of the present application further provides a chip packaging structure, wherein the chip packaging structure is manufactured by the chip packaging method described in any one of the first aspects above, and the chip packaging structure comprises:
[0026] A first redistribution layer, wherein the first redistribution layer comprises a first side and a second side opposite to each other, and the first redistribution layer comprises a first connection portion located on the first side and a second connection portion located on the second side;
[0027] A first chip layer is located on a first side of the first redistribution layer, the first chip layer includes at least one first chip, a pin side of the first chip faces the first redistribution layer, and the pin of the first chip is connected to the first connection portion;
[0028] The second chip layer is located at the second side of the first redistribution layer, the pin side of the second chip in the second chip layer faces the first redistribution layer, and the pin of the second chip is connected to the second connection portion.
[0029] In a possible implementation, the first chip layer further includes a first plastic encapsulation layer filled around the first chip, and an orthographic projection of the first plastic encapsulation layer on the first redistribution layer does not overlap with an orthographic projection of the first chip on the first redistribution layer;
[0030] The second chip layer further includes a second plastic encapsulation layer filled around the second chip, and an orthographic projection of the second plastic encapsulation layer on the first redistribution layer does not overlap with an orthographic projection of the second chip on the first redistribution layer;
[0031] Preferably, the first chip comprises a bridge chip;
[0032] Preferably, the second chip includes a system-level chip and a high-bandwidth memory chip.
[0033] In a possible implementation, a wiring through hole penetrating the first plastic packaging layer is provided on the first plastic packaging layer, a through hole lead is provided in the wiring through hole, and the through hole lead is connected to the first redistribution layer.
[0034] In a possible implementation, the chip packaging structure further includes a second redistribution layer and conductive balls;
[0035] The second redistribution layer is located on a side of the first chip layer away from the first redistribution layer, the conductive ball is located on a side of the second redistribution layer away from the first chip layer, and the conductive ball is electrically connected to the first redistribution layer through the second redistribution layer and the through-hole lead.
[0036] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a chip packaging structure manufactured according to the chip packaging method described in any one of the first aspects.
[0037] Based on any of the above aspects, the chip packaging method, chip packaging structure and electronic device provided by the embodiment of the present application give priority to making the first redistribution layer, and then flip-mount the first chip and the second chip on the first connector and the second connector respectively, so as to prevent the first chip and the second chip from being offset in the subsequent process, improve the patch accuracy, and flip-mount the first chip and the second chip can not only shorten the signal transmission path, but also make the chip packaging structure more compact and improve the chip integration. In addition, making the first redistribution layer in advance can also reduce the scrapping of chips due to poor redistribution layer and reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0039] Figure 1 A schematic diagram of a process flow of a chip packaging method provided in this application;
[0040] Figure 2 for Figure 1 The corresponding process diagram;
[0041] Figure 3 for Figure 1 A schematic flow chart of a sub-step of step S12;
[0042] Figure 4 for Figure 3 The corresponding process diagram;
[0043] Figure 5 for Figure 3 A schematic diagram of a sub-step flow chart of step S122;
[0044] Figure 6 for Figure 5 The corresponding process diagram;
[0045] Figure 7 for Figure 1 A schematic flow chart of a sub-step of step S13;
[0046] Figure 8 for Figure 7 The corresponding process diagram;
[0047] Fig. 9 A schematic diagram of the steps that may be included in the chip packaging method provided in this application;
[0048] Fig.10 for Fig. 9 The corresponding process diagram;
[0049] Fig.11 A schematic diagram of a chip packaging structure provided in this application Figure 1 ;
[0050] Fig.12 A schematic diagram of a chip packaging structure provided in this application Figure 2 ;
[0051] Fig.13 A schematic diagram of a chip packaging structure provided in this application Figure 3 . DETAILED DESCRIPTION
[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0053] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0054] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0055] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0056] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0057] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0058] To solve the problems in the prior art, please refer to Figure 1 , the present application embodiment provides a chip packaging method. Please refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram of a chip packaging method is shown in FIG. Figure 2 For the corresponding process diagram, the following is combined Figure 1 and Figure 2 , and each step of the chip packaging method is described in detail.
[0059] Step S11: providing a first carrier board, and manufacturing a first redistribution layer on one side of the first carrier board.
[0060] In this step, the first bonding layer 211 may be firstly fabricated on the first substrate 210, and the first redistribution layer 110 may be fabricated on a side of the first bonding layer 21 away from the first substrate 210. The first redistribution layer 110 may include a first side 110A and a second side 110B opposite to each other, the second side 110B may be in contact with the first substrate 210, and the first redistribution layer 110 may also include a first connection portion 112 located at the first side 110A and a second connection portion 113 located at the second side 110B. The first redistribution layer 110 may include a first conductive trace 111 for transmitting an electrical signal, and the first conductive trace 111 may be electrically connected to other electronic devices through the first connection portion 112 and / or the second connection portion 113.
[0061] Step S12: fabricating a first chip layer on a first side of the first redistribution layer.
[0062] Specifically, the first chip layer 120 includes at least one first chip 121, the pin side of the first chip 121 faces the first redistribution layer 110, and the pin of the first chip 121 is electrically connected to the first redistribution layer 110 through the first connecting part 112. Specifically, the electrical connection between the first chip 121 and the first redistribution layer 110 can be achieved by soldering.
[0063] Step S13: removing the first carrier board, and manufacturing a second chip layer on the second side of the first redistribution layer.
[0064] Specifically, the second chip layer 130 includes at least one second chip 131 , the pin side of the second chip 131 faces the first redistribution layer 110 , and the pins of the second chip 131 are electrically connected to the first redistribution layer 110 through the second connection portion 113 .
[0065] In this embodiment, the first rewiring layer 110 is first made, and then the first chip 121 and the second chip 131 are flipped on the first connection part 112 and the second connection part 113, respectively. This can prevent the first chip 121 and the second chip 131 from shifting in the subsequent process, improve the patch accuracy, and flip the first chip 121 and the second chip 131 can not only shorten the signal transmission path, but also make the chip packaging structure more compact, and improve the chip integration. In addition, making the first rewiring layer 110 in advance can also reduce chip scrapping due to poor rewiring layer and reduce production costs.
[0066] For further information, please refer to Figure 3 and Figure 4 , step S12 can be implemented by the following method.
[0067] Step S121: placing at least one first chip on a side of the first redistribution layer away from the first carrier, and welding the first chip to the first connection portion to electrically connect the electrode of the first chip to the first redistribution layer.
[0068] In this step, after the first chip 121 and the first connection part 112 are welded to form an electrical connection, bottom filling can be performed at the position where the first chip 121 contacts the first redistribution layer 110, and the connection between the first chip 121 and the first redistribution layer 110 is further enhanced by the bottom filling process, thereby improving the reliability of the package. Among them, the first connection part 112 includes a micro pad, and the first chip 121 includes a bridge chip, which can be used to realize the interconnection between different chips.
[0069] Step S122: forming a first plastic encapsulation layer on the peripheral side of the first chip, and making through-hole leads penetrating the first plastic encapsulation layer on the first plastic encapsulation layer to obtain a first chip layer.
[0070] In this step, the through-hole leads 123 are electrically connected to the first redistribution layer 110 , and the orthographic projection of the first plastic encapsulation layer 122 on the first redistribution layer 110 does not overlap with the orthographic projection of the first chip 121 on the first redistribution layer 110 .
[0071] In this embodiment, the first redistribution layer 110 is first manufactured, and then the first chip 121 is flipped onto the first connection portion 112, so that the first chip 121 can be prevented from being offset due to the influence of thermal expansion coefficient mismatch, mechanical impact, etc. during the manufacturing process of the first plastic packaging layer 122, thereby improving the chip mounting accuracy. At the same time, flipping the first chip 121 can also shorten the signal transmission path, making the chip packaging structure more compact, and improving the integration of the chip packaging structure.
[0072] For further information, please refer to Figure 5 and Figure 6 , step S122 can be implemented by the following method.
[0073] Step S1221: performing plastic encapsulation processing on the first redistribution layer after the first chip is welded to obtain a plastic encapsulation layer that embeds the first chip.
[0074] In this step, the first redistribution layer 110 welded with the first chip 121 can be placed in a plastic packaging mold, and then epoxy molding compound (EMC) is pressed into the mold by injection molding to form a plastic packaging layer 1201 that seals and embeds the first chip 121.
[0075] Step S1222: Grinding the plastic packaging layer that embeds the first chip until the orthographic projection of the plastic packaging layer on the first redistribution layer does not overlap with the orthographic projection of the first chip on the first redistribution layer, thereby obtaining a first plastic packaging layer.
[0076] In this step, the plastic encapsulation layer 1201 that embeds the first chip 121 is ground until the first chip 121 is exposed to obtain the first plastic encapsulation layer 122. The orthographic projection of the first plastic encapsulation layer 122 on the first redistribution layer 110 does not overlap with the orthographic projection of the first chip 121 on the first redistribution layer 110, that is, the first plastic encapsulation layer 122 fills the peripheral side of the first chip 121. The first plastic encapsulation layer 122 can protect the first chip 121 from physical damage (such as vibration, impact, etc.) and environmental factors (such as temperature, dust, etc.).
[0077] Step S1223: patterning the first plastic encapsulation layer to form a wiring through hole penetrating the first plastic encapsulation layer.
[0078] In this step, a photoresist layer can be first coated on the first plastic encapsulation layer 122, and the photoresist layer can be developed and exposed through a mask template to form a photoresist opening exposing the first plastic encapsulation layer 122, and finally the first plastic encapsulation layer 122 located at the photoresist opening is etched to obtain a wiring through hole 124 that passes through the first plastic encapsulation layer 122, wherein the projection of the wiring through hole 124 on the first redistribution layer 110 overlaps with at least a portion of the first conductive wiring 111 in the first redistribution layer 110.
[0079] Step S1224: performing metal deposition on the first redistribution layer after forming the routing through holes, forming through-hole leads in the routing through holes, and obtaining a first chip layer.
[0080] In this step, a through-hole lead 123 may be formed in the routing through-hole 124 by a physical or chemical vapor deposition or electroplating method, wherein the through-hole lead 123 is electrically connected to the first redistribution layer 110 .
[0081] For further information, please refer to Figure 7 and Figure 8 , step S130 can be implemented in the following manner.
[0082] Step S131: removing the first carrier, and transferring the first redistribution layer of the first chip layer to the second carrier.
[0083] In this step, the first redistribution layer 110 of the first chip layer 120 can be separated from the first carrier 210 by removing the first bonding 211, and then transferred to the second carrier 220. Specifically, the second bonding layer 221 can be made on one side of the second carrier 220, and then the first redistribution layer 110 of the first chip layer 120 can be transferred to the side of the second bonding layer 221 away from the second carrier 220, wherein the side of the first chip layer 120 away from the first redistribution layer 110 contacts the second carrier 220.
[0084] Step S132: placing at least one second chip on the second side of the first redistribution layer, and soldering the second chip to the second connection portion.
[0085] In this step, after the second chip 131 and the second connection portion 113 are welded to form an electrical connection, bottom filling can be performed at the position where the second chip 131 contacts the second connection portion 113, and the connection between the second chip 131 and the first redistribution layer 110 is further enhanced by the bottom filling process, thereby improving the reliability of the package. The second chip 131 includes functional chips such as a system-on-chip (SoC chip) and a high-bandwidth memory chip (HBM), and the second connection portion 113 may include a micro pad.
[0086] Step S133: forming a second plastic packaging layer on the peripheral side of the second chip to obtain a second chip layer.
[0087] In this step, the first redistribution layer 110 to which the second chip 131 is welded can be placed in a plastic encapsulation mold, and then the epoxy molding compound can be pressed into the mold by injection molding to form a plastic encapsulation layer that seals and embeds the second chip 131. Next, the plastic encapsulation layer that embeds the second chip 131 can be ground until the second chip 131 is exposed to obtain a second plastic encapsulation layer 132. The projection of the second plastic encapsulation layer 132 on the first redistribution layer 110 does not overlap with the projection of the second chip 131 on the first redistribution layer 110, that is, the second plastic encapsulation layer 132 is located on the peripheral side of the second chip 131.
[0088] In this embodiment, the first redistribution layer 110 is first manufactured, and then the second chip 131 is flipped onto the second connection portion 113, so that the second chip 131 can be prevented from being offset due to the influence of thermal expansion coefficient mismatch, mechanical impact, etc. during the manufacturing process of the second plastic packaging layer 132, thereby improving the chip mounting accuracy. At the same time, flipping the second chip 131 can also shorten the signal transmission path, making the chip packaging structure more compact, and improving the integration of the chip packaging structure.
[0089] For some possible embodiments, please refer to Fig. 9 and Fig.10After step S133, the chip packaging method provided in the embodiment of the present application may further include the following steps.
[0090] Step S141: remove the second carrier, and transfer the first redistribution layer on which the second chip layer is manufactured to a third carrier.
[0091] In this step, the first redistribution layer 110 on which the second chip layer 130 is made can be separated from the second carrier 220 by removing the second bonding layer 221, and then transferred to the third carrier 230. Specifically, the third bonding layer 231 can be firstly made on one side of the third carrier 230, and the first redistribution layer 110 on which the second chip layer 130 is made can be transferred to the third carrier 230, wherein the side of the second chip layer 130 away from the first redistribution layer 110 contacts the third carrier 230.
[0092] Step S142: manufacturing a second redistribution layer on a side of the first chip layer away from the third carrier board, wherein the second redistribution layer is electrically connected to the through-hole leads.
[0093] In this step, the second redistribution layer 140 includes a second conductive trace 141 for transmitting an electrical signal. The second conductive trace 141 may be electrically connected to the first redistribution layer 110 through a through-hole lead 123 .
[0094] Step S143: performing ball placement processing on a side of the second redistribution layer away from the third carrier board to obtain conductive balls electrically connected to the second redistribution layer.
[0095] In this step, the conductive ball 150 may be electrically connected to the first redistribution layer 110 through the second conductive trace 141 and the through-hole lead 123 .
[0096] In addition, after this step, the manufactured chip packaging structure and the third carrier 230 can be separated by removing the third bonding layer 231 , and the chip packaging structure can be welded with other electronic components through the conductive balls 150 .
[0097] Based on the same invention idea, please refer to Fig.11 The embodiment of the present application also provides a chip packaging structure 10 manufactured based on any one of the methods in the above embodiments. The chip packaging structure 10 includes a first redistribution layer 110 , a first chip layer 120 and a second chip layer 130 .
[0098] The first redistribution layer 110 may include a first side 110A and a second side 110B opposite to each other, and a first connection portion 112 located on the first side 110A and a second connection portion 113 located on the second side 110B. The first redistribution layer 110 may include a first conductive trace 111 for transmitting an electrical signal, and the first conductive trace 111 may be electrically connected to other electronic devices through the first connection portion 112 and / or the second connection portion 113. Exemplarily, the first connection portion 112 and the second connection portion 113 may be micro pads.
[0099] The first chip layer 120 may be located at a first side of the first redistribution layer 110. The first chip layer 120 includes at least one first chip 121, the pin side of the first chip 121 faces the first redistribution layer 110, and the pins of the first chip 121 may be welded to the first connection portion 112 to achieve electrical connection between the first chip 121 and the first redistribution layer 110. The first chip 121 includes a bridge chip, which may be used to achieve interconnection between different chips.
[0100] The second chip layer 130 may be located at the second side 110B of the first redistribution layer 110, and the second chip layer 130 includes at least one second chip 131, the pin side of the second chip 131 faces the first redistribution layer 110, and the pins of the second chip 131 may be welded to the second connection portion 113 to achieve electrical connection between the second chip 131 and the first redistribution layer 110. The second chip 131 may include functional chips such as a system-on-chip (SoC chip) and a high-bandwidth memory chip (HBM).
[0101] In the above structure, flipping the first chip 121 and the second chip 131 can not only shorten the signal transmission path, but also make the chip packaging structure 10 more compact and improve the chip integration. In addition, in the manufacturing process of the above chip packaging structure 10, the first redistribution layer is first manufactured, and then the first chip and the second chip are flipped through the first connection part and the second connection part, which can not only prevent the first chip and the second chip from being offset in the subsequent manufacturing process and improve the patch accuracy, but also reduce the chip scrapping caused by the poor redistribution layer and reduce the production cost.
[0102] For further information, please refer to Fig.12, the first chip layer 120 may further include a first plastic encapsulation layer 122 filled around the first chip 121, and the orthographic projection of the first plastic encapsulation layer 122 on the first redistribution layer 110 does not overlap with the orthographic projection of the first chip 121 on the first redistribution layer 110. The first plastic encapsulation layer 122 may be provided with a routing through hole penetrating the first plastic encapsulation layer 122, and a through hole lead 123 is provided in the routing through hole, and the through hole lead 123 is electrically connected to the first conductive trace 111 in the first redistribution layer 110. Similarly, the second chip layer 130 also includes a second plastic encapsulation layer 132 filled around the second chip 131, and the orthographic projection of the second plastic encapsulation layer 132 on the first redistribution layer 110 does not overlap with the orthographic projection of the second chip 131 on the first redistribution layer 110. The first plastic encapsulation layer 122 and the second plastic encapsulation layer 132 can protect the first chip 121 and the second chip 131 from physical damage (such as vibration, impact, etc.) and environmental factors (such as temperature, dust, etc.).
[0103] Furthermore, the chip package structure 10 may further include a second redistribution layer 140 and a conductive ball 150. The second redistribution layer 140 is located on a side of the first chip layer 120 away from the first redistribution layer 110, the conductive ball 150 is located on a side of the second redistribution layer 140 away from the first chip layer 120, and the conductive ball 150 is electrically connected to the first redistribution layer 110 through the second conductive trace 141 in the second redistribution layer 140 and the through-hole lead 123.
[0104] In addition, an embodiment of the present application further provides an electronic device, which includes a chip packaging structure manufactured according to the chip packaging method in any of the above embodiments.
[0105] In summary, the present application provides a chip packaging method, a chip packaging structure and an electronic device. In the above chip packaging method, the first redistribution layer is first made, and then the first chip and the second chip are flipped on the first connector and the second connector respectively. This can prevent the first chip and the second chip from being offset in the subsequent process, improve the patch accuracy, and flip the first chip and the second chip can not only shorten the signal transmission path, but also make the chip packaging structure more compact and improve the chip integration. In addition, making the first redistribution layer in advance can also reduce the chip scrapping caused by the defective redistribution layer and reduce production costs.
[0106] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip packaging method, characterized in that: The method comprises: Providing a first carrier board, and manufacturing a first redistribution layer on one side of the first carrier board, wherein the first redistribution layer comprises a first side and a second side opposite to each other, the second side of the redistribution layer contacts the first carrier board, and the first redistribution layer further comprises a first connecting portion located on the first side and a second connecting portion located on the second side; Manufacturing a first chip layer on a first side of the first redistribution layer, wherein the first chip layer includes at least one first chip, and pins of the first chip are electrically connected to the first redistribution layer through the first connection portion; The first carrier board is removed, and a second chip layer is manufactured on the second side of the first redistribution layer. The second chip layer includes at least one second chip, and the pins of the second chip are electrically connected to the first redistribution layer through the second connection portion.
2. The chip packaging method according to claim 1, characterized in that: The step of manufacturing the first chip layer on the first side of the first redistribution layer comprises: Placing at least one first chip on a side of the first redistribution layer away from the first carrier, and welding the first chip to the first connection portion so that an electrode of the first chip is electrically connected to the first redistribution layer; A first plastic encapsulation layer is formed on the peripheral side of the first chip, and through-hole leads are made on the first plastic encapsulation layer to penetrate the first plastic encapsulation layer, so as to obtain the first chip layer, wherein the through-hole leads are electrically connected to the first redistribution layer, and the orthographic projection of the first plastic encapsulation layer on the first redistribution layer does not overlap with the orthographic projection of the first chip on the first redistribution layer.
3. The chip packaging method according to claim 2, characterized in that: The step of forming a first plastic encapsulation layer on the peripheral side of the first chip and making through-hole leads penetrating the first plastic encapsulation layer on the first plastic encapsulation layer to obtain the first chip layer includes: Performing a plastic encapsulation process on the first redistribution layer after the first chip is welded, so as to obtain a plastic encapsulation layer that embeds the first chip; Grinding the plastic encapsulation layer that embeds the first chip until the first chip is exposed to obtain a first plastic encapsulation layer, wherein the orthographic projection of the first plastic encapsulation layer on the first redistribution layer does not overlap with the orthographic projection of the first chip on the first redistribution layer to obtain the first plastic encapsulation layer; Performing patterning on the first plastic encapsulation layer to form a wiring through hole penetrating the first plastic encapsulation layer; Metal deposition is performed on the first redistribution layer after the routing through hole is formed, and through-hole leads are formed in the routing through hole to obtain the first chip layer, wherein the through-hole leads are electrically connected to the first redistribution layer.
4. The chip packaging method according to claim 2, characterized in that: The step of removing the first carrier board and manufacturing a second chip layer on the second side of the first redistribution layer includes: Removing the first carrier board, and transferring the first redistribution layer on which the first chip layer is manufactured to a second carrier board, wherein a side of the first chip layer away from the first redistribution layer contacts the second carrier board; placing at least one second chip on the second side of the first redistribution layer, and soldering the second chip to the second connection portion; A second plastic packaging layer is formed on the peripheral side of the second chip to obtain the second chip layer.
5. The chip packaging method according to claim 4, characterized in that: After the step of forming a second plastic encapsulation layer on the peripheral side of the second chip to obtain the second chip layer, the method further includes: The second carrier is removed, and the first redistribution layer on which the second chip layer is made is transferred to a third carrier, wherein a side of the second chip layer away from the redistribution is in contact with the third carrier; A second redistribution layer is fabricated on a side of the first chip layer away from the third carrier board, wherein the second redistribution layer is electrically connected to the through-hole leads; A ball placement process is performed on a side of the second redistribution layer away from the third carrier board to obtain a conductive ball electrically connected to the second redistribution layer. The conductive ball is electrically connected to the first redistribution layer through the second redistribution layer and the through-hole lead.
6. A chip packaging structure, characterized in that: The chip packaging structure comprises: A first redistribution layer, wherein the first redistribution layer comprises a first side and a second side opposite to each other, and the first redistribution layer comprises a first connection portion located on the first side and a second connection portion located on the second side; A first chip layer is located on a first side of the first redistribution layer, the first chip layer includes at least one first chip, a pin side of the first chip faces the first redistribution layer, and the pin of the first chip is connected to the first connection portion; The second chip layer is located at the second side of the first redistribution layer, the pin side of the second chip in the second chip layer faces the first redistribution layer, and the pin of the second chip is connected to the second connection portion.
7. The chip packaging structure according to claim 6, characterized in that: The first chip layer further includes a first plastic encapsulation layer filled around the first chip, and an orthographic projection of the first plastic encapsulation layer on the first redistribution layer does not overlap with an orthographic projection of the first chip on the first redistribution layer; The second chip layer further includes a second plastic encapsulation layer filled around the second chip, and an orthographic projection of the second plastic encapsulation layer on the first redistribution layer does not overlap with an orthographic projection of the second chip on the first redistribution layer; Preferably, the first chip comprises a bridge chip; Preferably, the second chip includes a system-level chip and a high-bandwidth memory chip.
8. The chip packaging structure according to claim 7, characterized in that: The first plastic encapsulation layer is provided with a wiring through hole penetrating the first plastic encapsulation layer, a through hole lead is provided in the wiring through hole, and the through hole lead is connected to the first redistribution layer.
9. The chip packaging structure according to claim 8, characterized in that: The chip packaging structure also includes a second redistribution layer and conductive balls; The second redistribution layer is located on a side of the first chip layer away from the first redistribution layer, the conductive ball is located on a side of the second redistribution layer away from the first chip layer, and the conductive ball is electrically connected to the first redistribution layer through the second redistribution layer and the through-hole lead.
10. An electronic device, characterized in that: A chip packaging structure comprising a chip packaging method according to any one of claims 1 to 5, or a chip packaging structure according to any one of claims 6 to 9.