Semiconductor device, memory device, and memory system

Abstract

The invention relates to a semiconductor device, a memory device, and a memory system. In one example, a semiconductor device includes an interconnect layer including a bonding structure, a plurality of dummy bonding structures, and a first connection portion, where at least one dummy bonding structure of the plurality of dummy bonding structures is coupled to the bonding structure through the first connection portion. By coupling the bonding structure with the adjacent at least one dummy bonding structure, the protruding amount of the bonding structure can be effectively reduced or eliminated.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor device manufacturing, and more particularly to semiconductor devices, memory devices, and memory systems. Background Art

[0002] In the manufacturing process of the memory device, different wafers can be bonded together to form the memory device. The different wafers can be, for example, a memory array wafer and a logic circuit wafer, wherein the logic circuit wafer is also called a peripheral circuit wafer, which provides signals to the memory array wafer so that the memory array wafer can operate normally. In some examples, the logic circuit wafer is formed using complementary metal oxide semiconductor (CMOS) technology, and thus the logic circuit wafer is also called a CMOS wafer. Summary of the invention

[0003] The present disclosure provides a semiconductor device, a memory apparatus, and a memory system.

[0004] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: an interconnection layer, the interconnection layer comprising a bonding structure, a plurality of dummy bonding structures, and a first connection portion, wherein at least one dummy bonding structure of the plurality of dummy bonding structures is coupled to the bonding structure through the first connection portion.

[0005] In one example, the interconnect layer further includes a first dielectric layer, the bonding structure and the plurality of dummy bonding structures extend from a first side of the first dielectric layer toward a second side of the first dielectric layer in the first dielectric layer, and the first side is opposite to the second side.

[0006] In one example, the first connection portion is located on the first side of the first dielectric layer.

[0007] In one example, the first connection portion is located on the second side of the first dielectric layer.

[0008] In one example, the interconnect layer further includes a second dielectric layer and a second connection portion extending through the second dielectric layer, wherein the second connection portion is coupled to the bonding structure.

[0009] In one example, the bonding structure is located in a bonding hole in the first dielectric layer, and a dimension of the bonding hole at the first side is larger than a dimension of the bonding hole at the second side.

[0010] In one example, the semiconductor device further includes a substrate, the substrate includes a doped region, and the doped region is coupled to the second connection portion.

[0011] In one example, the first connection portion, the bonding structure, and the at least one dummy bonding structure are coupled to the doped region through the second connection portion.

[0012] In one example, the bonding structure and the plurality of dummy bonding structures each include a recessed portion.

[0013] In one example, the bonding structure, the plurality of dummy bonding structures, and the first connection portion include a same metal.

[0014] In one example, a diffusion barrier layer is provided between the bonding structure and each of the plurality of dummy bonding structures and the first dielectric layer.

[0015] In one example, the doped region includes a source or drain region of a transistor.

[0016] According to another aspect of the present disclosure, a memory device is provided, comprising: a first semiconductor device; and a second semiconductor device bonded to the first semiconductor device, wherein at least one of the first semiconductor device and the second semiconductor device comprises: an interconnect layer, the interconnect layer comprising a bonding structure, a plurality of dummy bonding structures, and a first connecting portion, wherein at least one of the plurality of dummy bonding structures is coupled to the bonding structure via the first connecting portion.

[0017] In one example, the interconnect layer further includes a first dielectric layer, the bonding structure and the plurality of dummy bonding structures extend from a first side of the first dielectric layer toward a second side of the first dielectric layer in the first dielectric layer, and the first side is opposite to the second side.

[0018] In one example, the first connection portion is located on the first side of the first dielectric layer.

[0019] In one example, the first connection portion is located on the second side of the first dielectric layer.

[0020] In one example, the interconnect layer further includes a second dielectric layer and a second connection portion extending through the second dielectric layer, wherein the second connection portion is coupled to the bonding structure.

[0021] In one example, the bonding structure is located in a bonding hole in the first dielectric layer, and a dimension of the bonding hole at the first side is larger than a dimension of the bonding hole at the second side.

[0022] In one example, the at least one semiconductor device of the first semiconductor device and the second semiconductor device further includes a substrate, the substrate includes a doped region, and the doped region is coupled to the second connection portion.

[0023] In one example, the first connection portion, the bonding structure, and the at least one dummy bonding structure are coupled to the doped region through the second connection portion.

[0024] In one example, the bonding structure and the plurality of dummy bonding structures each include a recessed portion.

[0025] In one example, the bonding structure, the plurality of dummy bonding structures, and the first connection portion include a same metal.

[0026] In one example, a diffusion barrier layer is provided between the bonding structure and each of the plurality of dummy bonding structures and the first dielectric layer.

[0027] In one example, the doped region includes a source or drain region of a transistor.

[0028] According to another aspect of the present disclosure, a memory system is provided, comprising: any one of the above-mentioned memory devices; and a memory controller, the memory controller being coupled to the memory device and configured to control the operation of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, some examples of the present disclosure will be described below with reference to the accompanying drawings, in which:

[0030] Figure 1 A cross-sectional view schematically showing the structure of a semiconductor device according to a first example of the present disclosure;

[0031] Figure 2 A cross-sectional view schematically showing a structure of a semiconductor device according to a second example of the present disclosure;

[0032] Figure 3 Schematically illustrates a plan view of a semiconductor device according to an example of the present disclosure;

[0033] Figure 4 A cross-sectional view schematically showing the structure of a memory device according to an example of the present disclosure;

[0034] Figure 5 A flowchart schematically shows a method for manufacturing a semiconductor device according to a first example of the present disclosure;

[0035] Figure 6Schematically shows a flow chart of a method for manufacturing a semiconductor device according to a second example of the present disclosure;

[0036] Figure 7 a cross-sectional view schematically showing a structure of a semiconductor device according to a third example of the present disclosure; and

[0037] Figure 8 A memory system according to one example of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0038] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. In addition, the present disclosure may also be used for various other applications. The functions and structural features described in the present disclosure may be combined, adjusted and modified with each other in a manner not specifically shown in the accompanying drawings, so that these combinations, adjustments and modifications are within the scope of the present disclosure.

[0039] It should be easily understood that the meaning of “on,” “over,” and “above” in the present disclosure should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “on” or “above” not only means “on something” or “over something,” but also includes the meaning of “on something” or “over something” without intervening features or layers therebetween (i.e., directly on something).

[0040] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," and "upper" may be used herein to describe the relationship of one element or feature to another element or features as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 180 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0041] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc.

[0042] In the manufacturing process of the memory device, a memory array wafer and a logic circuit wafer can be formed separately, and a bonding structure and a dummy bonding structure can be formed on both the memory array wafer and the logic circuit wafer, so that the memory array wafer and the logic circuit wafer can be bonded together using the bonding structure and the dummy bonding structure, thereby forming a memory device. In one example of forming the bonding structure and the dummy bonding structure, a bonding hole and a dummy bonding hole can be formed in a dielectric layer, and then a metal (e.g., copper) is filled in the bonding hole and the dummy bonding hole, and then the filled metal is chemically mechanically polished (CMP) to form a bonding structure and a dummy bonding structure. The introduction of the dummy bonding structure can not only enhance the bonding force between the memory array wafer and the logic circuit wafer, but also achieve load balance of chemical mechanical polishing.

[0043] However, free metal ions, such as copper ions, may exist on the bonding structure and the dummy bonding structure formed above. In addition, during the manufacture of the memory array wafer or the logic circuit wafer, an ion implantation process may be performed to form a doped region of the semiconductor device, which results in a potential difference between the bonding structure coupled to the doped region and the dummy bonding structure not coupled to the doped region. Driven by the potential difference, the free metal ions may gather on the bonding structure, so that the bonding structure has a protruding structure, which is not conducive to subsequent wafer bonding operations.

[0044] In order to avoid the bonding structure having a protruding structure or reduce the protruding amount of the bonding structure, the bonding structure can be coupled to at least one adjacent dummy bonding structure so that the two have the same potential. Since the bonding structure and the at least one dummy bonding structure have the same potential, that is, there is no potential difference between the two, the free metal ions on the at least one dummy bonding structure will not move toward the bonding structure. Moreover, the at least one dummy bonding structure can also share with the bonding structure the free metal ions from other dummy bonding structures that are not coupled to the bonding structure under the above-mentioned potential difference drive.

[0045] Therefore, by coupling the bonding structure with at least one adjacent dummy bonding structure, the protrusion of the bonding structure can be effectively reduced or eliminated. In one example, the bonding structure and the dummy bonding structure can also be configured to have a recessed portion (dishing), wherein the recessed portion is configured to have an appropriate recessed amount, thereby facilitating the bonding between the memory array wafer and the logic circuit wafer.

[0046] Figure 1 The cross-sectional view schematically shows a structure of a semiconductor device 100 according to a first example of the present disclosure. The semiconductor device 100 may include a semiconductor substrate 109 and an interconnection layer 110 located on the semiconductor substrate 109 .

[0047] like Figure 1 As shown, the substrate 109 may include a doped region 108. The doped region 108 may be formed by performing an ion implantation process in the semiconductor substrate 109. The doped region 108 may be an n-type doped region or a p-type doped region. For the n-type doped region, ions such as boron (B) or indium (In) may be implanted; and for the p-type doped region, ions such as arsenic (As) or phosphorus (P) may be implanted. In addition, the doped region may include a source or drain region of a transistor. It should be noted that although Figure 1 Only one doping region 108 is shown, but as can be understood by those skilled in the art, more than one doping region, that is, a plurality of doping regions, may be formed in the semiconductor substrate 109 .

[0048] The interconnect layer 110 may include: a first dielectric layer 105; a bonding structure 101 and a plurality of dummy bonding structures 102-1, 102-2, 102-3, 102-4 formed in the first dielectric layer 105; and a first side ( Figure 1 It should be noted that although Figure 1 Only one bonding structure 101 is shown, but as can be understood by those skilled in the art, more than one bonding structure, that is, a plurality of bonding structures, may be formed in the first dielectric layer 105 .

[0049] In one example, the bonding structure 101 , the plurality of dummy bonding structures 102 - 1 to 102 - 4 , and the first connection portion 103 may include the same metal, such as copper.

[0050] Reference Figure 1 The bonding structure 101 and the dummy bonding structures 102-1 to 102-4 are respectively located in the bonding holes and the dummy bonding holes formed in the first dielectric layer 105. Figure 1 As shown, the bonding holes and the dummy bonding holes are formed on the first side of the first dielectric layer 105 ( Figure 1 The size of the bonding hole and the dummy bonding hole on the second side ( Figure 1 The dimensions of the bottom side of the

[0051] Each of the dummy bonding structure and the bonding structure may have a diffusion barrier layer between the first dielectric layer. In one example, after forming the bonding hole and the dummy bonding hole, a diffusion barrier layer may be first formed on the sidewalls and bottom of the bonding hole and the dummy bonding hole, and then the bonding structure and the dummy bonding structure may be used to fill the remaining space of the bonding hole and the dummy bonding hole. Figure 1As shown, there is a diffusion barrier layer 104 between the dummy bonding structure 102-3 and the first dielectric layer 105, which can be used to prevent the metal material of the dummy bonding structure 102-3 from diffusing into the first dielectric layer 105. Similarly, there is a diffusion barrier layer 104 between the bonding structure 101 and the first dielectric layer 105.

[0052] In addition, if Figure 1 As shown, the bonding structure 101 and the dummy bonding structures 102 - 1 to 102 - 4 may each have a recessed portion, and the recessed portion is configured to have an appropriate recessed amount to facilitate bonding between the semiconductor device 100 and other devices.

[0053] exist Figure 1 In one example shown, the bonding structure 101 can be coupled to two adjacent dummy bonding structures 102-1 and 102-2 via the first connection portion 103. Figure 1 As shown, the bonding structure 101 is coupled to the dummy bonding structure 102-1 through the first connection portion 103 on the left, and is coupled to the dummy bonding structure 102-2 through the first connection portion 103 on the right. In other examples, the bonding structure 101 can be coupled to one dummy bonding structure through the first connection portion, or can be coupled to three or more dummy bonding structures through the first connection portion.

[0054] The interconnection layer 110 may further include a second dielectric layer 107 located on the semiconductor substrate 109, and a second connection portion 106 formed in the second dielectric layer 107. Figure 1 As shown, the bonding structure 101 is coupled to the doped region 108 in the semiconductor substrate 109 via the second connection portion 106 , so that the bonding structure 101 and the doped region 108 have the same electrical potential.

[0055] like Figure 1 As shown, the first connection portion 103 couples the bonding structure 101 with the two adjacent dummy bonding structures 102-1 and 102-2, and the coupled bonding structure 101 and the dummy bonding structures 102-1 and 102-2 are coupled to the doping region 108 through the second connection portion 106. Since the bonding structure 101 is coupled with the two adjacent dummy bonding structures 102-1 and 102-2, there is no potential difference between the bonding structure 101 and the two adjacent dummy bonding structures 102-1 and 102-2. However, as Figure 1 As shown, the dummy bonding structures 102 - 3 and 102 - 4 are not coupled to the bonding structure 101 , so there is a potential difference between the dummy bonding structures 102 - 3 and 102 - 4 and the bonding structure 101 .

[0056] On the one hand, due to the above structure, the bonding structure 101 and the two adjacent dummy bonding structures 102 - 1 and 102 - 2 have the same potential. As a result, the free metal ions existing on the dummy bonding structures 102 - 1 and 102 - 2 will not gather toward the bonding structure 101 .

[0057] On the other hand, due to the above structure, the dummy bonding structures 102 - 1 and 102 - 2 can also share free metal ions with the bonding structure 101 .

[0058] Therefore, the above structure can effectively reduce the amount of free metal ions gathered on the bonding structure 101 , thereby reducing or eliminating the protrusion amount of the bonding structure 101 .

[0059] Figure 2 The cross-sectional view schematically shows a structure of a semiconductor device 200 according to a second example of the present disclosure. The semiconductor device 200 may include a semiconductor substrate 209 and an interconnection layer 210 located on the semiconductor substrate 209 .

[0060] like Figure 2 As shown, the substrate 209 may include a doped region 208. The doped region 208 may be formed by performing an ion implantation process in the semiconductor substrate 209. The doped region may be an n-type doped region or a p-type doped region. For the n-type doped region, ions such as boron (B) or indium (In) may be implanted; and for the p-type doped region, ions such as arsenic (As) or phosphorus (P) may be implanted. In addition, the doped region may include a source or drain region of a transistor. It should be noted that although Figure 2 Only one doping region 208 is shown, but as can be understood by those skilled in the art, more than one doping region, that is, a plurality of doping regions, may be formed in the semiconductor substrate 209 .

[0061] The interconnect layer 210 may include: a first dielectric layer 205; and a bonding structure 201 and a plurality of dummy bonding structures 202-1, 202-2, 202-3, 202-4 formed in the first dielectric layer 205. It should be noted that although Figure 2 Only one bonding structure 201 is shown, but as can be understood by those skilled in the art, more than one bonding structure, that is, a plurality of bonding structures, may be formed in the first dielectric layer 205 .

[0062] Reference Figure 2 The bonding structure 201 and the dummy bonding structures 202-1 to 202-4 are respectively located in the bonding holes and the dummy bonding holes formed in the first dielectric layer 205. Figure 2 As shown, the bonding holes and the dummy bonding holes are formed on the first side of the first dielectric layer 205 ( Figure 2The size of the bonding hole and the dummy bonding hole on the second side ( Figure 2 The dimensions of the bottom side of the

[0063] Each of the dummy bonding structure and the bonding structure may have a diffusion barrier layer between the first dielectric layer. In one example, after forming the bonding hole and the dummy bonding hole, a diffusion barrier layer may be first formed on the sidewalls and bottom of the bonding hole and the dummy bonding hole, and then the bonding structure and the dummy bonding structure may be used to fill the remaining space of the bonding hole and the dummy bonding hole. Figure 2 As shown, there is a diffusion barrier layer 204 between the dummy bonding structure 202-3 and the first dielectric layer 205, which can be used to prevent the metal material of the dummy bonding structure 202-3 from diffusing into the first dielectric layer 205. Similarly, there is a diffusion barrier layer 204 between the bonding structure 201 and the first dielectric layer 205.

[0064] The bonding structure 201 and the dummy bonding structures 202 - 1 to 202 - 4 may each have a recessed portion, and the recessed portion is configured to have an appropriate recessed amount to facilitate bonding between the semiconductor device 200 and other devices.

[0065] like Figure 2 As shown, the semiconductor device 200 may further include a first connection portion 203, the first connection portion 203 being located at the second side ( Figure 2 In one example, the bonding structure 201, the plurality of dummy bonding structures 202-1 to 202-4, and the first connection portion 203 may include the same metal, such as copper.

[0066] exist Figure 2 In one example shown, the bonding structure 201 can be coupled to two adjacent dummy bonding structures 202-1 and 202-2 via the first connection portion 203. Figure 2 The bonding structure 201 and the dummy bonding structures 202-1, 202-2 are shown to be directly coupled to the first connection portion 203, but in other examples, the bonding structure 201 and the dummy bonding structures 202-1, 202-2 may be coupled to the first connection portion 203 through a wiring layer. In further examples, the bonding structure 201 may be coupled to one dummy bonding structure through the first connection portion, or may be coupled to three or more dummy bonding structures through the first connection portion.

[0067] The interconnection layer 210 may further include a second dielectric layer 207 located on the semiconductor substrate 209, and a second connection portion 206 formed in the second dielectric layer 207. Figure 2As shown, the bonding structure 201 is coupled to the doped region 208 in the semiconductor substrate 209 via the second connection portion 206 , so that the bonding structure 201 and the doped region 208 have the same electrical potential.

[0068] like Figure 2 As shown, the first connection portion 203 couples the bonding structure 201 and the two adjacent dummy bonding structures 202-1 and 202-2 together, and the coupled bonding structure 201 and the dummy bonding structures 202-1 and 202-2 are coupled to the doping region 208 through the second connection portion 206. Since the bonding structure 201 and the two adjacent dummy bonding structures 202-1 and 202-2 are coupled together, there is no potential difference between the bonding structure 201 and the two adjacent dummy bonding structures 202-1 and 202-2. However, as shown in FIG. Figure 2 As shown, the dummy bonding structures 202 - 3 and 202 - 4 are not coupled to the bonding structure 201 , so there is a potential difference between the dummy bonding structures 202 - 3 and 202 - 4 and the bonding structure 201 .

[0069] On the one hand, due to the above structure, the bonding structure 201 and the two adjacent dummy bonding structures 202 - 1 and 202 - 2 have the same potential. As a result, the free metal ions existing on the dummy bonding structures 202 - 1 and 202 - 2 will not gather toward the bonding structure 201 .

[0070] On the other hand, due to the above structure, the dummy bonding structures 202 - 1 and 202 - 2 can also share free metal ions with the bonding structure 201 .

[0071] Therefore, the above structure can effectively reduce the amount of free metal ions gathered on the bonding structure 201 , thereby reducing or eliminating the protrusion amount of the bonding structure 201 .

[0072] Figure 3 A plan view of a semiconductor device 300 according to an example of the present disclosure is schematically shown.

[0073] like Figure 3 As shown, the semiconductor device 300 may include a plurality of bonding structures 301, and a plurality of dummy bonding structures 302-1, 302-2, 302-3, and 302-4. Figure 3 In the example shown, each bonding structure 301 and four dummy bonding structures 302-1, 302-2, 302-3 and 302-4 are located in the same row, but the present disclosure is not limited thereto. As can be understood by those skilled in the art, multiple bonding structures and multiple dummy bonding structures may be arranged in each row.

[0074] exist Figure 3In one example shown, in each row, the bonding structure 301 can be coupled to the dummy bonding structures 302 - 1 and 302 - 2 through the first connection portion 303 so that the bonding structure 301 and the dummy bonding structures 302 - 1 and 302 - 2 have the same potential, thereby reducing or eliminating the protrusion of the bonding structure 301 .

[0075] Figure 4 A cross-sectional view schematically shows a structure of a memory device according to an example of the present disclosure. The memory device may include a first semiconductor device 400 - 1 and a second semiconductor device 400 - 2 .

[0076] exist Figure 4 In one example shown, the first semiconductor device 400-1 and the second semiconductor device 400-2 are connected to Figure 2 The semiconductor device 200 shown in FIG. 1 has the same or similar structure. In other examples, the first semiconductor device 400-1 and the second semiconductor device 400-2 may be the same as Figure 1 The semiconductor device 100 shown in FIG. 1 has the same or similar structure. In some other examples, one of the first semiconductor device 400 - 1 and the second semiconductor device 400 - 2 may be the same as Figure 1 The semiconductor device 100 shown has the same or similar structure, and the other semiconductor device of the first semiconductor device 400-1 and the second semiconductor device 400-2 may be the same as Figure 2 The semiconductor devices 200 shown have the same or similar structures.

[0077] like Figure 4 As shown, the first semiconductor device 400-1 may have a semiconductor substrate 409-1, a doped region 408-1 located in the semiconductor substrate 409-1, a first dielectric layer 405-1, a bonding structure 401-1 and multiple dummy bonding structures 402-1 located in the first dielectric layer 405-1, a second dielectric layer 407-1, and a second connection portion 406-1 located in the second dielectric layer 407-1, and the second semiconductor device 400-2 may have a semiconductor substrate 409-2, a doped region 408-2 located in the semiconductor substrate 409-2, a first dielectric layer 405-2, a bonding structure 401-2 and multiple dummy bonding structures 402-2 located in the first dielectric layer 405-2, a second dielectric layer 407-2, and a second connection portion 406-2 located in the second dielectric layer 407-2.

[0078] Reference Figure 4The first semiconductor device 400-1 further includes a first connection portion 403-1, and the first connection portion 403-1 couples the bonding structure 401-1 and two adjacent dummy bonding structures 402-1 together. In addition, the second semiconductor device 400-2 further includes a first connection portion 403-2, and the first connection portion 403-2 couples the bonding structure 401-2 and two adjacent dummy bonding structures 402-2 together.

[0079] For simplicity, Figure 4 The diffusion barrier layer between the bonding structure and the dummy bonding structure and the first dielectric layer is omitted.

[0080] As mentioned above, Figure 4 The first semiconductor device 400-1 and the second semiconductor device 400-2 are shown in FIG. Figure 2 The semiconductor device 200 shown has the same or similar structure, and thus will not be described in detail herein.

[0081] like Figure 4 As shown, the first semiconductor device 400 - 1 and the second semiconductor device 400 - 2 are bonded together through respective bonding structures 401 - 1 and 401 - 2 and respective dummy bonding structures 402 - 1 and 402 - 2 to form a memory device.

[0082] Since the first semiconductor device 400-1 and the second semiconductor device 400-2 of the memory device are Figure 2 The semiconductor device 200 shown has the same or similar structure, so the memory device has at least Figure 2 The same or similar advantages as those of the semiconductor device 200 are not described in detail here.

[0083] Figure 5 A flowchart of a method of manufacturing a semiconductor device according to a first example of the present disclosure is schematically shown.

[0084] The following will refer to Figure 5 Combined with Figure 1 A flowchart of a method 500 of manufacturing a semiconductor device according to a first example of the present disclosure is described.

[0085] The method 500 may include operation 510 . In operation 510 , a semiconductor substrate 109 is provided, and a doped region 108 is formed by performing an ion implantation process in the semiconductor substrate 109 .

[0086] After operation 510, the method 500 may proceed to operation 520. In operation 520, a second dielectric layer 107 is formed over the semiconductor substrate 109, and a second connection portion 106 is formed in the second dielectric layer 107. In one example, a through hole may be formed in the second dielectric layer 107, and a metal may be deposited in the through hole by a deposition process to form the second connection portion 106. The deposition process may include, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof.

[0087] After operation 520 , the method 500 may proceed to operation 530 . In operation 530 , a first dielectric layer 105 is formed over the second dielectric layer 107 , and a bonding structure 101 and a plurality of dummy bonding structures 102 - 1 , 102 - 2 , 102 - 3 , 102 - 4 are formed in the first dielectric layer 105 .

[0088] In one example, a bonding hole and a dummy bonding hole may be formed in the first dielectric layer 105, a diffusion barrier layer may be formed on the sidewalls and bottom of the bonding hole and the dummy bonding hole, and then a metal may be deposited in the bonding hole and the dummy bonding hole by a deposition process to fill the remaining space of the bonding hole and the dummy bonding hole, thereby forming the bonding structure 101 and the plurality of dummy bonding structures 102-1, 102-2, 102-3, 102-4. The deposition process may include, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof.

[0089] In order to couple the bonding structure 101 with the second connection portion 106, the extending depth of the bonding hole in the first dielectric layer 105 is greater than the extending depth of the dummy bonding hole in the first dielectric layer 105, so that the extending depth of the bonding structure 101 in the first dielectric layer 105 is greater than the extending depth of the dummy bonding structure in the first dielectric layer 105, as shown in FIG. Figure 1 shown.

[0090] After operation 530, the method 500 may proceed to operation 540. In operation 540, a first connection portion 103 is formed in the first dielectric layer 105. The first connection portion 103 couples the bonding structure 101 with the two adjacent dummy bonding structures 102-1 and 102-2, so that the bonding structure 101 and the two adjacent dummy bonding structures 102-1 and 102-2 have the same potential, thereby reducing or eliminating the protrusion of the bonding structure 101.

[0091] Figure 6 A flowchart of a method of manufacturing a semiconductor device according to a second example of the present disclosure is schematically shown.

[0092] The following will refer to Figure 6 Combined with Figure 2 A flowchart of a method 600 of manufacturing a semiconductor device according to a second example of the present disclosure is described.

[0093] The method 600 may include operation 610 . In operation 610 , a semiconductor substrate 209 is provided, and a doped region 208 is formed by performing an ion implantation process in the semiconductor substrate 209 .

[0094] After operation 610, the method 600 may proceed to operation 620. In operation 620, a second dielectric layer 207 is formed over the semiconductor substrate 209, and a second connection portion 206 is formed in the second dielectric layer 207. In one example, a through hole may be formed in the second dielectric layer 207, and a metal may be deposited in the through hole by a deposition process to form the second connection portion 206. The deposition process may include, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof.

[0095] After operation 620 , the method 600 may proceed to operation 630 . In operation 630 , a first connection portion 203 is formed in the second dielectric layer 207 .

[0096] After operation 630 , the method 600 may proceed to operation 640 . In operation 640 , a first dielectric layer 205 is formed over the second dielectric layer 207 , and a bonding structure 201 and a plurality of dummy bonding structures 202 - 1 , 202 - 2 , 202 - 3 , 202 - 4 are formed in the first dielectric layer 205 .

[0097] In one example, a bonding hole and a dummy bonding hole may be formed in the first dielectric layer 205, a diffusion barrier layer may be formed on the sidewalls and bottom of the bonding hole and the dummy bonding hole, and then a metal may be deposited in the bonding hole and the dummy bonding hole by a deposition process to fill the remaining space of the bonding hole and the dummy bonding hole, thereby forming the bonding structure 201 and the plurality of dummy bonding structures 202-1, 202-2, 202-3, 202-4. The deposition process may include, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof.

[0098] In order to couple the bonding structure 201 and the dummy bonding structures 202-1 and 202-2 to the first connection portion 203, the bonding structure 201 and the dummy bonding structures 202-1 and 202-2 may extend to a depth greater than the depth of the dummy bonding structures 202-3 and 202-4 extending to the first dielectric layer 105. Figure 2 shown.

[0099] By coupling the bonding structure 201 and the dummy bonding structures 202 - 1 and 202 - 2 together, the bonding structure 201 and the two adjacent dummy bonding structures 202 - 1 and 202 - 2 have the same potential, so that the protrusion of the bonding structure 201 can be reduced or eliminated.

[0100] Although Figure 1-2 The interconnection layer may include two dielectric layers, but the present disclosure is not limited thereto. That is, the interconnection layer may include three or more dielectric layers. For example, based on Figure 1 and Figure 2 With regard to the semiconductor device and the method for manufacturing the same shown, those skilled in the art can also conceive of a semiconductor device and a method for manufacturing the same in which the interconnect layer may include three or more dielectric layers.

[0101] Figure 7 A cross-sectional view schematically illustrates the structure of a semiconductor device 700 according to a third example of the present disclosure.

[0102] Figure 7 The semiconductor device 700 and Figure 2 The difference between the semiconductor devices 200 is that: Figure 7 The interconnect layer 210 in the semiconductor device 700 includes three dielectric layers. Figure 7 The semiconductor device 700 and Figure 2 The above-mentioned differences between the semiconductor device 200 and the semiconductor device 200 are described, and the components common to both are indicated by the same reference numerals.

[0103] like Figure 7 As shown, the interconnection layer 210 includes a first dielectric layer 205, a second dielectric layer 207, and a third dielectric layer 211, and the bonding structure 201 in the first dielectric layer 205 can be coupled to the doped region 208 via the first connection portion 203, the second connection portion 206, and the wiring layer 212 and the third connection portion 213 in the third dielectric layer 211. As can be understood by those skilled in the art, the combination of the second dielectric layer 207 and the third dielectric layer 211 can be regarded as one dielectric layer, and the combination of the second connection portion 206, the wiring layer 212, and the third connection portion 213 can be regarded as one connection portion.

[0104] To manufacture Figure 7 The semiconductor device 700 may form a third dielectric layer 211 on a semiconductor substrate 209 having a doped region 208, and then sequentially form a third connection portion 213 and a wiring layer 212 in the third dielectric layer 211, wherein the wiring layer 212 is configured to realize the connection between the third connection portion 213 in the third dielectric layer 211 and the dielectric layer thereon (for example, Figure 7The second dielectric layer 207 in the connecting portion (eg, Figure 7 Then, the coupling between the second connection part 206 in the embodiment can be performed. Figure 6 Operations 620-640 are performed to obtain Figure 7 A semiconductor device 700 is shown.

[0105] Figure 8 A memory system according to one example of the present disclosure is schematically shown.

[0106] like Figure 8 As shown, the memory system 800 may include a memory controller 800-1 and a memory device 800-2, wherein the memory controller 800-1 may be coupled to the memory device 800-2 and may be configured to control the operation of the memory device 800-2. The memory device 800-2 may include any semiconductor device in the above examples, such as Figure 1 , Figure 2 or Figure 7 The semiconductor device shown.

[0107] The present disclosure is not limited to the above disclosed examples, and other examples that can be derived from them by those skilled in the art are also within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be defined by the attached claims.

Claims

1. A semiconductor device, comprising: an interconnection layer, the interconnection layer comprising a bonding structure, a plurality of dummy bonding structures, and a first connection portion, At least one dummy bonding structure among the plurality of dummy bonding structures is coupled to the bonding structure through the first connecting portion.

2. The semiconductor device according to claim 1, wherein The interconnect layer further includes a first dielectric layer, the bonding structure and the plurality of dummy bonding structures extending from a first side of the first dielectric layer toward a second side of the first dielectric layer in the first dielectric layer, and the first side is opposite to the second side.

3. The semiconductor device according to claim 2, wherein: The first connection portion is located on the first side of the first dielectric layer.

4. The semiconductor device according to claim 2, wherein: The first connecting portion is located on the second side of the first dielectric layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The interconnect layer further includes a second dielectric layer and a second connection portion extending through the second dielectric layer, wherein the second connection portion is coupled to the bonding structure.

6. The semiconductor device according to claim 2, wherein: The bonding structure is located in a bonding hole in the first dielectric layer, and a dimension of the bonding hole at the first side is larger than a dimension of the bonding hole at the second side. 7 . The semiconductor device according to claim 5 , further comprising a substrate, the substrate comprising a doped region, and the doped region is coupled to the second connection portion.

8. The semiconductor device according to claim 7, wherein: The first connection portion, the bonding structure, and the at least one dummy bonding structure are coupled to the doped region through the second connection portion.

9. The semiconductor device according to any one of claims 1 to 4 and 6 to 8, wherein: The bonding structure and the plurality of dummy bonding structures each include a recessed portion.

10. The semiconductor device according to any one of claims 1 to 4 and 6 to 8, wherein: The bonding structure, the plurality of dummy bonding structures, and the first connection portion include a same metal.

11. The semiconductor device according to claim 10, wherein: A diffusion barrier layer is provided between the bonding structure and each of the plurality of dummy bonding structures and the first dielectric layer.

12. The semiconductor device according to claim 7, wherein: The doped region includes a source or drain region of a transistor.

13. A memory device comprising: a first semiconductor device; as well as a second semiconductor device bonded to the first semiconductor device, Wherein, at least one semiconductor device among the first semiconductor device and the second semiconductor device comprises: an interconnection layer, the interconnection layer comprising a bonding structure, a plurality of dummy bonding structures, and a first connection portion, At least one dummy bonding structure among the plurality of dummy bonding structures is coupled to the bonding structure through the first connecting portion.

14. The memory device according to claim 13, wherein: The interconnect layer further includes a first dielectric layer, the bonding structure and the plurality of dummy bonding structures extending from a first side of the first dielectric layer toward a second side of the first dielectric layer in the first dielectric layer, and the first side is opposite to the second side.

15. The memory device of claim 14, wherein: The first connection portion is located on the first side of the first dielectric layer.

16. The memory device of claim 14, wherein: The first connecting portion is located on the second side of the first dielectric layer.

17. The memory device according to any one of claims 13 to 16, wherein: The interconnect layer further includes a second dielectric layer and a second connection portion extending through the second dielectric layer, wherein the second connection portion is coupled to the bonding structure.

18. The memory device of claim 14, wherein: The bonding structure is located in a bonding hole in the first dielectric layer, and a dimension of the bonding hole at the first side is larger than a dimension of the bonding hole at the second side.

19. The memory device of claim 17, wherein: The at least one semiconductor device of the first semiconductor device and the second semiconductor device further includes a substrate, the substrate includes a doped region, and the doped region is coupled to the second connection portion.

20. The memory device of claim 19, wherein: The first connection portion, the bonding structure, and the at least one dummy bonding structure are coupled to the doped region through the second connection portion.

21. The memory device according to any one of claims 13 to 16 and 18 to 20, wherein: The bonding structure and the plurality of dummy bonding structures each include a recessed portion.

22. The memory device according to any one of claims 13 to 16 and 18 to 20, wherein: The bonding structure, the plurality of dummy bonding structures, and the first connection portion include a same metal.

23. The memory device of claim 22, wherein: A diffusion barrier layer is provided between the bonding structure and each of the plurality of dummy bonding structures and the first dielectric layer.

24. The memory device of claim 19, wherein: The doped region includes a source or drain region of a transistor.

25. A memory system comprising: A memory device according to any one of claims 13 to 24; as well as A memory controller is coupled to the memory device and is configured to control the operation of the memory device.

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