Bonding structure and stacked semiconductor device including same

Abstract

The invention relates to a bonding structure and a stacked semiconductor device including the same. The bonding structure may include a bonding surface in which a component may be integrated. The bonding surface may include a first bonding region, a second bonding region, and at least one bonding wire. The first bonding region may include a plurality of first bonding pads and a first bonding insulating layer. The first bond pads may be distributed at a first density. The first bonding insulating layer may be between the first bonding pads. The second bonding region may include a plurality of second bonding pads and a second bonding insulating layer. The second bond pads may be distributed at a second density less than the first density. The second bonding insulating layer may be between the second bonding pads. The bonding wiring may be exposed toward the bonding surface in the second bonding region. The bonding wire may receive a voltage from an external device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Korean Patent Application No. 10-2023-0080433, filed on June 22, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a bonding structure and a stacked semiconductor device including the same, and more particularly, to a bonding structure and a stacked semiconductor device including the same. Background Art

[0004] As the size of electronic devices decreases, the size of each die in a wafer is also decreasing. In addition, in order to provide electronic devices with large capacity, the dies are stacked to form a module.

[0005] To efficiently assemble small-sized dies, multiple wafers are directly bonded to each other through a hybrid bonding process.

[0006] Hybrid bonding can be either fusion bonding or direct bonding. In a hybrid bonding process, dies or wafers can be bonded directly to each other without an intermediate layer in between.

[0007] For example, when the first wafer and the second wafer may be hybrid-bonded to each other, the first bonding pad and the first bonding insulating layer of the first wafer and the second bonding pad and the second bonding insulating layer of the second wafer may be directly bonded to each other.

[0008] Depending on the type of components on the first wafer and the second wafer, the arrangement of the first bonding pad and the second bonding pad may be different from each other. In addition, depending on the type of components on the first wafer and the second wafer, the integration density of the bonding pads of the region of each wafer may also be different from each other. Summary of the invention

[0009] According to various embodiments of the present disclosure, a bonding structure may be provided. The bonding structure may include a bonding surface, in which components may be integrated. The bonding surface may include a first bonding area, a second bonding area, and at least one bonding wiring. The first bonding area may include a plurality of first bonding pads and a first bonding insulating layer. The first bonding pads may be distributed at a first density. The first bonding insulating layer may be located between the first bonding pads. The second bonding area may include a plurality of second bonding pads and a second bonding insulating layer. The second bonding pads may be distributed at a second density less than the first density. The second bonding insulating layer may be located between the second bonding pads. The bonding wiring may be arranged at the second bonding area. The bonding wiring may be configured to receive and transmit a voltage from an external device.

[0010] According to other embodiments of the present disclosure, a stacked semiconductor device may be provided. The stacked semiconductor device may include a first structure and a second structure. The first structure may include a first bonding region and a second bonding region. The first bonding region may include a plurality of first bonding pads and a first bonding insulating layer located between the first bonding pads. The second bonding region may include at least one second bonding pad, a second bonding insulating layer, and at least one first bonding wiring. The second bonding insulating layer may insulate the second bonding pad. The first bonding wiring may be located in the second bonding insulating layer. The second structure may include a third bonding region and a fourth bonding region. The third bonding region may include a plurality of third bonding pads and a third bonding insulating layer. The third bonding pad may be hybrid bonded with the first bonding pad. The third bonding insulating layer may be hybrid bonded with the first bonding insulating layer. The fourth bonding region may include at least one fourth bonding pad, a fourth bonding insulating layer, and at least one second bonding wiring. The fourth bonding pad may be hybrid bonded with the second bonding pad. The fourth bonding insulating layer may be hybrid bonded with at least one of the first bonding wirings. The second bonding wire may be hybrid-bonded with at least one of the first bonding wire and the second bonding insulating layer.

[0011] According to some other embodiments of the present disclosure, a stacked semiconductor device may be provided. The stacked semiconductor device may include a first die and a second die hybrid bonded with the first die. The first die may include a first bonding region, a second bonding region, and at least one bonding wiring. The first bonding region may include a plurality of bonding pads distributed at a first density. The second bonding region may have a first region and a second region. The bonding pads may be distributed in the first region at a second density less than the first density. The bonding pads may not be arranged in the second region. The first bonding wiring may be arranged in the second region. The first bonding wiring may be hybrid bonded with the second die to transmit electrical signals. The second die may include a third bonding region, a fourth bonding region, and at least one second bonding wiring. The third bonding region may include a plurality of bonding pads hybrid bonded with the bonding pads of the first die. The fourth bonding region may include a plurality of bonding pads arranged at a density less than the density of the bonding pads in the third region. The second bonding wiring may be arranged in a selected portion of the fourth bonding region. The second bonding wiring may be hybrid bonded with the second bonding region to transmit electrical signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a perspective view showing a stacked semiconductor device according to various embodiments of the present disclosure;

[0014] Figure 2is a plan view showing a first structure of a stacked semiconductor device according to other embodiments of the present disclosure;

[0015] Figure 3 is a plan view showing a second structure of a stacked semiconductor device according to still other embodiments of the present disclosure;

[0016] Figure 4 is a plan view showing a bonding surface of hybrid bonding of a first structure and a second structure according to still another embodiment of the present disclosure;

[0017] Figure 5 is along Figure 4 The cross-sectional view taken along the line x1-x1';

[0018] Fig. 6A and Figure 6B is a flow chart illustrating a hybrid bonding process according to various embodiments of the present disclosure;

[0019] Figure 7 is a plan view showing a first structure of a stacked semiconductor device according to other embodiments of the present disclosure;

[0020] Figure 8 is a plan view showing a second structure of a stacked semiconductor device according to still other embodiments of the present disclosure;

[0021] Fig. 9 is a plan view showing a bonding surface of hybrid bonding of a first structure and a second structure according to still another embodiment of the present disclosure;

[0022] Fig.10 is along Fig. 9 The cross-sectional view taken along the line x2-x2';

[0023] Fig.11 is a plan view showing a first die of a stacked semiconductor device according to another embodiment of the present disclosure;

[0024] Fig.12 is a plan view showing a second die of a stacked semiconductor device according to various embodiments of the present disclosure;

[0025] Fig.13 is a plan view showing a bonding surface of a hybrid bond of a first die and a second die according to other embodiments of the present disclosure; and

[0026] Fig.14 is along Fig.13 Cross-sectional view taken along the x3-x3' line. DETAILED DESCRIPTION

[0027] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic illustrations of various embodiments and intermediate structures. Therefore, due to, for example, manufacturing techniques and / or tolerances, variations in the configurations and shapes illustrated are to be expected. Therefore, the described embodiments should not be construed as limited to the specific configurations and shapes shown herein, but include deviations from the configurations and shapes described herein.

[0028] The present disclosure is described herein with reference to the cross-sectional illustrations and / or plan views of the embodiments of the present disclosure. However, the embodiments of the present disclosure should not be construed as limiting the present disclosure. Although some embodiments of the present disclosure will be shown and described, it will be understood by those of ordinary skill in the art that these embodiments may be changed without departing from the principles and scope of the present disclosure.

[0029] Figure 1 is a perspective view showing a stacked semiconductor device according to various embodiments of the present disclosure.

[0030] As described above, depending on the type of components on different wafers, the integration density of bonding pads on different wafers may be different from each other. When hybrid bonding connects two different wafers together, the difference between the integration density of bonding pads may cause bonding errors. The present disclosure is generated in this context.

[0031] Reference Figure 1 The stacked semiconductor device 100 may include at least two wafers, for example, first to nth wafers W1-Wn. Each of the wafers W1-Wn may include an upper surface W_F and a lower surface W_B.

[0032] For example, each of the wafers W1-Wn may include a plurality of dies 10. A plurality of circuit patterns may be integrated in each of the dies 10 on the upper surface W_F of the wafer to form an electronic component, for example, a memory component.

[0033] A plurality of bonding pads and a bonding insulating layer may be arranged on the upper surface W_F and the lower surface W_B of each of the wafers Wl~Wn. The bonding pads may be electrically connected to the circuit pattern.

[0034] For example, in order to directly bond the upper surface W_F of the lower wafer to the lower surface W_B of the upper wafer, the first wafer W1 to the nth wafer Wn may be stacked. Alternatively, in order to directly bond the upper surface W_F of the lower wafer to the upper surface W_F of the upper wafer or to directly bond the lower surface W_B of the lower wafer to the lower surface W_B of the upper wafer, the first wafer W1 to the nth wafer Wn may be stacked.

[0035] Hereinafter, the wafer bonding surface or bonding surface may correspond to the upper surface W_F or the lower surface W_B of the wafer, or the bonded surface of a different wafer or structure.

[0036] Figure 2 is a plan view showing a first structure of a stacked semiconductor device according to various embodiments of the present disclosure, Figure 3 is a plan view showing a second structure of a stacked semiconductor device according to another embodiment of the present disclosure, Figure 4 is a plan view showing a bonding surface of hybrid bonding of a first structure and a second structure according to still another embodiment of the present disclosure, Figure 5 is along Figure 4 The cross-sectional view taken along the line x1-x1' in Fig. 6A and Figure 6B is a flow chart illustrating a hybrid bonding process according to another embodiment of the present disclosure.

[0037] Reference Figures 2 to 6B , the stacked semiconductor device 100a may include a first structure 200 and a second structure 300 hybrid-bonded to the first structure 200. For example, the first structure 200 and the second structure 300 may be a wafer, a portion of a wafer, a bare die, etc. In addition, each of the first structure 200 and the second structure 300 may include at least one electronic component having a variety of circuit patterns. Each electronic component may include a plurality of conductive terminals.

[0038] like Figure 5 As shown, the first structure 200 may include a first bonding surface BS1 bonded to the second structure 300. The first bonding surface BS1 may include a first bonding area A1 and a second bonding area A2.

[0039] The first bonding area A1 may include a plurality of first bonding pads 210 and a first bonding insulating layer 220. The first bonding pads 210 may have a first density. The first bonding insulating layer 220 may be located between the first bonding pads 210. The first bonding pads 210 and the first bonding insulating layer 220 may be exposed at the first bonding surface BS1.

[0040] The second bonding region A2 may include a plurality of second bonding pads 230 and a second bonding insulating layer 240. The second bonding pads 230 may be exposed toward the first bonding surface BS1. The second bonding insulating layer 240 may be located between the second bonding pads 230. The second bonding pads 230 may have a second density lower than the first density of the first bonding pads 210.

[0041] The second bonding area A2 may further include at least one first bonding wire 250. The first bonding wire 250 may be positioned with the second bonding insulating layer 240 therebetween. Similar to the second bonding pad 230 and the second bonding insulating layer 240, the first bonding wire 250 may be exposed at the first bonding surface BS1.

[0042] In the depicted embodiment, the first bonding wire 250 may be arranged in a region of the second bonding area A2 where only the second bonding insulating layer 240 exists and the second bonding pad 230 is not arranged, for example, in the first dummy area DA1 .

[0043] Alternatively, the second bonding pad 230 may be disposed in a region of the second bonding area A2 having the first bonding wire 250 , for example, in the first dummy area DA1 .

[0044] The occupation ratio of the first bonding insulation layer 220 (based on the unit area SA1 of the first bonding region A1) may be similar to the occupation ratio of the second bonding insulation layer 240 (based on the unit area SA2 of the second bonding region A2) within the error range of the first bonding wiring 250. For example, the unit area SA1 of the first bonding region A1 and the unit area SA2 of the second bonding region A2 may be arbitrarily placed c. The unit area SA1 of the first bonding region A1 may be substantially the same as the unit area SA2 of the second bonding region A2.

[0045] In addition, the occupation ratio of the first bonding insulating layer 220 (based on the unit area SA1 of the first bonding region A1) and the occupation area of ​​the second bonding insulating layer 240 (based on the unit area SA2 of the second bonding region A2) can occupy, for example, about 50% to about 90% of the unit area. For example, when the bonding insulating layers 220 and 240 occupy at least 50% of the unit areas SA1 and SA2, mixed bonding errors can be prevented. The unit areas SA1 and SA2 and the percentages can be changed according to the design and process recipe.

[0046] For example, the first bonding wiring 250 may include a plurality of wirings. The first bonding wirings 250a to 250c may receive the same signal or different signals. The first bonding wirings 250a to 250c may transmit signals to conductive terminals of electronic components. In addition, the first bonding wirings 250a to 250c may have a variety of shapes and a variety of widths according to the shape of the first dummy area DA1 and according to the size of the received (and / or transmitted) voltage. For example, the first bonding wirings 250a and 250b may extend in the x-direction, and the first bonding wiring 250c may extend in the y-direction, but the present disclosure is not limited thereto.

[0047] The first bonding wirings 250a, 250b, and 250c may operate as one or more of a signal compensation line, a power compensation line, an address transmission line, a storage capacitor, etc., according to the received voltage. In addition, the width of the first bonding wirings 250a, 250b, and 250c may be changed according to the size of the received (and / or transmitted) voltage.

[0048] The first bonding pad 210, the second bonding pad 230 and the first bonding wiring 250 may include the same conductive material, such as, for example, at least one of Cu, W, Au, Ag and Al. The first bonding insulating layer 220 and the second bonding insulating layer 240 may include a dielectric material, such as, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon carbonitride layer and a silicon carbide layer. The first bonding insulating layer 220 and the second bonding insulating layer 240 may extend on the first bonding surface BS1 without being disconnected.

[0049] Reference Figure 3 , the second structure 300 may include a second bonding surface BS2 bonded to the first structure 200. The second bonding surface BS2 may include a third bonding area A3 and a fourth bonding area A4.

[0050] The third bonding area A3 may include a plurality of third bonding pads 310 and a third bonding insulating layer 320. The third bonding pads 310 may have a third density. The third bonding insulating layer 320 may be located between the third bonding pads 310. The third density may be substantially the same as the first density of the first bonding pads 210. The third bonding pads 310 and the third bonding insulating layer 320 may be exposed toward the second bonding surface BS2. For example, the third bonding pads 310 may correspond to the first bonding pads 210. Therefore, the third bonding area A3 may correspond to the bonding pad concentration area together with the first bonding area A1.

[0051] The fourth bonding area A4 may include a plurality of fourth bonding pads 330 and a fourth bonding insulating layer 340. The fourth bonding pads 330 may be exposed toward the second bonding plane BS2. The fourth bonding insulating layer 340 may be located between the fourth bonding pads 330. The fourth bonding pads 330 may have a fourth density lower than the third density of the bonding pads 310. For example, the fourth density may be substantially the same as the second density of the second bonding pads 230. The fourth bonding pads 330 may be arranged corresponding to the second bonding pads 230.

[0052] Therefore, the fourth bonding area A4 may include a second dummy area DA2 having a pattern density similar to that of the second bonding area A2. In various embodiments, at least one second bonding wiring 350 may be arranged in the second dummy area DA2 of the fourth bonding area A4. The second bonding wiring 350 may be arranged with a fourth bonding insulating layer 340 therebetween. The second bonding wiring 350 may be exposed toward the second bonding surface BS2.

[0053] In various embodiments, the second bonding wire 350 may be arranged in a region of the fourth bonding area A4 in which the fourth bonding pad 330 has a pattern layout forming, for example, the second dummy area DA2 .

[0054] Alternatively, the fourth bonding pad 330 may be arranged in a region of the fourth bonding area A4 in which the second bonding wiring 350 has a pattern layout forming, for example, the second dummy area DA2. For example, within the error range of the second bonding wiring 350, the occupation ratio of the third bonding insulating layer 320 (based on the unit area SA1 of the third bonding area A3) may be similar to the occupation area of ​​the fourth bonding insulating layer 340 (based on the unit area SA2 of the fourth bonding area A4).

[0055] In other embodiments, the second bonding wiring 350 may include a plurality of wirings. The second bonding wirings 350a, 350b, and 350c may extend in the x-direction or the y-direction. The second bonding wirings 350a, 350b, and 350c may be arranged corresponding to the first bonding wirings 250a, 250b, and 250c. For example, the second bonding wirings 350a, 350b, and 350c may have a width and length substantially the same as the width and length of the first bonding wirings 250a, 250b, and 250c.

[0056] The second bonding wires 350 a , 350 b , and 350 c may operate as one or more of a signal compensation line, a power compensation line, an address transmission line, a storage capacitor, etc. of electronic components integrated in the second structure 300 .

[0057] The third bonding pad 310, the fourth bonding pad 330, and the second bonding wiring 350 may include a material substantially the same as that of the first bonding pad 210, the second bonding pad 230, and the first bonding wiring 250, for example, at least one of Cu, W, Au, Ag, and Al. The third bonding insulating layer 320 and the fourth bonding insulating layer 340 may include a dielectric material substantially the same as that of the first bonding insulating layer 220 and the second bonding insulating layer 240, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon carbonitride layer, and a silicon carbide layer. The third bonding insulating layer 320 and the fourth bonding insulating layer 340 may extend on the second bonding surface BS2 without being disconnected.

[0058] exist Figure 5 In the disclosed embodiment shown, the first structure 200 may further include a plurality of first interconnects 260. The first interconnects 260 may connect the conductive terminals of the electronic components in the first structure 200 with the first bonding pads 210, the second bonding pads 230, and the first bonding wires 250. In addition, the first structure 200 may further include a first insulating interlayer 270, which is configured to isolate the first interconnects 260 from each other.

[0059] Figure 5The second structure 300 shown may further include a plurality of second interconnects 360. The second interconnects 360 may connect the electronic components in the second structure 300 with the third bonding pad 310, the fourth bonding pad 330, and the second bonding wire 350. In addition, the second structure 300 may further include a second insulating interlayer 370, which is configured to isolate the second interconnects 360 from each other.

[0060] The first interconnect 260 and the second interconnect 360 may be at least one through silicon via (TSV) and at least one vertical wiring structure configured to transmit a voltage. The first interconnect 260 and the second interconnect 360 may include at least one insulating layer.

[0061] In addition, the first bonding wire 250 and the second bonding wire 350 may contact the first interconnect 260 and the second interconnect 360 to transmit a voltage to the corresponding electronic component. In addition, when the first bonding wire 250 is directly bonded to the second bonding wire 350, the electrical characteristics of the bonded electronic component may be compensated in both directions. Figure 2 , Figure 3 and Figure 4 ) may represent the contact of the interconnections 260 and 360 with the bonding wires 250 and 350. The bidirectional direction represents a direction having an angle difference of 180 degrees.

[0062] Reference Fig. 6A , in process S10 , the second structure 300 may be stacked on the first structure 200 .

[0063] The first structure 200 and the second structure 300 may be stacked so that the bonding surfaces BS1 and BS2 of the first structure 200 and the second structure 300 face each other. In addition, the first bonding area A1 of the first structure 200 may face the third bonding area A3 of the second structure 300. The second bonding area A2 of the first structure 200 may face the fourth bonding area A4 of the second structure 300.

[0064] like Figure 5 As shown, the first bonding pad 210 and the first bonding insulating layer 220 in the first bonding region A1 may face the third bonding pad 310 and the third bonding insulating layer 320 in the third bonding region A3. The second bonding pad 230 and the second bonding insulating layer 240 in the second bonding region A2 may face the fourth bonding pad 330 and the fourth bonding insulating layer 340 in the fourth bonding region A4. In process S20, the stacked first structure 200 and the second structure 300 may be hybrid-bonded to each other.

[0065] In the hybrid bonding process, the insulating material of the first structure 200 can be directly bonded to the insulating material of the second structure 300 (without intermediate materials different from the insulating material). The conductive material of the first structure 200 can be directly bonded to the conductive material of the second structure 300 (without intermediate materials different from the conductive material).

[0066] Specifically, Figure 6B As shown, in process S21 , the bonding insulation layers 220 and 240 of the first structure 200 may be directly bonded to the bonding insulation layers 320 and 340 of the second structure 300 (without intermediate materials other than the bonding insulation layers).

[0067] The first bonding insulating layer 220 and the second bonding insulating layer 240 corresponding to the dielectric layer of the first structure 200 may be directly bonded to the third bonding insulating layer 320 and the fourth bonding insulating layer 340 corresponding to the dielectric layer of the second structure 300 (without intermediate materials different from the dielectric layer and the bonding insulating layer). For example, plasma may be used to treat the surfaces of the first bonding insulating layer 220 and the second bonding insulating layer 240 of the first structure 200 and the surfaces of the third bonding insulating layer 320 and the fourth bonding insulating layer 340. Pressure may be applied to the first structure 200 and the second structure 300 to directly bond the first bonding insulating layer 220 and the second bonding insulating layer 240 to the third bonding insulating layer 320 and the fourth bonding insulating layer 340.

[0068] In another embodiment, the bonding region between the first bonding insulation layer 220 and the third bonding insulation layer 320 may be similar to the bonding region between the second bonding insulation layer 240 and the fourth bonding insulation layer 340 through the first bonding wire 250 and the second bonding wire 350. Therefore, the first structure 200 and the second structure 300 may be directly bonded to each other in a dielectric-to-dielectric bonding manner through uniform bonding conditions at any position across the bonding region. In the present embodiment, the bonding conditions may include both plasma and pressure, but the present disclosure is not limited thereto.

[0069] In process S22 , the bonding pads 210 and 230 and the first bonding wire 250 of the first structure 200 may be directly bonded to the bonding pads 310 and 320 and the second bonding wire 350 of the second structure 300 (without intermediate materials other than the bonding pads and the bonding wires).

[0070] Specifically, the first bonding pad 210, the second bonding pad 230, the first bonding wire 250, the third bonding pad 310, the fourth bonding pad 330 and the second bonding wire 350 corresponding to the conductive layers of the first structure 200 and the second structure 300 may be thermally bonded to each other during the temperature heating process.

[0071] The conductive layers of the first structure 200 and the second structure 300 may be thermally expanded to form conductive layer-to-conductive layer bonding of the first structure 200 and the second structure 300 .

[0072] exist Figure 4 , B1 is the bonding surface between the first bonding pad 210 and the third bonding pad 310. B2 is the bonding surface between the first bonding insulating layer 220 and the third bonding insulating layer 320. B3 is the bonding surface between the second bonding pad 230 and the fourth bonding pad 330. B4 is the bonding surface between the second bonding insulating layer 240 and the fourth bonding insulating layer 340. B5 is the bonding surface between the first bonding wiring 250 and the second bonding wiring 350. BS is the surface to be bonded between the first bonding surface BS1 and the second bonding surface BS2.

[0073] In another embodiment, the first bonding wire 250 and the second bonding wire 350 can be arranged in the dummy area of ​​each structure to ensure bonding uniformity. In addition, the first bonding wire 250 and the second bonding wire 350 can continuously receive a voltage to provide a voltage as a signal, address or power to the electronic component. The first bonding wire 250 and the second bonding wire 350 can operate as a storage capacitor to improve the operating characteristics of the electronic component. Therefore, the electronic components in the first structure 200 and the second structure 300 can have improved electrical characteristics.

[0074] Other embodiments may provide bonding wires having the same shape in each of the dummy areas DA1 and DA2. Alternatively, the bonding wires 250 and 350 may be selectively bonded through the bonding structures 250b and 350b.

[0075] Figure 7 is a plan view showing a first structure of a stacked semiconductor device according to various embodiments of the present disclosure, Figure 8 is a plan view showing a second structure of a stacked semiconductor device according to another embodiment of the present disclosure, Fig. 9 is a plan view showing a bonding surface of hybrid bonding of a first structure and a second structure according to another embodiment of the present disclosure. Fig.10 is along Fig. 9 Cross-sectional view taken along the x2-x2' line.

[0076] Reference Figures 7 to 10 , the stacked semiconductor device 100 b may include a first structure 200 a and a second structure 300 a .

[0077] The first structure 200a may include a first bonding region A1a and a second bonding region A2a.

[0078] The first bonding region A1a may include a plurality of first bonding pads 210 and a first bonding insulating layer 220. The first bonding pads 210 and the first bonding insulating layer 220 may be connected to Figure 2 The first bonding pad 210 and the first bonding insulating layer 220 in FIG. 2 are substantially the same.

[0079] The second bonding region A2a may include a plurality of second bonding pads 230, a second bonding insulating layer 240, and a first bonding wire 251. The second bonding pads 230 may be connected to the first bonding wire 251. Figure 2 The second bonding pad 230 in is basically the same.

[0080] In the disclosed embodiment, the first bonding wire 251 may include a plurality of bonding wires 250a and 250c. For example, the number of the first bonding wires 251 may be less than Figure 2 The number of first bonding wires 250 in FIG.

[0081] like Figure 8 As shown, the second bonding structure 300a may include a third bonding region A3a and a fourth bonding region A4a. The third bonding region A3a may include a plurality of third bonding pads 310 and a third bonding insulating layer 320. The third bonding pads 310 may correspond to the first bonding pads 210 in the first bonding region A1a. The third bonding insulating layer 320 may correspond to the first bonding insulating layer 220.

[0082] The fourth bonding region A4 a may include a plurality of fourth bonding pads 330 , a fourth bonding insulating layer 340 , and a second bonding wire 351 .

[0083] In this embodiment, the fourth bonding pads 330 may have substantially the same arrangement as that of the second bonding pads 230 .

[0084] The second bonding wire 351 may include a plurality of bonding wires 350b and 350c. The number of the second bonding wires 351 may be less than Figure 3 The number of second bonding wires 350 in .

[0085] Therefore, the second bonding wire 351 may include a portion 350c corresponding to the first bonding wire 251 and a portion 350b not corresponding to the first bonding wire 251. Similarly, the first bonding wire 251 may include a portion 250c corresponding to the second bonding wire 351 and a portion 250a not corresponding to the second bonding wire 351.

[0086] like Fig. 9 and Fig.10As shown in the illustrated embodiment, when the first structure 200a is hybrid bonded to the second structure 300a, conductive layer-to-conductive layer bonding (B1, B3, and B5) is formed between the first bonding pad 210 and the third bonding pad 310, between the second bonding pad 230 and the fourth bonding pad 330, and between at least one of the first bonding wires 250c and at least one of the second bonding wires. In addition, dielectric layer-to-dielectric layer bonding (B2 and B4) may be formed between the first bonding insulating layer 220 and the third bonding insulating layer 320, and between the second bonding insulating layer 240 and the fourth bonding insulating layer 340.

[0087] The bonding surface BS between the second bonding area A2a of the first structure 200a and the fourth bonding area A4a of the second structure 300a may further include a conductive layer and a dielectric layer (B51) formed between the first bonding wire 250a and the fourth bonding insulating layer 340 and between the second bonding wire 350b and the second bonding insulating layer 240.

[0088] As described above, the number of the first bonding wires 251 of the first structure 200a may be less than Figure 2 Therefore, an occupation ratio of the first bonding insulating layer 220 per unit area SA11 at the first bonding region A1a may be different from an occupation ratio of the second bonding insulating layer 240 per unit area SA12 at the second bonding region A2a.

[0089] Similarly, the number of the second bonding wires 351 of the second structure 300a may be less than Figure 3 Therefore, an occupation ratio of the third bonding insulating layer 320 per unit area SA11 of the third bonding region A3a may be different from an occupation ratio of the fourth bonding insulating layer 340 per unit area SA12 of the fourth bonding region A4a.

[0090] However, when the hybrid-bonded first structure 200a and second structure 300a are observed from the side of the first structure 200a and the second structure 300a, the bonding area B51 between the second bonding wiring 350b and the second bonding insulating layer 240 and the bonding area B51 between the first bonding wiring 250a and the fourth bonding insulating layer 340 may be excluded from the bonding area B4 between the second bonding insulating layer 240 and the fourth bonding insulating layer 340.

[0091] Therefore, the area B2 occupied by the first bonding insulation layer 220 and the third bonding insulation layer 320 in the first bonding area A1a and the third bonding area A3a, and the area B4 occupied by the second bonding insulation layer 240 and the fourth bonding insulation layer 340 in the second bonding area A2a and the fourth bonding area A4a can be uniform within the specified range through the first bonding wiring 251 and the second bonding wiring 351.

[0092] That is, the occupied area of ​​the bonding insulating layer in the stacked semiconductor devices 100 and 100a per unit area SA11 and SA12 can correspond to the area bonding of the dielectric layer to the area bonding of the dielectric layer. In addition, when the ratio of the dielectric layer to the dielectric layer bonding B2 and B4 per unit area SA11 and SA12 at any position of the bonding surface BS can be uniform and not less than the specified range, it can be determined that the bonding is normal.

[0093] also, Figure 5 and Fig.10 The interconnections 260h and 360h indicated by dotted lines in FIG. 8 may be covered by insulating interlayers 270 and 370.

[0094] In another embodiment, the bonding wires 251 and 351 may be selectively formed in the dummy areas DA1 and DA2 of the bonding structure, but the present disclosure is not limited thereto.

[0095] Fig.11 is a plan view showing a first die of a stacked semiconductor device according to various embodiments of the present disclosure, Fig.12 is a plan view showing a second die of a stacked semiconductor device according to other embodiments of the present disclosure, Fig.13 is a plan view showing a bonding surface of a hybrid bond of a first die and a second die according to another embodiment of the present disclosure, and Fig.14 is along Fig.13 Cross-sectional view taken along the x3-x3' line.

[0096] refer to Figures 11 to 14 , the stacked semiconductor device 100 c may include a first die 400 and a second die 500 .

[0097] The first die 400 may be a part of the first wafer. Alternatively, the first die 400 may be separated from the first wafer.

[0098] The first die 400 may include a first component DE1 and a first bonding structure 200 b .

[0099] For example, Fig.14As shown, the first component DE1 may include at least one cell array area CA1 and at least one peripheral circuit area. The cell array area CA1 may include a plurality of densely arranged memory cells. The peripheral circuit area may include a driving circuit and a logic circuit configured to operate the memory cells. The peripheral circuit area may have an integration density lower than that of the cell array area CA1. In other embodiments, the peripheral circuit area may include first to fourth sub-peripheral areas peri1, peri2, peri3 and peri4. The first sub-peripheral area peri1 and the second sub-peripheral area peri2 may be located on both sides of the cell array area CA1. The third sub-peripheral area peri3 and the fourth sub-peripheral area peri4 may be located in the cell array area CA1. The third sub-peripheral area peri3 and the fourth sub-peripheral area peri4 may have a relatively low pattern density in the cell array area CA1. Fig.14 In the embodiment, the cell array region CA1 may be substantially coplanar with the first to fourth sub-peripheral regions peri1, peri2, peri3, and peri4, but the present disclosure is not limited thereto. Alternatively, in the peripheral lower cell structure, at least one of the first to fourth sub-peripheral regions peri1, peri2, peri3, and peri4 may be located between the cell array region CA1 and the first bonding structure 200b.

[0100] The first bonding structure 200 b may include a first bonding region A10 and a second bonding region A20 .

[0101] The first bonding area A10 may include a plurality of first bonding pads 410 and a first bonding insulating layer 415 configured to isolate the first bonding pads 410 from each other. The first bonding pads 410 may be densely arranged to provide signals, addresses and / or power to the cell array area CA1 of the first component DE1. Therefore, the first bonding pads 410 having a set density may be arranged in the first bonding area A10. In another embodiment, the first bonding area A10 may correspond to the cell array area CA1.

[0102] The second bonding area A20 may include an area in which bonding pads may be arranged at a density lower than a set density. In further embodiments, the bonding pads in the second bonding area A20 may be second bonding pads 420 .

[0103] In one embodiment, the second bonding area A20 may include first to fourth sub-bonding areas A21, A22, A23, and A24 corresponding to the first to fourth sub-peripheral areas peri1, peri2, peri3, and peri4. For example, the first sub-bonding area A21 and the second sub-bonding area A22 may be located at one side of the first bonding area A10. The third sub-bonding area A23 and the fourth sub-bonding area A24 may be located in the first bonding area A10.

[0104] For example, the area of ​​the third sub-bonding area A23 and the fourth sub-bonding area A24 may be smaller than the area of ​​the first sub-bonding area A21 and the second sub-bonding area A22. In addition, the first to fourth sub-bonding areas A21, A22, A23, and A24 may correspond to the first to fourth sub-peripheral areas peri1, peri2, peri3, and peri4 having a relatively high pattern density. Therefore, the second bonding pad 420 having a density lower than the set density may be arranged in at least one of the first to fourth sub-bonding areas A21, A22, A23, and A24. For example, the second bonding pad 420 may not be arranged in at least one of the first to fourth sub-bonding areas A21, A22, A23, and A24.

[0105] The second bonding region A20 , for example, first to fourth sub-bonding regions A21 , A22 , A23 , and A24 , may include a second bonding pad 420 , at least one of the first bonding wires 430 , and a second bonding insulating layer 425 .

[0106] The second bonding pads 420 may be arranged in at least one of the first to fourth sub-bonding regions A21, A22, A23, and A24. In this case, the second bonding pads 420 may have a density not greater than a set density. For example, the spacing between the second bonding pads 420 may be greater than the spacing between the first bonding pads 410.

[0107] The first bonding wire 430 may include a plurality of first bonding wires 430a and 430b having various widths. For example, the widths of the first bonding wires 430a and 430b may be determined according to the areas of the first to fourth sub-bonding regions A21, A22, A23, and A24. Fig.11 In the illustrated embodiment, the first and second sub-bonding regions A21 and A22 having relatively large areas may include at least one of a first bonding wire 430 a having a relatively wide width w1 and a first bonding wire 430 b having a relatively narrow width w2 .

[0108] The third and fourth sub-bonding regions A23 and A24 having relatively small areas may include at least one of the first bonding wires 430 b having a relatively narrow width w2 .

[0109] The first bonding wire 430a having a relatively wide width w1 may be used for a power transmission wire or a storage capacitor. The first bonding wire 430b having a relatively narrow width w2 may transmit a signal or an address to the first component DE1.

[0110] That is, considering the shapes and numbers of the first to fourth sub-bonding areas A21, A22, A23, and A24, the first bonding wires 430a and 430b having various widths, various extension directions, and various numbers may be integrated in the first to fourth sub-bonding areas A21, A22, A23, and A24. For example, the first bonding wire 430a may be integrated in a selected portion of the first sub-bonding area A21 along the y direction. The first bonding wires 430a and 430b extending in the y direction may be arranged with a gap spaced apart from each other in a selected portion of the second sub-bonding area A22. The first bonding wires 430b extending in the x direction may be arranged with a gap spaced apart from each other in the third sub-bonding area A23. The first bonding wire 430b extending in the x direction may be arranged in a selected portion of the fourth sub-bonding area A24.

[0111] Furthermore, the first bonding pad 410 and the first bonding insulating layer 415 in the first bonding region A10 and the second bonding pad 420 , the second bonding insulating layer 425 and the first bonding wires 430 a and 430 b in the second bonding region A20 may be exposed toward the first bonding surface BS11 of the first bonding structure 200 b .

[0112] The second die 500 may be a part of the second wafer. Alternatively, the second die 500 may be separated from the second wafer.

[0113] The second die 500 may include a second component DE2 and a second bonding structure 300 b .

[0114] For example, Fig.14 As shown, the second part DE2 may include at least one cell array region CA2 and at least one peripheral circuit region. The peripheral circuit region may include fifth to eighth sub-peripheral regions peri5, peri6, peri7, and peri8. The fifth to eighth sub-peripheral regions peri5, peri6, peri7, and peri8 may correspond to the first to fourth sub-peripheral regions peri1, peri2, peri3, and peri4, respectively.

[0115] The second bonding structure 300b may include a third bonding region A30 and a fourth bonding region A40. The third bonding region A30 may correspond to the cell array region CA2 and the first bonding region A10 of the second part DE2. The fourth bonding region A40 may correspond to the fifth to eighth sub-peripheral regions peri5, peri6, peri7, and peri8 of the second part DE2 and the second bonding region A20.

[0116] The third bonding region A30 may include a plurality of third bonding pads 510 and a third bonding insulating layer 515 configured to isolate the third bonding pads 510 from each other. The third bonding pads 510 may correspond to the first bonding pads 410.

[0117] In various embodiments, the fourth bonding area A40 may include fifth to eighth sub-bonding areas A41, A42, A43 and A44. The fifth to eighth sub-bonding areas A41, A42, A43 and A44 may face the fifth to eighth sub-peripheral areas peri5, peri6, peri7 and peri8 and the first to fourth sub-bonding areas A21, A22, A23 and A24 of the first bonding structure 200b. The fifth sub-bonding area A41 and the sixth sub-bonding area A42 may be located on one side of the third bonding area A30. The seventh sub-bonding area A43 and the eighth sub-bonding area A44 may be located in the dummy area of ​​the third bonding area A30. For example, the area of ​​the seventh sub-bonding area A43 and the eighth sub-bonding area A44 may be smaller than the area of ​​the fifth sub-bonding area A41 and the sixth sub-bonding area A42.

[0118] When the fourth bonding pads 520 may be arranged in at least one of the fifth to eighth sub-bonding regions A41, A42, A43, and A44, the fourth bonding pads 520 may have a density lower than a set density. The fourth bonding pads 520 may or may not correspond to the second bonding pads 420 of the first die 400.

[0119] Considering the shapes and numbers of the fifth to eighth sub-bonding regions A41, A42, A43, and A44, the second bonding wires 530 having various widths, various lengths, various extension directions, and various numbers may be arranged in the fifth to eighth sub-bonding regions A41, A42, A43, and A44. The second bonding wires 530 may include a second bonding wire 530a having a relatively wide width w1 and a second bonding wire 530b having a relatively narrow width w2, but the present disclosure is not limited thereto. The second bonding wire 530a having a relatively wide width w1 and the second bonding wire 530b having a relatively narrow width w2 may all be integrated in at least one of the fifth to eighth sub-bonding regions A41, A42, A43, and A44, or may be selectively integrated in the fifth to eighth sub-bonding regions A41, A42, A43, and A44. The second bonding wires 530a and 530b may extend in the same direction or in different directions. The second bonding wires 530 a and 530 b may be arranged at positions corresponding to the first bonding wires 430 a and 430 b. Alternatively, the second bonding wires 530 a and 530 b may correspond to the second bonding insulating layer 425 of the first die 400 .

[0120] In one embodiment, similar to the first bonding wires 430a and 430b, the second bonding wires 530a and 530b may be used for remaining conductive wiring to provide the second component DE2 with power, electrical signals, and addresses from the first component 400 or an external device.

[0121] For example, the second bonding wire 530a extending in the y direction may be integrated in a selected portion of the fifth sub-bonding region A41. The second bonding wires 430a and 430b extending in the y direction may be arranged to be spaced apart from each other by a gap in a selected portion of the sixth sub-bonding region A42. The second bonding wire 430b may not be arranged in the seventh sub-bonding region A43. The second bonding wire 530b extending in the x direction may be arranged in a selected portion of the eighth sub-bonding region A44.

[0122] Furthermore, the third bonding pad 510 and the third bonding insulating layer 515 in the third bonding region A30, and the fourth bonding pad 520, the fourth bonding insulating layer 525 and the first bonding wires 430a and 430b in the fourth bonding region A40 may be exposed toward the second bonding surface BS12 of the second bonding structure 300b.

[0123] like Fig.13 and Fig.14 As shown, the first die 400 and the second die 500 may be stacked such that the first bonding surface BS11 and the second bonding surface BS12 face each other. Then, the first die 400 and the second die 500 may be hybrid-bonded to each other.

[0124] Bond B11 may be a conductive layer-to-conductive layer bonding between the first bonding pad 410 and the third bonding pad 510. Bond B12 may be a dielectric layer-to-dielectric layer bonding between the first bonding insulating layer 415 and the third bonding insulating layer 515. Bond B13 may be a conductive layer-to-conductive layer bonding between the second bonding pad 420 and the fourth bonding pad 520. Bond B14 may be a dielectric layer-to-dielectric layer bonding between the second bonding insulating layer 425 and the fourth bonding insulating layer 525. Bond B15 may be a conductive layer-to-conductive layer bonding between the first bonding wire 430 and the second bonding wire 530. Bond B15a may be a conductive layer-to-dielectric layer bonding between the first bonding wire 430a or 430b and the fourth bonding insulating layer 525. The bonding B15 b may be a conductive layer-to-dielectric layer bonding between the second bonding wire 530 a or 530 b and the second bonding insulating layer 425 .

[0125] The first and second bonding wires 430a, 430b, 530a, and 530b may be electrically connected to conductive terminals of the first and second components DE1 and DE2 through the interconnections 460 and 560, and the first and second components DE1 and DE2 may be integrated in the corresponding die 400 or 500. Therefore, the first and second components DE1 and DE2 may receive electrical signals such as operating voltage, address, and power that may be provided from an external device through the bonding wires 430 and 530 and the bonding pads 410, 420, 510, and 520.

[0126] In addition, the bonding wires 430 and 530 may be used for a redistribution layer. For example, the first bonding wire 430 may be electrically connected to the first bonding pad 410. The first bonding wire 430 may be used as a part of a redistribution layer configured to transfer a voltage from the first bonding pad 410 to a conductive terminal of the first component DE1. In addition, the bonding wires 430 and 530 may operate as storage capacitors configured to stabilize power of the first component DE1 and the second component DE2.

[0127] The bonding wiring 430 and 530 can be formed in a dummy area such as the second bonding area and the fourth bonding area, wherein the bonding pads can be roughly arranged to replace the conventional dummy pads to which the electrical signal cannot be provided. Thus, the bonding wiring 430 and 530 can improve the electrical characteristics of the stacked semiconductor device. In addition, the bonding wiring 430 and 530 can replace the dummy pads to improve the bonding uniformity.

[0128] In another embodiment, the first bonding wiring 430 and the second bonding wiring 530 may extend in the x-direction or the y-direction, but the present disclosure is not limited thereto. The directions of the first bonding wiring 430 and the second bonding wiring 530 may be changed according to the size of the dummy area, the occupation ratio of the bonding insulating layer per unit area in the bonding surface BS10 (i.e., the bonding ratio between the dielectric layer and the dielectric layer), and the signal transmission path.

[0129] In addition, the interconnection may include TSV, but the present disclosure is not limited thereto. The interconnection may be changed according to a plurality of vertical plugs between multi-layer metal wirings and a plurality of multi-layer metal wirings.

[0130] According to various embodiments, at least one bonding wire can receive and send electrical signals to a dummy area where bonding pads can be roughly arranged. The signal transmitted by the bonding wire can improve the signal transmission characteristics and electrical characteristics of the stacked semiconductor device. In addition, because the bonding wire can be hybrid bonded to the bonding pad, the area occupied by the insulating layer on the bonding surface of the stacked semiconductor device can be controlled to improve the bonding uniformity of the stacked semiconductor device.

[0131] The above embodiments of the present disclosure are intended to explain the present disclosure and are not intended to limit the present disclosure. Various alternatives and equivalents are possible. The present disclosure is not limited by the embodiments described herein. The present disclosure is also not limited to any particular type of semiconductor device. In view of the present disclosure, other additions, reductions or modifications are obvious. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A bonding structure comprising a component and a bonding surface, The bonding surface includes a first bonding area, a second bonding area and at least one bonding wire, in, The first bonding region includes a plurality of first bonding pads and a first bonding insulating layer, the first bonding pads having a first density distributed in the first bonding region, and the first bonding insulating layer being located between the first bonding pads, wherein the second bonding region comprises a plurality of second bonding pads and a second bonding insulating layer, the second bonding pads having a second density less than the first density and distributed in the second bonding region, and the second bonding insulating layer being located between the second bonding pads, and The at least one bonding wire is arranged at the second bonding region, and the at least one bonding wire receives an external voltage and transmits the external voltage to the component. 2 . The bonding structure of claim 1 , further comprising a plurality of interconnects electrically connecting the first bonding pad, the second bonding pad, and the bonding wire with a conductive terminal of the component.

3. The bonding structure according to claim 1, wherein: The bonding wire is arranged in the second bonding region to maintain a percentage of the second bonding insulation layer per unit area of ​​the second bonding region within a specified range.

4. The bonding structure according to claim 3, wherein: The percentage of the first bonding insulation layer to the unit area of ​​the first bonding region is maintained within the specified range.

5. The bonding structure according to claim 4, wherein: The prescribed range is a range of an occupation ratio of the first bonding insulating layer or the second bonding insulating layer per unit area, and the prescribed range is 50% to 90%.

6. The bonding structure according to claim 1, wherein: The voltage supplied to the bonding wire includes a voltage supplied to the component corresponding to at least one of power, an operation signal, and an address.

7. The bonding structure according to claim 1, wherein: The second bonding region includes a dummy region where the second bonding pad is not arranged, and a shape and a number of the at least one bonding wire are determined based on a shape and a size of the dummy region.

8. A stacked semiconductor device, comprising: A first structure comprising a first bonding region and a second bonding region, the first bonding region comprising a plurality of first bonding pads and a first bonding insulation layer located between the first bonding pads, and the second bonding region comprising at least one second bonding pad, a second bonding insulation layer and at least one first bonding wire, the second bonding insulation layer insulating the second bonding pad, and the at least one first bonding wire located in the second bonding insulation layer; as well as The second structure includes a third bonding area and a fourth bonding area, the third bonding area includes a plurality of third bonding pads and a third bonding insulating layer, the plurality of third bonding pads are hybrid-bonded with the first bonding pads, and the third bonding insulating layer is hybrid-bonded with the first bonding insulating layer, The fourth bonding area includes a fourth bonding pad and a fourth bonding insulating layer, the fourth bonding pad is hybrid bonded with the second bonding pad, and the fourth bonding insulating layer is hybrid bonded with at least one of the second bonding insulating layer and the first bonding wiring. At least one second bonding wire is hybrid-bonded to at least one of the at least one first bonding wire and the second bonding insulation layer.

9. The stacked semiconductor device according to claim 8, wherein: An area ratio between the first bonding insulating layer and the third bonding insulating layer and an area ratio between the second bonding insulating layer and the fourth bonding insulating layer are within a prescribed range.

10. The stacked semiconductor device according to claim 9, wherein: The specified range is a range of an occupancy ratio between the first bonding insulating layer and the third bonding insulating layer or between the second bonding insulating layer and the fourth bonding insulating layer, and the occupancy ratio is based on a unit area on the bonding surface between the first structure and the second structure, and the specified range is 50% to 90% of the unit area.

11. The stacked semiconductor device according to claim 8, further comprising: a first component including a plurality of conductive terminals electrically connected to the first structure; as well as The second component includes a plurality of conductive terminals electrically connected to the second structure.

12. The stacked semiconductor device according to claim 11, wherein: The first structure includes a plurality of first interconnects connecting the first bonding pad, the second bonding pad, and the first bonding wire with the conductive terminal of the first component.

13. The stacked semiconductor device according to claim 12, wherein: The at least one first bonding wire receives a voltage corresponding to at least one of power, an operation signal, and an address, and the voltage is transmitted to the conductive terminal of the first component through the first interconnect.

14. The stacked semiconductor device according to claim 11, wherein: The second structure includes a plurality of second interconnects connecting the third bonding pad, the fourth bonding pad, and the second bonding wire with the conductive terminal of the second component.

15. The stacked semiconductor device according to claim 14, wherein: The second bonding wire receives a voltage corresponding to at least one of power, an operation signal, and an address, and the voltage is transmitted to the conductive terminal of the second component through the second interconnect.

16. The stacked semiconductor device according to claim 11, wherein: Each of the first component and the second component includes a cell array region and a peripheral circuit region, the second bonding region corresponds to the peripheral circuit region of the first component, and the fourth bonding region corresponds to the peripheral circuit region of the second component.

17. A stacked semiconductor device, comprising: a first die, and a second die hybrid-bonded to the first die, The first die includes a first bonding area, a second bonding area and at least one first bonding wire, wherein bonding pads having a first density are arranged in the first bonding area, wherein the second bonding region includes a first region and a second region, the bonding pads having a second density are arranged in the first region, and the bonding pads are not arranged in the second region, wherein the second density is less than the first density, and The at least one first bonding wire is arranged in the second region and hybrid-bonded to the second die, and the at least one first bonding wire receives and transmits an electrical signal.

18. The stacked semiconductor device according to claim 17, wherein: The second die includes a third bonding area, a fourth bonding area and at least one second bonding wire, The third bonding area includes a bonding pad, and the bonding pad is hybrid-bonded with the bonding pad in the first bonding area. wherein the fourth bonding region comprises bonding pads having a density lower than that of the bonding pads in the third bonding region, and The at least one second bonding wire is arranged in the fourth region and hybrid-bonded to the second bonding region, and the at least one second bonding wire receives and transmits the electrical signal.

19. The stacked semiconductor device according to claim 18, wherein: Each of the first to fourth bonding regions further includes a bonding insulation layer.

20. The stacked semiconductor device according to claim 19, wherein: The first bonding wire is hybrid-bonded to at least one of the at least one second bonding wire and the bonding insulating layer in the fourth bonding region, and the second bonding wire is hybrid-bonded to at least one of the at least one first bonding wire and the bonding insulating layer in the second bonding region.

Images