Power device

Abstract

The invention provides a power device, and the power device comprises a lining plate, the upper surface of the lining plate is provided with a first conductive layer, a second conductive layer and a third conductive layer which are arranged at intervals, and the second conductive layer is located between the first conductive layer and the third conductive layer; the chip assembly comprises a plurality of first chips and a plurality of second chips, the drain electrode of each first chip is electrically connected with the second conductive layer, and the drain electrode of each second chip is electrically connected with the third conductive layer; the first interconnection component is provided with a conductive connection part and a plurality of interconnection parts, the conductive connection part is electrically connected with the first conductive layer, and the plurality of interconnection parts are electrically connected with the source electrodes of the plurality of first chips in a one-to-one correspondence manner; and the second conductive layer is conductively connected with the source electrodes of the plurality of second chips through the second interconnection component. Through the technical scheme provided by the invention, the problem of poor junction temperature consistency of the chip of the power device in the related technology can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to a power device. Background Art

[0002] Power devices are devices used in the field of power electronics to control and convert electrical energy. They are used to perform power conversion functions such as rectification, inversion, chopping, and frequency conversion. They are widely used in power management, motor drive, solar inverter, power system, energy storage and other fields.

[0003] In the related art, a power device is provided with multiple bridge arms, each of which has multiple power chips connected in parallel and cooperates with corresponding power terminals to form a power circuit, and different bridge arms are alternately turned on to generate the required output voltage and current waveforms. For example, in a half-bridge inverter, when one bridge arm is turned on, the other bridge arm should be in the off state to prevent the current from flowing back directly from the power supply and causing a short circuit.

[0004] However, since each bridge arm has multiple chips, the chip layout in the power device is complex, the internal chips are often distributed more concentratedly, and the chip interconnection method is mostly bonding wire connection, which leads to the problem of poor consistency of chip junction temperature. Summary of the invention

[0005] The present invention provides a power device to solve the problem of poor chip junction temperature consistency of the power device in the related art.

[0006] The present invention provides a power device, which comprises: a liner, the upper surface of which is provided with a first conductive layer, a second conductive layer and a third conductive layer which are arranged at intervals, and the second conductive layer is located between the first conductive layer and the third conductive layer; a chip assembly, which comprises a plurality of first chips and a plurality of second chips, the drain of each first chip is conductively connected to the second conductive layer, and the drain of each second chip is conductively connected to the third conductive layer; a first interconnection component, which comprises a conductive connection portion and a plurality of interconnections, the conductive connection portion is electrically connected to the first conductive layer, and the plurality of interconnections are conductively connected to the source electrodes of the plurality of first chips in a one-to-one correspondence; and a second interconnection component, the second conductive layer is conductively connected to the source electrodes of the plurality of second chips via the second interconnection component.

[0007] Furthermore, the second conductive layer includes a first conductive area, a second conductive area, and an avoidance hollow area located between the first conductive area and the second conductive area, a plurality of first chips are located in the first conductive area, the second interconnection member is connected to the second conductive area, and a first gate conductive layer and a first auxiliary source conductive layer are also provided on the upper surface of the liner, the first gate conductive layer and the first auxiliary source conductive layer are located in the avoidance hollow area, the first gate conductive layer is connected to the gate of the first chip, and the first auxiliary source conductive layer is connected to the auxiliary source of the first chip.

[0008] Furthermore, the power device also includes multiple resistors, and a resistor conductive layer is also provided on the upper surface of the liner. There are multiple first gate conductive layers, and the multiple first gate conductive layers are respectively conductively connected to the gates of the multiple first chips one by one. The two pins of each resistor are respectively electrically connected to the resistor conductive layer and the corresponding first gate conductive layer.

[0009] Furthermore, the plurality of first chips are arranged along the length direction of the second conductive layer, and the length direction of the hollowed-out area is parallel to the length direction of the second conductive layer.

[0010] Furthermore, the width of the second conductive region is smaller than the width of the first conductive layer.

[0011] Furthermore, a second gate conductive layer and a second auxiliary source conductive layer are also provided on the upper surface of the liner, the second gate conductive layer is connected to the gate of the second chip, the second auxiliary source conductive layer is connected to the auxiliary source of the second chip, and the second gate conductive layer and the second auxiliary source conductive layer are both located on the side of the third conductive layer away from the second conductive layer.

[0012] Furthermore, the resistive conductive layer is located between the plurality of first gate conductive layers and the first auxiliary source conductive layer.

[0013] Furthermore, the first conductive layer and the third conductive layer together form a U-shaped structure, and the second conductive layer extends from an opening of the U-shaped structure into the U-shaped structure.

[0014] Furthermore, the first conductive layer includes a first interface connection layer and a first terminal connection layer connected to a first end of the first interface connection layer, the second conductive layer includes a second interface connection layer and a second terminal connection layer connected to the second interface connection layer, and the third conductive layer includes a third interface connection layer and a third terminal connection layer connected to a first end of the third interface connection layer; the first terminal connection layer, the second terminal connection layer and the third terminal connection layer extend along the width direction of the lining, the first interface connection layer, the second interface connection layer and the third interface connection layer extend along the length direction of the lining, the first terminal connection layer and the third terminal connection layer are arranged opposite to each other, the first interface connection layer, the first terminal connection layer, the third terminal connection layer and the third interface connection layer together form a U-shaped structure, the second interface connection layer is located between the first interface connection layer and the third interface connection layer, and the second terminal connection layer is located outside the U-shaped structure and at the second end of the first interface connection layer.

[0015] Further, the plurality of first chips are electrically connected to the second interface connection layer, the plurality of second chips are electrically connected to the third interface connection layer, the conductive connection portion is electrically connected to the first interface connection layer, and the second interconnection member is electrically connected to the second interface connection layer.

[0016] Furthermore, the power device also includes power terminals, which include a first power terminal, a second power terminal and a third power terminal, the first power terminal is connected to the first terminal connection layer, the second power terminal is connected to the second terminal connection layer, and the third power terminal is connected to the third terminal connection layer.

[0017] Further, the first conductive layer includes a first interconnect layer and a second interconnect layer that are connected and spaced apart, the first interconnect layer and the second interconnect layer are electrically connected to the source of the corresponding first chip respectively, the second conductive layer includes a first intermediate conductive layer and a second intermediate conductive layer that are connected and spaced apart, a plurality of first intermediate conductive layers and second intermediate conductive layers are electrically connected to the drain of the corresponding first chip respectively, the first intermediate conductive layer and the second intermediate conductive layer are electrically connected to the source of the corresponding second chip respectively, the third conductive layer includes a third interconnect layer and a fourth interconnect layer that are connected and spaced apart, the third interconnect layer and the fourth interconnect layer are electrically connected to the drain of the corresponding second chip respectively.

[0018] Furthermore, the liner includes a first liner and a second liner which are spaced apart from each other, the first interconnect layer, the first intermediate conductive layer and the third interconnect layer are arranged on the first liner, and the second interconnect layer, the second intermediate conductive layer and the fourth interconnect layer are arranged on the second liner.

[0019] Furthermore, the power device also includes a connecting board having a first connecting surface and a second connecting surface, the first connecting surface is electrically connected to the first interconnect layer or the first intermediate conductive layer or the third interconnect layer, and the second connecting surface is electrically connected to the second interconnect layer or the second intermediate conductive layer or the fourth interconnect layer.

[0020] Furthermore, the connecting plate includes a first flat plate, an arc-shaped plate and a second flat plate which are connected in sequence, the first connecting surface is the lower surface of the first flat plate, and the second connecting surface is the lower surface of the second flat plate.

[0021] Furthermore, the conductive connection part and the multiple interconnection parts are arranged at intervals along the first direction, and the first interconnection component includes a connecting block, the connecting block has a first dividing groove, the first dividing groove runs through the lower surface of the connecting block, the first dividing groove extends along the second direction and runs through two oppositely arranged side walls of the connecting block, and the conductive connection part and the multiple interconnection parts are respectively located on both sides of the first dividing groove.

[0022] Furthermore, the connecting block has a plurality of second dividing grooves, a plurality of interconnecting parts are arranged at intervals along the second direction, the second dividing grooves pass through the lower surface of the connecting block, a plurality of second dividing grooves are arranged at intervals along the second direction, each second dividing groove is located between two adjacent interconnecting parts, the second dividing grooves extend along the first direction, one end of each second dividing groove is connected to the first dividing groove, and the other end of each second dividing groove passes through the side wall of the connecting block, and there is an angle between the first direction and the second direction.

[0023] Further, the groove wall of the first dividing groove includes a first arc segment, and / or the groove wall of the second dividing groove includes a second arc segment.

[0024] Furthermore, the power device also includes a packaging shell, which includes a shell and a cover plate covered on the shell, the liner is arranged in the shell, and the chip assembly and the interconnection component are both located in the shell.

[0025] According to the technical solution of the present invention, the power device includes a liner, a chip assembly, a first interconnection member and a second interconnection member. The current flows through the second conductive layer, the drain of the first chip, the source of the first chip, the interconnection part of the first interconnection member, the conductive connection part of the first interconnection member, and the first conductive layer to form a first bridge arm commutation loop. The current flows through the third conductive layer, the drain of the second chip, the source of the second chip, the second interconnection member, and the second conductive layer to form a second bridge arm commutation loop. Since the sources of the plurality of first chips are electrically connected to the first conductive layer through the first interconnection member, the sources of the plurality of second chips are electrically connected to the second conductive layer through the second interconnection member, and the conductive connection part and the plurality of interconnection parts are arranged on the first interconnection member and form an integrated structure, the heat of the plurality of first chips can be conducted to the first conductive layer through the first interconnection member, and the heat of the plurality of first chips can be mutually conducted through the first interconnection member, so that the junction temperatures of the plurality of first chips are made consistent on the one hand, and the heat dissipation area of ​​the first chip can be increased by using the first conductive layer and the second conductive layer on the other hand, thereby reducing the thermal resistance of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0027] Figure 1 A schematic diagram of the structure of a power device provided in an embodiment of the present invention is shown;

[0028] Figure 2 Another schematic diagram of the structure of a power device provided according to an embodiment of the present invention is shown;

[0029] Figure 3 A top view of a power device provided according to an embodiment of the present invention is shown;

[0030] Figure 4 An assembly diagram of a first liner of a power device provided in an embodiment of the present invention is shown;

[0031] Figure 5 An assembly diagram of a second liner of a power device provided in an embodiment of the present invention is shown;

[0032] Figure 6A schematic diagram showing the structure of a connection board of a power device provided in an embodiment of the present invention is shown;

[0033] Figure 7 A schematic structural diagram of a first interconnection component of a power device provided in an embodiment of the present invention is shown;

[0034] Figure 8 Another schematic structural diagram of a first interconnection component of a power device provided according to an embodiment of the present invention is shown;

[0035] Fig. 9 A bottom view of a first interconnection member of a power device provided according to an embodiment of the present invention is shown;

[0036] Fig.10 A packaging diagram of a power device provided according to an embodiment of the present invention is shown;

[0037] Fig.11 A left side view of a first interconnection member of a power device provided in an embodiment of the present invention is shown;

[0038] Fig.12 A front view of a first interconnection member of a power device provided according to an embodiment of the present invention is shown;

[0039] Fig.13 Another left side view of the first interconnection member of the power device provided according to the embodiment of the present invention is shown;

[0040] Fig.14 Another front view of a first interconnection member of a power device according to an embodiment of the present invention is shown.

[0041] The above drawings include the following reference numerals:

[0042] 10. liner; 11. first conductive layer; 111. first interconnection layer; 112. second interconnection layer; 12. second conductive layer; 121. first conductive area; 122. second conductive area; 123. avoidance hollow area; 124. first intermediate conductive layer; 125. second intermediate conductive layer; 13. third conductive layer; 131. third interconnection layer; 132. fourth interconnection layer; 14. first gate conductive layer; 15. first auxiliary source conductive layer; 16. resistor conductive layer; 17. second gate conductive layer; 18. second auxiliary source conductive layer; 191. first liner; 192. second liner;

[0043] 20. chip assembly; 21. first chip; 22. second chip;

[0044] 30. first interconnection member; 31. conductive connection portion; 32. interconnection portion; 33. first separation groove; 331. first arc segment; 332. first straight segment; 333. second straight segment; 34. second separation groove; 341. second arc segment; 342. third straight segment; 343. fourth straight segment;

[0045] 40. a second interconnecting member;

[0046] 50. Resistance;

[0047] 60, power terminal; 61, first power terminal; 62, second power terminal; 63, third power terminal;

[0048] 70, connecting plate; 71, first flat plate; 72, curved plate; 73, second flat plate;

[0049] 80. packaging shell; 81. housing; 82. cover plate;

[0050] L1, the distance between the highest point of the first arc segment and the upper surface of the connecting block;

[0051] H1, the distance between the lower surface of the conductive connection portion of the connection block and the upper surface of the connection block;

[0052] h1, the vertical height of the first straight section; B1, the width of the first dividing groove; B2, the width of the connecting block;

[0053] L2, the distance between the highest point of the second arc segment and the upper surface of the connecting block;

[0054] H2, the height between the lower surface of the interconnection unit and the upper surface of the connection block;

[0055] h2, the vertical height of the third straight segment; B3, the width of the second dividing groove; B4, the width of the interconnected unit. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] like Figures 1 to 14As shown, an embodiment of the present invention provides a power device, which includes a substrate 10, a chip assembly 20, a first interconnection member 30, and a second interconnection member 40. The upper surface of the substrate 10 has a first conductive layer 11, a second conductive layer 12, and a third conductive layer 13 arranged at intervals, and the second conductive layer 12 is located between the first conductive layer 11 and the third conductive layer 13; the chip assembly 20 includes a plurality of first chips 21 and a plurality of second chips 22, the drain of each first chip 21 is conductively connected to the second conductive layer 12, and the drain of each second chip 22 is conductively connected to the third conductive layer 13; the first interconnection member 30 has a conductive connection portion 31 and a plurality of interconnection portions 32, the conductive connection portion 31 is electrically connected to the first conductive layer 11, and the plurality of interconnection portions 32 are conductively connected to the source electrodes of the plurality of first chips 21 in a one-to-one correspondence; the second conductive layer 12 is conductively connected to the source electrodes of the plurality of second chips 22 through the second interconnection member 40.

[0058] By applying the technical solution of the present invention, the power device includes a liner 10, a chip assembly 20, a first interconnection component 30 and a second interconnection component 40. The current flows through the second conductive layer 12, the drain of the first chip 21, the source of the first chip 21, the interconnection portion 32 of the first interconnection component 30, the conductive connection portion 31 of the first interconnection component 30, and the first conductive layer 11 to form a first bridge arm commutation loop. The current flows through the third conductive layer 13, the drain of the second chip 22, the source of the second chip 22, the second interconnection component 40, and the second conductive layer 12 to form a second bridge arm commutation loop. Since the source electrodes of the plurality of first chips 21 are electrically connected to the first conductive layer 11 through the first interconnection member 30, the source electrodes of the plurality of second chips 22 are electrically connected to the second conductive layer 12 through the second interconnection member 40, and the conductive connection portion 31 and the plurality of interconnection portions 32 are arranged on the first interconnection member 30 and form an integrated structure, the heat of the plurality of first chips 21 can be conducted to the first conductive layer 11 through the first interconnection member 30, and the heat of the plurality of first chips 21 can be mutually conducted through the first interconnection member 30, so that on the one hand, the junction temperatures of the plurality of first chips 21 are made consistent, and on the other hand, the first conductive layer 11 and the second conductive layer 12 can be used to increase the heat dissipation area of ​​the first chip 21, thereby reducing the thermal resistance of the power device.

[0059] Moreover, compared with the bonding wire connection method, the first interconnection member 30 can form a current balancing effect, so that the current at the source of the plurality of first chips 21 is equal, thereby making the entire power device better achieve current balancing. At the same time, the first interconnection member 30 can increase the upper limit of the current, simplify the welding process, and increase reliability.

[0060] It should be noted that the second interconnection member 40 may be one component or multiple components, and each second chip 22 corresponds to one second interconnection member 40 connected to the first conductive layer 11 .

[0061] In this embodiment, the first interconnection member 30 and the second interconnection member 40 have the same structure. The second interconnection member 40 can transfer the heat of the plurality of second chips 22 to each other, so that the junction temperatures of the plurality of second chips 22 are consistent, and the third conductive layer 13 and the second conductive layer 12 can be used to increase the heat dissipation area of ​​the second chip 22, thereby reducing the thermal resistance of the power device. At the same time, current balancing can be achieved, the upper limit of the current can be increased, the welding process can be simplified, and the reliability can be increased.

[0062] The plurality of first chips 21 form a first chipset, and each first chipset can be electrically connected to the first conductive layer 11 by using the first interconnection member 30. Similarly, the plurality of second chips 22 form a second chipset, and each second chipset can be electrically connected to the second conductive layer 12 by using the second interconnection member 40.

[0063] In this embodiment, the first interconnection member 30 and the second interconnection member 40 are both block structures with a certain thickness and grooves to separate the conductive connection part 31 and the interconnection part 32. Of course, a bent sheet structure may also be used.

[0064] like Figure 4 and Figure 5 As shown, the second conductive layer 12 includes a first conductive area 121, a second conductive area 122 and an avoidance hollow area 123 located between the first conductive area 121 and the second conductive area 122, a plurality of first chips 21 are located in the first conductive area 121, a second interconnection member 40 is connected to the second conductive area 122, a first gate conductive layer 14 and a first auxiliary source conductive layer 15 are further provided on the upper surface of the liner 10, the first gate conductive layer 14 and the first auxiliary source conductive layer 15 are located in the avoidance hollow area 123, the first gate conductive layer 14 is connected to the gate of the first chip 21, and the first auxiliary source conductive layer 15 is connected to the auxiliary source of the first chip 21. By adopting the above structure, by setting the first gate conductive layer 14 and the first auxiliary source conductive layer 15 in the avoidance hollow area 123 formed by the second conductive layer 12, the connection distance between the first gate conductive layer 14 and the gate of the first chip 21 and the connection distance between the first auxiliary source conductive layer 15 and the auxiliary source of the first chip 21 can be reduced, which is beneficial to reduce the length of the bonding wire and facilitate connection.

[0065] In this embodiment, by arranging the first conductive area 121 and the second conductive area 122 on both sides of the avoiding hollow area 123, the first conductive area 121 is arranged close to the first conductive layer 11 and the second conductive area 122 is arranged close to the third conductive layer 13, which is beneficial to the interconnection between the first chip 21 and the first conductive layer 11, and the interconnection between the second chip 22 and the second conductive area 122.

[0066] Furthermore, the avoidance hollow area 123 can increase the distance between the first chip 21 and the second chip 22 , thereby enabling a larger heat dissipation area between the first chip 21 and the second chip 22 , thereby improving the heat dissipation capability.

[0067] like Figure 4 and Figure 5 As shown, the power device further includes a plurality of resistors 50, a resistor conductive layer 16 is further provided on the upper surface of the liner 10, there are a plurality of first gate conductive layers 14, and the plurality of first gate conductive layers 14 are respectively and electrically connected to the gates of the plurality of first chips 21 in a one-to-one correspondence, and the two pins of each resistor 50 are respectively electrically connected to the resistor conductive layer 16 and the corresponding first gate conductive layer 14. By connecting the resistor 50 in series in the drive circuit using the resistor conductive layer 16, the resistor 50 can be used to eliminate gate oscillation, reduce the power loss of the first chip 21, and improve the switching speed of the power device.

[0068] In this embodiment, the current flows through the resistor conductive layer 16 , the resistor 50 , the first gate conductive layer 14 , the gate of the first chip 21 , the source of the first chip 21 , and the first auxiliary source conductive layer 15 to form a driving circuit.

[0069] like Figure 4 As shown, the plurality of first chips 21 are arranged along the length direction of the second conductive layer 12, and the length direction of the avoidance hollow area 123 is parallel to the length direction of the second conductive layer 12. With the above arrangement, the length direction of the second conductive layer 12 can be fully utilized to set the avoidance hollow area 123.

[0070] In this embodiment, the first gate conductive layer 14, the first auxiliary source conductive layer 15, and the resistor conductive layer 16 are all strip structures, and a plurality of first gate conductive layers 14 are arranged along the length direction of the second conductive layer 12. The length direction of the hollow area 123 is fully utilized to improve space utilization.

[0071] The power device further includes a first gate terminal and a first auxiliary source terminal, the first gate terminal is electrically connected to the resistive conductive layer 16, and the first auxiliary source terminal is electrically connected to the first auxiliary source conductive layer 15. The first gate terminal and the first auxiliary source terminal are located on a side of the first conductive layer 11 away from the second conductive layer 12.

[0072] Specifically, the width of the second conductive area 122 is smaller than the width of the first conductive layer 11. With the above arrangement, the area of ​​the first conductive layer 11 can be larger than the area of ​​the second conductive area 122. When heat is conducted, the upper surface of the second chip 22 can be dissipated through the entire second conductive layer 12, and the upper surface of the first chip 21 can be dissipated through the first conductive layer 11, thereby making the heat on the upper surface of the first chip 21 and the upper surface of the second chip 22 more balanced.

[0073] like Figure 4 and Figure 5 As shown, the upper surface of the liner 10 is also provided with a second gate conductive layer 17 and a second auxiliary source conductive layer 18, the second gate conductive layer 17 is connected to the gate of the second chip 22, the second auxiliary source conductive layer 18 is connected to the auxiliary source of the second chip 22, and the second gate conductive layer 17 and the second auxiliary source conductive layer 18 are both located on the side of the third conductive layer 13 away from the second conductive layer 12. With the above structure, the distance between the second gate conductive layer 17 and the gate of the second chip 22 can be reduced, and the distance between the second auxiliary source conductive layer 18 and the auxiliary source of the second chip 22 can be reduced, which is conducive to reducing the length of the bonding wire and facilitating connection.

[0074] In this embodiment, a resistor is also connected in series to the driving circuit of the second chip 22 .

[0075] The power device further includes a second gate terminal and a second auxiliary source terminal, the second gate terminal is electrically connected to the resistance conductive layer corresponding to the second chip 22, and the second auxiliary source terminal is electrically connected to the second auxiliary source conductive layer corresponding to the second chip 22. The second gate terminal and the second auxiliary source terminal are located on a side of the third conductive layer 13 away from the second conductive layer 12.

[0076] like Figure 4 As shown, the resistor conductive layer 16 is located between the plurality of first gate conductive layers 14 and the first auxiliary source conductive layer 15. With the above structure, the resistor 50 can be connected between the first gate conductive layer 14 and the resistor conductive layer 16.

[0077] like Figure 2 and Figure 3 As shown, the first conductive layer 11 and the third conductive layer 13 together form a U-shaped structure, and the second conductive layer 12 extends from the opening of the U-shaped structure into the U-shaped structure. With the above structure, the internal space of the power device can be fully utilized, and a conductive layer with a larger area can be arranged, which is beneficial to the heat dissipation of the first chip 21 and the second chip 22.

[0078] like Figure 2 and Figure 3As shown, the first conductive layer 11 includes a first interface connection layer and a first terminal connection layer connected to a first end of the first interface connection layer, the second conductive layer 12 includes a second interface connection layer and a second terminal connection layer connected to the second interface connection layer, the third conductive layer 13 includes a third interface connection layer and a third terminal connection layer connected to a first end of the third interface connection layer, the first terminal connection layer, the second terminal connection layer and the third terminal connection layer extend along the width direction of the liner 10, the first interface connection layer, the second interface connection layer and the third interface connection layer extend along the length direction of the liner 10, the first terminal connection layer and the third terminal connection layer are arranged opposite to each other, the first interface connection layer, the first terminal connection layer, the third terminal connection layer and the third interface connection layer together form a U-shaped structure, the second interface connection layer is located between the first interface connection layer and the third interface connection layer, the second terminal connection layer is located outside the U-shaped structure and at the second end of the first interface connection layer, a plurality of first chips 21 are electrically connected to the second interface connection layer, a plurality of second chips 22 are electrically connected to the third interface connection layer, the conductive connection portion 31 is electrically connected to the first interface connection layer, and the second interconnection member 40 is electrically connected to the second interface connection layer. By adopting the above structure, the internal space of the power device can be fully utilized, and a conductive layer with a larger area can be provided, which is beneficial to the heat dissipation of the first chip 21 and the second chip 22 .

[0079] like Figure 1 As shown, the power device further includes a power terminal 60, which includes a first power terminal 61, a second power terminal 62 and a third power terminal 63. The first power terminal 61 is connected to the first terminal connection layer, the second power terminal 62 is connected to the second terminal connection layer, and the third power terminal 63 is connected to the third terminal connection layer. With the above structure, by using the first terminal connection layer provided at the end of the power device to connect, the second terminal connection layer, and the third terminal connection layer to connect the corresponding power terminals, the internal space of the power device is fully utilized, and the space utilization rate is improved.

[0080] In this embodiment, the first power terminal 61 is a DC-terminal, the second power terminal 62 is an AC terminal, and the third power terminal 63 is a DC+terminal.

[0081] like Figure 4 and Figure 5As shown, the liner 10 includes a first liner 191 and a second liner 192 arranged at intervals, the first conductive layer 11 includes a first interconnect layer 111 and a second interconnect layer 112 connected and arranged at intervals, the first interconnect layer 111 and the second interconnect layer 112 are respectively electrically connected to the source of the corresponding first chip 21, the second conductive layer 12 includes a first intermediate conductive layer 124 and a second intermediate conductive layer 125 connected and arranged at intervals, a plurality of first intermediate conductive layers 124 and a second intermediate conductive layer 125 are respectively electrically connected to the drain of the corresponding first chip 21, the first intermediate conductive layer 124 and the second intermediate conductive layer 125 are respectively electrically connected to the drain of the corresponding first chip 21, The conductive layer 124 and the second intermediate conductive layer 125 are respectively conductively connected to the source of the corresponding second chip 22, the third conductive layer 13 includes a third interconnection layer 131 and a fourth interconnection layer 132 which are connected and spaced apart, the third interconnection layer 131 and the fourth interconnection layer 132 are respectively conductively connected to the drain of the corresponding second chip 22, the first interconnection layer 111, the first intermediate conductive layer 124 and the third interconnection layer 131 are arranged on the first liner 191, and the second interconnection layer 112, the second intermediate conductive layer 125 and the fourth interconnection layer 132 are arranged on the second liner 192. By setting the liner 10 as the first liner 191 and the second liner 192, when welding the first chip 21 and the second chip 22 to the conductive layer, and welding the first interconnection member 30 and the second interconnection member 40 to the conductive layer, when the same heat is conducted, the deformation of the liner can be reduced by setting the first liner 191 and the second liner 192, thereby reducing the interlayer stress generated at the interconnection interface and improving the stability of the power device.

[0082] Among them, the first liner 191 and the second liner 192 are both copper-clad ceramic substrates, which are three-layer structures, with the upper and lower layers being conductor layers and the middle layer being a ceramic substrate. The upper conductor layer is a conductive layer, forming a topological structure of the circuit. The ceramic substrate of the middle layer plays an insulating and heat-conducting role. The lower copper foil is generally connected to the housing through a thermal interface material to play a heat-conducting role.

[0083] The ceramic substrate of the middle layer can generally be made of ceramic materials such as alumina, aluminum nitride, alumina doped with zirconium oxide, and silicon nitride. Alumina has excellent mechanical strength and chemical corrosion resistance, and is suitable for applications with high durability requirements. Zirconia is known for its outstanding toughness and high temperature resistance, and performs well in high temperature and high stress environments. Aluminum nitride has high thermal conductivity and low expansion coefficient, can effectively dissipate heat, and is suitable for high-power electronic devices. Silicon carbide not only has high hardness and high wear resistance, but also can remain stable at extremely high temperatures, making it very popular in high-temperature electronic devices and high-frequency applications. The diversity and excellent properties of these ceramic materials provide a wide range of choices and significant performance improvements for the design and application of silicon carbide devices.

[0084] In this embodiment, the first intermediate conductive layer 124 and the second intermediate conductive layer 125 are both provided with a plurality of first chips 21, which is equivalent to a first chip group being provided on each of the first intermediate conductive layer 124 and the second intermediate conductive layer 125, and the third interconnection layer 131 and the fourth interconnection layer 132 are both provided with a plurality of second chips 22, which is equivalent to a second chip group being provided on each of the third interconnection layer 131 and the fourth interconnection layer 132. Moreover, each first chip group is electrically connected to the first interconnection layer 111 and the second interconnection layer 112 through the first interconnection member 30, and each second chip group is electrically connected to the first intermediate conductive layer 124 and the second intermediate conductive layer 125 through the second interconnection member 40.

[0085] Among them, the first conductive area 121 is divided into two parts, which are respectively arranged in the first intermediate conductive layer 124 and the second intermediate conductive layer 125; the second conductive area 122 is divided into two parts, which are respectively arranged in the first intermediate conductive layer 124 and the second intermediate conductive layer 125; the first intermediate conductive layer 124 and the second intermediate conductive layer 125 are both provided with an avoidance hollow area 123.

[0086] like Figure 3 As shown, the power device further includes a connection board 70, the connection board 70 having a first connection surface and a second connection surface, the first connection surface being electrically connected to the first interconnection layer 111 or the first intermediate conductive layer 124 or the third interconnection layer 131, and the second connection surface being electrically connected to the second interconnection layer 112 or the second intermediate conductive layer 125 or the fourth interconnection layer 132. Using the connection board 70 to connect different conductive layers has the advantages of simple structure and easy assembly.

[0087] like Figure 6 As shown, the connecting plate 70 includes a first flat plate 71, an arc plate 72 and a second flat plate 73 connected in sequence, the first connecting surface is the lower surface of the first flat plate 71, and the second connecting surface is the lower surface of the second flat plate 73. The connecting plate 70 with the above structure has the advantages of simple structure and easy processing.

[0088] like Figures 7 to 9As shown, the first interconnection member 30 includes a connection block, the connection block has a first dividing groove 33 and a plurality of second dividing grooves 34, the conductive connection part 31 and the interconnection part 32 are arranged at intervals along the first direction, and the plurality of interconnection parts 32 are arranged at intervals along the second direction, the first dividing groove 33 passes through the lower surface of the connection block, the first dividing groove 33 extends along the second direction and passes through two oppositely arranged side walls of the connection block, the conductive connection part 31 and the plurality of interconnection parts 32 are respectively located on both sides of the first dividing groove 33, the groove wall of the first dividing groove 33 includes a first arc segment, the second dividing groove 34 passes through the lower surface of the connection block, the plurality of second dividing grooves 34 are arranged at intervals along the second direction, each second dividing groove 34 is located between two adjacent interconnection parts 32, the second dividing groove 34 extends along the first direction, one end of each second dividing groove 34 is connected to the first dividing groove 33, and the other end of each second dividing groove 34 passes through the side wall of the connection block, the groove wall of the second dividing groove 34 includes a second arc segment, and an angle is formed between the first direction and the second direction. Compared with the metal wire bonding connection method, the first interconnection component 30 with the above structure has a larger flow area for the conductive connection part 31 and the interconnection part 32, which can withstand large currents to meet the current requirements of high-power chips. Moreover, the conductive connection part 31 and the conductive layer, and the interconnection part 32 and the source of the chip have a larger connection area, which improves the connection strength between the interconnection interfaces and reduces the aging and shedding caused by the temperature shock caused by the chip switching. At the same time, the first interconnection component 30 is used to conduct the heat generated by the chip to the conductive layer by using its large volume, which improves the heat conduction capacity, makes the temperature more uniform everywhere, accelerates the heat dissipation of the chip, and uses the exposed surfaces of the first interconnection component 30 for heat dissipation, which reduces the temperature inside the power device and further reduces the aging and shedding caused by the temperature shock caused by the chip switching.

[0089] It should be noted that the plurality of interconnecting parts 32 can be separately provided and connected to the conductive connecting part 31 to form an interconnecting part. In this embodiment, the plurality of interconnecting parts 32 are connected to form an interconnecting part, which can make the first interconnecting member 30 have greater mechanical strength and heat dissipation area.

[0090] The first direction refers to the width direction of the lining plate 10 , and the second direction refers to the length direction of the lining plate 10 .

[0091] In the related technology, some new power semiconductor modules use copper clips or copper strips to replace metal wire bonding to achieve internal electrical interconnection. They are usually connected to the chip and the liner surface by pressure welding or sintering, and have higher current carrying capacity and heat dissipation capacity than metal wires. However, this technology still has the following disadvantages: copper clips are usually made of thinner copper sheets, with low mechanical strength, easy to deform under pressure or temperature, and difficult to weld or sinter; in order to ensure the consistency of welding or sintering quality of all connection surfaces, copper clips have high requirements for cutting, stamping, bending and other manufacturing process precision, and high design and manufacturing costs; the increase in the number of parallel and series power chips will greatly increase the copper clip manufacturing precision requirements and welding or sintering process difficulty, making copper clips difficult to apply to multi-chip module packaging; in order to ensure the processing performance of copper clips, their thickness is usually small, and the current carrying capacity and heat dissipation capacity are still difficult to meet the requirements of high-power chips.

[0092] By using the first interconnection component 30 provided in this embodiment, while increasing the flow area, improving the current bearing capacity, and enhancing the heat dissipation capacity, the first interconnection component 30 can use a sintering or welding process to achieve connection of the interconnection interface. Moreover, when using the sintering process, since the upper surface of the first interconnection component 30 is a planar structure, it is beneficial for the pressure head to pressurize and heat the upper surface of the first interconnection component 30.

[0093] Furthermore, due to the use of the first interconnection member 30 of this embodiment, multiple chips can be connected to the conductive layer of the substrate to form an electrical loop, thereby achieving higher packaging efficiency.

[0094] like Figure 8 and Fig. 9 As shown, the first interconnection member 30 has a first separation groove 33, the first separation groove 33 passes through the lower surface of the first interconnection member 30, the first separation groove 33 extends along the second direction and passes through two oppositely arranged side walls of the first interconnection member 30, and the conductive connection part 31 and the plurality of interconnection parts 32 are respectively located on both sides of the first separation groove 33. The first interconnection member 30 is separated into the conductive connection part 31 and the interconnection part by the first separation groove 33, so that the first interconnection member 30 has the advantages of simple structure and easy processing while ensuring the integrity of the first interconnection member 30.

[0095] In this embodiment, by dividing the first interconnection member 30 in the form of grooves, the integrity of the first interconnection member 30 can be ensured, and the connection strength of the interconnection interface can be improved while ensuring the mechanical strength.

[0096] like Fig.13As shown, the groove wall of the first dividing groove 33 includes a first arc segment 331 and a first straight segment 332 connected to one end of the first arc segment 331, and the lower end of the first straight segment 332 is arranged to intersect with the plurality of interconnecting portions 32. The first straight segment 332 can be used to quickly increase the distance between the lower end of the first arc segment 331 and the conductive layer of the liner, thereby enhancing the insulation performance between the first interconnecting member 30 and the conductive layer of the liner.

[0097] In other embodiments, the groove wall of the first dividing groove 33 may be directly set to a straight segment structure. Compared with the first arc segment 331 of this embodiment, the first arc segment 331 can make the first interconnecting member 30 have greater mechanical strength.

[0098] like Fig.13 As shown, the groove wall of the first dividing groove 33 further includes a second straight segment 333, the second straight segment 333 is connected to the other end of the first arc segment 331, and the lower end of the second straight segment 333 is arranged to intersect with the conductive connecting portion 31. By providing the second straight segment 333, the first straight segment 331 and the second straight segment 333 can be processed at the same time, which has the advantage of easy processing.

[0099] In this embodiment, the first straight section 331 and the second straight section 333 have the same height.

[0100] like Fig.13 As shown, the first straight section 332 and the second straight section 333 are both vertical sections. The use of vertical sections has the advantage of being easy to process and can quickly increase the height of the first dividing groove 33 to quickly increase the distance between the lower end of the first arc section 331 and the conductive layer of the liner.

[0101] In other embodiments, the first straight section 332 and the second straight section 333 may both be configured as inclined surface structures.

[0102] like Fig.11 As shown, the distance between the highest point of the first arc segment 331 and the upper surface of the first interconnection member 30 is L1, the distance between the lower surface of the conductive connection portion 31 of the first interconnection member 30 and the upper surface of the first interconnection member 30 is H1, and H1 / L1 is between 2.2 and 3.2. The above ratio range can make the first interconnection member 30 have sufficient mechanical strength to improve the stability of the first interconnection member 30 during the pressurization operation, and can ensure that there is a sufficient distance between the first arc segment 331 and the conductive layer of the liner.

[0103] Among them, L1 / H1 can be 2.2, 2.5, 2.7, 2.9, 3, 3.2 and any value between 2.2 and 3.2.

[0104] like Fig.11As shown, the vertical height h1 of the first straight segment 332 is between 0.4 mm and 0.6 mm. With the above size range, the lower end of the first arc segment 331 can have a sufficient distance from the conductive layer of the liner.

[0105] The vertical height h1 of the first straight segment 332 may be 0.4 mm, 0.5 mm, 0.6 mm, or any value between 0.4 mm and 0.6 mm.

[0106] like Fig.11 As shown, the ratio between the width B1 of the first separation groove 33 and the width B2 of the first interconnection member 30 is between 0.3 and 0.5. With the above ratio range, it is possible to ensure that the conductive connection portion 31 and the conductive layer of the liner, and the interconnection portion 32 and the upper surface of the chip have sufficient connection areas while ensuring the mechanical strength of the first interconnection member 30.

[0107] The ratio of the width B1 of the first dividing groove 33 to the width B2 of the first interconnecting member 30 may be 0.3, 0.4, 0.5, or any value between 0.3 and 0.5.

[0108] like Fig.14 As shown, the first interconnection member 30 has a plurality of second dividing grooves 34, which penetrate the lower surface of the first interconnection member 30, are arranged at intervals along the second direction, and each second dividing groove 34 is located between two adjacent interconnection parts 32. The second dividing grooves 34 extend along the first direction, and one end of each second dividing groove 34 is connected to the first dividing groove 33, and the other end of each second dividing groove 34 penetrates the side wall of the first interconnection member 30. The interconnection part of the first interconnection member 30 is divided into a plurality of interconnection parts 32 by the second dividing grooves 34, so that the first interconnection member 30 has the advantages of simple structure and easy processing while ensuring the integrity of the first interconnection member 30.

[0109] like Fig.14 As shown, the groove wall of the second dividing groove 34 includes a second arc segment 341 and a third straight segment 342 and a fourth straight segment 343 connected to both ends of the second arc segment 341, and the lower ends of the third straight segment 342 and the fourth straight segment 343 are respectively arranged to intersect with the interconnection portion 32. The second dividing groove 34 adopting the above structure has the advantages of simple structure and easy processing.

[0110] In this embodiment, the third straight segment 342 and the fourth straight segment 343 can quickly increase the distance between the lower end of the second arc segment 341 and the conductive layer of the liner, thereby ensuring a sufficient distance between the first interconnection member 30 and the conductive layer of the liner.

[0111] Of course, the groove wall of the second dividing groove 34 may also include only the second arc segment 341 , and the lower end of the second arc segment 341 is respectively arranged to intersect with two adjacent interconnecting portions 32 .

[0112] It should be noted that, during the sintering process, in order to make the force between the upper surface of the chip and the conductive layer of the liner reasonable so as to avoid excessive force on one side and damage to the chip or the liner, a plurality of arched grooves can be arranged on the conductive connection part 31 during the pressurization operation. The arched grooves are connected with the adjacent second separation grooves 34 and pass through the side wall of the first interconnecting member 30 away from the second separation grooves 34, so that each arched groove coincides with the axis of the adjacent second separation groove 34, and the size of the arched groove is set according to the degree of pressure borne by the conductive connection part 31 and the interconnecting part 32.

[0113] like Fig.12 As shown, the distance between the highest point of the second arc segment 341 and the upper surface of the first interconnection member 30 is L2, the height between the lower surface of the interconnection portion 32 and the upper surface of the first interconnection member 30 is H2, and L2 / H2 is between 0.4 and 0.55. By adopting the above ratio range, the first interconnection member 30 can have sufficient mechanical strength to improve the stability of the first interconnection member 30 during the pressurization operation, and can ensure that there is a sufficient distance between the second separation groove 34 and the lower surface of the chip.

[0114] Among them, L2 / H2 can be 0.4, 0.43, 0.46, 0.48, 0.5, 0.52, 0.55 and any value between 0.4 and 0.55.

[0115] In this embodiment, the top of the first dividing groove 33 and the top of the second dividing groove 34 are located at the same height.

[0116] like Fig.12 As shown, the vertical height of the third straight segment 342 and the vertical height of the fourth straight segment 343 are both h2, and h2 is between 0.25 mm and 0.35 mm. With the above size range, the lower end of the second arc segment 341 can have a sufficient distance from the conductive layer of the liner.

[0117] Among them, h2 can be 0.25mm, 0.27mm, 0.3mm, 0.33mm, 0.35mm, and any value between 0.25mm and 0.35mm.

[0118] like Fig.12As shown, the ratio between the width B3 of the second separation groove 34 and the width B4 of the interconnection portion 32 is between 1.2 and 1.8. With the above ratio range, the second separation groove 34 and the interconnection portion 32 have appropriate sizes, and the first interconnection member 30 has sufficient connection strength while ensuring the connection area between the interconnection portion 32 and the chip.

[0119] The ratio of the width B3 of the second dividing groove 34 to the width B4 of the interconnection portion 32 may be 1.2, 1.4, 1.5, 1.6, 1.8, or any value between 1.2 and 1.8.

[0120] like Fig.13 and Fig.14 As shown, the lower surface of the interconnection part 32 is higher than the lower surface of the conductive connection part 31. With the above structure, it can adapt to the upper surface of the chip and the conductive layer of the substrate, so that the upper surface of the first interconnection member 30 remains horizontal.

[0121] like Fig.13 As shown, the top surface of the first interconnection member 30 is a plane, and a planar structure is adopted, which can facilitate the pressurization operation when the first interconnection member 30 is connected by a sintering process.

[0122] In this embodiment, the first interconnection member 30 is a copper block, which has the advantages of good thermal conductivity, electrical conductivity and ductility.

[0123] like Fig.10 As shown, the power device further includes a packaging shell 80, which includes a housing 81 and a cover plate 82 covering the housing 81, a liner 10 is disposed in the housing 81, and a chip assembly 20 and an interconnection member are both located in the housing 81. The packaging shell can be used to protect the components inside the power device to form a complete packaging structure.

[0124] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0125] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0126] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0127] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0128] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0129] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power device, characterized in that: The power device comprises: A lining plate (10), wherein the upper surface of the lining plate (10) comprises a first conductive layer (11), a second conductive layer (12) and a third conductive layer (13) which are arranged at intervals, and the second conductive layer (12) is located between the first conductive layer (11) and the third conductive layer (13); A chip assembly (20), comprising a plurality of first chips (21) and a plurality of second chips (22), wherein the drain electrode of each of the first chips (21) is conductively connected to the second conductive layer (12), and the drain electrode of each of the second chips (22) is conductively connected to the third conductive layer (13); A first interconnection member (30) comprising a conductive connection portion (31) and a plurality of interconnection portions (32), wherein the conductive connection portion (31) is electrically connected to the first conductive layer (11), and the plurality of interconnection portions (32) are conductively connected to source electrodes of a plurality of the first chips (21) in a one-to-one correspondence; a second interconnection member (40), wherein the second conductive layer (12) is conductively connected to the source electrodes of the plurality of second chips (22) via the second interconnection member (40); The second conductive layer (12) comprises a first conductive area (121), a second conductive area (122) and an avoidance hollow area (123) located between the first conductive area (121) and the second conductive area (122); a plurality of the first chips (21) are located in the first conductive area (121); the second interconnection member (40) is connected to the second conductive area (122); a first gate conductive layer (14) and a first auxiliary source conductive layer (15) are further provided on the upper surface of the liner (10); the first gate conductive layer (14) and the first auxiliary source conductive layer (15) are located in the avoidance hollow area (123); the first gate conductive layer (14) is connected to the gate of the first chip (21); and the first auxiliary source conductive layer (15) is connected to the auxiliary source of the first chip (21).

2. The power device according to claim 1, characterized in that: The power device further comprises a plurality of resistors (50); a resistor conductive layer (16) is further provided on the upper surface of the liner (10); there are a plurality of first gate conductive layers (14); the plurality of first gate conductive layers (14) are respectively and electrically connected to the gates of the plurality of first chips (21) in a one-to-one correspondence; and two pins of each resistor (50) are respectively and electrically connected to the resistor conductive layer (16) and the corresponding first gate conductive layer (14).

3. The power device according to claim 1, characterized in that: A plurality of the first chips (21) are arranged along the length direction of the second conductive layer (12), and the length direction of the avoidance hollow area (123) is parallel to the length direction of the second conductive layer (12).

4. The power device according to claim 1, characterized in that: The width of the second conductive area (122) is smaller than the width of the first conductive layer (11).

5. The power device according to claim 1, characterized in that: A second gate conductive layer (17) and a second auxiliary source conductive layer (18) are also provided on the upper surface of the liner (10); the second gate conductive layer (17) is connected to the gate of the second chip (22); the second auxiliary source conductive layer (18) is connected to the auxiliary source of the second chip (22); and the second gate conductive layer (17) and the second auxiliary source conductive layer (18) are both located on a side of the third conductive layer (13) away from the second conductive layer (12).

6. The power device according to claim 2, characterized in that: The resistive conductive layer (16) is located between the plurality of the first gate conductive layers (14) and the first auxiliary source conductive layer (15).

7. The power device according to claim 1, characterized in that: The first conductive layer (11) and the third conductive layer (13) together form a U-shaped structure, and the second conductive layer (12) extends from an opening of the U-shaped structure into the U-shaped structure.

8. The power device according to claim 7, characterized in that: The first conductive layer (11) comprises a first interface connection layer and a first terminal connection layer connected to a first end of the first interface connection layer, the second conductive layer (12) comprises a second interface connection layer and a second terminal connection layer connected to the second interface connection layer, and the third conductive layer (13) comprises a third interface connection layer and a third terminal connection layer connected to a first end of the third interface connection layer; The first terminal connection layer, the second terminal connection layer and the third terminal connection layer extend along the width direction of the lining plate (10), the first interface connection layer, the second interface connection layer and the third interface connection layer extend along the length direction of the lining plate (10), the first terminal connection layer and the third terminal connection layer are arranged opposite to each other, the first interface connection layer, the first terminal connection layer, the third terminal connection layer and the third interface connection layer together form the U-shaped structure, the second interface connection layer is located between the first interface connection layer and the third interface connection layer, and the second terminal connection layer is located outside the U-shaped structure and at the second end of the first interface connection layer.

9. The power device according to claim 8, characterized in that: A plurality of the first chips (21) are electrically connected to the second interface connection layer, a plurality of the second chips (22) are electrically connected to the third interface connection layer, the conductive connection portion (31) is electrically connected to the first interface connection layer, and the second interconnection member (40) is electrically connected to the second interface connection layer.

10. The power device according to claim 8, characterized in that: The power device further comprises a power terminal (60), wherein the power terminal (60) comprises a first power terminal (61), a second power terminal (62), and a third power terminal (63), wherein the first power terminal (61) is connected to the first terminal connection layer, the second power terminal (62) is connected to the second terminal connection layer, and the third power terminal (63) is connected to the third terminal connection layer.

11. The power device according to claim 1, characterized in that: The first conductive layer (11) comprises a first interconnection layer (111) and a second interconnection layer (112) which are connected and spaced apart, the first interconnection layer (111) and the second interconnection layer (112) are respectively electrically connected to the source electrode of the corresponding first chip (21), the second conductive layer (12) comprises a first intermediate conductive layer (124) and a second intermediate conductive layer (125) which are connected and spaced apart, a plurality of the first intermediate conductive layers (124) and the second intermediate conductive layers (125) are respectively electrically connected to the drain electrode of the corresponding first chip (21), the first intermediate conductive layer (124) and the second intermediate conductive layer (125) are respectively electrically connected to the source electrode of the corresponding second chip (22), and the third conductive layer (13) comprises a third interconnection layer (131) and a fourth interconnection layer (132) which are connected and spaced apart, the third interconnection layer (131) and the fourth interconnection layer (132) are respectively electrically connected to the drain electrode of the corresponding second chip (22).

12. The power device according to claim 11, characterized in that: The liner (10) comprises a first liner (191) and a second liner (192) which are arranged at intervals; the first interconnection layer (111), the first intermediate conductive layer (124) and the third interconnection layer (131) are arranged on the first liner (191); and the second interconnection layer (112), the second intermediate conductive layer (125) and the fourth interconnection layer (132) are arranged on the second liner (192).

13. The power device according to claim 11, characterized in that: The power device further comprises a connection board (70), the connection board (70) having a first connection surface and a second connection surface, the first connection surface being electrically connected to the first interconnection layer (111) or the first intermediate conductive layer (124) or the third interconnection layer (131), and the second connection surface being electrically connected to the second interconnection layer (112) or the second intermediate conductive layer (125) or the fourth interconnection layer (132).

14. The power device according to claim 13, characterized in that: The connecting plate (70) comprises a first flat plate (71), an arc-shaped plate (72), and a second flat plate (73) which are connected in sequence, the first connecting surface being the lower surface of the first flat plate (71), and the second connecting surface being the lower surface of the second flat plate (73).

15. The power device according to claim 1, characterized in that: The conductive connection part (31) and the plurality of interconnection parts (32) are arranged at intervals along a first direction, the first interconnection member (30) comprises a connection block, the connection block has a first separation groove (33), the first separation groove (33) runs through the lower surface of the connection block, the first separation groove (33) extends along a second direction and runs through two oppositely arranged side walls of the connection block, the conductive connection part (31) and the plurality of interconnection parts (32) are respectively located on both sides of the first separation groove (33).

16. The power device according to claim 15, characterized in that: The connection block has a plurality of second dividing grooves (34), a plurality of the interconnecting parts (32) are arranged at intervals along the second direction, the second dividing grooves (34) penetrate the lower surface of the connection block, a plurality of the second dividing grooves (34) are arranged at intervals along the second direction, each of the second dividing grooves (34) is located between two adjacent interconnecting parts (32), the second dividing grooves (34) extend along the first direction, one end of each of the second dividing grooves (34) is connected to the first dividing groove (33), the other end of each of the second dividing grooves (34) penetrates the side wall of the connection block, and an angle is formed between the first direction and the second direction.

17. The power device according to claim 16, characterized in that: The groove wall of the first dividing groove (33) comprises a first arc segment, and / or the groove wall of the second dividing groove (34) comprises a second arc segment.

18. The power device according to claim 1, characterized in that: The power device further comprises a packaging shell (80), the packaging shell (80) comprising a shell (81) and a cover plate (82) disposed on the shell (81), the liner (10) being disposed in the shell (81), and the chip assembly (20) and the interconnection member both being located in the shell (81).

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