Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. Provided is a semiconductor device capable of suppressing heat generation in a transformer. The semiconductor device includes a first coil, a second coil, a third coil, and a fourth coil, a lead, and an insulating layer. The lead is formed on the same layer as the first coil and the second coil. The first coil and the second coil are adjacent to each other by a lead in plan view and electrically connected in series by a lead. The insulating layer covers the first and second coils, and the lead. A third coil is formed on the first coil so as to face the first coil through the insulating layer. A fourth coil is formed on the second coil so as to face the second coil through the insulating layer. The third coil and the fourth coil are adjacent to each other in a plan view and electrically connected to each other.

Description

[0001] Cross-application of related applications

[0002] The disclosure of Japanese Patent Application No. 2023-102527 filed on June 22, 2023 includes a specification, drawings and an abstract, and the entire contents are incorporated herein by reference. Background Art

[0003] The present disclosure relates to semiconductor devices.

[0004] International Publication No. WO 2014 / 097425 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a transformer having coils facing each other through an insulating layer. As another transformer having coils facing each other through an insulating layer, there is a semiconductor device described in Japanese Patent Laid-Open No. 2011-082212 (Patent Document 2). Summary of the invention

[0005] Patent Document 1 and Patent Document 2 only show examples of transformers in which a receiving coil is located on an upper layer of a transmitting coil. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0006] The semiconductor device of the present disclosure includes a semiconductor substrate, a first coil, a second coil, a third coil, and a fourth coil, a lead, and an insulating layer. The lead is formed on the same layer as the first coil and the second coil on the semiconductor substrate. The first coil and the second coil are adjacent to each other through the lead in a plan view and are electrically connected in series through the lead. The insulating layer covers the first coil, the second coil, and the lead. The third coil is formed on the first coil so as to face the first coil through the insulating layer. The fourth coil is formed on the second coil so as to face the second coil through the insulating layer. The third coil and the fourth coil are adjacent to each other in a plan view and are electrically connected to each other.

[0007] According to the semiconductor device of the present disclosure, in a transformer in which a transmitting coil is located on an upper layer of a receiving coil, heat generation of the transmitting coil caused by a constant current flowing in the transmitting coil can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a semiconductor device DEV1.

[0009] Figure 2 is a diagram showing an example of signal transmission from the control circuit CC to the drive circuit DR.

[0010] Figure 3 is a first plan view of the semiconductor chip CHP3.

[0011] Figure 4is a second plan view of the semiconductor chip CHP3.

[0012] Figure 5 yes Figure 4 Cross-sectional view at VV in the figure.

[0013] Figure 6 is a flow chart for manufacturing the semiconductor chip CHP3.

[0014] Figure 7 is a cross-sectional view for explaining the first insulating film forming process S2.

[0015] Figure 8 is a cross-sectional view for explaining the wiring forming process S3.

[0016] Fig. 9 is a cross-sectional view for explaining the second insulating film forming process S4.

[0017] Fig.10 is a cross-sectional view for explaining the via plug forming process S5.

[0018] Fig.11 is a cross-sectional view for explaining the first coil forming process S6.

[0019] Fig.12 is a cross-sectional view for explaining the insulating layer forming process S7.

[0020] Fig.13 is a cross-sectional view for explaining the second coil forming process S8.

[0021] Fig.14 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV2.

[0022] Fig.15 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV3. DETAILED DESCRIPTION

[0023] Embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following drawings, the same or corresponding parts are marked with the same reference numerals, and redundant descriptions will not be repeated.

[0024] (First embodiment)

[0025] A semiconductor device according to a first embodiment will be described. The semiconductor device according to the first embodiment is a semiconductor device DEV1.

[0026] (Configuration of semiconductor device DEV1)

[0027] The configuration of the semiconductor device DEV1 will be described below.

[0028] (Overview of semiconductor device DEV1)

[0029] The outline of the semiconductor device DEV1 will be described below.

[0030] Figure 1 is a block diagram of a semiconductor device DEV1. Figure 1 As shown in FIG. 1 , the semiconductor device DEV1 includes a semiconductor chip CHP1 , a semiconductor chip CHP2 , and a semiconductor chip CHP3 .

[0031] The semiconductor chip CHP1 includes a control circuit CC, a first transmitting circuit TX1, and a second receiving circuit RX2. The semiconductor chip CHP2 includes a drive circuit DR, a first receiving circuit RX1, and a second transmitting circuit TX2. The first transmitting circuit TX1 and the second receiving circuit RX2 are electrically connected to the control circuit CC. The first receiving circuit RX1 and the second transmitting circuit TX2 are electrically connected to the drive circuit DR.

[0032] The semiconductor chip CHP3 includes transformers TR1 and TR2, and leads PL1 and PL2.

[0033] The transformer TR1 includes a transmitting coil CL1 and a receiving coil CL2. The transmitting coil CL1 includes a coil CL11 and a coil CL12, and the receiving coil CL2 includes a coil CL21 and a coil CL22. The transmitting coil CL1 and the receiving coil CL2 are each electrically connected to a first transmitting circuit TX1 and a first receiving circuit RX1, respectively.

[0034] More specifically, one end of the coil CL11 is electrically connected to the first transmitting circuit TX1, the other end of the coil CL11 is electrically connected to one end of the coil CL12, and the other end of the coil CL12 is electrically connected to the first transmitting circuit TX1. One end of the coil CL21 is also electrically connected to the first receiving circuit RX1, the other end of the coil CL21 is electrically connected to one end of the coil CL22 through the lead PL1, and the other end of the coil CL22 is electrically connected to the first receiving circuit RX1. The lead PL1 is connected to a reference potential. The reference potential is, for example, a ground potential.

[0035] The transformer TR2 includes a transmitting coil CL3 and a receiving coil CL4. The transmitting coil CL3 includes a coil CL31 and a coil CL32, and the receiving coil CL4 includes a coil CL41 and a coil CL42. The transmitting coil CL3 and the receiving coil CL4 are each electrically connected to the second transmitting circuit TX2 and the second receiving circuit RX2, respectively.

[0036] More specifically, one end of the coil CL31 is electrically connected to the second transmitting circuit TX2, the other end of the coil CL31 is electrically connected to one end of the coil CL32, and the other end of the coil CL32 is electrically connected to the second transmitting circuit TX2. One end of the coil CL41 is also electrically connected to the second receiving circuit RX2, the other end of the coil CL41 is electrically connected to one end of the coil CL42 through the lead PL2, and the other end of the coil CL42 is electrically connected to the second receiving circuit RX2. The lead PL2 is connected to a reference potential.

[0037] In the semiconductor device DEV1, signals are transmitted from the control circuit CC to the drive circuit DR by the first transmitting circuit TX1, the transformer TR1, and the first receiving circuit RX1. In the semiconductor device DEV1, signals are also transmitted from the drive circuit DR to the control circuit CC by the second transmitting circuit TX2, the transformer TR2, and the second receiving circuit RX2.

[0038] Figure 2 is a diagram showing an example of signal transmission from the control circuit CC to the drive circuit DR. Figure 2 As shown in FIG. 1 , the control circuit CC inputs a signal SG1 to the first transmitting circuit TX1. The signal SG1 is a square wave. The first transmitting circuit TX1 modulates the signal SG1 into a signal SG2 and transmits the signal SG2 to the transmitting coil CL1. When the signal SG2 flows through the transmitting coil CL1, due to the induced electromotive force, a signal SG3 corresponding to the signal SG2 flows through the receiving coil CL2. The first receiving circuit RX1 receives the signal SG3 and demodulates it into a signal SG4 (square wave), which is then output to the driving circuit DR. In this way, the signal is transmitted from the control circuit CC to the driving circuit DR. Note that the signal transmission from the driving circuit DR to the control circuit CC is also performed in the same manner. Therefore, in the semiconductor device DEV1, the signal transmission between the first transmitting circuit TX1 and the first receiving circuit RX1 and the signal transmission between the second transmitting circuit TX2 and the second receiving circuit RX2 are performed by the pulse communication method.

[0039] (Detailed Configuration of Semiconductor Chip CHP3)

[0040] The detailed configuration of the semiconductor chip CHP3 will be described below.

[0041] Figure 3 is a first plan view of the semiconductor chip CHP3. Figure 4 is a second plan view of the semiconductor chip CHP3. Figure 5 It is along Figure 4 The cross-sectional view taken along the line VV in FIG. Figure 4 and Figure 5As shown in the figure, the semiconductor chip CHP3 includes a semiconductor substrate SUB, an insulating film IF1, wiring WL1, wiring WL2, wiring WL3 and wiring WL4, an insulating film IF2, a via plug VP1, a via plug VP2, a via plug VP3, a via plug VP4, a via plug VP5, a via plug VP6, a via plug VP7 and a via plug VP8, a transmitting coil CL1, a receiving coil CL4, wiring WL5, wiring WL6, wiring WL7 and wiring WL8, a lead PL2, an insulating layer IL, a receiving coil CL2, a lead PL1, a transmitting coil CL3, an electrode pad PD1, an electrode pad PD2, an electrode pad PD3, an electrode pad PD4 and an electrode pad PD5, a guard ring GR, and a passivation film PF.

[0042] The material of the semiconductor substrate SUB is, for example, single crystal silicon. The insulating film IF1 is arranged on the semiconductor substrate SUB. The material of the insulating film IF1 is, for example, silicon oxide. The wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4 are arranged on the insulating film IF1. The material of the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4 is, for example, aluminum or an aluminum alloy. The insulating film IF2 is arranged on the insulating film IF1 so as to cover the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4.

[0043] The via plug VP1, the via plug VP2, the via plug VP3, the via plug VP4, the via plug VP5, the via plug VP6, the via plug VP7 and the via plug VP8 are embedded in the insulating film IF2. The material of the via plug VP1, the via plug VP2, the via plug VP3, the via plug VP4, the via plug VP5, the via plug VP6, the via plug VP7 and the via plug VP8 is, for example, tungsten.

[0044] The transmitting coil CL1 (coil CL11 and coil CL12), the receiving coil CL4 (coil CL41 and coil CL42), and the lead PL2 are arranged on the insulating film IF2. In other words, the coil CL11, the coil CL12, the coil CL41 and the coil CL42, and the lead PL2 are formed on the same layer of the semiconductor substrate SUB. The material of the coil CL11, the coil CL12, the coil CL41 and the coil CL42, and the lead PL2 is, for example, aluminum or an aluminum alloy.

[0045] Coil CL11 and coil CL12 are wound into a spiral shape in a plan view. Coil CL11 and coil CL12 are adjacent to each other in a plan view. Coil CL11 and coil CL12 are electrically connected in series. More specifically, the outermost ends of coil CL11 and coil CL12 are electrically connected to each other. No other leads are formed on the same layer as coil CL11, coil CL12, coil CL41 and coil CL42, and lead PL2 between coil CL11 and coil CL12. In other words, coil CL11 and coil CL12 are directly adjacent to each other in a plan view.

[0046] The innermost end of coil CL11 is electrically connected to wiring WL1 by via plug VP1. The innermost end of coil CL12 is electrically connected to wiring WL2 by via plug VP2. The end portion located at the innermost circumference of coil CL41 is electrically connected to wiring WL3 by via plug VP3. The end portion located at the outermost circumference of coil CL42 is electrically connected to wiring WL4 by via plug VP4. Lead PL2 is electrically connected to an electrode pad (not shown) located on insulating layer IL.

[0047] Wiring WL5, wiring WL6, wiring WL7 and wiring WL8 are located on the insulating layer IF2. The constituent material of the wiring WL5, wiring WL6, wiring WL7 and wiring WL8 is, for example, aluminum or an aluminum alloy. The wiring WL5 is electrically connected to the wiring WL1 by a via plug VP5, and the wiring WL6 is electrically connected to the wiring WL2 by a via plug VP6. The wiring WL7 is electrically connected to the wiring WL3 by a via plug VP7, and the wiring WL8 is electrically connected to the wiring WL4 by a via plug VP8. The wiring WL5, wiring WL6, wiring WL7 and wiring WL8 are each electrically connected to an electrode pad (not shown) located on the insulating layer IL.

[0048] In a plan view, coil CL11 is wound counterclockwise from the innermost circumference to the outermost circumference. Coil CL12 is wound clockwise from the outermost circumference to the innermost circumference. In other words, the winding direction of coil CL11 can be opposite to the winding direction of coil CL12. From another angle, coil CL11 and coil CL12 are in a series auxiliary configuration.

[0049] The coil CL41 and the coil CL42 are wound into a spiral shape in a plan view. The coil CL41 and the coil CL42 are adjacent to each other in a plan view. The coil CL41 and the coil CL42 are electrically connected in series. More specifically, the end portion located at the outermost circumference of the coil CL41 and the end portion located at the outermost circumference of the coil CL42 are electrically connected to each other. The lead PL2 is formed between the coil CL41 and the coil CL42. From another angle, the coil CL41 and the coil CL42 are adjacent to each other in a plan view through the lead PL2 and are electrically connected in series through the lead PL2.

[0050] In a plan view, coil CL41 is wound counterclockwise from the innermost circumference to the outermost circumference. Coil CL42 is wound clockwise from the outermost circumference to the innermost circumference. In other words, the winding direction of coil CL41 can be opposite to the winding direction of coil CL42. From another angle, coil CL41 and coil CL42 are in a series auxiliary configuration.

[0051] The insulating layer IL is arranged on the insulating film IF2 to cover the coils CL11, CL12, CL41 and CL42, the lead PL2, the wiring WL5, the wiring WL6, the wiring WL7 and the wiring WL8. Although not shown, the insulating layer IL can be formed by stacking a plurality of insulating films. The constituent material of each insulating film forming the insulating layer IL is, for example, silicon oxide.

[0052] The receiving coil CL2 (coil CL21 and coil CL22), the transmitting coil CL3 (coil CL31, coil CL32), and the lead PL1 are arranged on the insulating layer IL. The constituent material of the coil CL21, coil CL22, coil CL31 and coil CL32, and the lead PL1 is, for example, aluminum or an aluminum alloy.

[0053] The coil CL21 and the coil CL22 are respectively opposite to the coil CL11 and the coil CL12 through the insulating layer IL. From another angle, in a plan view, the coil CL21 and the coil CL22 overlap with the coil CL11 and the coil CL12. From yet another angle, the coil CL21 and the coil CL22 are respectively magnetically coupled to the coil CL11 and the coil CL12. As described above, since the coil CL21 and the coil CL22 are on the insulating film IL, the coil CL21 and the coil CL22 are respectively arranged on the coil CL11 and the coil CL12 through the insulating film IL.

[0054] The coil CL21 and the coil CL22 are wound into a spiral shape when visible in a plan view. The coil CL21 and the coil CL22 are adjacent to each other in a plan view. The coil CL21 and the coil CL22 are electrically connected in series. More specifically, the ends located at the outermost peripheries of the coil CL21 and the coil CL22 are electrically connected to each other. The lead PL1 is formed between the coil CL21 and the coil CL22. In other words, the coil CL21 and the coil CL22 are adjacent to each other in a plan view through the lead PL1, and are electrically connected in series through the lead PL1.

[0055] In a plan view, coil CL21 is wound counterclockwise from the innermost periphery to the outermost periphery. In a plan view, coil CL22 is wound clockwise from the outermost periphery to the innermost periphery. That is, the winding direction of coil CL21 can be opposite to the winding direction of coil CL22. In other words, coil CL21 and coil CL22 are in a series auxiliary configuration.

[0056] The coil CL31 and the coil CL32 face the coil CL41 and the coil CL42 respectively through the insulating layer IL. In other words, in a plan view, the coil CL31 and the coil CL32 overlap with the coil CL41 and the coil CL42. From another angle, the coil CL31 and the coil CL32 are magnetically coupled with the coil CL41 and the coil CL42. As mentioned above, since the coil CL31 and the coil CL32 are on the insulating layer IL, the coil CL31 and the coil CL32 are arranged on the coil CL41 and the coil CL42 respectively through the insulating film IL.

[0057] When viewed in plan view, coil CL31 and coil CL32 are wound in a spiral shape. Coil CL31 and coil CL32 are adjacent to each other in plan view. Coil CL31 and coil CL32 are electrically connected in series. More specifically, the ends located at the outermost peripheries of coil CL31 and coil CL32 are electrically connected to each other. No other leads are formed on the same layer as coil CL21, coil CL22, coil CL31 and coil CL32, and lead PL between coil CL31 and coil CL32. In other words, in plan view, coil CL31 and coil CL32 are directly adjacent to each other.

[0058] In a plan view, coil CL31 is wound counterclockwise from the innermost periphery to the outermost periphery. In a plan view, coil CL32 is wound clockwise from the outermost periphery to the innermost periphery. That is, the winding direction of coil CL31 can be opposite to the winding direction of coil CL32. In other words, coil CL31 and coil CL32 are in a series auxiliary configuration.

[0059] The distance between coil CL11 and coil CL21 or the distance between coil CL12 and coil CL22 is, for example, 6 micrometers or more and 10 micrometers or less. The distance between coil CL11 and coil CL21 or the distance between coil CL12 and coil CL22 may be 10 micrometers or more and 14 micrometers or less. The distance between coil CL41 and coil CL31 or the distance between coil CL42 and coil CL32 is, for example, 6 micrometers or more and 10 micrometers or less. The distance between coil CL41 and coil CL31 or the distance between coil CL42 and coil CL32 may be 10 micrometers or more and 14 micrometers or less.

[0060] Electrode pad PD1, electrode pad PD2, electrode pad PD3, electrode pad PD4 and electrode pad PD5 are arranged on the insulating layer IL. The material of electrode pad PD1, electrode pad PD2, electrode pad PD3, electrode pad PD4 and electrode pad PD5 is, for example, aluminum or an aluminum alloy. Electrode pad PD1 is connected to the end of the innermost periphery of coil CL21. Electrode pad PD2 is connected to the end of the innermost periphery of coil CL22. Electrode pad PD3 is connected to the end of the innermost periphery of coil CL31. Electrode pad PD4 is connected to the end of the innermost periphery of coil CL32. Electrode pad PD5 is connected to the end of lead PL1 on opposite sides of coil CL21 and coil CL22.

[0061] The guard ring GR is arranged on the insulating layer IL. The guard ring GR has a first portion GR1 and a second portion GR2. The first portion GR1 surrounds the receiving coil CL2 in a plan view. The second portion GR2 surrounds the transmitting coil CL3 in a plan view. The electrode pad PD5 is in contact with the guard ring GR (first portion GR1). Therefore, the guard ring GR is connected to the reference potential in the same manner as the lead PL1. The material of the guard ring GR is, for example, aluminum or an aluminum alloy.

[0062] The passivation film PF is arranged on the insulating layer IL to cover the receiving coil CL2 (coil CL21 and coil CL22), the transmitting coil CL3 (coil CL31 and coil CL32), the lead PL1, the electrode pad PD1, the electrode pad PD2, the electrode pad PD3, the electrode pad PD4 and the electrode pad PD5, and the guard ring GR. The electrode pad PD1, the electrode pad PD2, the electrode pad PD3, the electrode pad PD4 and the electrode pad PD5 are exposed from the opening of the passivation film PF. The material of the passivation film PF is, for example, silicon nitride.

[0063] (Method for manufacturing semiconductor chip CHP3)

[0064] Hereinafter, a method of manufacturing the semiconductor chip CHP3 will be explained.

[0065] Figure 6 1 is a flow chart for manufacturing semiconductor chip CHP3. Figure 6 As shown in the figure, the manufacturing method of the semiconductor chip CHP3 includes a preparation step S1, a first insulating film forming step S2, a wiring forming step S3, a second insulating film forming step S4, a via plug forming step S5, a first coil forming step S6, an insulating film forming step S7, a second coil forming step S8, and a passivation film forming step S9.

[0066] In the preparation step S1, a semiconductor substrate SUB is prepared. After the preparation step S1, a first insulating film forming step S2 is performed. Figure 72 is a cross-sectional view for explaining the first insulating film forming step S2. Figure 7 As shown in FIG. 1 , in the first insulating film forming step S2 , the insulating film IF1 is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. After the first insulating film forming step S2 , the wiring forming step S3 is performed.

[0067] Figure 8 2 is a cross-sectional view for explaining the wiring forming step S3. Figure 8 As shown in FIG. 1 , in the wiring forming step S3, the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4 are formed on the insulating film IF1. In the wiring forming step S3, first, the constituent materials of the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4 are deposited by, for example, a sputtering method. Second, the constituent materials of the deposited wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4 are patterned by dry etching using a resist pattern formed by photolithography as a mask. After the wiring forming step S3, a second insulating film forming step S4 is performed.

[0068] Fig. 9 2 is a cross-sectional view for explaining the second insulating film forming step S4. In the second insulating film forming step S4, as Fig. 9 As shown in FIG. 1 , the insulating film IF2 is formed on the insulating film IF1 so as to cover the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4. In the second insulating film forming step S4, first, the constituent material of the insulating film IF2 is deposited by, for example, a CVD method. Second, the constituent material of the deposited insulating film IF2 is flattened by, for example, a CMP (chemical mechanical polishing) method. After the second insulating film forming step S4, a via plug forming step S5 is performed.

[0069] Fig.10 2 is a cross-sectional view for explaining the via plug forming step S5. Fig.10 As shown in FIG. 1 , in the via plug forming step S5, via plug VP1, via plug VP2, via plug VP3, via plug VP4, via plug VP5, via plug VP6, via plug VP7, and via plug VP8 are embedded in the insulating film IF2. In the via plug forming step S5, first, a through hole is formed in the insulating film IF2 by dry etching using a resist pattern formed by photolithography as a mask. Second, the constituent materials of the via plug VP1, via plug VP2, via plug VP3, via plug VP4, via plug VP5, via plug VP6, via plug VP7, and via plug VP8 are embedded in the through hole by, for example, a CVD method.

[0070] Third, constituent materials of via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7 and VP8 protruding from the through hole are removed by, for example, a CMP method. After the via plug forming step S5, a first coil forming step S6 is performed.

[0071] Fig.11 2 is a cross-sectional view for explaining the first coil forming step S6. Fig.11 As shown in FIG. 1 , in the first coil forming step S6, the transmitting coil CL1, the receiving coil CL4, the lead PL2, and the wirings WL5, WL6, WL7, and WL8 are formed on the insulating film IF2. In the first coil forming step S6, first, the constituent materials of the transmitting coil CL1, the receiving coil CL4, the lead PL2, and the wirings WL5, WL6, WL7, and WL8 are deposited by, for example, sputtering. Second, the constituent materials of the formed transmitting coil CL1, the receiving coil CL4, the lead PL2, and the wirings WL5, WL6, WL7, and WL8 are patterned by using a resist pattern formed by photolithography, for example, dry etching as a mask. After the first coil forming step S6, the insulating layer forming step S7 is performed.

[0072] Fig.12 2 is a cross-sectional view for explaining the insulating layer forming step S7. Fig.12 As shown in FIG. 1 , an insulating layer IL is formed on the insulating film IF so as to cover the transmitting coil CL1, the receiving coil CL4, the lead PL2, and the wirings WL5, WL6, WL7, and WL8. The insulating layer IL is formed by repeating the same process as the second insulating film forming step S4. After the insulating layer forming step S7, the second coil forming step S8 is performed.

[0073] Fig.13 2 is a cross-sectional view for explaining the second coil forming step S8. Fig.13As shown in FIG. 1 , in the second coil forming step S8, the receiving coil CL2, the transmitting coil CL3, the lead PL1, the electrode pad PD1, the electrode pad PD2, the electrode pad PD3, the electrode pad PD4 and the electrode pad PD5, and the guard ring GR are formed on the insulating layer IL. In the second coil forming step S8, first, for example, the constituent materials of the receiving coil CL2, the transmitting coil CL3, the lead PL1, the electrode pad PD1, the electrode pad PD2, the electrode pad PD3, the electrode pad PD4 and the electrode pad PD5, and the guard ring GR are formed by sputtering. Second, the constituent materials of the formed receiving coil CL2, the transmitting coil CL3, the lead PL1, the electrode pad PD1, the electrode pad PD2, the electrode pad PD3, the electrode pad PD4 and the electrode pad PD5, and the guard ring GR are patterned by using a resist pattern formed by photolithography, for example, dry etching as a mask. After the second coil forming step S8, the passivation film forming step S9 is performed.

[0074] In the passivation film forming step S9, the passivation film PF is formed on the insulating film IL so as to cover the receiving coil CL2, the transmitting coil CL3, the lead PL1, the electrode pad PD1, the electrode pad PD2, the electrode pad PD3, the electrode pad PD4 and the electrode pad PD5, and the guard ring GR. In the passivation film forming step S9, first, for example, the constituent material of the passivation film PF is formed by a CVD method. Second, the constituent material of the passivation film PF is patterned by using a resist pattern formed by photolithography, for example, dry etching as a mask. Thus, the passivation film PF is formed. Figures 3 to 5 2. The structure of the semiconductor chip CHP3 is shown in FIG.

[0075] (Effect of semiconductor device DEV1)

[0076] The effects of the semiconductor device DEV1 will be explained below.

[0077] In the semiconductor device DEV1, the transformer TR1 and the transformer TR2 are integrated in the semiconductor chip CHP3. Since no semiconductor element such as a transistor is formed in the semiconductor chip CHP3, the manufacturing process of the semiconductor chip CHP3 can be optimized based on the transformer TR1 and the transformer TR2.

[0078] In the semiconductor device DEV1, no lead is formed between the coil CL11 and the coil CL12. In the semiconductor device DEV1, no lead is formed between the coil CL31 and the coil CL32. Therefore, a constant current does not flow in the coils CL11, CL12, CL31, and CL32 (current flows only during transmission). Therefore, according to the semiconductor device DEV1, the heat generation of the semiconductor chip CHP3 can be suppressed. Since the heat generation of the semiconductor chip CHP3 is suppressed, the occurrence of electromigration of the coils CL11, CL12, CL31, and CL32 can also be suppressed.

[0079] In the semiconductor device DEV1, the lead PL1 is formed between the coil CL21 and the coil CL22, and the lead PL2 is formed between the coil CL41 and the coil CL42. Then, the lead PL1 and the lead PL2 are connected to a reference potential. Therefore, in the semiconductor device DEV1, the potential at the connection portion between the coil CL21 and the coil CL22 and the connection portion between the coil CL41 and the coil CL42 can be stabilized. In the semiconductor device DEV1, common mode noise can be suppressed by configuring the coil CL11 and the coil CL12 (coil CL31 and coil CL32) in a series auxiliary configuration.

[0080] (Second embodiment)

[0081] A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment is defined as a semiconductor device DEV2. Here, the difference from the semiconductor device DEV1 will be mainly described, and redundant description will not be repeated.

[0082] (Configuration of semiconductor device DEV2)

[0083] The configuration of the semiconductor device DEV2 will be described below.

[0084] The semiconductor device DEV2 includes a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV2 is the same as that of the semiconductor device DEV1.

[0085] Fig.14 FIG. 1 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV2. Fig.14 As shown in FIG. 1 , in the semiconductor device DEV2 , the semiconductor chip CHP3 does not have the lead PL1 . In contrast, in the semiconductor device DEV2 , the coil CL21 and the coil CL22 are adjacent to each other through the electrode pad PD5 in a plan view, and are electrically connected in series through the electrode pad PD5 .

[0086] The semiconductor device DEV2 also has an electrode pad PD6 on the semiconductor chip CHP3. The electrode pad PD6 is arranged on the insulating layer IL. The material of the electrode pad PD6 is, for example, aluminum or an aluminum alloy. In the semiconductor device DEV2, the coil CL31 and the coil CL32 are adjacent to each other in a plan view through the electrode pad PD6, and are electrically connected in series through the electrode pad PD6. However, since the electrode pad PD6 is not connected to the reference potential, the electrode pad PD6 is not exposed from the passivation film PF.

[0087] In the semiconductor device DEV2, since the electrode pad PD2 is formed between the coil CL21 and the coil CL22, the electrode pad PD5 is separated from the guard ring GR (first portion GR1). In the semiconductor device DEV2, the guard ring GR also has a connecting portion GR3 that connects the first portion GR1 and the second portion GR2. Although shown, in the semiconductor device DEV2, the guard ring GR is provided with a reference potential because the connecting portion GR3 is exposed from the passivation film PF. In these respects, the configuration of the semiconductor device DEV2 is different from that of the semiconductor device DEV1.

[0088] (Effect of semiconductor device DEV2)

[0089] The effects of the semiconductor device DEV2 will be described below.

[0090] In the semiconductor device DEV1, the electrode pad PD5 and the guard ring GR (first part GR1) are in contact, and the contact portion becomes a singular point, which causes a decrease in the breakdown voltage due to the electric field concentration. However, in the semiconductor device DEV2, since the electrode pad PD5 is separated from the guard ring GR (first part GR1), such a singular point does not appear, and the breakdown voltage of the semiconductor chip CHP3 can be ensured.

[0091] (Third Embodiment)

[0092] A semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment is defined as a semiconductor device DEV3. Here, the difference from the semiconductor device DEV2 will be mainly described, and redundant description will not be repeated.

[0093] (Configuration of semiconductor device DEV3)

[0094] The configuration of the semiconductor device DEV3 will be described below.

[0095] The semiconductor device DEV3 includes a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV3 is the same as that of the semiconductor device DEV2.

[0096] Fig.15 FIG. 1 is a plan view of a semiconductor chip CHP3 in a semiconductor device DEV3. Fig.15 As shown in FIG. 1 , in the semiconductor device DEV3, the semiconductor device DEV3 does not have the electrode pad PD6. In other words, in the semiconductor device DEV3, in a plan view, the shape of the receiving coil CL2 is different from the shape of the transmitting coil CL3. In this respect, the configuration of the semiconductor device DEV3 is different from the configuration of the semiconductor device DEV2.

[0097] (Effect of semiconductor device DEV3)

[0098] The effects of the semiconductor device DEV3 will be described below.

[0099] In the semiconductor device DEV3, the width of the transmitting coil CL3 becomes smaller than that of the semiconductor device DEV2 because the electrode pad PD6 is not formed. Therefore, according to the semiconductor device DEV3, it becomes possible to reduce the layout of the transmitting coil CL3.

[0100] (appendix)

[0101] The above embodiment includes the following configurations.

[0102] (Appendix 1)

[0103] A semiconductor device comprising:

[0104] a first semiconductor chip;

[0105] a second semiconductor chip; and

[0106] A third semiconductor chip, wherein

[0107] The first semiconductor chip has a first receiving circuit.

[0108] The second semiconductor chip has a first transmitting circuit,

[0109] The third semiconductor chip has a first receiving coil electrically connected to the first receiving circuit, a first transmitting coil electrically connected to the first transmitting circuit, a first lead, and an insulating layer.

[0110] The first receiving coil has a first coil and a second coil,

[0111] The first transmitting coil has a third coil and a fourth coil,

[0112] The first lead is formed on the same layer as the first coil and the second coil,

[0113] The first coil and the second coil are adjacent to each other on the first lead in a plan view and are electrically connected in series via the first lead,

[0114] The insulating layer covers the first coil, the second coil, and the first lead wire,

[0115] The third coil is formed so that the third coil faces the first coil through the insulating layer,

[0116] The fourth coil is formed so that the fourth coil faces the second coil through the insulating layer,

[0117] The third coil and the fourth coil are adjacent to each other in a plan view and are electrically connected to each other in series.

[0118] The first transmitting circuit transmits a signal to the first receiving circuit via the first transmitting coil and the first receiving coil.

[0119] (Appendix 2)

[0120] The semiconductor device according to Appendix 1, wherein

[0121] In a plan view, a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is 6 micrometers or more and 10 micrometers or less.

[0122] (Appendix 3)

[0123] The semiconductor device according to Appendix 1, wherein

[0124] In a plan view, a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is 10 micrometers or more and 14 micrometers or less.

[0125] (Appendix 4)

[0126] The semiconductor device according to Appendix 1, wherein

[0127] The first coil and the third coil overlap each other in a plan view, and

[0128] The second coil and the fourth coil overlap each other in a plan view.

[0129] (Appendix 5)

[0130] The semiconductor device according to Appendix 1, wherein

[0131] The first coil and the third coil are magnetically coupled to each other, and

[0132] The second coil and the fourth coil are magnetically coupled to each other.

[0133] (Appendix 6)

[0134] The semiconductor device according to Appendix 1, wherein

[0135] The first lead is connected to a reference potential.

[0136] (Appendix 7)

[0137] The semiconductor device according to Appendix 1, wherein

[0138] No lead wire is formed between the third coil and the fourth coil in the same layer as the third coil and the fourth coil, and

[0139] The third coil and the fourth coil are directly adjacent to each other in plan view.

[0140] (Appendix 8)

[0141] The semiconductor device according to Appendix 1 further comprises:

[0142] The first semiconductor chip has a second receiving circuit,

[0143] The second semiconductor chip has a second transmitting circuit,

[0144] The third semiconductor chip has a second transmitting coil electrically connected to the second transmitting circuit, a second receiving coil electrically connected to the second receiving circuit, and a second lead.

[0145] The second transmitting coil has a fifth coil and a sixth coil,

[0146] The second receiving coil has a seventh coil and an eighth coil,

[0147] The insulating layer covers the fifth coil and the sixth coil,

[0148] The seventh coil is formed so that the seventh coil faces the fifth coil through the insulating layer,

[0149] The eighth coil is formed so that the eighth coil faces the sixth coil through the insulating layer,

[0150] The seventh coil and the eighth coil are adjacent to each other on the second lead in a plan view and are electrically connected in series via the second lead,

[0151] The second transmitting circuit transmits a signal to the second receiving circuit via the second transmitting coil and the second receiving coil.

Claims

1. A semiconductor device, comprising: a first coil, a second coil, a third coil, and a fourth coil; lead; Insulation layer, The lead wire is formed on the same layer as the first coil and the second coil, The first coil and the second coil are adjacent to each other across the lead in a plan view and are electrically connected in series via the lead, The insulating layer covers the first coil, the second coil, and the lead wire, The third coil is formed so that the third coil passes through the insulating layer to face the first coil, The fourth coil is formed so that the fourth coil passes through the insulating layer to face the second coil, The third coil and the fourth coil are adjacent to each other in a plan view and are electrically connected to each other.

2. The semiconductor device according to claim 1, wherein In a cross-sectional view, a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is 6 micrometers or more and 10 micrometers or less.

3. The semiconductor device according to claim 1, wherein In a cross-sectional view, a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is 10 micrometers or more and 14 micrometers or less.

4. The semiconductor device according to claim 1, wherein The first coil and the third coil overlap each other in a plan view, and The second coil and the fourth coil overlap each other in a plan view.

5. The semiconductor device according to claim 1, wherein The first coil and the third coil are magnetically coupled to each other, and The second coil and the fourth coil are magnetically coupled to each other.

6. The semiconductor device according to claim 1, wherein The leads are connected to a reference potential.

7. The semiconductor device according to claim 1, wherein No lead wire is formed between the third coil and the fourth coil in the same layer as the third coil and the fourth coil, and The third coil and the fourth coil are directly adjacent to each other in plan view.

8. A semiconductor device comprising: a first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil and an eighth coil; A first lead and a second lead; and Insulation layer, The first lead is formed on the same layer as the first coil, the second coil, the third coil, and the fourth coil, The first coil and the second coil are adjacent to each other across the first lead in a plan view and are electrically connected in series via the first lead, The third coil and the fourth coil are adjacent to each other in a plan view and are electrically connected in series, The insulating layer covers the first coil, the second coil, the third coil, the fourth coil and the first lead wire, The fifth coil is formed so that the fifth coil passes through the insulating layer and faces the first coil. The sixth coil is formed so that the sixth coil passes through the insulating layer to face the second coil, The seventh coil is formed so that the seventh coil passes through the insulating layer to face the third coil, The eighth coil is formed so that the eighth coil passes through the insulating layer to face the fourth coil, The fifth coil and the sixth coil are adjacent to each other in a plan view and are electrically connected in series, The seventh coil and the eighth coil are adjacent to each other across the second lead in a plan view and are electrically connected in series via the second lead.

9. The semiconductor device according to claim 8, wherein No lead wire is formed between the third coil and the fourth coil in the same layer as the first coil, the second coil, the third coil, and the fourth coil, The third coil and the fourth coil are directly adjacent to each other in a plan view, No lead wire is formed between the fifth coil and the sixth coil in the same layer as the fifth coil, the sixth coil, the seventh coil, and the eighth coil, and The fifth coil and the sixth coil are directly adjacent to each other in a plan view.

10. A semiconductor device comprising: a first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil and an eighth coil; lead; a first electrode pad, a second electrode pad, a third electrode pad, a fourth electrode pad, and a fifth electrode pad; and Insulation layer, The lead wire is formed on the same layer as the first coil, the second coil, the third coil, and the fourth coil, The first coil and the second coil are adjacent to each other across the lead in a plan view and are electrically connected in series via the lead, The third coil and the fourth coil are adjacent to each other in a plan view and are electrically connected in series, The insulating layer covers the first coil, the second coil, the third coil, the fourth coil and the lead wire, The fifth coil is formed so that the fifth coil passes through the insulating layer and faces the first coil. The sixth coil is formed so that the sixth coil passes through the insulating layer to face the second coil, The seventh coil is formed so that the seventh coil passes through the insulating layer to face the third coil, The eighth coil is formed so that the eighth coil passes through the insulating layer and faces the fourth coil. The first electrode pad, the second electrode pad, the third electrode pad and the fourth electrode pad are electrically connected to the innermost peripheries of the fifth coil, the sixth coil, the seventh coil and the eighth coil, respectively. The fifth coil and the sixth coil are adjacent to each other in a plan view and are electrically connected in series, The seventh coil and the eighth coil are adjacent to each other across the fifth electrode pad in a plan view and are electrically connected in series via the fifth electrode pad.

11. The semiconductor device according to claim 10, further comprising: a sixth electrode pad, and Passivation film, where the fifth coil and the sixth coil are adjacent to each other across the sixth electrode pad in a plan view and are electrically connected in series via the sixth electrode pad, The passivation film covers the fifth coil, the sixth coil, the seventh coil, and the eighth coil and the first electrode pad, the second electrode pad, the third electrode pad, the fourth electrode pad, the fifth electrode pad, and the sixth electrode pad, and forming an opening in the passivation film so that the fifth electrode pad is exposed, and An opening through which the sixth electrode pad is exposed is not formed in the passivation film.

12. The semiconductor device according to claim 10, wherein In a cross-sectional view, a distance between the first coil and the fifth coil or a distance between the second coil and the sixth coil is 6 micrometers or more and 10 micrometers or less.

13. The semiconductor device according to claim 10, wherein In a cross-sectional view, a distance between the first coil and the fifth coil or a distance between the second coil and the sixth coil is 10 micrometers or more and 14 micrometers or less.

14. The semiconductor device according to claim 10, wherein The first coil and the fifth coil overlap each other in a plan view, The second coil and the sixth coil overlap each other in a plan view, The third coil and the seventh coil overlap each other in a plan view, The fourth coil and the eighth coil overlap each other in a plan view.

15. The semiconductor device according to claim 10, wherein The first coil and the fifth coil are magnetically coupled to each other, The second coil and the sixth coil are magnetically coupled to each other, The third coil and the seventh coil are magnetically coupled to each other, The fourth coil and the eighth coil are magnetically coupled to each other.

16. The semiconductor device according to claim 10, wherein The lead wire and the fifth electrode pad are connected to a reference potential.

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