Integrated circuit structure with deep via strip isolation

Abstract

Integrated circuit structures with deep via strip isolation are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extend over the plurality of source or drain structures, individual trench contacts of the plurality of trench contacts alternating with individual gate lines of the plurality of gate lines. A backside metal wiring layer extends under one or more of the plurality of gate lines and under one or more of the plurality of trench contacts. A conductive structure couples the backside metal wiring layer to one of the one or more trench contacts of the plurality of trench contacts. The conductive structure has a cutout between a first conductive structure portion and a second conductive structure portion. A cut in a first gate line of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second gate line of the plurality of gate lines adjacent to the first conductive structure portion or the second conductive structure portion.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of advanced integrated circuit structure fabrication, and more particularly to the field of integrated circuit structures with deep via bar isolation. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased on the limited space of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory or logic devices to be incorporated on a chip, thereby facilitating the manufacture of products with increased capacity. However, the drive for greater capacity is not without its problems. The necessity to optimize the performance of each device has become increasingly significant.

[0003] Variability in conventional and currently known manufacturing processes may limit the possibility of further extending them to the 10 nm node or sub-10 nm node range. Therefore, the fabrication of functional components required for future technology nodes may require the introduction of new methodologies in current manufacturing processes or the integration of new technologies into current manufacturing processes or replacing current manufacturing processes.

[0004] In the manufacture of integrated circuit devices, multi-gate transistors such as tri-gate transistors are becoming more common as device dimensions continue to shrink. Tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure.

[0005] However, scaling multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuitry decreases, and as the absolute number of basic building blocks that can be fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0007] Figure 2 An angled cross-sectional view of an integrated circuit structure having a deep via bar (DVB) architecture is shown in accordance with an embodiment of the present disclosure.

[0008] Figure 3 A front side-up plan view of an integrated circuit structure including a deep via bar cut in the location of an existing gate cut is shown.

[0009] Figure 4A front side-up plan view of an integrated circuit structure including a gate cut in an existing location of a deep via bar cut, which may be referred to as a gate cut after deep via bar cut approach, is shown according to an embodiment of the present disclosure.

[0010] Figure 5 An angled cross-sectional view of an integrated circuit structure having a recessed deep via bar (DVB) architecture is shown in accordance with an embodiment of the present disclosure.

[0011] Figure 6-8 Angled cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a recessed deep via bar (DVB) architecture are illustrated in accordance with an embodiment of the present disclosure.

[0012] Fig. 9 Angled cross-sectional views and plan cross-sectional views of an integrated circuit structure having a recessed deep via bar (DVB) architecture according to an embodiment of the present disclosure are shown.

[0013] Fig. 10A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0014] Fig. 10B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0015] Fig.11A A plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0016] Fig. 11B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode according to an embodiment of the present disclosure is shown.

[0017] Figures 12A-12J Cross-sectional views are illustrated of various operations in a method of fabricating an all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0018] Fig.13 A computing device according to an embodiment of the present disclosure is shown.

[0019] Fig.14 An insert including one or more embodiments of the present disclosure is shown.

[0020] Fig.15is an isometric view of a mobile computing platform according to an embodiment of the present disclosure, the mobile computing platform employing an IC manufactured according to one or more processes described herein, or including one or more features described herein.

[0021] Fig.16 A cross-sectional view of a flip chip mounted die is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Integrated circuit structures with deep via bar isolation are described. In the following description, many specific details, such as specific integration and material schemes, are set forth to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other cases, well-known features, such as integrated circuit design layouts, are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0023] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of these embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as being preferred or advantageous over other implementations. In addition, there is no intention to be bound by any express or implied theory presented in the foregoing technical field, background technology, summary of the invention, or the following detailed description.

[0024] This description includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0025] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0026] “Comprising”. This term is open ended. As used in the accompanying claims, this term does not exclude additional structures or operations.

[0027] "Configured to." Various units or components may be described or claimed as being "configured to" perform one or more tasks. In this context, "configured to" is used to imply structure by indicating that the unit or component includes structure to perform the one or more tasks during operation. Thus, even if a specified unit or component is not currently operational (e.g., not turned on or activated), the unit or component may be said to be configured to perform a task. Reciting a unit or circuit or component as "configured to" perform one or more tasks is an express intention that the provisions of paragraph 6 of 35 U.S.C. § 112 should not be invoked with respect to that unit or component.

[0028] "First," "second," etc. As used herein, these terms are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0029] "Coupled." - The following description refers to elements, nodes or features being "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element, node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element, node or feature, and not necessarily mechanically.

[0030] In addition, certain terminology may also be used in the following description for reference purposes only, and therefore is not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the figures to which reference is made. Terms such as "front," "rear," "posterior," "side," "outer," and "inner" describe the orientation or position, or both, of portions of a component within a consistent but arbitrary reference system that is clear by reference to the text and associated figures describing the component in question. Such terminology may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0031] “Inhibit.” — As used herein, inhibit is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, act, or condition, it may completely prevent a result or consequence or future state. Additionally, “inhibit” may also refer to reducing or mitigating a result, manifestation, or effect that might otherwise occur. Thus, when a component, element, or feature is said to inhibit a result or state, it need not completely prevent or eliminate that result or state.

[0032] Embodiments described herein may relate to front-end (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0033] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., metallization layers (single or multiple)) on a wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0034] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such approaches may also be applicable to BEOL processing. Likewise, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such approaches may also be applicable to FEOL processing.

[0035] One or more embodiments relate to deep via bar (DVB) isolation using polysilicon cut (poly cut, PCT) processing. One or more embodiments relate to approaches including the use of PCT to eliminate DVG and DVP for certain layouts. One or more embodiments described herein relate to a full-surround gate integrated circuit structure that is manufactured to include deep via bar isolation. It should be understood that unless otherwise indicated, references to nanowires herein may indicate nanowires or nanoribbons or nanosheets or fork sheets. One or more embodiments described herein relate to fin-based integrated circuit structures that are manufactured to include deep via bar isolation.

[0036] Embodiments may be implemented to reduce process complexity by eliminating two immersion layers and a large number of process operations. Embodiments may be implemented to eliminate the need for a power plug process while maintaining targeted connectivity.

[0037] To provide context, in a standard cell design, the diffusion placement and metal routing layers are designed around a power delivery scheme. This can be a through-front side bump to M0 and diffusion contact, or in newer architectures, it can be a through-wafer backside metal that tapers through vias that contact the diffusion contact on the front side. When doing these, there is a space allocation for delivering power, whether it is on the front side metal or the diffusion.

[0038] Traditionally, power is delivered from the positive side interconnect. At the standard cell level, power can be delivered directly at the top of the transistor or from the top and bottom cell boundaries. The power delivered from the top and bottom cell boundaries enables a relatively short standard cell height with a slightly higher grid resistance. However, the positive side grid shares the interconnect stack with the signal wiring and reduces the signal wiring trace. In addition, for high-performance design, the top and bottom cell boundary power metal wires must be wide enough to reduce the grid resistance and improve performance. This usually leads to an increase in cell height. According to one or more embodiments of the present disclosure, it is possible to deliver power from the back side of the wafer or substrate to solve area and performance problems. At the cell level, wider metal 0 power may no longer be required at the top and bottom cell boundaries, and therefore, the cell height can be reduced. In addition, the grid resistance can be significantly reduced, thereby improving performance. At the block and chip level, due to the removal of power wiring, the positive side signal wiring trace increases, and due to very wide wires, large vias and reduced interconnect layers, the grid resistance is significantly reduced.

[0039] In earlier technologies, the power delivery network from the bumps to the transistors required a significant amount of block resources. Such resource usage on the metal stack manifests itself in some process nodes as a standard cell architecture with layout revision control or cell placement restrictions at the block level. In an embodiment, eliminating the power delivery network from the front-side metal stack allows free sliding cell placement in the block without power delivery complexity and placement-related delay timing variations.

[0040] As a comparison, Figure 1 Cross-sectional views of an interconnect stack with front-side power delivery and an interconnect stack with back-side power delivery are shown according to embodiments of the present disclosure.

[0041] refer to Figure 1 , an interconnect stack 100 with front-side power delivery includes a transistor 102 and a signal and power delivery metallization 104. The transistor 102 includes a bulk substrate 106, a semiconductor fin 108, a terminal 110, and a device contact 112. The signal and power delivery metallization 104 includes a conductive via 114, a conductive line 116, and a metal bump 118.

[0042] Reference again Figure 1, an interconnect stack 150 with backside power delivery includes a transistor 152, a front side signal metallization 154A, and a power delivery metallization 154B. The transistor 152 includes a semiconductor nanowire or nanoribbon 158, a terminal 160 and a device contact 162, and a deep via bar 163. The front side signal metallization 154A includes a conductive via 164A and a conductive line 166A. The power delivery metallization 154B includes a conductive via 164B, a conductive line 166B, and a metal bump 168.

[0043] To provide further context, one of the ultimate goals of standard cell design is to minimize the impact of power delivery on signal routing in terms of area while maintaining a robust power delivery scheme that will have minimal supply voltage drop. For positive side power delivery, a commercialized standard cell architecture must allocate routing traces for power and ground from the top of the positive side stack to the first metal wiring layer M0. This approach will utilize metal wiring traces. This means that tighter metal pitch is required when routing signals to deliver power. Tighter metal pitch results in higher caps and resistances, resulting in higher power consumption. In addition, a larger voltage drop occurs from the top of the stack to the transistor source due to resistance.

[0044] Power delivery based on deep via bars (DVB) enables power delivery from the back side without allocating tracks in the front side metal wiring tracks. However, this technology requires space across the cell boundary between the NMOS and PMOS devices to deliver power to the front side diffusion contacts for standard cells. With deep via bar (DVB) technology, power delivery is done from the back side through the space between the N diffusion and the P diffusion.

[0045] As an exemplary structure, Figure 2 An angled cross-sectional view of an integrated circuit structure having a deep via bar (DVB) architecture is shown in accordance with an embodiment of the present disclosure.

[0046] refer to Figure 2 , the integrated circuit structure 200 includes a gate line 202, an N-type source or drain structure 204A, a P-type source / drain structure 204, a deep via bar (DVB) 206, a positive side local interconnect 208, and a backside metal wiring layer 210 (BM0 layer). The PP differential distance and the NN differential distance are shown to accommodate the intervening deep via bar (DVB) 206. The gate line 202 is above a channel structure, such as a nanowire-based, nanoribbon-based, or nanosheet-based channel structure, or a fin-based channel structure. The location where the gate line 202 is cut also accommodates the deep via bar (DVB) 206.

[0047] Although depicted as continuous deep via bars 206, in embodiments, one or more cuts may be made in one of the deep via bars 206 at locations where connectivity is to be removed. Using state-of-the-art deep via bar technology, deep via bars 206 are cut in locations where gate lines 202 have been cut. Deep via bar cut dielectric plugs are formed in the cut locations. As an example, Figure 3 A front side-up plan view of an integrated circuit structure is shown that includes a deep via bar cut in the location of an existing gate cut, which may be referred to as a deep via bar cut before gate cut approach.

[0048] refer to Figure 3 , the integrated circuit structure 300 includes a plurality of gate lines 302, all of which have the same cutout spacing 304. The deep via bar portions 306A and 306B are separated by a deep via bar cutout 310. Optionally, the deep via bar 306A is shown as having a column portion 308, for example, including a combination of the following Figure 5 30. The gate line 302 and the deep via bar portions 306A and 306B are shown relative to the backside metallization 312A and 312B (e.g., BM0 lines). The dielectric plug is ultimately formed in the deep via bar cut location 310. However, the manufacture of the dielectric plug may be challenging because all gate lines 302 are cut at the same relatively large interval 304 (e.g., about 30 nm) before forming the cut between the deep via bar portions 306A and 306B.

[0049] and Figure 3 on the contrary, Figure 4 A front side upward plan view of an integrated circuit structure according to an embodiment of the present disclosure is shown, the integrated circuit structure including a gate cut in the existing location of a deep via bar cut, which can be referred to as a deep via bar cut followed by a gate cut approach. It should be understood that according to embodiments of the present disclosure, this deep via bar cut followed by a gate cut approach can be used to manufacture Figure 2 An integrated circuit structure 200 is provided.

[0050] refer to Figure 4 , the integrated circuit structure 400 includes a plurality of gate lines 402, wherein the cutout interval of the first gate line 402A is greater than the cutout interval 404 of the second gate line 402B. The deep via bar portions 406A and 406B are separated by a deep via bar cutout 410. Optionally, the deep via bar 406A is shown as having a column portion 408, for example, including a combination of the following Figure 5 The depression described is deep in the via bar. In this case, Figure 3Instead, deep via bar cutouts 410 are formed before cutouts 404 are formed in gate line 402B. Gate line 402 and deep via bar portions 406A and 406B are shown relative to backside metallizations 412A and 412B (e.g., BM0 lines). Dielectric plugs are ultimately formed in deep via bar cutout locations 410. However, gate cutout plugs may be fabricated to plug deep via bar cutouts 410 and cutout spacing 404 (e.g., about 14 nm) for a second gate line 402B in the gate lines, which may reduce processing costs.

[0051] In another aspect, according to embodiments of the present disclosure, implementation of a metal gate notch process enables a self-aligned manufacturing scheme for a DVB, wherein the DVB and gate terminal distance is defined by a conformal liner rather than an edge defined by a resist, resulting in a significantly reduced DVB gate terminal distance without compromising reliability. With respect to recessing, even with a self-aligned scheme, the DVB can be made closer to the gate terminal, below a certain distance, further increases in drive do not overcome the capacitance drawbacks caused by the coupling between the gate and the DVB in terms of performance. In an embodiment, recessing the DVB in the region aligned with the gate terminal reduces capacitance, which in turn allows for a reduction in liner thickness, resulting in cell scaling by increasing active transistor area or reducing cell height.

[0052] To provide further context, the current deep via bar (DVB) process edge is resist defined relative to the gate terminal. It is the via wall that rises from the backside metal layer BM0. Currently, the distance between the DVB and the gate terminal is resist defined. Therefore, in the case of edge placement errors, the DVB may end up closer to the gate terminal than nominally intended. Therefore, the distance between the DVB and the gate terminal needs to be set to a distance that must take into account the distance required to avoid insulator breakdown and edge placement errors, resulting in a greater than desired cell height or in other words area loss. Since the DVB is a continuous wall of the via, it is coupled to the polysilicon (poly) terminal and drain diffusion of the transistor, resulting in a higher capacitance than the desired capacitance, limiting scaling in terms of cell level performance.

[0053] According to one or more embodiments of the present disclosure, a process flow is used that enables self-alignment of the DVB edge to the polysilicon edge and recessing of the body vias that are not connected to the source.

[0054] Advantages of implementing one or more of the embodiments described herein may include one or more of the following: (1) self-alignment to the gate edge and recessing of the DVB enables area and performance scaling of the technology; (2) enables a reduction of approximately 40% in the distance from the DVB to the gate end, which is useful for cell height reduction and / or performance improvement; and (3) self-alignment of the DVB can be detected by distinctive material changes around regular thickness deep via bars.

[0055] A recessed DVB can be full thickness in some locations and recessed in other locations. As an example architecture, Figure 5 1 shows an angled cross-sectional view of an integrated circuit structure 500 having a recessed deep via bar (DVB) architecture according to an embodiment of the present disclosure. It should be understood that according to an embodiment of the present disclosure, the integrated circuit structure 500 may be manufactured using, for example, the above-mentioned combination of Figure 4 The deep via cut followed by the gate cut path is described.

[0056] refer to Figure 5 , the integrated circuit structure 500 includes a gate line 502, an N-type source or drain structure 504A, a P-type source and drain structure 504, a recessed deep via bar (DVB) structure 506 / 506A, a positive side local interconnect 508 and a back side metal wiring layer 510 (BMO layer). In one embodiment, a self-aligned process scheme is used to form a recessed deep via bar (DVB). The gate line 502 is above a channel structure, such as a nanowire-based, nanobelt-based or nanosheet-based channel structure, or a fin-based channel structure. The location where the gate line 502 is cut also accommodates the recessed deep via bar (DVB) structure 506 / 506A.

[0057] Reference again Figure 5 According to one or more embodiments of the present disclosure, the integrated circuit structure 500 includes a plurality of gate lines 502. In one embodiment, the plurality of gate lines 502 extend over a plurality of semiconductor nanowire stack channel structures (which may also be referred to as nanoribbon structures or nanosheet structures). In another embodiment, the plurality of gate lines 502 extend over a plurality of semiconductor fin structures.

[0058] The integrated circuit structure 500 also includes a plurality of trench contacts 508 extending over the plurality of source or drain structures 504A / 504B, individual trench contacts in the plurality of trench contacts 508 alternating with individual gate lines in the plurality of gate lines 502. A backside metal wiring layer 510 extends under one or more gate lines in the plurality of gate lines 502 and under one or more trench contacts in the plurality of trench contacts 508. A conductive structure 506 / 506A couples the backside metal wiring layer 510 to one of the one or more trench contacts in the plurality of trench contacts 508. The conductive structure 506 / 506A includes a pillar portion 506A in contact with the one of the one or more trench contacts in the plurality of trench contacts 508, the pillar portion 506A being on a line portion 506 that contacts and extends along the backside metal wiring layer 510.

[0059] In an embodiment, backside metal wiring layer 510 is a backside power delivery line. In an embodiment, conductive structure 506A / 506 is a recessed deep via bar structure.

[0060] In an embodiment, the pillar portion 506A of the conductive structure 506 / 506A extends between a pair of N-type source or drain structures 504A of the plurality of source or drain structures 504A / 504B, as depicted for the right conductive structure 506 / 506A. In an embodiment, the pillar portion 506A of the conductive structure 506 / 506A extends between a pair of P-type source or drain structures 504B of the plurality of source or drain structures 504A / 504B.

[0061] As an exemplary treatment scheme, Figure 6-8 Angled cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a recessed deep via bar (DVB) architecture are illustrated in accordance with an embodiment of the present disclosure. Fig. 9 Angled cross-sectional views and plan cross-sectional views of an integrated circuit structure 900 having a recessed deep via bar (DVB) architecture according to an embodiment of the present disclosure are shown. It should be understood that according to an embodiment of the present disclosure, for example, the above combined method can be used in the manufacture of the integrated circuit structure 900. Figure 4 The deep via cut followed by the gate cut path is described.

[0062] refer to Figure 6 , a starting structure 600 includes a plurality of fins or sub-fins 604 on a substrate 602. The fins may be used for a FinFET device, or may be sub-fins beneath a nanowire stack. A plurality of gate lines 606 (e.g., each gate line including a metal gate and a high-k gate dielectric) are over the plurality of fins or sub-fins 604. An insulating cap 608 is over the plurality of gate lines 606. Epitaxial source or drain structures 610 alternate with the plurality of gate lines 606. Dielectric gate cut plugs 612 may cut some of the plurality of gate lines 606. A trench 614 is etched in a location where a recessed deep via bar is to be formed.

[0063] refer to Figure 7 ,exist Figure 6 A protective cap layer 618 is formed on the structure 600. A conductive fill material 616 is formed in the trench 614. The structure 600 can effectively be considered as a non-recessed deep via bar.

[0064] refer to Figure 8 , the conductive fill material 616 is recessed in selected locations to provide a recessed deep via bar structure 616A having an intersecting dielectric plug portion 620 .

[0065] refer to Fig. 9, the structure 900 obtained by the above process may include multiple fins or sub-fins 904 on a substrate 902. The fins may be used for FinFET devices, or may be sub-fins under a nanowire stack. Multiple gate lines 906 (e.g., each gate line includes a metal gate and a high-k gate dielectric) are above the multiple fins or sub-fins 904. An insulating cap 908 is on the multiple gate lines 906. Epitaxial source or drain structures 910 alternate with the multiple gate lines 906. The structure includes a recessed deep via bar structure 916A with an intersecting dielectric plug portion 920. A trench contact structure 930 and a trench contact plug 932 may also be included. From the perspective view on the right, a lower line portion 916B of the recessed deep via bar structure 916A can be seen. In one embodiment, the deep via bar structure 916A or power rail is self-aligned with the gate / S / D cut by the dielectric liner. In one embodiment, the metal in the rail is recessed everywhere except for the connection to the above-mentioned metal layer / contact portion.

[0066] In another aspect, contact over active gate (COAG) structures and processes are described, which, for example, can enable further compact structures of cell architectures including deep via bar isolation. One or more embodiments of the present disclosure relate to semiconductor structures or devices having one or more gate contact structures (e.g., as gate contact vias) disposed above an active portion of a gate electrode of a semiconductor structure or device. One or more embodiments of the present disclosure relate to methods of manufacturing semiconductor structures or devices having one or more gate contact structures formed above an active portion of a gate electrode of a semiconductor structure or device. The approaches described herein can be used to reduce standard cell areas by enabling gate contacts to be formed above active gate regions. According to one or more embodiments, tapered gates and trench contacts are implemented to enable COAG manufacturing. Embodiments can be implemented to enable patterning at close spacings.

[0067] To provide further context for the significance of the COAG processing scheme, in a technology where space and layout constraints are slightly relaxed compared to current generation space and layout constraints, a contact to a gate structure may be made by contacting a portion of a gate electrode disposed over an isolation region. As an example, Fig. 10A A plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown.

[0068] refer to Fig. 10A, semiconductor structure or device 1000A includes a diffusion or active region 1004 disposed in substrate 1002 and within isolation region 1006. One or more gate lines (also referred to as polysilicon lines), such as gate lines 1008A, 1008B, and 1008C, are disposed over diffusion or active region 1004 and over a portion of isolation region 1006. Source or drain contacts (also referred to as trench contacts), such as contacts 1010A and 1010B, are disposed over source and drain regions of semiconductor structure or device 1000A. Trench contact vias 1012A and 1012B provide contact to trench contacts 1010A and 1010B, respectively. A separate gate contact 1014 and an overlying gate contact via 1016 provide contact to gate line 1008B. In contrast to the source or drain trench contacts 1010A or 1010B, from a plan view perspective, the gate contact 1014 is disposed over the isolation region 1006 but not over the diffusion or active region 1004. In addition, neither the gate contact 1014 nor the gate contact via 1016 is disposed between the source or drain trench contacts 1010A and 1010B.

[0069] Fig. 10B A cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode is shown. Fig. 10B , a semiconductor structure or device 1000B, such as Fig. 10A A non-planar version of the device 1000A includes a non-planar diffusion or active region 1004B (e.g., a fin structure) formed from the substrate 1002 and within the isolation region 1006. A gate line 1008B is disposed over the non-planar diffusion or active region 1004B and over a portion of the isolation region 1006. As shown, the gate line 1008B includes a gate electrode 1050 and a gate dielectric layer 1052, as well as a dielectric cap layer 1054. The gate contact 1014 and overlying gate contact via 1016 and overlying metal interconnect 1060 are also viewed from this perspective, all of which are disposed in an interlayer dielectric stack or layer 1070. Also from this perspective are the gate contacts 1014 and overlying gate contact vias 1016 and overlying metal interconnects 1060, all of which are disposed in an interlayer dielectric stack or layer 1070. Fig. 10B From the perspective of FIG. 1 , the gate contact 1014 is disposed over the isolation region 1006 but not over the non-planar diffusion or active region 1004B.

[0070] Reference again Fig. 10A and 10B, the arrangement of semiconductor structures or devices 1000A and 1000B respectively places the gate contact above the isolation region. Such an arrangement wastes layout space. However, placing the gate contact above the active area will require an extremely tight registration budget, or the gate size will have to be increased to provide sufficient space to land the gate contact. In addition, historically, contact with the gate above the diffusion region has been avoided due to the risk of drilling through other gate materials (such as polysilicon) and contacting the underlying active area. One or more embodiments described herein solve the above-mentioned problems by providing a feasible approach and resulting structure to manufacture a contact structure that contacts a portion of the gate electrode formed above the diffusion or active region.

[0071] As an example, Fig.11A FIG. 1 is a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure. Fig.11A , semiconductor structure or device 1100A includes a diffusion or active region 1104 disposed in a substrate 1102 and within an isolation region 1106. One or more gate lines, such as gate lines 1108A, 1108B, and 1108C, are disposed over the diffusion or active region 1104 and over a portion of the isolation region 1106. Source or drain trench contacts, such as trench contacts 1110A and 1110B, are disposed over source and drain regions of the semiconductor structure or device 1100A. Trench contact vias 1112A and 1112B provide contact to trench contacts 1110A and 1110B, respectively. Gate contact via 1116, without an intervening separate gate contact layer, provides contact to gate line 1108B. Fig. 10A In contrast, from a plan view perspective, gate contact 1116 is disposed over diffusion or active region 1104 and between source or drain contacts 1110A and 1110B.

[0072] Fig. 11B A cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to an embodiment of the present disclosure is shown. Fig. 11B , semiconductor structure or device 1100B, such as Fig.11AA non-planar version of the device 1100A includes a non-planar diffusion or active region 1104B (e.g., a fin structure) formed by a substrate 1102 and within an isolation region 1106. A gate line 1108B is disposed over the non-planar diffusion or active region 1104B and over a portion of the isolation region 1106. As shown, the gate line 1108B includes a gate electrode 1150 and a gate dielectric layer 1152, as well as a dielectric cap layer 1154. The gate contact via 1116 and the overlying metal interconnect 1160 are also viewed from this perspective, both of which are disposed in an interlayer dielectric stack or layer 1170. Also from Fig. 11B From the perspective of FIG. 1 , the gate contact via 1116 is disposed above the non-planar diffusion or active region 1104B.

[0073] Therefore, refer again Fig.11A and 11B In an embodiment, the trench contact vias 1112A, 1112B and the gate contact via 1116 are formed in the same layer and are substantially coplanar. Fig. 10A and 10B In contrast, the contact to the gate line would otherwise include an additional gate contact layer, which may, for example, extend orthogonally to the corresponding gate line. Fig.11A and 11B In the described structures, structures 1100A and 1100B are manufactured so that the contact can land directly on the active gate portion from the metal interconnect layer without shorting to the adjacent source and drain regions. In an embodiment, such an arrangement provides a large area reduction of the circuit layout by eliminating the need to extend the transistor gate on the isolation to form a reliable contact. As used throughout, in an embodiment, reference to the active portion of the gate refers to the portion of the gate line or structure that is disposed above the active or diffusion region of the underlying substrate (from a plan view perspective). In an embodiment, reference to the non-active portion of the gate refers to the portion of the gate line or structure that is disposed above the isolation region of the underlying substrate (from a plan view perspective).

[0074] In an embodiment, the semiconductor structure or device 1100 is a non-planar device, such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of gate lines 1108A and 1108B surrounds at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is made into a discrete three-dimensional body, such as in a full-surround gate device. In one such embodiment, the gate stacks of gate lines 1108A and 1108B each completely surround the channel region.

[0075] In general, one or more embodiments relate to approaches for landing gate contact vias directly on the gate of an active transistor and structures formed thereby. Such an approach can eliminate the need to extend a gate line on isolation for contact purposes. Such an approach can also eliminate the need for a separate gate contact (GCN) layer for conducting signals from a gate line or structure. In an embodiment, the elimination of the above features is achieved by recessing the contact metal in the trench contact (TCN) and introducing an additional dielectric material (e.g., a trench insulation layer (TILA)) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer, which has different etching characteristics than the gate dielectric material cap layer used for trench contact alignment in a gate aligned contact process (GAP) processing scheme (e.g., using a gate insulation layer (GILA)).

[0076] As an exemplary manufacturing scheme, the starting structure includes one or more gate stack structures disposed above a substrate. The gate stack structure may include a gate dielectric layer and a gate electrode. A trench contact, for example, a contact to a diffusion region of the substrate or to an epitaxial region formed in the substrate, is spaced apart from the gate stack structure by a dielectric spacer. An insulating cap layer may be disposed on the gate stack structure (e.g., GILA). In one embodiment, a contact barrier region or "contact plug" that may be made of an interlayer dielectric material is included in the region where the contact is to be blocked from being formed.

[0077] In an embodiment, the contact pattern is substantially perfectly aligned with the existing gate pattern while eliminating the use of lithography operations with extremely tight registration budgets. In one such embodiment, the approach enables the use of essentially highly selective wet etching (or anisotropic dry etching processes, some of which are non-plasma, gas phase isotropic etching (e.g., compared to classical dry or plasma etching) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the approach enables the elimination of the need for other critical lithography operations to generate the contact pattern as used in other approaches. This also allows perfect or near-perfect self-alignment with greater edge placement error tolerance. In an embodiment, the trench contact grid is not patterned separately, but is formed between the polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grating is patterned but before the gate grating is cut.

[0078] In addition, the gate stack structure can be manufactured by a replacement gate process. In such a scheme, the dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process as opposed to being performed from an earlier process. In an embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etch process including SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etch process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etch including aqueous phosphoric acid.

[0079] In embodiments, one or more approaches described herein substantially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in a particular such embodiment, an anneal of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, such as after forming the gate dielectric layer. The anneal is performed before forming the permanent contact.

[0080] Next, the trench contact can be recessed to provide a recessed trench contact having a height lower than the top surface of the adjacent spacer. An insulating capping layer is then formed on the recessed trench contact (e.g., TILA). According to an embodiment of the present disclosure, the insulating capping layer on the recessed trench contact is composed of a material having different etching characteristics from the insulating capping layer on the gate stack structure.

[0081] The trench contact may be recessed by a process that is selective to the materials of the spacer and the gate insulating capping layer. For example, in one embodiment, the trench contact is recessed by an etching process such as a wet etching process or a dry etching process. The trench contact insulating capping layer may be formed by a process suitable for providing a conformal and sealing layer over the exposed portion of the trench contact. For example, in one embodiment, the trench contact insulating capping layer is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, such as by chemical mechanical polishing (CMP), to provide the trench contact insulating capping layer material only over the recessed trench contact.

[0082] With respect to suitable material combinations for the gate or trench contact insulating capping layers, in one embodiment, one of the pair of gate-to-trench contact insulating capping materials consists of silicon oxide and the other consists of silicon nitride. In another embodiment, one of the pair of gate-to-trench contact insulating capping materials consists of silicon oxide and the other consists of carbon-doped silicon nitride. In another embodiment, one of the pair of gate-to-trench contact insulating capping materials consists of silicon oxide and the other consists of silicon carbide. In another embodiment, one of the pair of gate-to-trench contact insulating capping materials consists of silicon nitride and the other consists of carbon-doped silicon nitride. In another embodiment, one of the pair of gate-to-trench contact insulating capping materials consists of silicon nitride and the other consists of silicon carbide. In another embodiment, one of the pair of gate-to-trench contact insulating capping materials consists of silicon nitride and the other consists of silicon carbide. In another embodiment, one of the pair of gate-to-trench contact insulating capping materials consists of carbon-doped silicon nitride and the other consists of silicon carbide.

[0083] In another aspect, a nanowire or nanoribbon structure is described. A nanowire or nanoribbon release process can be performed by replacing the gate trench. An example of such a release process is described below. In addition, on another aspect, back-end (BE) interconnect scaling can result in lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein can be implemented to enable positive and back-side interconnect integration for nanowire transistors. The embodiments described herein can provide a way to achieve a relatively wide interconnect spacing. The result can be improved product performance and lower patterning cost. The embodiments can be implemented to enable the robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0084] One or more embodiments described herein relate to directional bi-epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In an embodiment, an integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trenches are formed on one of the source or drain sides to enable direct contact to a backside interconnect level.

[0085] As an exemplary process flow for fabricating another all-around gate device, Figures 12A-12J Cross-sectional views are illustrated of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0086] refer to Fig. 12A, a method of manufacturing an integrated circuit structure includes forming a starting stack above a fin 1202 (e.g., a silicon fin), the starting stack including alternating sacrificial layers 1204 and nanowires 1206. The nanowires 1206 may be referred to as a vertical arrangement of nanowires. A protective cap 1208 may be formed above the alternating sacrificial layers 1204 and nanowires 1206, as depicted. A relaxed buffer layer 1252 and a defect modification layer 1250 may be formed below the alternating sacrificial layers 1204 and nanowires 1206, as depicted.

[0087] refer to Fig. 12B , a gate stack 1210 is formed over the vertical arrangement of the horizontal nanowires 1206. Then, portions of the vertical arrangement of the horizontal nanowires 1206 are released by removing portions of the sacrificial layer 1204 to provide a recessed sacrificial layer 1204' and a cavity 1212, as shown in FIG. Fig. 12C Depicted.

[0088] It should be understood that Fig. 12C The structure can be fabricated without first performing the deep etch and asymmetric contact processing described below. In either case (e.g., with or without asymmetric contact processing), in an embodiment, the fabrication process involves using a process scheme that provides a fully-around-gate integrated circuit structure with an epitaxial raised portion, which can be a vertically discrete source or drain structure.

[0089] refer to Fig.12D , an upper gate spacer 1214 is formed at the sidewalls of the gate structure 1210. A cavity spacer 1216 is formed in the cavity 1212 below the upper gate spacer 1214. A deep trench contact etch is then optionally performed to form a trench 1218 and form a recessed nanowire 1206'. There may also be a patterned relaxed buffer layer 1252' and a patterned defect modification layer 1250', as depicted.

[0090] Then, a sacrificial material 1220 is formed in the trench 1218, such as Fig.12E In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0091] refer to Fig.12F , a first epitaxial source or drain structure (e.g., left-hand feature 1222) is formed at a first end of the vertical arrangement of horizontal nanowire 1206'. A second epitaxial source or drain structure (e.g., right-hand feature 1222) is formed at a second end of the vertical arrangement of horizontal nanowire 1206'. In an embodiment, as depicted, epitaxial source or drain structure 1222 is a vertically discrete source or drain structure and may be referred to as an epitaxial bump.

[0092] An interlayer dielectric (ILD) material 1224 is then formed on the sides of the gate electrode 1210 and adjacent to the source or drain structure 1222, such as Figure 12G Depicted. Reference Fig.12H , a replacement gate process is used to form a permanent gate dielectric 1228 and a permanent gate electrode 1226. The ILD material 1224 is then removed, such as Fig.12I The sacrificial material 1220 is then removed from one of the source drain locations (eg, the right hand side) to form the trench 1232 , but is not removed from the other of the source drain locations to form the channel 1230 .

[0093] refer to Fig.12J , forming a first conductive contact structure 1234 coupled to the first epitaxial source or drain structure (e.g., left-hand feature 1222). A second conductive contact structure 1236 is formed to couple to the second epitaxial source or drain structure (e.g., right-hand feature 1222). The second conductive contact structure 1236 is formed deeper along the fin 1202 than the first conductive contact structure 1234. In an embodiment, although Fig.12J Not depicted, but the method also includes forming an exposed surface of a second conductive contact structure 1236 at the bottom of the fin 1202. The conductive contact may include a contact resistance reducing layer and a main contact electrode layer, examples of which may include Ti, Ni, Co (for the former) and W, Ru, Co (for the latter).

[0094] In an embodiment, the second conductive contact structure 1236 is deeper along the fin 1202 than the first conductive contact structure 1234, as depicted. In one such embodiment, the first conductive contact structure 1234 is not along the fin 1202, as depicted. In another such embodiment not depicted, the first conductive contact structure 1234 is partially along the fin 1202.

[0095] In an embodiment, the second conductive contact structure 1236 is along the entire fin 1202. In an embodiment, although not depicted, the second conductive contact structure 1236 has an exposed surface at the bottom of the fin 1202 if the bottom of the fin 1202 is exposed by a backside substrate removal process.

[0096] In another aspect, in order to be able to access two conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be manufactured using a backside exposure manufacturing approach for the front side structure. In some exemplary embodiments, the exposure of the back side of the transistor or other device structure requires wafer-level backside processing. Compared to traditional TSV-type technology, the exposure of the back side of the transistor as described herein can be performed at the density of the device unit, and even within a sub-region of the device. In addition, such exposure of the back side of the transistor can be performed to substantially remove all donor substrates on which the device layers are disposed during the front side device processing. Therefore, micron-deep TSVs become unnecessary because the semiconductor thickness in the device unit after the back side of the transistor is exposed may be only tens or hundreds of nanometers.

[0097] The revealing techniques described herein can enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer employed in front-side fabrication, exposed from the backside, and employed again in back-side fabrication. Processing of the front side and exposed backside of a device structure can address many of the challenges associated with fabricating 3D ICs when relying primarily on front-side processing.

[0098] A transistor backside exposure approach can be used, for example, to remove at least a portion of the carrier layer and intervening layers of the donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0099] In some embodiments, prior to performing the above operations, the carrier layer is cleaved along a fracture plane substantially parallel to the intervening layer. A cleaving or fracture process can be used to remove a substantial portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved away by practicing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted to a uniform target depth within the carrier layer at the desired fracture plane. After such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a greater thickness of the carrier layer.

[0100] Next, the exposure of the intervening layer is detected. The detection is used to identify the time point at which the back surface of the donor substrate has advanced to the proximity of the device layer. Any endpoint detection technology known to be suitable for detecting the transition between the materials for the carrier layer and the intervening layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting the change in light absorption or emission of the back surface of the donor substrate during the execution of polishing or etching. In some other embodiments, the endpoint criteria are associated with the change in light absorption or emission of the byproducts during the polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproduct can be changed based on the different compositions of the carrier layer and the intervening layer. In other embodiments, the endpoint criteria are associated with the change in the mass of the substance in the byproducts of polishing or etching the back surface of the donor substrate. For example, the byproducts of the treatment can be sampled by a quadrupole mass analyzer, and the change in the mass of the substance can be related to the different compositions of the carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criteria are associated with the change in friction between the back surface of the donor substrate and the polishing surface in contact with the back surface of the donor substrate.

[0101] In cases where the removal process is selective for the carrier layer relative to the intermediary layer, detection of the intermediary layer can be enhanced because the etch rate delta between the carrier layer and the intermediary layer can mitigate non-uniformities in the carrier removal process. Detection can even be skipped if the grinding, polishing and / or etching operation removes the intermediary layer at a rate sufficiently lower than the rate at which the carrier layer is removed. If no endpoint criteria is used, the grinding, polishing and / or etching operation can be stopped on the intermediary layer material for a predetermined fixed duration if the thickness of the intermediary layer is sufficient for the selectivity of the etching. In some examples, the carrier etch rate:intermediary layer etch rate is 3:1-10:1 or higher.

[0102] When exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more constituent layers of the intervening layer may be removed. For example, the thickness of the intervening layer may be uniformly removed by polishing. Alternatively, the thickness of the intervening layer may be removed using a mask or blanket etching process. The process may employ the same process as the polishing or etching process employed to thin the carrier, or may be a different process with different process parameters. For example, in the case where the intervening layer provides an etch stop for the carrier removal process, the latter operation may employ a different polishing or etching process that is advantageous for removing the intervening layer rather than removing the device layer. In the case where the thickness of the intervening layer is to be removed to be less than a few hundred nanometers, the removal process may be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than the process employed to remove the carrier layer. The CMP process employed may, for example, employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or higher) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded in the intervening layer (e.g., as electrical isolation between adjacent device regions).

[0103] For embodiments where the device layer is exposed by completely removing the intervening layer, backside processing may be initiated on the exposed backside of the device layer or a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intervening layer and a pre-fabricated device region (e.g., source or drain region) in the device layer.

[0104] In some embodiments where the backside of a carrier layer, an intervening layer, or a device layer is recessed with wet and / or plasma etching, such etching may be a substantially selective etch or patterned etch that imparts significant non-planarity or topography into the backside surface of the device layer. As further described below, patterning may be within a device cell (i.e., "intra-cell" patterning) or may be across device cells (i.e., "inter-cell" patterning). In some patterned etching embodiments, at least a portion of the thickness of the intervening layer is employed as a hard mask for patterning the backside device layer. Thus, the mask etching process may be performed prior to etching the corresponding masked device layer.

[0105] The above processing scheme can produce a donor-host substrate assembly including an IC device having a back side of an intervening layer, a back side of a device layer, and / or a back side of one or more semiconductor regions within a device layer, and / or an exposed front side metallization. Additional back side processing can then be performed on any of these exposed regions during downstream processing.

[0106] As described throughout the present application, the substrate can be composed of a semiconductor material that can withstand the manufacturing process and in which the charge can migrate. In an embodiment, the substrate described herein is a body substrate composed of crystalline silicon, silicon / germanium or germanium layers doped with charge carriers (such as but not limited to phosphorus, arsenic, boron or a combination thereof) to form an active region. In one embodiment, the concentration of silicon atoms in such a body substrate is greater than 97%. In another embodiment, the body substrate is composed of an epitaxial layer grown on top of a different crystalline substrate, the epitaxial layer being, for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The body substrate may alternatively be composed of III-V group materials. In an embodiment, the body substrate is composed of III-V group materials, such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide or a combination thereof. In one embodiment, the body substrate is composed of III-V group materials, and the charge carrier dopant impurity atoms are, for example, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium impurity atoms.

[0107] As described throughout this application, an isolation region, such as a shallow trench isolation region or a sub-fin isolation region, may be composed of a material suitable for ultimately electrically isolating or facilitating electrical isolation of a portion of a permanent gate structure from an underlying substrate or isolating an active region (such as an isolated fin active region) formed within an underlying substrate. For example, in one embodiment, the isolation region is composed of one or more layers of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or a combination thereof.

[0108] As described throughout the present application, the gate line or gate structure may be composed of a gate electrode stack including a gate dielectric layer and a gate electrode layer. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of, for example, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a natural oxide layer formed by the top layers of the semiconductor substrate. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion, and the lower portion is composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, a portion of the gate dielectric is a "U" shaped structure including a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially orthogonal to a top surface of the substrate.

[0109] In one embodiment, the gate electrode is composed of a metal layer, and the metal layer is, for example, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function setting filling material formed above the metal work function setting layer. Depending on whether the transistor is a PMOS transistor or an NMOS transistor, the gate electrode layer can be composed of a P-type work function metal or an N-type work function metal. In some embodiments, the gate electrode layer can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9eV and about 5.2eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may be composed of a "U"-shaped structure, the "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially orthogonal to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and not including a sidewall portion substantially orthogonal to the top surface of the substrate. In a further embodiment of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0110] As described throughout this application, a spacer associated with a gate line or electrode stack may be composed of a material suitable for ultimately electrically isolating or facilitating isolation of a permanent gate structure from an adjacent conductive contact (e.g., a self-aligned contact). For example, in one embodiment, the spacer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0111] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a dielectric or insulating material layer. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0112] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. A common example is the use of copper lines and structures, which may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Therefore, the interconnect may be a single material layer, or may be formed by several layers including a conductive liner layer and a filling layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form an interconnect. In an embodiment, the interconnect is composed of a conductive material, such as but not limited to Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or its alloy. Interconnects are sometimes also referred to as traces, wires, lines, metals, or simply interconnects in the art.

[0113] In an embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etching selectivities for each other and the underlying dielectric and metal layers. In some embodiments, the hard mask layer includes a silicon nitride layer (e.g., silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material includes a metallic substance. For example, the hard mask or other overlying material may include a nitride (e.g., titanium nitride) layer of titanium or another metal. Other materials, such as oxygen, that may be included in one or more of these layers may be in smaller amounts. Alternatively, other hard mask layers known in the art may be used, according to a particular embodiment. The hard mask layer may be formed by CVD, PVD, or other deposition methods.

[0114] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, and / or electron beam direct write (EBDW) lithography, etc. Positive tone or negative tone resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topographic mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0115] In an embodiment, the approach described herein can involve forming a contact pattern that is very well aligned with an existing gate pattern while eliminating the use of a lithography operation with a very tight registration budget. In one such embodiment, this approach enables the use of a highly selective wet etch (e.g., relative to a dry or plasma etch) to generate a contact opening. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, the approach enables the elimination of the need for other critical lithography operations for generating contact patterns as used in other approaches. In an embodiment, the trench contact grid is not patterned separately, but is formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grating is patterned but before the gate grating cuts.

[0116] In addition, the gate stack structure can be manufactured by a replacement gate process. In such a scheme, the dummy gate material such as polysilicon or silicon nitride column material can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, contrary to the earlier processing. In an embodiment, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etching process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etching process including aqueous phosphoric acid.

[0117] In an embodiment, one or more approaches described herein substantially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to obtain a structure. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for a high temperature anneal of at least a portion of the permanent gate stack. For example, in a particular such embodiment, an anneal of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius, such as after forming the gate dielectric layer. The annealing is performed before forming the permanent contact.

[0118] In some embodiments, the arrangement of the semiconductor structure or device places the gate contact on the gate line or the portion of the gate stack above the isolation region. However, this arrangement can be regarded as an inefficient use of the layout space. In another embodiment, the semiconductor device has a contact structure that contacts the portion of the gate electrode formed above the active region. Typically, before forming a gate contact structure (e.g., a via) on the active portion of the gate and in the same layer as the trench contact via (e.g., in addition to forming a gate contact structure (e.g., a via) on the active portion of the gate and in the same layer as the trench contact via), one or more embodiments of the present disclosure include first using a gate alignment trench contact process. Such a process can be implemented to form a trench contact structure for semiconductor structure manufacturing (e.g., for integrated circuit manufacturing). In an embodiment, the trench contact pattern is formed to align with an existing gate pattern. In contrast, other approaches typically involve additional lithography processes that combine selective contact etching to closely align the lithography contact pattern to the existing gate pattern. For example, another process may include patterning a polysilicon (gate) grid with a separate patterning of contact features.

[0119] It should be understood that the pitch division process and patterning scheme can be implemented to enable the embodiments described herein, or the pitch division process and patterning scheme can be included as part of the embodiments described herein. Pitch division patterning typically refers to halving the pitch, quartering the pitch, etc. The pitch division scheme can be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., strictly unidirectional or primarily unidirectional) at a predefined pitch. Then the pitch division process is implemented as a technique to increase line density.

[0120] In an embodiment, the term "grating structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a close pitch grating structure. In one such embodiment, a close pitch cannot be achieved directly by a selected lithography. For example, a pattern based on a selected lithography can be formed first, but the pitch can be halved by patterning using a spacer mask known in the art. In addition, the original pitch can be divided into four equal parts by a second round of spacer mask patterning. Therefore, the grating-like pattern described herein can have metal lines, ILD lines, or hard mask lines spaced at substantially uniform spacings and having substantially uniform widths. For example, in some embodiments, the spacing variation will be within ten percent, and the width variation will be within ten percent, and in some embodiments, the spacing variation will be within five percent, and the width variation will be within five percent. The pattern can be manufactured by halving the spacing or by quartering the spacing or by other spacing division approaches. In an embodiment, the grating is not necessarily of a single spacing.

[0121] In an embodiment, a blanket film is patterned using a lithography and etching process, which may involve, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning or pitch quartering. It should be understood that other pitch division approaches may also be implemented. In any case, in an embodiment, a grid layout may be manufactured by a selected lithography approach, such as 193nm immersion lithography (193i). Pitch division may be implemented to increase the line density in the grid layout by a factor of n. A grid layout formed using 193i lithography plus "n" times the pitch division may be designated as 193i+P / n pitch division. In one such embodiment, 193nm immersion scaling may be extended for many generations through cost-effective pitch division.

[0122] It should be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, a dummy gate need not have been formed before a gate contact is made on the active portion of the gate stack. The above-described gate stack may actually be an initially formed permanent gate stack. In addition, the processes described herein may be used to manufacture one or more semiconductor devices. The semiconductor device may be a transistor or a similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, an independently accessed dual-gate device, a FIN-FET, a nanowire, a nanobelt. One or more embodiments may be particularly suitable for manufacturing semiconductor devices at a 10 nanometer (10nm) technology node or a sub-10 nanometer (10nm) technology node.

[0123] Additional or intermediate operations for FEOL layer or structure fabrication may include standard microelectronics fabrication processes, such as photolithography, etching, thin film deposition, planarization (e.g., chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, and use of planarization stop layers, or any other actions associated with microelectronic component fabrication. Furthermore, it should be understood that the process operations described with respect to the foregoing process flows may be practiced in alternative sequences, not necessarily performing each operation, or additional process operations may be performed, or both.

[0124] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, the integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, etc. The integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the approaches disclosed herein.

[0125] Fig.13 A computing device 1300 is shown according to one embodiment of the present disclosure. The computing device 1300 houses a board 1302. The board 1302 may include a number of components, including, but not limited to, a processor 1304 and at least one communication chip 1306. The processor 1304 is physically and electrically coupled to the board 1302. In some embodiments, the at least one communication chip 1306 is also physically and electrically coupled to the board 1302. In further embodiments, the communication chip 1306 is part of the processor 1304.

[0126] Depending on its application, the computing device 1300 may include other components that may or may not be physically and electrically coupled to the board 1302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, encryption processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0127] The communication chip 1306 enables wireless communication for transmitting data to and from the computing device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not contain wires. The communication chip 1306 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing device 1300 may include multiple communication chips 1306. For example, the first communication chip 1306 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, while the second communication chip 1306 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0128] The processor 1304 of the computing device 1300 includes an integrated circuit die packaged within the processor 1304. In some embodiments of the present disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures, constructed according to embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0129] The communication chip 1306 also includes an integrated circuit die packaged within the communication chip 1306. According to another embodiment of the present disclosure, the integrated circuit die of the communication chip is constructed according to an embodiment of the present disclosure.

[0130] In further implementations, another component housed within computing device 1300 may contain an integrated circuit die constructed in accordance with implementations of embodiments of the present disclosure.

[0131] In various embodiments, computing device 1300 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, computing device 1300 may be any other electronic device that processes data.

[0132] Fig.14 An interposer 1400 is shown that includes one or more embodiments of the present disclosure. The interposer 1400 is an intermediate substrate for bridging a first substrate 1402 to a second substrate 1404. The first substrate 1402 may be, for example, an integrated circuit die. The second substrate 1404 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interposer 1400 is to extend the connection to a wider spacing or to rewire the connection to a different connection. For example, the interposer 1400 may couple the integrated circuit die to a ball grid array (BGA) 1406, which may then be coupled to the second substrate 1404. In some embodiments, the first and second substrates 1402 / 1404 are attached to opposite sides of the interposer 1400. In other embodiments, the first and second substrates 1402 / 1404 are attached to the same side of the interposer 1400. And, in further embodiments, three or more substrates are interconnected by the interposer 1400.

[0133] The interposer 1400 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further embodiments, the interposer 1400 may be formed of alternative rigid or flexible materials, which may include the same materials described above for the semiconductor substrate, such as silicon, germanium, and other III-V and IV materials.

[0134] The interposer 1400 may include metal interconnects 1408 and vias 1410, including but not limited to through silicon vias (TSVs) 1412. The interposer 1400 may also include embedded devices 1414, including both passive and active devices. The devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1400. According to embodiments of the present disclosure, the apparatus or process disclosed herein may be used to manufacture the interposer 1400 or to manufacture components included in the interposer 1400.

[0135] Fig.15is an isometric view of a mobile computing platform 1500 according to an embodiment of the present disclosure, which uses an integrated circuit (IC) manufactured according to one or more processes described herein, or includes one or more features described herein.

[0136] The mobile computing platform 1500 may be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 1500 may be any one of a tablet computer, a smart phone, a laptop computer, etc., and includes a display screen 1505, which in an exemplary embodiment is a touch screen (capacitive, inductive, resistive, etc.), a chip-level (SoC) or package-level integrated system 1510, and a battery 1513. As shown, the greater the integration in the system 1510 achieved by a higher transistor packaging density, the greater the portion of the mobile computing platform 1500 that may be occupied by the battery 1513 or non-volatile memory (e.g., a solid-state drive), or the greater the transistor gate count for improving the functionality of the platform. Similarly, the greater the carrier mobility of each transistor in the system 1510, the greater the functionality. Therefore, the techniques described herein may enable improvements in performance and form factor in the mobile computing platform 1500.

[0137] The integrated system 1510 is further shown in the enlarged view 1520. In an exemplary embodiment, the packaged device 1577 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or a graphics processor) manufactured according to one or more processes described herein, or includes one or more features described herein. The packaged device 1577 is also coupled to the board 1560 together with one or more of a power management integrated circuit (PMIC) 1515, an RF (wireless) integrated circuit (RFIC) 1525 and its controller 1511, and the RF (wireless) integrated circuit (RFIC) 1525 includes a broadband RF (wireless) transmitter and / or receiver (e.g., including a digital baseband, and the analog front-end module also includes a power amplifier on the transmit path and a low noise amplifier on the receive path). Functionally, the PMIC 1515 performs battery power regulation, DC to DC conversion, etc., and therefore has an input terminal coupled to the battery 1513, and has an output terminal that provides current supply to all other functional modules. As further shown, in an exemplary embodiment, RFIC 1525 has an output coupled to an antenna to provide implementation of any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In alternative embodiments, each of these board-level modules can be integrated into a separate IC coupled to the packaging substrate of the packaged device 1577, or integrated within a single IC (SoC) coupled to the packaging substrate of the packaged device 1577.

[0138] On the other hand, semiconductor packages are used to protect integrated circuit (IC) chips or dies and also to provide an electrical interface for the die to external circuit systems. As the demand for smaller electronic devices continues to increase, semiconductor packages are designed to be more compact and must support greater circuit density. In addition, the demand for higher performance devices has led to a need for improved semiconductor packages that enable thin package profiles and low overall warpage that is compatible with subsequent assembly processes.

[0139] In an embodiment, wire bonding to a ceramic or organic packaging substrate is used. In another embodiment, a C4 process is used to mount the die to a ceramic or organic packaging substrate. In particular, the C4 solder ball connection can be implemented to provide a flip chip interconnect between a semiconductor device and a substrate. Flip chip or controlled folded chip connection (C4) is a type of mounting for a semiconductor device (e.g., an integrated circuit (IC) chip, MEMS, or component) that utilizes solder bumps instead of wire bonding. Solder bumps are deposited on C4 pads, which are located on the top side of the substrate package. In order to mount the semiconductor device on the substrate, it is flipped so that the active side is facing down on the mounting area. Solder bumps are used to directly connect the semiconductor device to the substrate.

[0140] Fig.16 A cross-sectional view of a flip chip mounted die is shown according to an embodiment of the present disclosure.

[0141] refer to Fig.16 , apparatus 1600 includes a die 1602 according to an embodiment of the present disclosure, such as an integrated circuit (IC) manufactured according to one or more processes described herein or including one or more features described herein. The die 1602 includes metallization pads 1604 thereon. A package substrate 1606, such as a ceramic or organic substrate, includes connections 1608 thereon. The die 1602 and the package substrate 1606 are electrically connected via solder balls 1610 coupled to the metallization pads 1604 and the connections 1608. An underfill material 1612 surrounds the solder balls 1610.

[0142] Processing a flip chip can be similar to traditional IC manufacturing, with some additional operations. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically includes several treatments. Small solder bumps are then deposited on each metallized pad. The chip is then cut from the wafer as usual. To attach the flip chip to a circuit, the chip is turned upside down and the solder bumps are brought to the underlying electronic device or connector on the circuit board. The solder is then melted again to create an electrical connection, typically using an ultrasonic or alternative reflow solder process. This also leaves a small space between the chip's circuitry and the underlying mounting. In most cases, an electrically insulating adhesive is then "underfilled" to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed by differential heating of the chip and the rest of the system.

[0143] In other embodiments, newer packaging and die-to-die interconnect approaches, such as through-silicon vias (TSVs) and silicon interposers, are implemented to manufacture high-performance multi-chip modules (MCMs) and systems in packages (SiPs) that incorporate integrated circuits (ICs) manufactured according to one or more processes described herein in accordance with embodiments of the present disclosure, or include one or more features described herein.

[0144] Thus, embodiments of the present disclosure include integrated circuit structures having deep via bar isolation.

[0145] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even in the case where only a single embodiment is described for specific features. Unless otherwise stated, the examples of features provided in the present disclosure are intended to be illustrative rather than restrictive. The above description is intended to cover such substitutions, changes, and equivalents that are obvious to those skilled in the art and have the benefit of this disclosure.

[0146] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems dealt with herein. Accordingly, new claims may be made during the prosecution of the present application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims, and features from individual independent claims may be combined in any appropriate manner and not merely in the specific combinations listed in the appended claims.

[0147] The following examples relate to further embodiments. The various features of the different embodiments may be combined differently, with some features included and other features not included, to suit a variety of different applications.

[0148] Example embodiment 1: An integrated circuit structure comprising: a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures. A plurality of trench contacts extending over a plurality of source or drain structures, individual trench contacts in the plurality of trench contacts alternating with individual gate lines in the plurality of gate lines. A backside metal wiring layer extends under one or more of the plurality of gate lines and under one or more of the plurality of trench contacts. A conductive structure couples the backside metal wiring layer to one of the one or more trench contacts in the plurality of trench contacts. The conductive structure has a cutout between a first conductive structure portion and a second conductive structure portion. The cutout in a first gate line in the plurality of gate lines adjacent to the cutout in the conductive structure is smaller than the cutout in a second gate line in the plurality of gate lines adjacent to the first conductive structure portion or the second conductive structure portion.

[0149] Example Embodiment 2: The integrated circuit structure according to Example Embodiment 1, wherein the backside metal wiring layer is a backside power delivery line.

[0150] Example Embodiment 3: The integrated circuit structure according to Example Embodiment 1 or 2, wherein the conductive structure is a deep via bar structure.

[0151] Example Embodiment 4: The integrated circuit structure according to Example Embodiment 1 or 2, wherein the conductive structure is a recessed deep via bar structure.

[0152] Example Embodiment 5: The integrated circuit structure according to Example Embodiment 1, 2, 3 or 4, further comprising a dielectric plug in the cutout of the first gate line of the plurality of gate lines and in the cutout in the conductive structure.

[0153] Example embodiment 6: An integrated circuit structure comprising: a plurality of gate lines extending over a plurality of semiconductor fin structures. A plurality of trench contacts extending over a plurality of source or drain structures, individual trench contacts in the plurality of trench contacts alternating with individual gate lines in the plurality of gate lines. A backside metal wiring layer extends under one or more of the plurality of gate lines and under one or more of the plurality of trench contacts. A conductive structure couples the backside metal wiring layer to one of the one or more trench contacts in the plurality of trench contacts. The conductive structure has a cutout between a first conductive structure portion and a second conductive structure portion. The cutout in a first gate line in the plurality of gate lines that is adjacent to the cutout in the conductive structure is smaller than the cutout in a second gate line in the plurality of gate lines that is adjacent to the first conductive structure portion or the second conductive structure portion.

[0154] Example Embodiment 7: The integrated circuit structure according to Example Embodiment 6, wherein the backside metal wiring layer is a backside power delivery line.

[0155] Example Embodiment 8: The integrated circuit structure according to Example Embodiment 6 or 7, wherein the conductive structure is a deep via bar structure.

[0156] Example embodiment 9: The integrated circuit structure according to example embodiment 6 or 7, wherein the conductive structure is a recessed deep via bar structure.

[0157] Example Embodiment 10: The integrated circuit structure according to Example Embodiment 6, 7, 8 or 9, further comprising a dielectric plug in the cutout of the first gate line of the plurality of gate lines and in the cutout in the conductive structure.

[0158] Example embodiment 11: A computing device, comprising: a board; and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure including: a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures or semiconductor fin structures. A plurality of trench contacts extend over a plurality of source or drain structures, individual trench contacts in the plurality of trench contacts alternating with individual gate lines in the plurality of gate lines. A backside metal wiring layer extends under one or more of the plurality of gate lines and under one or more of the plurality of trench contacts. A conductive structure couples the backside metal wiring layer to one of the one or more trench contacts in the plurality of trench contacts. The conductive structure has a cutout between a first conductive structure portion and a second conductive structure portion. The cutout in a first gate line in the plurality of gate lines adjacent to the cutout in the conductive structure is smaller than the cutout in a second gate line in the plurality of gate lines adjacent to the first conductive structure portion or the second conductive structure portion.

[0159] Example Embodiment 12: The computing device according to Example Embodiment 11, comprising the semiconductor nanowire stack channel structure.

[0160] Example Embodiment 13: The computing device according to Example Embodiment 11, comprising the semiconductor fin structure.

[0161] Example Embodiment 14: The computing device of Example Embodiment 11, 12 or 13, further comprising a memory coupled to the board.

[0162] Example Embodiment 15: The computing device of Example Embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the board.

[0163] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14 or 15, further comprising a battery coupled to the board.

[0164] Example Embodiment 17: The computing device of Example Embodiment 11, 12, 13, 14, 15 or 16, further comprising a camera coupled to the board.

[0165] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a display coupled to the board.

[0166] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0167] Example Embodiment 20: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: A plurality of gate lines extending over the plurality of semiconductor nanowire stack channel structures; a plurality of trench contacts extending over the plurality of source or drain structures, individual trench contacts of the plurality of trench contacts alternating with individual gate lines of the plurality of gate lines; a backside metal wiring layer extending under one or more of the plurality of gate lines and under one or more of the plurality of trench contacts; as well as A conductive structure is provided to couple the back metal wiring layer to one of the one or more groove contacts in the plurality of groove contacts, the conductive structure having a cut between a first conductive structure portion and a second conductive structure portion, wherein the cut in a first gate line in the plurality of gate lines adjacent to the cut in the conductive structure is smaller than the cut in a second gate line in the plurality of gate lines adjacent to the first conductive structure portion or the second conductive structure portion.

2. The integrated circuit structure according to claim 1, wherein: The backside metal wiring layer is a backside power transmission line.

3. The integrated circuit structure according to claim 1 or 2, wherein: The conductive structure is a deep via bar structure.

4. The integrated circuit structure according to claim 1 or 2, wherein: The conductive structure is a recessed deep via bar structure.

5. The integrated circuit structure of claim 1 or 2, further comprising a dielectric plug in the cutout of the first of the plurality of gate lines and in the cutout in the conductive structure.

6. An integrated circuit structure comprising: A plurality of gate lines extending over the plurality of semiconductor fin structures; a plurality of trench contacts extending over the plurality of source or drain structures, individual trench contacts of the plurality of trench contacts alternating with individual gate lines of the plurality of gate lines; a backside metal wiring layer extending under one or more of the plurality of gate lines and under one or more of the plurality of trench contacts; as well as A conductive structure is provided to couple the back metal wiring layer to one of the one or more groove contacts in the plurality of groove contacts, the conductive structure having a cut between a first conductive structure portion and a second conductive structure portion, wherein the cut in a first gate line in the plurality of gate lines adjacent to the cut in the conductive structure is smaller than the cut in a second gate line in the plurality of gate lines adjacent to the first conductive structure portion or the second conductive structure portion.

7. The integrated circuit structure according to claim 6, wherein: The backside metal wiring layer is a backside power transmission line.

8. The integrated circuit structure according to claim 6 or 7, wherein: The conductive structure is a deep via bar structure.

9. The integrated circuit structure according to claim 6 or 7, wherein: The conductive structure is a recessed deep via bar structure.

10. The integrated circuit structure of claim 6 or 7, further comprising a dielectric plug in the cutout of the first of the plurality of gate lines and in the cutout in the conductive structure.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: A plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures or semiconductor fin structures; a plurality of trench contacts extending over the plurality of source or drain structures, individual trench contacts of the plurality of trench contacts alternating with individual gate lines of the plurality of gate lines; a backside metal wiring layer extending under one or more of the plurality of gate lines and under one or more of the plurality of trench contacts; and A conductive structure is provided to couple the back metal wiring layer to one of the one or more groove contacts in the plurality of groove contacts, the conductive structure having a cut between a first conductive structure portion and a second conductive structure portion, wherein the cut in a first gate line in the plurality of gate lines adjacent to the cut in the conductive structure is smaller than the cut in a second gate line in the plurality of gate lines adjacent to the first conductive structure portion or the second conductive structure portion.

12. The computing device of claim 11, comprising the semiconductor nanowire stack channel structure.

13. The computing device of claim 11, comprising the semiconductor fin structure.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12 or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12 or 13, further comprising: A battery coupled to the board.

17. The computing device of claim 11, 12 or 13, further comprising: A camera is coupled to the board.

18. The computing device of claim 11, 12 or 13, further comprising: A display is coupled to the panel.

19. The computing device of claim 11, 12 or 13, wherein: The component is a packaged integrated circuit die.

20. The computing device of claim 11, 12 or 13, wherein: The component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

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