EMI optimized semiconductor device

Abstract

The invention relates to an EMI (Electro-Magnetic Interference) optimized semiconductor device, which comprises an active area grid electrode bonding pad and a grid bus, an active area comprises a plurality of cells, grid electrodes are arranged in the cells, and the grid electrodes in the plurality of cells are connected in series; the gate bonding pad comprises first polycrystalline silicon and a first metal layer which are arranged in sequence; the grid bus is connected with the grid electrode bonding pad, the grid bus comprises a first part and a second part, the first part comprises second polycrystalline silicon and a second metal layer, the second part comprises third polycrystalline silicon, the second polycrystalline silicon and the third polycrystalline silicon are integrally formed, the second polycrystalline silicon is connected with the grid electrode in series, and the third polycrystalline silicon is connected with the grid electrode bonding pad. The third polycrystalline silicon is connected with the first polycrystalline silicon, a gap is reserved between the first metal layer and the second metal layer, and the terminal structure has the advantages that device turn-on oscillation can be reduced, the EMI characteristic is improved, and the design complexity and cost of a terminal circuit cannot be increased.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an EMI optimized semiconductor device. Background Art

[0002] Semiconductor devices are electronic devices with conductivity between that of good conductors and insulators. They use the special electrical properties of semiconductor materials to perform specific functions. They can be used to generate, control, receive, transform, amplify signals and perform energy conversion. With the rapid development of emerging industries such as new energy, there is an increasing demand for high-power, high-voltage, and high-reliability power semiconductor devices. Among them, superjunction devices, as a new type of power device, are widely used in high-voltage and high-power power electronic equipment due to their advantages of low on-resistance and high breakdown voltage.

[0003] A superjunction semiconductor device usually includes a gate pad and an active area. A plurality of cells are arranged in the active area. A gate is arranged in the cell, and a gate bus is also arranged, so that the signal of the gate pad is evenly transmitted to the gate of each cell. The gate pad and the gate bus are usually composed of polysilicon, a dielectric layer and a metal layer, and the gate pad and the gate bus are directly connected. A through hole is arranged on the dielectric layer to make the metal layer and the polysilicon contact. The signal of the gate pad can be directly connected to the polysilicon of the gate bus through the metal layer. Since the metal resistance is extremely low, the opening speed of the device is too fast, which is easy to cause large oscillations, and thus leads to poor electromagnetic interference (EMI) characteristic capabilities.

[0004] In order to improve these problems, in the prior art, an additional resistor is usually connected in series with the gate to reduce turn-on oscillation and thus improve EMI characteristics, but this solution increases the complexity of circuit design and manufacturing costs. Therefore, how to reduce device turn-on oscillation and optimize the device's EMI characteristics without increasing design complexity and cost has become a technical problem that needs to be solved urgently in related fields. Summary of the invention

[0005] In view of this, an object of the present invention is to provide an EMI optimized semiconductor device to solve the technical problem in the prior art of how to reduce device turn-on oscillation and improve EMI characteristics without increasing complexity and cost.

[0006] The present invention provides an EMI optimized semiconductor device, comprising:

[0007] The active region includes a plurality of cells, each of which is provided with a gate, and the gates in the plurality of cells are connected in series;

[0008] A gate pad includes a first polysilicon layer and a first metal layer arranged in sequence;

[0009] A gate bus is connected to a gate pad, the gate bus includes a first part and a second part, the first part includes a second polysilicon and a second metal layer, the second part includes a third polysilicon, the second polysilicon and the third polysilicon are integrally formed, the second polysilicon and the gate are connected in series, the third polysilicon is connected to the first polysilicon, and a gap is left between the first metal layer and the second metal layer.

[0010] Optionally, the gate bus is configured to be ring-shaped, the gate bus is disposed at the periphery of the active area and surrounds the active area, and the gate in the cell close to the inner side wall of the gate bus is connected to the gate bus.

[0011] Optionally, two second parts are provided, and the two second parts are respectively provided at two ends of the gate bus, and one end of the two second parts is connected to the second part, and the other end is connected to the gate pad.

[0012] Optionally, the length of the third polysilicon is set to 30 μm-120 μm.

[0013] Optionally, the width of the third polysilicon is 4 μm-20 μm.

[0014] Optionally, the thickness of the third polysilicon is set to 4000 angstroms-8000 angstroms.

[0015] Optionally, a first insulating dielectric layer is provided on the front side of the first polycrystalline silicon, the front side of the second polycrystalline silicon, and the front side of the third polycrystalline silicon;

[0016] A first metal contact through hole is formed on the first insulating dielectric layer at the first polysilicon, and the first metal layer extends into the first metal contact through hole until the first metal contact through hole is completely filled;

[0017] A second metal contact through hole is opened at the first insulating dielectric layer at the second polysilicon, and the second metal layer extends into the second metal contact through hole until the second metal contact through hole is completely filled.

[0018] Optionally, the semiconductor device is configured as a MOSFET device or an IGBT device.

[0019] Optionally, the cell comprises:

[0020] a first conductive type substrate;

[0021] A first conductive type epitaxial layer, disposed on a front surface of the first conductive type substrate;

[0022] A second conductive type body region is disposed on the front surface of the first conductive type epitaxial layer and is located in the first conductive type epitaxial layer;

[0023] There are at least two first conductivity type source regions, which are arranged on the front side of the second conductivity type body region and in the second conductivity type body region, and the gate is located between the two second conductivity type source regions;

[0024] A second insulating dielectric layer is disposed on the front surface of the first conductive type epitaxial layer, and a plurality of third metal contact through holes are disposed on the second insulating dielectric layer, and the third metal contact through holes are connected to the second conductive type body region and the first conductive type source region;

[0025] A front metal layer is disposed on the front side of the second insulating dielectric layer, and a portion of the front metal layer located at the third metal contact through hole extends into the third metal contact through hole until the third metal contact through hole is completely filled;

[0026] The back metal layer is arranged on the back side of the first conductive type substrate.

[0027] Optionally, at least two second conductive type columns are provided, and the second conductive type columns extend from the front side to the back side of the first conductive type epitaxial layer.

[0028] The technical solution of the present invention has the following advantages:

[0029] The EMI optimized semiconductor device provided by the present invention directly changes the gate bus so that the gate bus includes a first part and a second part, wherein the second part only includes the third polysilicon, and the first part still includes the second polysilicon and the second metal layer, and there is a gap between the first metal layer and the second metal layer, so the direct connection between the first metal layer and the second metal layer is cut off, and when the electric signal of the gate pad is applied to the first metal layer, it needs to pass through the third polysilicon to transmit the electric signal to the entire gate bus, and under the action of the first part, it is transmitted to the gate in the cell, and because the third polysilicon has a certain resistivity, the turn-on oscillation of the device is effectively reduced and the EMI characteristics are improved. At the same time, only the gate bus is changed, and the metal layer is reduced at the second part of the gate bus, and there is no need to increase the resistance, which will not affect the terminal circuit design, avoid the terminal circuit design being more complicated, and will not increase the cost. It can reduce the turn-on oscillation of the device and improve the EMI characteristics without increasing the complexity and cost of the terminal circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 A schematic diagram of the front side of a semiconductor device optimized for EMI of the present invention;

[0032] Figure 2 For the present invention Figure 1 Schematic diagram of the cross section at AA in the middle;

[0033] Figure 3 For the present invention Figure 1 Schematic diagram of the cross section at the middle BB;

[0034] Figure 4 For the present invention Figure 1 Schematic diagram of the cross section at CC;

[0035] Figure 5 Schematic diagram of the internal structure of the cell in the present invention.

[0036] Description of reference numerals:

[0037] 1. Active area; 2. Cell; 21. First conductive type substrate; 22. First conductive type epitaxial layer; 23. Second conductive type body region; 24. First conductive type source region; 25. Second insulating dielectric layer; 26. Front metal layer; 27. Back metal layer; 28. Second conductive type column; 29. ​​Gate; 3. Gate pad; 31. First polysilicon; 32. First metal layer; 4. Gate bus; 41. First part; 411. Second polysilicon; 412. Second metal layer; 42. Second part; 421. Third polysilicon; 5. First insulating dielectric layer; 6. First metal contact through hole; 7. Second metal contact through hole; 8. Third metal contact through hole; 9. Groove; 10. Shielding gate; 11. Gate oxide layer. DETAILED DESCRIPTION

[0038] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the description of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Unless otherwise clearly specified and limited, the terms "disposed", "installed", "connected" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0040] The directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inside" and "outside" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of description and simplified description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on the present invention. In addition, in the present embodiment, the top surface is set as the front surface and the bottom surface is set as the back surface.

[0041] The terms "first", "second", "third" and the like are merely used to distinguish elements of similar nature, and do not indicate or imply relative importance or a particular order.

[0042] The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of the elements listed and may also include additional elements not expressly listed.

[0043] Example

[0044] The present invention provides an EMI optimized semiconductor device, wherein the semiconductor device is configured as a MOSFET device or an IGBT device. In this embodiment, a MOSFET device is taken as an example. The MOSFET device includes an N-type MOSFET device and a P-type MOSFET device. For the N-type MOSFET device, the first conductivity type is N-type and the second conductivity type is P-type; for the P-type MOSFET device, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, an N-type MOSFET device is taken as an example.

[0045] Reference Figure 1-Figure 5 As shown, the EMI optimized semiconductor device includes an active area 1, a gate pad 3 and a gate bus 4, wherein the active area 1 includes a plurality of cells 2, the plurality of cells 2 are uniformly arranged in the active area 1, a gate 29 is arranged in the cell 2, the gates 29 in the plurality of cells 2 are connected in series, the gate pad 3 and the plurality of cells 2 are in the same plane, the gate pad 3 includes a first polysilicon 31 and a first metal layer 32 arranged layer by layer, and the gate bus 4 is connected to the gate pad 3;

[0046] Specifically, refer to Figure 1-4As shown, the gate bus 4 includes a first part 41 and a second part 42, the first part 41 is connected to the gate pad 3 through the second part 42, the first part 41 includes a second polysilicon 411 and a second metal layer 412 arranged layer by layer, the second part 42 includes a third polysilicon 421, the first polysilicon 31, the second polysilicon 411 and the third polysilicon 421 are all composed of conductive polysilicon, the second polysilicon 411 and the third polysilicon 421 are deposited and formed as a whole, the second polysilicon 411 and the gate 29 are connected in series, the third polysilicon 421 and the first polysilicon 31 are connected, at this time, the first metal layer 32 and the second metal layer 412 are separated by the third polysilicon 421, so that a gap is left between the first metal layer 32 and the second metal layer 412.

[0047] By directly changing the gate bus 4, the gate bus 4 includes a first part 41 and a second part 42, wherein the second part 42 only includes the third polysilicon 421, and the first part 41 still includes the second polysilicon 411 and the second metal layer 412, and there is a gap between the first metal layer 32 and the second metal layer 412, so the direct connection between the first metal layer 32 and the second metal layer 412 is cut off, and when the electrical signal of the gate pad 3 is applied to the first metal layer 32, the electrical signal needs to pass through the third polysilicon 421 to be transmitted to the entire gate bus 4, and under the action of the first part 41, it is transferred to the gate 29 in the cell 2. Since the third polysilicon 421 has a certain resistivity, it can effectively reduce the turn-on oscillation of the device and improve the EMI characteristics. At the same time, only the gate bus 4 is changed, and the metal layer is reduced at the second part 42 of the gate bus 4. There is no need to add additional resistance, which will not affect the terminal circuit design and avoid making the terminal circuit design more complicated. At the same time, it will not increase the cost. It can reduce the turn-on oscillation of the device and improve the EMI characteristics without increasing the complexity and cost of the terminal circuit design.

[0048] As a specific implementation, the gate bus 4 is arranged in a ring shape, and the gate bus 4 is arranged on the periphery of the active area 1 and surrounds the active area 1, and the gate 29 in the cell 2 close to the inner side wall of the gate bus 4 is connected to the gate bus 4. Specifically, the gate 29 in the cells 2 in a circle around the active area 1 will be connected to the second polysilicon 411 in the first part 41 of the gate bus 4, and any cell 2 in a circle around the active area 1 is connected to the closest side wall of the second polysilicon 411, so that the electrical signal of the gate pad 3 can be evenly transmitted to each cell 2.

[0049] There are two second parts 42, and the two second parts 42 are respectively arranged at the two ends of the gate bus 4, and the two second parts 42 are connected to the second part 42 at one end, and connected to the gate pad 3 at the other end. Specifically, a gap is left between the two second parts 42, and the gate pad 3 is located between the two second parts 42, and the first polysilicon 31 in the gate pad 3 and the third polysilicon 421 in the two second parts 42 are connected. When the electrical signal of the gate pad 3 is applied to the first metal layer 32, the electrical signal needs to pass through the third polysilicon 421 in the second part 42 to be transmitted to the entire gate bus 4, and under the action of the first part 41, it is transmitted to the gate 29 in the cell 2.

[0050] Furthermore, in the present embodiment, the length of the third polysilicon 421 is set to 30μm-120μm, the width of the third polysilicon 421 is 4μm-20μm, and the thickness of the third polysilicon 421 is set to 4000 angstroms-8000 angstroms. The length, thickness and width of the third polysilicon 421 are limited to control the resistance of the third polysilicon 421, so that the resistance of the third polysilicon 421 can meet the requirements of reducing the device turn-on oscillation and improving the EMI characteristics without affecting the performance of the device.

[0051] As a specific implementation, a first insulating dielectric layer 5 is disposed on the front side of the first polysilicon 31, and a first metal layer 32 is disposed on the front side of the first insulating dielectric layer 5 at the first polysilicon 31. A first metal contact hole 6 is provided on the first insulating dielectric layer 5 at the first polysilicon 31, and the first metal layer 32 extends into the first metal contact hole 6 until the first metal contact hole 6 is filled, so that the first metal layer 32 can be in contact with the first polysilicon 31 through the first metal contact hole 6; the front sides of the second polysilicon 411 and the third polysilicon 421 A first insulating dielectric layer 5 is also provided, and a second metal layer 412 is provided on the front side of the first insulating dielectric layer 5 at the second polysilicon 411. A second metal contact through hole 7 is provided on the first insulating dielectric layer 5 at the second polysilicon 411, and the second metal layer 412 extends into the second metal contact through hole 7 until the first metal contact through hole 6 is filled, so that the second metal layer 412 can be in contact with and connected to the second polysilicon 411; during preparation, conductive polysilicon is directly deposited to form the first polysilicon 31, the second polysilicon 411 and the third polysilicon 412 connected to each other. 21, and depositing a first insulating dielectric layer 5 on the front of the first polysilicon 31, the second polysilicon 411 and the third polysilicon 421, so that the first insulating dielectric layer 5 covers the entire front of the first polysilicon 31, the second polysilicon 411 and the third polysilicon 421, and then etching the first insulating dielectric layer 5 by photolithography shielding, etching a plurality of through holes on the first insulating dielectric layer 5 at the first polysilicon 31 and the first insulating dielectric layer 5 at the second polysilicon 411, thereby forming a first metal contact through hole 6 and a second metal contact through hole 7, and during etching, Etch a little more into the first polysilicon 31 and the second polysilicon 411 to ensure that the first insulating dielectric layer 5 can be completely removed, so that the metal contact points are exposed, ensuring the stability and reliability of the electrical connection; finally, the third polysilicon 421 is blocked again through photolithography, and metal is deposited on the front side of the first insulating dielectric layer 5 at the first polysilicon 31 and the front side of the first insulating dielectric layer 5 at the second polysilicon 411, and the first metal contact through-hole 6 and the second metal contact through-hole 7 are filled to form a first metal layer 32 and a second metal layer 412.

[0052] As another embodiment, referring to Figure 1 and 5As shown, the active area 1 is composed of a plurality of groups of cells 2, wherein the cells 2 include a first conductive type substrate 21, a first conductive type epitaxial layer 22, a first conductive type source region 24, a second insulating dielectric layer 25, a front metal layer 26 and a back metal layer 27, wherein the first conductive type substrate 21 selects N-type silicon as a substrate, the first conductive type epitaxial layer 22 is arranged on the front side of the first conductive type substrate 21, and the first conductive type epitaxial layer 22 is grown by an epitaxial process, the second conductive type body region 23 is arranged on the front side of the first conductive type epitaxial layer 22 and is located in the first conductive type epitaxial layer 22, the second conductive type body region 23 and the first conductive type epitaxial layer 22 have the same width, the first conductive type source region 24 is arranged on the front side of the second conductive type body region 23 and is located in the second conductive type body region 23, and each gate 29 corresponds to two first conductive type source regions 24, and the gate 29 is located between the two first conductive type source regions 24;

[0053] The second insulating dielectric layer 25 is arranged on the front side of the second conductive type body region 23 and covers the entire second conductive type body region 23. A plurality of third metal contact holes 8 are opened in the second insulating dielectric layer 25. The third metal contact holes 8 are connected to the second conductive type body region 23 and the first conductive type source region 24. The front metal layer 26 is arranged on the front side of the second insulating dielectric layer 25. The front metal layer 26 is located at the third metal contact hole 8 and partially extends into the third metal contact hole 8 until the third metal contact hole 8 is filled. At this time, part of the front metal layer 26 in the third metal contact hole 8 contacts the first conductive type source region 24. The back metal layer 27 is arranged on the back side of the first conductive type substrate 21 and covers the entire back side of the first conductive type substrate 21.

[0054] Furthermore, it also includes a groove 9 opened on the front side of the first conductive type epitaxial layer 22, the groove 9 extends from the front side of the first conductive type epitaxial layer 22 having the second conductive type body region 23 to the back side of the first conductive type epitaxial layer 22, until it extends to the first conductive type epitaxial layer 22 on the back side of the second conductive type body region 23, the gate 29 is located in the groove 9, a gate oxide layer 11 is arranged between the gate 29 and the inner wall of the groove 9, the gate 29 is separated from the inner wall of the groove 9 by the gate oxide layer 11, the thickness of the gate oxide layer 11 between the gate 29 and the bottom wall of the groove 9 is greater than the thickness of the gate oxide layer 11 between the gate 29 and the inner side wall of the groove 9, and the thicker gate oxide layer 11 at the bottom can improve the gate oxide reliability of the device.

[0055] As another embodiment, it also includes a shielding gate 10 arranged in the groove 9, the shielding gate 10 is located below the gate 29, and the shielding gate 10 and the inner wall of the groove 9 are also separated by the gate oxide layer 11. There is a gap between the shielding gate 10 and the gate 29 and they are also separated by the gate oxide layer 11. By setting the shielding gate 10, faster switching speed and lower switching loss can be achieved, further reducing the on-resistance and Miller capacitance, and improving the switching speed.

[0056] In addition, it includes a second conductive type column 28, two of which are provided. The second conductive type column 28 extends from the front side of the first conductive type epitaxial layer 22 having the second conductive type body region 23 to the back side of the first conductive type epitaxial layer 22, until it extends from the second conductive type body region 23 to the first conductive type epitaxial layer 22 below the second conductive type body region 23. The gate 29 is located between the two second conductive type columns 28. The two first conductive type source regions 24 are located on both sides of the groove 9 in the direction toward the second conductive type column 28, and extend toward the second conductive type column 28 and contact the second conductive type column 28. The third metal contact through hole 8 is provided correspondingly to the second conductive type column 28, and the third metal contact through hole 8 is connected to the second conductive type column 28, so that the part of the front metal layer 26 located in the third metal contact through hole 8 is in contact with the second conductive type column 28. By providing the second conductive type column 28, based on the charge balance technology, the thickness of the first conductive type epitaxial layer 22 is reduced under the same withstand voltage, thereby further reducing the on-resistance.

[0057] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. An EMI optimized semiconductor device, characterized in that: include: The active region includes a plurality of cells, each of which is provided with a gate, and the gates in the plurality of cells are connected in series; A gate pad includes a first polysilicon layer and a first metal layer arranged in sequence; A gate bus is connected to a gate pad, the gate bus includes a first part and a second part, the first part includes a second polysilicon and a second metal layer, the second part includes a third polysilicon, the second polysilicon and the third polysilicon are integrally formed, the second polysilicon and the gate are connected in series, the third polysilicon is connected to the first polysilicon, and a gap is left between the first metal layer and the second metal layer.

2. The EMI optimized semiconductor device according to claim 1, characterized in that The gate bus is arranged in a ring shape, the gate bus is arranged at the periphery of the active area and surrounds the active area, and the gate in the cell close to the inner side wall of the gate bus is connected to the gate bus.

3. The EMI optimized semiconductor device according to claim 2, characterized in that: Two second parts are provided, and the two second parts are respectively provided at two ends of the gate bus, and one end of the two second parts is connected to the second part, and the other end is connected to the gate pad.

4. The EMI optimized semiconductor device according to claim 1, characterized in that The length of the third polysilicon is set to be 30 μm-120 μm.

5. The EMI optimized semiconductor device according to claim 1, wherein: The width of the third polysilicon is 4 μm-20 μm.

6. The EMI optimized semiconductor device according to claim 1, characterized in that: The thickness of the third polysilicon is set to be 4000 angstroms-8000 angstroms.

7. The EMI optimized semiconductor device according to claim 1, characterized in that A first insulating dielectric layer is disposed on the front surface of the first polycrystalline silicon, the front surface of the second polycrystalline silicon, and the front surface of the third polycrystalline silicon; A first metal contact through hole is formed on the first insulating dielectric layer at the first polysilicon, and the first metal layer extends into the first metal contact through hole until the first metal contact through hole is completely filled; A second metal contact through hole is opened at the first insulating dielectric layer at the second polysilicon, and the second metal layer extends into the second metal contact through hole until the second metal contact through hole is completely filled.

8. The EMI optimized semiconductor device according to any one of claims 1 to 7, characterized in that: The semiconductor device is configured as a MOSFET device or an IGBT device.

9. The EMI optimized semiconductor device according to claim 1, wherein: The cell comprises: a first conductive type substrate; A first conductive type epitaxial layer, disposed on a front surface of the first conductive type substrate; A second conductive type body region is disposed on the front surface of the first conductive type epitaxial layer and is located in the first conductive type epitaxial layer; There are at least two first conductivity type source regions, which are arranged on the front side of the second conductivity type body region and in the second conductivity type body region, and the gate is located between the two second conductivity type source regions; A second insulating dielectric layer is disposed on the front surface of the first conductive type epitaxial layer, and a plurality of third metal contact through holes are disposed on the second insulating dielectric layer, and the third metal contact through holes are connected to the second conductive type body region and the first conductive type source region; A front metal layer is disposed on the front side of the second insulating dielectric layer, and a portion of the front metal layer located at the third metal contact through hole extends into the third metal contact through hole until the third metal contact through hole is completely filled; The back metal layer is arranged on the back side of the first conductive type substrate.

10. The EMI optimized semiconductor device according to claim 9, characterized in that It also includes at least two second conductive type columns, and the second conductive type columns extend from the front side to the back side of the first conductive type epitaxial layer.

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