Semiconductor epitaxial structure and preparation method thereof

Abstract

The invention provides a semiconductor epitaxial structure and a preparation method thereof, the semiconductor epitaxial structure comprises a substrate, a first arsenic-doped epitaxial layer, a non-active doping structure layer, a second arsenic-doped epitaxial layer and a phosphorus-doped epitaxial layer from bottom to top in sequence, the first arsenic-doped epitaxial layer comprises a first gradual transition layer and an epitaxial limiting layer from bottom to top in sequence, and the second arsenic-doped epitaxial layer comprises a second gradual transition layer and a phosphorus-doped limiting layer from bottom to top in sequence; and the doping concentration of the first arsenic-doped epitaxial layer is greater than that of the second arsenic-doped epitaxial layer. Through the arrangement of the first arsenic-doped epitaxial layer, the problem of smoothness of the transition region of the epitaxial layer is solved, and the purpose of improving the electrical performance and the application reliability of the device is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor epitaxial structure and a preparation method thereof. Background Art

[0002] The epitaxial process is the first step in chip manufacturing and is the basis for the formation of device structure. During the epitaxial thin film deposition process on the silicon wafer surface, the electrical parameter performance and application reliability of the device can be improved by changing the doping conditions to control the resistivity. The silicon epitaxial process is a traditional epitaxial technology with the longest application time and the widest application range.

[0003] At present, the market has put forward the demand for low conduction, high withstand voltage, and low switching loss devices such as SGT MOSFET (shielded gate trench metal oxide semiconductor field effect transistor). The performance of this device depends to a great extent on the quality of the epitaxial layer. Studies have shown that multi-layer epitaxial layers can increase the breakdown voltage, reduce the specific on-resistance, and improve the electrical performance of the device. However, the growth of multi-layer epitaxial layers faces many problems. For example, the lightly doped epitaxial layer is easily affected by self-doping such as evaporation and diffusion of impurities in the heavily doped epitaxial layer. The transition zone between different epitaxial layers is relatively flat, which affects the breakdown voltage and stability of the device. The steep and reasonably thick transition zone is an important factor in obtaining excellent device performance. In addition, due to the thin thickness of the epitaxial layer and the short reaction time, the resistivity obtained under the conventional epitaxial process is difficult to stably reach the preset value in a short time, and it is easily seriously affected by self-doping, and it is difficult to achieve distribution flatness.

[0004] Therefore, it is necessary to provide a semiconductor epitaxial structure and a preparation method thereof to solve the problem of a smooth transition zone of the epitaxial layer, and at the same time achieve a resistivity reaching a preset resistivity value in a short time, so as to increase the breakdown voltage, improve the electrical performance of the device and enhance the application reliability. Summary of the invention

[0005] The purpose of the present invention is to provide a semiconductor epitaxial structure and a preparation method thereof, so as to solve the problem of smooth transition zone of epitaxial layer and improve the electrical performance and application reliability of the device.

[0006] In order to achieve the above-mentioned purpose and other related purposes, the present invention provides a semiconductor epitaxial structure, which includes, from bottom to top: a substrate, a first arsenic-doped epitaxial layer, a non-actively doped structure layer, a second arsenic-doped epitaxial layer and a phosphorus-doped epitaxial layer, wherein the first arsenic-doped epitaxial layer includes, from bottom to top, a first gradual transition layer and an epitaxial confinement layer, and the doping concentration of the first arsenic-doped epitaxial layer is greater than the doping concentration of the second arsenic-doped epitaxial layer.

[0007] Optionally, in the semiconductor epitaxial structure, the dopants of the first arsenic-doped epitaxial layer and the second arsenic-doped epitaxial layer are both arsine, and the doping concentration of the first arsenic-doped epitaxial layer is 1E18 cm -3 ~1E20cm -3 The doping concentration of the second arsenic-doped epitaxial layer is 1E16cm -3 ~1E18cm -3 .

[0008] Optionally, in the semiconductor epitaxial structure, the dopant of the phosphorus-doped epitaxial layer is phosphine, and its doping concentration is 1E16cm -3 ~1E18cm -3 .

[0009] Optionally, in the semiconductor epitaxial structure, the second arsenic-doped epitaxial layer includes, from bottom to top, a second gradient transition layer and a first epitaxial layer; and the phosphorus-doped epitaxial layer includes, from bottom to top, a third gradient transition layer and a second epitaxial layer.

[0010] Optionally, in the semiconductor epitaxial structure, the thickness of the non-actively doped structure layer is 0.5 μm to 2 μm.

[0011] Optionally, in the semiconductor epitaxial structure, the substrate is a phosphorus-doped polished wafer, and the resistivity of the substrate is less than 1 Ohm-cm.

[0012] Optionally, in the semiconductor epitaxial structure, the semiconductor epitaxial structure further includes other epitaxial layers located on the phosphorus-doped epitaxial layer, and the number of structural layers of the other epitaxial layers is at least one.

[0013] Optionally, in the semiconductor epitaxial structure, the first arsenic-doped epitaxial layer is a heavily doped epitaxial layer, and the second arsenic-doped epitaxial layer, the phosphorus-doped epitaxial layer and the other epitaxial layers are all lightly doped epitaxial layers.

[0014] In order to achieve the above object and other related objects, the present invention also provides a method for preparing a semiconductor epitaxial structure, comprising the following steps:

[0015] providing a substrate;

[0016] Growing a first arsenic-doped epitaxial layer on the substrate, wherein the first arsenic-doped epitaxial layer comprises a first gradient transition layer and an epitaxial confinement layer grown in sequence;

[0017] A non-actively doped structure layer, a second arsenic-doped epitaxial layer and a phosphorus-doped epitaxial layer are sequentially grown on the first arsenic-doped epitaxial layer, and the doping concentration of the first arsenic-doped epitaxial layer is greater than the doping concentration of the second arsenic-doped epitaxial layer.

[0018] Optionally, in the preparation method of the semiconductor epitaxial structure, after the step of growing a non-actively doped structural layer on the first arsenic-doped epitaxial layer, the preparation method further includes: high-temperature baking the growth machine, and increasing the exhaust gas negative pressure after the high-temperature baking, while performing gas purging.

[0019] Optionally, in the method for preparing the semiconductor epitaxial structure, the temperature range of the high-temperature baking is 1100°C to 1200°C.

[0020] Optionally, in the method for preparing the semiconductor epitaxial structure, the gas used for the purge is H2.

[0021] Optionally, in the method for preparing the semiconductor epitaxial structure, after the high-temperature baking is completed, the negative pressure of the tail gas is increased to -4 torr to -8 torr.

[0022] Optionally, in the method for preparing the semiconductor epitaxial structure, during the growth of the first arsenic-doped epitaxial layer, the non-actively doped structure layer, the second arsenic-doped epitaxial layer and the phosphorus-doped epitaxial layer, the base of the growth machine always maintains a rotation speed of 45rpm to 50rpm.

[0023] Optionally, in the method for preparing the semiconductor epitaxial structure, the dopants of the first arsenic-doped epitaxial layer and the second arsenic-doped epitaxial layer are both arsine, and the doping concentration of the first arsenic-doped epitaxial layer is 1E18 cm -3 ~1E20cm -3 The doping concentration of the second arsenic-doped epitaxial layer is 1E16cm -3 ~1E18cm -3 .

[0024] Optionally, in the method for preparing the semiconductor epitaxial structure, the dopant of the phosphorus-doped epitaxial layer is phosphine, and its doping concentration is 1E16cm -3 ~1E18cm -3 .

[0025] Optionally, in the method for preparing the semiconductor epitaxial structure, the second arsenic-doped epitaxial layer includes a second gradient transition layer and a first epitaxial layer grown sequentially; the phosphorus-doped epitaxial layer includes a third gradient transition layer and a second epitaxial layer grown sequentially.

[0026] Optionally, in the method for preparing the semiconductor epitaxial structure, the thickness of the non-actively doped structure layer is 0.5 μm to 2 μm.

[0027] Optionally, in the method for preparing the semiconductor epitaxial structure, the substrate is a phosphorus-doped polished wafer, and the resistivity of the substrate is less than 1 Ohm-cm.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] The present invention adopts the first arsenic-doped epitaxial layer as a limiting layer and utilizes the characteristics of arsenic in silicon, such as high solubility, large segregation coefficient, and small diffusion coefficient, to achieve the preparation of a thin low-resistance epitaxial layer, inhibit the influence of P atom diffusion and evaporation in the substrate on the lightly doped epitaxial layer, thereby obtaining an epitaxial layer with a steep transition zone, and at the same time can achieve the purpose of achieving a preset resistivity value in a short time, thereby increasing the breakdown voltage, and improving the electrical performance of the device and the application reliability.

[0030] Secondly, the present invention can absorb impurities remaining in the production machine by setting a non-actively doped structure layer between the first arsenic-doped epitaxial layer and the second arsenic-doped epitaxial layer, and at the same time can inhibit the diffusion and evaporation of arsenic atoms in the first arsenic-doped epitaxial layer, thereby reducing the influence of the heavily doped epitaxial layer on the lightly doped epitaxial layer.

[0031] Moreover, the present invention can quickly and thoroughly discharge impurities remaining in the cavity of the production machine by high-temperature baking after epitaxial growth of the non-actively doped structural layer, increasing the exhaust gas negative pressure and hydrogen purge, inhibiting the interaction and self-doping effect between epitaxial layers of different doping concentrations, improving the uniformity of the thickness and resistivity parameters of the epitaxial layer, greatly reducing the probability of lattice defects, and thereby obtaining an epitaxial layer with a steep transition zone. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic structural diagram of a semiconductor epitaxial structure according to an embodiment of the present invention;

[0033] Figure 2 is a flow chart of a method for preparing a semiconductor epitaxial structure according to an embodiment of the present invention;

[0034] Figure 1 to Figure 2 middle:

[0035] 10-substrate, 20-first arsenic-doped epitaxial layer, 201-first gradient transition layer, 202-epitaxial restriction layer, 30-non-actively doped structure layer, 40-second arsenic-doped epitaxial layer, 401-second gradient transition layer, 402-first epitaxial layer, 50-phosphorus-doped epitaxial layer, 501-third gradient transition layer, 502-second epitaxial layer. DETAILED DESCRIPTION

[0036] The semiconductor epitaxial structure and the method for preparing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0037] See also Figure 1 The present invention provides a semiconductor epitaxial structure, which includes, from bottom to top, a substrate 10, a first arsenic-doped epitaxial layer 20, a non-actively doped structure layer 30, a second arsenic-doped epitaxial layer 40 and a phosphorus-doped epitaxial layer 50.

[0038] In this embodiment, the semiconductor epitaxial structure is preferably a heavily arsenic-doped multilayer silicon epitaxial structure. The first arsenic-doped epitaxial layer 20 is a heavily doped epitaxial layer, and the first arsenic-doped epitaxial layer 20 may include a first gradient transition layer 201 and an epitaxial restriction layer 202 from bottom to top. This embodiment adopts the first arsenic-doped epitaxial layer 20 as a restriction layer, and utilizes the characteristics of arsenic in silicon such as high solubility, large segregation coefficient, and small diffusion coefficient to achieve the preparation of a thin layer of low-resistance epitaxial layer, inhibit the diffusion and evaporation of P (phosphorus) atoms in the substrate 10 on the lightly doped epitaxial layer (such as the second arsenic-doped epitaxial layer 40 and the phosphorus-doped epitaxial layer 50), thereby obtaining an epitaxial layer with a steep transition zone, and at the same time, it can also achieve the purpose of achieving a preset resistivity value in a short time, improving the breakdown voltage, and improving the electrical performance of the device and the reliability of application.

[0039] In this embodiment, a non-actively doped structure layer 30 is provided between the first arsenic-doped epitaxial layer 20 and the second arsenic-doped epitaxial layer 40, and the non-actively doped structure layer 30 may be a cap layer. In this embodiment, the provision of the non-actively doped structure layer 30 can further suppress the generation of impurities, and at the same time, can also suppress the diffusion and evaporation of arsenic atoms in the first arsenic-doped epitaxial layer 20, and reduce the influence of the heavily doped epitaxial layer (i.e., the first arsenic-doped epitaxial layer 20) on the lightly doped epitaxial layer (e.g., the second arsenic-doped epitaxial layer 40 and the phosphorus-doped epitaxial layer 50). In this embodiment, after the non-actively doped structure layer 30 is grown, the machine is subjected to high-temperature baking, and after the high-temperature baking, the negative pressure of the exhaust gas is increased, and gas purging is performed at the same time. In this embodiment, by high-temperature baking after the epitaxial growth of the non-actively doped structural layer 30, the negative pressure of the exhaust gas and the hydrogen purge are increased, so that the impurities remaining in the cavity of the production machine can be quickly and completely discharged, the interaction and self-doping effect between the epitaxial layers of different doping concentrations can be suppressed, the uniformity of the thickness and resistivity parameters of the epitaxial layer is improved, the probability of lattice defects is greatly reduced, and an epitaxial layer with a steep transition zone is obtained.

[0040] In this embodiment, the second arsenic-doped epitaxial layer 40 is a lightly doped epitaxial layer, and the doping concentration of the first arsenic-doped epitaxial layer 20 is greater than the doping concentration of the second arsenic-doped epitaxial layer 40. The second arsenic-doped epitaxial layer 40 may include a second gradient transition layer 401 and a first epitaxial layer 402 from bottom to top; the phosphorus-doped epitaxial layer 50 is a lightly doped epitaxial layer, which may include a third gradient transition layer 501 and a second epitaxial layer 502 from bottom to top. In this embodiment, the device-related functions can be realized through the second arsenic-doped epitaxial layer 40 and the phosphorus-doped epitaxial layer 50.

[0041] In other embodiments, the semiconductor epitaxial structure may further include other epitaxial layers located on the phosphorus-doped epitaxial layer 50, and the number of structural layers of the other epitaxial layers is at least one. The structure of the other epitaxial layers and the number of structural layers may be adjusted according to the actual process requirements. For example, the other epitaxial layers may also be structural layers formed by alternating growth of the first structural layer and the second structural layer, the first structural layer being the same as the second arsenic-doped epitaxial layer 40, and the second structural layer being the same as the phosphorus-doped epitaxial layer 50. The number of epitaxial layers in the semiconductor epitaxial structure may be adjusted according to actual requirements, but only the first epitaxial layer is heavily arsenic-doped epitaxial (i.e., the first arsenic-doped epitaxial layer 20), the second arsenic-doped epitaxial layer 40, the phosphorus-doped epitaxial layer 50, and the other epitaxial layers are all lightly doped epitaxial layers, and the non-actively doped structural layer 30 is grown between the first arsenic-doped epitaxial layer 20 and the lightly doped epitaxial layer.

[0042] See also Figure 2 The method for preparing the semiconductor epitaxial structure of this embodiment may include the following steps:

[0043] Step S1: providing a substrate 10;

[0044] Step S2: growing a first arsenic-doped epitaxial layer 20 on the substrate 10, wherein the first arsenic-doped epitaxial layer 20 comprises, from bottom to top, a first gradient transition layer 201 and an epitaxial restriction layer 202 grown sequentially;

[0045] Step S3 : sequentially growing a non-actively doped structure layer 30 , a second arsenic-doped epitaxial layer 40 and a phosphorus-doped epitaxial layer 50 on the first arsenic-doped epitaxial layer 20 , wherein the doping concentration of the first arsenic-doped epitaxial layer 20 is greater than the doping concentration of the second arsenic-doped epitaxial layer 40 .

[0046] The production equipment (machine) of the semiconductor epitaxial structure of this embodiment is preferably a flat-plate CVD epitaxial furnace, but is not limited thereto.

[0047] Execute step S1 to provide a substrate 10. The substrate 10 is preferably a phosphorus-doped polishing sheet, and further preferably a heavily phosphorus-doped polishing sheet, and the specific doping concentration is provided by the manufacturer. Furthermore, the substrate 10 is preferably an edge-polished substrate, but is not limited thereto. The heavily phosphorus-doped substrate and the edge-polished substrate are used in this embodiment to suppress the overflow of impurities from the back and edges of the substrate 10 during the high-temperature process of the subsequent preparation process of the semiconductor epitaxial structure. The thickness of the substrate 10 is not limited, and the resistivity parameter can be unlimited. Furthermore, the resistivity of the substrate 10 (i.e., the heavily phosphorus-doped polishing sheet) is preferably <1Ohm-cm.

[0048] Step S2 is performed to grow a first arsenic-doped epitaxial layer 20 on the substrate 10. The dopant of the first arsenic-doped epitaxial layer 20 is preferably arsine (AsH3), and the first arsenic-doped epitaxial layer 20 is a heavily doped epitaxial layer, and its doping concentration is preferably 1E18cm -3 ~1E20cm -3 The first arsenic-doped epitaxial layer 20 is preferably a silicon epitaxial layer. The first arsenic-doped epitaxial layer 20 can utilize the characteristics of arsenic atoms in silicon, such as large solubility, large segregation coefficient, and small diffusion coefficient, to form a thin low-resistivity epitaxial layer in a short time, and at the same time can inhibit the influence of the diffusion and evaporation of P atoms in the heavily phosphorus-doped substrate (i.e., substrate 10) on the lightly doped epitaxial layer, shorten the width of the epitaxial layer transition zone, and the steep transition zone formed can improve the electrical parameter performance and application reliability of the device.

[0049] In this embodiment, the first arsenic-doped epitaxial layer 20 may include a first gradient transition layer 201 and an epitaxial restriction layer 202 grown sequentially. The thickness of the first arsenic-doped epitaxial layer 20 is preferably 1 μm to 5 μm; the thickness of the first gradient transition layer 201 is determined by the width of the transition region between epitaxial layers, which is not described in detail here; the thickness of the epitaxial restriction layer 202 is preferably 0.5 μm to 4.5 μm.

[0050] In this embodiment, the growth temperature of the first arsenic-doped epitaxial layer 20 is preferably 1000° C. to 1150° C. For example, a flat-plate CVD epitaxial furnace is used to grow the first arsenic-doped epitaxial layer 20 with a thickness of 2.2 μm at a temperature of 1100° C.

[0051] Execute step S3 to grow a non-actively doped structure layer 30 on the first arsenic-doped epitaxial layer 20. The material of the non-actively doped structure layer 30 is preferably a silicon epitaxial material. The non-actively doped structure layer 30 is not doped with any element, and can absorb impurities remaining in the production machine. At the same time, it can inhibit the diffusion and evaporation of arsenic atoms in the first arsenic-doped epitaxial layer 20, and reduce the influence of the heavily doped epitaxial layer (i.e., the first arsenic-doped epitaxial layer 20) on the lightly doped epitaxial layer (e.g., the second arsenic-doped epitaxial layer 40 and the phosphorus-doped epitaxial layer 50).

[0052] In this embodiment, the thickness of the non-actively doped structure layer 30 is preferably 0.5 μm to 2 μm. The growth temperature of the non-actively doped structure layer 30 is preferably 1000° C. to 1150° C. For example, the non-actively doped structure layer 30 with a thickness of 1 μm is grown at a temperature of 1100° C. using the same flat-plate CVD epitaxial furnace.

[0053] After the step of growing the non-active doping structure layer 30, the method for preparing the semiconductor epitaxial structure may further include: high-temperature baking the growth machine, and increasing the tail gas negative pressure after the high-temperature baking, and performing gas purging at the same time. In this embodiment, the temperature range of the high-temperature baking is preferably 1100°C to 1200°C; the gas used for the purging is preferably H2; and the tail gas negative pressure is increased to -4torr to -8torr after the high-temperature baking. That is, after growing the non-active doping structure layer 30, the reaction chamber temperature of the flat-plate CVD epitaxial furnace is increased to 1100°C to 1200°C to perform high-temperature baking on the chamber, and the baking time is preferably 60s to 180s; after the baking is completed, the tail gas negative pressure is increased from -2torr to -4torr to -4torr to -8torr, and H2 is used to purge the chamber, and the purge time is preferably 60s to 180s. For example, the chamber of the flat-plate CVD epitaxial furnace is baked at 1150°C for 120 seconds; then, the tail gas negative pressure is increased to -6torr, and the chamber is purged with H2 for 100 seconds. This embodiment further evaporates the impurities remaining inside the chamber and the base through high-temperature baking; the pressure difference between the inside and outside of the chamber is increased by increasing the tail gas negative pressure, and the gaseous impurities are discharged more thoroughly by purging, thereby reducing the self-doping of the next epitaxial layer and shortening the width of the transition zone.

[0054] After the gas purging step, a second arsenic-doped epitaxial layer 40 is grown on the non-actively doped structure layer 30. The dopant of the second arsenic-doped epitaxial layer 40 is preferably arsine. The doping concentration of the second arsenic-doped epitaxial layer 40 is greater than the doping concentration of the first arsenic-doped epitaxial layer 20, and the doping concentration of the second arsenic-doped epitaxial layer 40 is preferably 1E16cm -3 ~1E18cm -3 The second arsenic-doped epitaxial layer 40 is preferably a silicon epitaxial layer.

[0055] In this embodiment, the second arsenic-doped epitaxial layer 40 may include a second gradually-changing transition layer 401 and a first epitaxial layer 402 grown sequentially. The thickness of the second arsenic-doped epitaxial layer 40 may be set according to the thickness of the lightly-doped epitaxial layer in the existing silicon epitaxial layer, which is not described in detail here; the thickness of the second gradually-changing transition layer 401 is determined by the width of the transition region between epitaxial layers, that is, by the process requirements, which is not described in detail here; the thickness of the first epitaxial layer 402 may be set according to the thickness of the existing epitaxial layer, which is not described in detail here.

[0056] In this embodiment, the growth temperature of the second arsenic-doped epitaxial layer 40 is preferably 1000° C. to 1150° C. For example, the second arsenic-doped epitaxial layer 40 is grown at a temperature of 1100° C. using a flat-plate CVD epitaxial furnace.

[0057] After the step of growing the second arsenic-doped epitaxial layer 40, a phosphorus-doped epitaxial layer 50 is grown on the second arsenic-doped epitaxial layer 40. The phosphorus-doped epitaxial layer 50 is a lightly doped epitaxial layer, and its dopant is preferably phosphine (PH3). The doping concentration of the phosphorus-doped epitaxial layer 50 is preferably 1E16 cm -3 ~1E18cm -3 The phosphorus-doped epitaxial layer 50 is preferably a silicon epitaxial layer.

[0058] In this embodiment, the phosphorus-doped epitaxial layer 50 may include a third gradual transition layer 501 and a second epitaxial layer 502 grown sequentially. The thickness of the phosphorus-doped epitaxial layer 50 may be set according to the thickness of the lightly doped epitaxial layer in the existing silicon epitaxial layer, which is not described in detail here; the thickness of the third gradual transition layer 501 is determined by the width of the transition region between epitaxial layers, that is, by the process requirements, which is not described in detail here; the thickness of the second epitaxial layer 502 may be set according to the thickness of the existing epitaxial layer, which is not described in detail here.

[0059] In this embodiment, the growth temperature of the phosphorus-doped epitaxial layer 50 is preferably 1000° C. to 1150° C. For example, a flat-plate CVD epitaxial furnace is used to grow the phosphorus-doped epitaxial layer 50 at a temperature of 1100° C.

[0060] In this embodiment, during the growth of the first arsenic-doped epitaxial layer 20, the non-actively doped structure layer 30, the second arsenic-doped epitaxial layer 40, and the phosphorus-doped epitaxial layer 50, the base of the growth machine always maintains a rotation speed of 45 rpm to 50 rpm. If the rotation speed of the base is too low, it may affect the resistivity and uneven film thickness distribution, and if the rotation speed is too high, it may cause the epitaxial wafer to overlap and be scrapped.

[0061] In summary, the present invention utilizes the first arsenic-doped epitaxial layer as a limiting layer to realize the preparation of a thin low-resistance epitaxial layer, and suppresses the influence of the diffusion and evaporation of P atoms in the heavily phosphorus-doped substrate on the lightly doped epitaxial layer; the generation of impurities is further suppressed by the non-actively doped structural layer; the present invention increases the negative pressure of the exhaust gas and the hydrogen purge through high-temperature baking after the growth of the non-actively doped structural layer, quickly and thoroughly discharges the impurities remaining in the production machine cavity, suppresses the interaction and self-doping effect between epitaxial layers with different doping concentrations, improves the uniformity of epitaxial thickness and resistivity parameters, greatly reduces the probability of lattice defects, and obtains an epitaxial layer with a steep transition zone; and the present invention realizes device-related functions through the second arsenic-doped epitaxial layer and the phosphorus-doped epitaxial layer.

[0062] In addition, it is understood that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0063] It should also be understood that the present invention is not limited to the specific methods, compounds, materials, manufacturing techniques, usages and applications described herein, which may vary. It should also be understood that the terms described herein are only used to describe specific embodiments, rather than to limit the scope of the present invention. It must be noted that the singular forms "one", "a kind" and "the" used herein and in the appended claims include plural references unless the context clearly indicates the opposite meaning. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates the opposite meaning. The structure described herein will be understood to also quote the functional equivalent of the structure. Language that can be interpreted as approximate should be understood as such, unless the context clearly indicates the opposite meaning.

Claims

1. A semiconductor epitaxial structure, characterized in that: From bottom to top, it includes: a substrate, a first arsenic-doped epitaxial layer, a non-actively doped structure layer, a second arsenic-doped epitaxial layer and a phosphorus-doped epitaxial layer, wherein the first arsenic-doped epitaxial layer includes, from bottom to top, a first gradual transition layer and an epitaxial confinement layer, and the doping concentration of the first arsenic-doped epitaxial layer is greater than the doping concentration of the second arsenic-doped epitaxial layer.

2. The semiconductor epitaxial structure according to claim 1, characterized in that: The dopants of the first arsenic-doped epitaxial layer and the second arsenic-doped epitaxial layer are both arsine, and the doping concentration of the first arsenic-doped epitaxial layer is 1E18 cm -3 ~1E20cm -3 The doping concentration of the second arsenic-doped epitaxial layer is 1E16cm -3 ~1E18cm -3 .

3. The semiconductor epitaxial structure according to claim 1, characterized in that: The dopant of the phosphorus-doped epitaxial layer is phosphine, and its doping concentration is 1E16cm -3 ~1E18cm -3 .

4. The semiconductor epitaxial structure according to claim 1, characterized in that: The second arsenic-doped epitaxial layer includes, from bottom to top, a second gradual transition layer and a first epitaxial layer in sequence; the phosphorus-doped epitaxial layer includes, from bottom to top, a third gradual transition layer and a second epitaxial layer in sequence.

5. The semiconductor epitaxial structure according to claim 1, wherein: The thickness of the non-actively doped structure layer is 0.5 μm to 2 μm.

6. The semiconductor epitaxial structure according to claim 1, characterized in that: The substrate is a phosphorus-doped polished sheet, and the resistivity of the substrate is less than 1 Ohm-cm.

7. The semiconductor epitaxial structure according to claim 1, characterized in that: The semiconductor epitaxial structure further includes other epitaxial layers located on the phosphorus-doped epitaxial layer, and the number of structural layers of the other epitaxial layers is at least one.

8. The semiconductor epitaxial structure according to claim 7, characterized in that: The first arsenic-doped epitaxial layer is a heavily doped epitaxial layer, and the second arsenic-doped epitaxial layer, the phosphorus-doped epitaxial layer and the other epitaxial layers are all lightly doped epitaxial layers.

9. A method for preparing a semiconductor epitaxial structure, characterized in that: The following steps are involved: providing a substrate; Growing a first arsenic-doped epitaxial layer on the substrate, wherein the first arsenic-doped epitaxial layer comprises a first gradient transition layer and an epitaxial confinement layer grown in sequence; A non-actively doped structure layer, a second arsenic-doped epitaxial layer and a phosphorus-doped epitaxial layer are sequentially grown on the first arsenic-doped epitaxial layer, and the doping concentration of the first arsenic-doped epitaxial layer is greater than the doping concentration of the second arsenic-doped epitaxial layer.

10. The method for preparing a semiconductor epitaxial structure according to claim 9, characterized in that: After the step of growing a non-actively doped structural layer on the first arsenic-doped epitaxial layer, the preparation method further comprises: high-temperature baking the growth machine, and after the high-temperature baking, increasing the negative pressure of the tail gas and performing gas purging at the same time.

11. The method for preparing a semiconductor epitaxial structure according to claim 10, characterized in that: The temperature range of the high temperature baking is 1100°C to 1200°C.

12. The method for preparing a semiconductor epitaxial structure according to claim 10, characterized in that: The gas used for the purge is H2.

13. The method for preparing a semiconductor epitaxial structure according to claim 10, characterized in that: After the high temperature baking is completed, the exhaust gas negative pressure is increased to -4torr~-8torr.

14. The method for preparing a semiconductor epitaxial structure according to claim 9, characterized in that: During the growth of the first arsenic-doped epitaxial layer, the non-actively doped structural layer, the second arsenic-doped epitaxial layer and the phosphorus-doped epitaxial layer, the base of the growth machine always maintains a rotation speed of 45 rpm to 50 rpm.

15. The method for preparing a semiconductor epitaxial structure according to claim 9, characterized in that: The dopants of the first arsenic-doped epitaxial layer and the second arsenic-doped epitaxial layer are both arsine, and the doping concentration of the first arsenic-doped epitaxial layer is 1E18 cm -3 ~1E20cm -3 The doping concentration of the second arsenic-doped epitaxial layer is 1E16cm -3 ~1E18cm -3 .

16. The method for preparing a semiconductor epitaxial structure according to claim 9, characterized in that: The dopant of the phosphorus-doped epitaxial layer is phosphine, and its doping concentration is 1E16cm -3 ~1E18cm -3 .

17. The method for preparing a semiconductor epitaxial structure according to claim 9, characterized in that: The second arsenic-doped epitaxial layer includes a second gradient transition layer and a first epitaxial layer grown in sequence; the phosphorus-doped epitaxial layer includes a third gradient transition layer and a second epitaxial layer grown in sequence.

18. The method for preparing a semiconductor epitaxial structure according to claim 9, characterized in that: The thickness of the non-actively doped structure layer is 0.5 μm to 2 μm.

19. The method for preparing a semiconductor epitaxial structure according to claim 9, characterized in that: The substrate is a phosphorus-doped polished sheet, and the resistivity of the substrate is less than 1 Ohm-cm.

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