Digital circuit and microprocessor chip

Abstract

The invention provides a digital circuit and a microprocessor chip, the digital circuit comprises one or more transistors, and at least one transistor in the one or more transistors fails, so that the digital circuit is adjusted from a first functional circuit to a second functional circuit. Since the transistors are not obviously different in physical appearance before and after modification, the digital circuit can be camouflaged by modifying at least one transistor into a failure device, the problem that the difficulty of reverse engineering is increased due to the fact that a third party cracks the digital circuit through an image acquisition method is avoided, and the reliability of the digital circuit is improved. And the digital circuit is prevented from being copied or plagiarized as much as possible.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a digital circuit and a microprocessor chip. Background Art

[0002] Digital circuits are circuits composed of basic logic elements such as logic gates and triggers, which are used to process and transmit digital signals. Digital circuits are widely used in integrated circuits because of their high integration, small size, and low power consumption. For some digital circuits, such as NAND gate circuits, the structure is relatively simple, which makes it easy to be cracked through integrated circuit reverse engineering technology, thereby obtaining the digital circuit structure inside the chip. Furthermore, the functions of digital circuits are simulated and verified by electronic design automation (EDA) tools, making digital circuits easy to copy or plagiarize.

[0003] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0004] The present application provides a digital circuit and a microprocessor chip, so as to solve the problem in the prior art that digital circuits are easily copied or plagiarized.

[0005] In a first aspect, an embodiment of the present application provides a digital circuit, including:

[0006] One or more transistors, at least one of the one or more transistors fails, so that the digital circuit is adjusted from the first functional circuit to the second functional circuit. Since there is no obvious difference in physical appearance before and after the transistor is modified, by modifying at least one transistor to a failed device, the digital circuit can be camouflaged to prevent a third party from cracking the digital circuit through image acquisition methods, increase the difficulty of reverse engineering, and prevent the digital circuit from being copied or plagiarized as much as possible.

[0007] In a possible implementation, the at least one transistor fails, including: the doping type of a partial region of the at least one transistor changes, so that the at least one transistor fails. Since different types of doping regions are difficult to distinguish in physical appearance, the difficulty of reverse engineering can be further increased by changing the doping type of a partial region of the transistor to make the transistor fail.

[0008] In a possible implementation manner, the doping type is changed, including: adjusting from P-type doping to N-type doping; or adjusting from N-type doping to P-type doping.

[0009] In one possible implementation, the at least one transistor includes: a PMOS tube, the source of which is adjusted from P-type doping to N-type doping, so that the PMOS tube fails; and / or an NMOS tube, the drain of which is adjusted from N-type doping to P-type doping, so that the NMOS tube fails.

[0010] In a possible implementation manner, the first functional circuit is a NAND gate circuit, and the second functional circuit is an inverter circuit.

[0011] In a possible implementation, the digital circuit includes:

[0012] a first PMOS tube, wherein a gate of the first PMOS tube is used to connect to a first signal input terminal, a source of the first PMOS tube is used to connect to a power supply terminal, and a drain of the first PMOS tube is used to connect to a signal output terminal;

[0013] a second PMOS tube, wherein the gate of the second PMOS tube is used to connect to the second signal input terminal, the source of the second PMOS tube is used to connect to the power supply terminal, and the drain of the second PMOS tube is used to connect to the signal output terminal;

[0014] a first NMOS transistor, wherein a gate of the first NMOS transistor is used to connect to the first signal input terminal, and a drain of the first NMOS transistor is used to connect to the signal output terminal;

[0015] a second NMOS transistor, wherein the gate of the second NMOS transistor is used to connect to the second signal input terminal, the drain of the second NMOS transistor is electrically connected to the source of the first NMOS transistor, and the source of the first NMOS transistor is used to connect to the ground terminal;

[0016] The source of the second PMOS tube is adjusted from P-type doping to N-type doping and the drain of the second NMOS tube is adjusted from N-type doping to P-type doping, so that the digital circuit is adjusted from a NAND gate circuit to an inverter circuit.

[0017] In a possible implementation, the layout structure of the digital circuit includes:

[0018] An N-well region, wherein a first N-type doping region, a first P-type doping region, and a second P-type doping region are sequentially arranged in a first direction and extend in a second direction, and the first direction is perpendicular to the second direction;

[0019] A P-well region, wherein a second N-type doping region, a third P-type doping region, a third N-type doping region and a fourth N-type doping region are sequentially arranged along the first direction and extend along the second direction;

[0020] a first polysilicon region, wherein the first polysilicon region extends along the second direction, a first end of the first polysilicon region is located between the first N-type doping region and the first P-type doping region, and a second end of the first polysilicon region is located between the second N-type doping region and the third P-type doping region;

[0021] a second polysilicon region, wherein the second polysilicon region extends along the second direction, a first end of the second polysilicon region is located between the first P-type doping region and the second P-type doping region, and a second end of the second polysilicon region is located between the third N-type doping region and the fourth N-type doping region;

[0022] a first metal wire, wherein a first end of the first metal wire is connected to the first N-type doping region through a connecting hole, and a second end of the first metal wire is connected to a power supply terminal;

[0023] a second metal wire, wherein a first end of the second metal wire is connected to the second P-type doping region through a connecting hole, and a second end of the second metal wire is connected to a power supply terminal;

[0024] a third metal wire, wherein a first end of the third metal wire is connected to the second N-type doping region through a connecting hole, and a second end of the third metal wire is connected to a ground terminal;

[0025] a fourth metal wire, wherein a first end of the fourth metal wire is connected to the first P-type doping region through a connection hole, a second end of the fourth metal wire is connected to the fourth N-type doping region through a connection hole, and the fourth metal wire is connected to the signal output terminal;

[0026] a fifth metal wire, wherein a first end of the fifth metal wire is connected to the third P-type doping region through a connection hole, and a second end of the fifth metal wire is connected to the third N-type doping region through a connection hole;

[0027] a sixth metal wire, wherein a first end of the sixth metal wire is connected to the first polysilicon through a connection hole, and a second end of the sixth metal wire is connected to the first signal input terminal;

[0028] A seventh metal wire, wherein a first end of the seventh metal wire is connected to the second polysilicon through a connection hole, and a second end of the seventh metal wire is connected to the second signal input end.

[0029] In a second aspect, an embodiment of the present application provides a microprocessor chip, including:

[0030] At least one digital circuit as described in any one of the first aspects.

[0031] In a possible implementation, the present invention further includes: a processing module, wherein at least one of the digital circuits is configured in the processing module to execute logic operations in the processing module.

[0032] In a possible implementation, the present invention further includes: a security module, wherein at least one of the digital circuits is configured in the security module for performing security protection on a target signal path in the microprocessor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0034] Figure 1 A layout of a NAND gate circuit in the related art;

[0035] Figure 2 for Figure 1 The equivalent circuit diagram of the NAND gate circuit shown;

[0036] Figure 3 A layout of a digital circuit provided in an embodiment of the present application;

[0037] Figure 4 for Figure 3 Equivalent circuit diagram of the digital circuit shown;

[0038] Figure 5 A schematic diagram of the structure of a microprocessor chip provided in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of the structure of another microprocessor chip provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of the structure of another microprocessor chip provided in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of the structure of another microprocessor chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0043] It should be clear that the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are protected by this application.

[0044] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0045] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0046] In view of the problem that digital circuits in the prior art are easily copied or plagiarized, an embodiment of the present application provides a digital circuit, including one or more transistors, and at least one of the one or more transistors is modified into a failed device, so that the digital circuit is adjusted from a first functional circuit to a second functional circuit. That is to say, before at least one transistor is modified into a failed device, the digital circuit has a first function; after at least one transistor is modified into a failed device, the digital circuit has a second function. Since there is no obvious difference in physical appearance before and after the transistor is modified, by modifying at least one transistor into a failed device, the digital circuit can be disguised, that is, the digital circuit with the second function (second functional circuit) is disguised as a digital circuit with the first function (first functional circuit), so as to prevent a third party from cracking the digital circuit through image acquisition methods, thereby increasing the difficulty of reverse engineering.

[0047] In the manufacturing process of integrated circuits, the doping process is a key step. Different doping regions can be formed on silicon wafers by different doping types. For example, N-type doping regions and P-type doping regions. In integrated circuit reverse engineering, it is difficult to distinguish between different types of doping regions. The main reason is that although different types of doping regions have different chemical compositions (N-type doping regions are doped with N-type impurities, and P-type doping regions are doped with P-type impurities), these chemical differences are not easy to reflect in physical appearance. The color and texture of different types of doping regions may be very similar, making it difficult to distinguish them by visual observation alone. For example, under an ordinary optical microscope, different types of doping regions look almost the same on a silicon wafer.

[0048] Based on this, in a possible implementation, in order to further increase the difficulty of reverse engineering, the transistor is rendered inoperable by changing the doping type of a part of the transistor. In practical applications, the doping types of transistors generally include N-type doping and P-type doping. Accordingly, changing the doping type of a part of the transistor may specifically include: adjusting the doping type of a part of the transistor from P-type doping to N-type doping; or, adjusting the doping type of a part of the transistor from N-type doping to P-type doping. It should be pointed out that with the development of semiconductor technology, in addition to N-type doping and P-type doping, there may be other doping types, and the embodiments of the present application do not impose specific restrictions on this.

[0049] The "transistor failure" involved in the embodiments of the present application refers to the transistor losing its original function. For example, when the transistor is a PMOS tube, after the source of the PMOS tube is adjusted from P-type doping to N-type doping, the PMOS tube is rendered inoperative, that is, the adjusted device does not have the function of the PMOS tube. It is understandable that the PMOS tube can also be rendered inoperative by changing the doping type of other regions (for example, the drain) of the PMOS tube. For another example, after the drain of the NMOS tube is adjusted from N-type doping to P-type doping, the NMOS tube is rendered inoperative, that is, the adjusted device does not have the function of the NMOS tube. It is understandable that the NMOS tube can also be rendered inoperative by changing the doping type of other regions (for example, the source) of the NMOS tube.

[0050] Since different types of doping regions are difficult to distinguish in physical appearance, the difficulty of reverse engineering can be further increased by changing the doping type of some areas of the transistor to make the transistor fail.

[0051] In a possible implementation, the first functional circuit is a NAND gate circuit, and the second functional circuit is an inverter circuit, that is, the inverter circuit is disguised as a NAND gate circuit. This will be described in detail below in conjunction with a specific implementation.

[0052] See also Figure 1 , is a layout diagram of a NAND gate circuit in the related art. Figure 1 A first direction X and a second direction Y that are perpendicular to each other are defined in the figure, wherein the first direction X is the left-right direction of the orientation shown in the figure, and the second direction Y is the up-down direction of the orientation shown in the figure. Figure 1As shown, the layout of the NAND gate circuit includes an N-well region NWELL and a P-well region PWELL. In the N-well region NWELL, a P-type doping region 111, a P-type doping region 112, and a P-type doping region 113 are sequentially arranged along the first direction X and extending along the second direction Y. Further, the layout of the NAND gate circuit also includes a first polysilicon region 201 and a second polysilicon region 202 extending along the second direction Y. In the layout of the NAND gate circuit, a first end of the first polysilicon region 201 is located between the P-type doping region 111 and the P-type doping region 112; a first end of the second polysilicon region 202 is located between the P-type doping region 112 and the P-type doping region 113. Further, the layout of the NAND gate circuit also includes a first metal line 301 and a second metal line 302. Among them, the first end of the first metal wire 301 is connected to the P-type doped area 111 through a connecting hole, and the second end of the first metal wire 301 is connected to the power supply terminal VS; the first end of the second metal wire 302 is connected to the P-type doped area 113 through a connecting hole, and the second end of the second metal wire 302 is connected to the power supply terminal VS.

[0053] According to the above structure of the layout, two PMOS tubes are formed in the N-well region NWELL. For the convenience of explanation, the PMOS tube located on the right side of the N-well region NWELL is defined as the "first PMOS tube PM1", and the PMOS tube located on the left side of the N-well region NWELL is defined as the "second PMOS tube PM2". Under normal circumstances, the physical structure of the source and the drain in the PMOS tube is the same, both are P-type doped regions, and the difference between the two lies in the physical connection. Specifically, in the circuit, the P-type doped region connected to a higher potential is defined as the source, and the P-type doped region connected to a lower potential is defined as the drain. In the embodiment of the present application, since the P-type doped region 113 is connected to the power supply terminal VS, the P-type doped region 113 is compared with the P-type doped region 112, and the P-type doped region 113 is a P-type doped region connected to a higher potential, and the P-type doped region 112 is a P-type doped region connected to a lower potential. According to the definition of the source and drain in the above PMOS tube, the P-type doping region 113 constitutes the source of the first PMOS tube PM1, and the side (right side) of the P-type doping region 112 close to the second polysilicon region 202 constitutes the drain of the first PMOS tube PM1. In addition, the first end of the second polysilicon region 202 constitutes the gate of the first PMOS tube PM1. Since the P-type doping region 111 is connected to the power supply terminal VS, therefore, compared with the P-type doping region 111 and the P-type doping region 112, the P-type doping region 111 is a P-type doping region connected to a higher potential, and the P-type doping region 112 is a P-type doping region connected to a lower potential. According to the definition of the source and drain in the above PMOS tube, the P-type doping region 111 constitutes the source of the first PMOS tube PM1, and the side (left side) of the P-type doping region 112 close to the first polysilicon region 201 constitutes the drain of the first PMOS tube PM1. In addition, the first end of the first polysilicon region 201 constitutes the gate of the second PMOS tube PM2.

[0054] Please continue reading Figure 1 , an N-type doping region 121, an N-type doping region 122 and an N-type doping region 123 are sequentially arranged in the P-well region PWELL along the first direction X and extending along the second direction Y. The second end of the first polysilicon region 201 is located between the N-type doping region 121 and the N-type doping region 122; the second end of the second polysilicon region 202 is located between the N-type doping region 122 and the N-type doping region 123. Further, the layout of the NAND gate circuit also includes a third metal wire 303, a fourth metal wire 304 and a fifth metal wire 305. Among them, the first end of the third metal wire 303 is connected to the N-type doping region 121 through a connecting hole, and the second end of the third metal wire 303 is connected to the ground terminal GS; the first end of the fourth metal wire 304 is connected to the P-type doping region 112 through a connecting hole, and the second end of the fourth metal wire 304 is connected to the N-type doping region 123 through a connecting hole; the fifth metal wire 305 is connected to the N-type doping region 122 through a connecting hole.

[0055] According to the above structure of the layout, two NMOS tubes are formed in the P-well region PWELL. For the sake of convenience, the NMOS tube located on the right side of the P-well region PWELL is defined as the "first NMOS tube NM1", and the NMOS tube located on the left side of the P-well region PWELL is defined as the "second NMOS tube NM2". Under normal circumstances, the physical structure of the source and drain in the NMOS tube is the same, both are N-type doped regions, and the difference between the two lies in the physical connection. Specifically, the N-type doped region connected to a higher potential in the circuit is defined as a drain, and the N-type doped region connected to a lower potential is defined as a source. In the embodiment of the present application, since the N-type doped region 121 is connected to the ground terminal GS, the N-type doped region 123 is connected to the P-type doped region 112 through the fourth metal wire 304, and therefore, the potentials of the N-type doped region 121, the N-type doped region 122, and the N-type doped region 123 gradually increase. It can be understood that, compared with the N-type doping region 123 and the N-type doping region 122, the N-type doping region 123 is an N-type doping region connected to a higher potential, and the N-type doping region 122 is an N-type doping region connected to a lower potential. According to the definition of the source and drain in the above-mentioned NMOS tube, the N-type doping region 123 constitutes the drain of the first NMOS tube NM1, and the side (right side) of the N-type doping region 122 close to the second polysilicon region 202 constitutes the source of the first NMOS tube NM1. In addition, the second end of the second polysilicon region 202 constitutes the gate of the first NMOS tube NM1. Similarly, compared with the N-type doping region 121 and the N-type doping region 122, the N-type doping region 122 is an N-type doping region connected to a higher potential, and the N-type doping region 121 is an N-type doping region connected to a lower potential. According to the definition of the source and drain in the above NMOS transistor, the side (left side) of the N-type doping region 122 close to the first polysilicon region 201 constitutes the drain of the second NMOS transistor NM2, and the N-type doping region 121 constitutes the source of the second NMOS transistor NM2. In addition, the second end of the first polysilicon region 201 constitutes the gate of the second NMOS transistor NM2.

[0056] It should be noted that, in the embodiment of the present application, the drain of the first PMOS tube PM1, the drain of the second PMOS tube PM2 and the drain of the first NMOS tube NM1 can be electrically connected through the fourth metal wire 304; the source of the first NMOS tube NM1 and the drain of the second NMOS tube NM2 can be electrically connected through the fifth metal wire 305; the gate of the second PMOS tube PM2 and the gate of the second NMOS tube NM2 can be electrically connected through the first polysilicon region 201; and the gate of the first PMOS tube PM1 and the gate of the first NMOS tube NM1 can be electrically connected through the second polysilicon region 202.

[0057] Furthermore, the layout of the NAND gate circuit also includes a sixth metal line 306 and a seventh metal line 307. Among them, the first end of the sixth metal line 306 is connected to the second polysilicon region 202 through a connection hole, and the second end of the sixth metal line 306 is connected to the first signal input terminal A; the first end of the seventh metal line 307 is connected to the first polysilicon region 201 through a connection hole, and the second end of the seventh metal line 307 is connected to the second signal input terminal B. It can be understood that the signal can be input through the sixth metal line 306 and the seventh metal line 307. In addition, the fourth metal line 304 is connected to the signal output terminal Z. It can be understood that the signal can be output through the fourth metal line 304.

[0058] For ease of understanding, the following Figure 1 The equivalent circuit diagram of the NAND gate circuit shown illustrates the working principle of the NAND gate circuit.

[0059] See also Figure 2 ,for Figure 1 The equivalent circuit diagram of the NAND gate circuit is shown in Figure . Figure 2 As shown, the NAND gate circuit includes two PMOS transistors and two NMOS transistors. Among them, the gate of the first PMOS transistor PM1 is used to connect to the first signal input terminal A, the source of the first PMOS transistor PM1 is used to connect to the power supply terminal VS, and the drain of the first PMOS transistor PM1 is used to connect to the signal output terminal Z; the gate of the second PMOS transistor PM2 is used to connect to the second signal input terminal B, the source of the second PMOS transistor PM2 is used to connect to the power supply terminal VS, and the drain of the second PMOS transistor PM2 is used to connect to the signal output terminal Z; the gate of the first NMOS transistor NM1 is used to connect to the first signal input terminal A, and the drain of the first NMOS transistor NM1 is used to connect to the signal output terminal Z; the gate of the second NMOS transistor NM2 is used to connect to the second signal input terminal B, and the drain of the second NMOS transistor NM2 is electrically connected to the source of the first NMOS transistor NM1.

[0060] Below Figure 1 and Figure 2 The input and output signals of the NAND gate circuit shown are analyzed:

[0061] First, when the first signal input terminal A and the second signal input terminal B are both at a high level (logic "1"), the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off (the gate of the PMOS transistor is turned off when it is higher than the source), blocking the path from the power supply terminal VS to the signal output terminal Z. At the same time, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on (the gate of the NMOS transistor is turned on when it is higher than the source), connecting the signal output terminal Z to the ground terminal GS, so that the signal output terminal Z is at a low level (logic "0").

[0062] Second, when the first signal input terminal A is at a high level (logic "1") and the second signal input terminal B is at a low level (logic "0"), the first NMOS transistor NM1 is turned on and the second NMOS transistor NM2 is turned off, blocking the path from the ground terminal GS to the signal output terminal Z. At the same time, the first PMOS transistor PM1 is turned off and the second PMOS transistor PM2 is turned on, and the signal output terminal Z can be connected to the power supply terminal VS through the second PMOS transistor PM2, so that the signal output terminal Z outputs a high level (logic "1").

[0063] Third, when the first signal input terminal A is at a low level (logic "0") and the second input terminal is at a high level (logic "1"), the first NMOS transistor NM1 is turned off and the second NMOS transistor NM2 is turned on, blocking the path from the ground terminal GS to the signal output terminal Z. At the same time, the first PMOS transistor PM1 is turned on and the second PMOS transistor PM2 is turned off, and the signal output terminal Z can be connected to the power supply terminal VS through the first PMOS transistor PM1, so that the signal output terminal Z outputs a high level (logic "1").

[0064] Fourth, when the first signal input terminal A and the second signal input terminal B are both at a low level (logic "0"), the first NMOS tube NM1 and the second NMOS tube NM2 are turned off, blocking the path from the ground terminal GS to the signal output terminal Z. At the same time, the first PMOS tube PM1 and the second PMOS tube PM2 are turned on, and the signal output terminal Z can be connected to the power supply terminal VS through the first PMOS tube PM1 and the second PMOS tube PM2, so that the signal output terminal Z outputs a high level (logic "1").

[0065] In summary, Figure 1 and Figure 2 The truth table corresponding to the NAND gate circuit shown is shown in Table 1.

[0066] Table 1:

[0067] The first signal input terminal A The second signal input terminal B Signal output terminal Z 1 1 0 1 0 1 0 1 1 0 0 1

[0068] It can be understood that the signal output terminal Z outputs "0" only when the first signal input terminal A and the second signal input terminal B are both "1"; in other cases, the signal output terminal Z outputs "1". Figure 1 and Figure 2 The NAND gate circuit shown can implement the “NAND” logical operation.

[0069] In the embodiment of the present application, in order to prevent the inverter circuit from being copied or plagiarized, the inverter circuit is disguised as Figure 1 and Figure 2The NAND gate circuit shown. Specifically, the source of the second PMOS transistor PM2 in the NAND gate circuit can be adjusted from P-type doping to N-type doping, so that the second PMOS transistor PM2 fails; and the drain of the second NMOS transistor NM2 in the NAND gate circuit can be adjusted from N-type doping to P-type doping, so that the second NMOS transistor NM2 fails, and then the NAND gate circuit is adjusted to an inverter circuit. This is described in detail below in conjunction with a specific implementation method.

[0070] See also Figure 3 , is a layout of a digital circuit provided in an embodiment of the present application. Figure 1 and Figure 2 The difference between the NAND gate circuit shown is that the source (P-type doping region 111) of the second PMOS transistor PM2 in the NAND gate circuit is adjusted from P-type doping to N-type doping, so that the second PMOS transistor PM2 fails; and the drain (N-type doping region 122) of the second NMOS transistor NM2 in the NAND gate circuit is adjusted from N-type doping to P-type doping, so that the second NMOS transistor NM2 fails. When the second PMOS transistor PM2 and the second NMOS transistor NM2 fail, the input signal of the second signal input terminal B will no longer affect the output signal of the signal output terminal Z, so that the NAND gate circuit is adjusted to an inverter circuit. Since the digital circuit involved in the embodiment of the present application is an inverter circuit, for the sake of simplicity, the digital circuit is directly referred to as an "inverter circuit" in the following text.

[0071] like Figure 3 As shown, in the embodiment of the present application, the layout of the inverter circuit includes an N-well region NWELL and a P-well region PWELL. Among them, the first N-type doping region 421, the first P-type doping region 411 and the second P-type doping region 412 are arranged in the first direction X and extended along the second direction Y in sequence in the N-well region NWELL. Further, the layout of the inverter circuit also includes a first polysilicon region 201 and a second polysilicon region 202 extending along the second direction Y. Among them, the first end of the first polysilicon region 201 is located between the first N-type doping region 421 and the first P-type doping region 411; the first end of the second polysilicon region 202 is located between the first P-type doping region 411 and the second P-type doping region 412. Further, the layout of the NAND gate circuit also includes a first metal line 301 and a second metal line 302. Among them, the first end of the first metal wire 301 is connected to the first N-type doped region 421 through a connecting hole, and the second end of the first metal wire 301 is connected to the power supply terminal VS; the first end of the second metal wire 302 is connected to the second P-type doped region 412 through a connecting hole, and the second end of the second metal wire 302 is connected to the power supply terminal VS.

[0072] As described above, in the PMOS tube, the P-type doping region connected to a higher potential is defined as a source, and the P-type doping region connected to a lower potential is defined as a drain. In the embodiment of the present application, since the second P-type doping region 412 is connected to the power supply terminal VS, the second P-type doping region 412 is compared with the first P-type doping region 411, and the second P-type doping region 412 is a P-type doping region connected to a higher potential, and the first P-type doping region 411 is a P-type doping region connected to a lower potential. According to the definition of the source and drain in the above PMOS tube, the second P-type doping region 412 constitutes the source of the first PMOS tube PM1, and the side (right side) of the first P-type doping region 411 close to the second polysilicon region 202 constitutes the drain of the first PMOS tube PM1. In addition, the first end of the second polysilicon region 202 constitutes the gate of the first PMOS tube PM1. However, for the second PMOS tube PM2, since the original "P-type doping region 111" of the second PMOS tube PM2 is adjusted to the "first N-type doping region 421", that is, the region is adjusted from P-type doping to N-type doping, the structure of the second PMOS tube PM2 is destroyed, making the second PMOS tube PM2 ineffective.

[0073] Please continue reading Figure 3 , a second N-type doping region 422, a third P-type doping region 413, a third N-type doping region 423 and a fourth N-type doping region are sequentially arranged in the P-well region PWELL along the first direction X and extending along the second direction Y. The second end of the first polysilicon region 201 is located between the second N-type doping region 422 and the third P-type doping region 413; the second end of the second polysilicon region 202 is located between the third N-type doping region 423 and the fourth N-type doping region. Furthermore, the layout of the inverter circuit also includes a third metal line 303, a fourth metal line 304 and a fifth metal line 305. Among them, the first end of the third metal wire 303 is connected to the second N-type doping region 422 through a connecting hole, and the second end of the third metal wire 303 is connected to the ground terminal GS; the first end of the fourth metal wire 304 is connected to the first P-type doping region 411 through a connecting hole, and the second end of the fourth metal wire 304 is connected to the fourth N-type doping region through a connecting hole; the first end of the fifth metal wire 305 is connected to the third P-type doping region 413 through a connecting hole, and the second end of the fifth metal wire 305 is connected to the third N-type doping region 423 through a connecting hole.

[0074] As described above, in the NMOS tube, the N-type doping region connected to a higher potential is defined as a drain, and the N-type doping region connected to a lower potential is defined as a source. In the embodiment of the present application, since the second N-type doping region 422 is connected to the ground terminal GS, and the fourth N-type doping region is connected to the first P-type doping region 411 through the fourth metal line 304, the potentials of the second N-type doping region 422, the third P-type doping region 413, the third N-type doping region 423 and the fourth N-type doping region gradually increase. It can be understood that, compared with the third N-type doping region 423, the fourth N-type doping region is an N-type doping region connected to a higher potential, and the third N-type doping region 423 is an N-type doping region connected to a lower potential. According to the definition of the source and drain in the above NMOS tube, the fourth N-type doping region constitutes the drain of the first NMOS tube NM1, and the third N-type doping region 423 constitutes the source of the first NMOS tube NM1. In addition, the second end of the second polysilicon region 202 constitutes the gate of the first NMOS tube NM1. However, for the second NMOS tube NM2, since the "side of the N-type doping region 122 close to the first polysilicon region 201" of the original second NMOS tube NM2 is adjusted to the "third P-type doping region 413", that is, the region is adjusted from N-type doping to P-type doping, the structure of the second NMOS tube NM2 is destroyed, making the second NMOS tube NM2 ineffective.

[0075] It should be noted that, in the embodiment of the present application, the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1 can be electrically connected through the fourth metal wire 304; the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 can be electrically connected through the first polysilicon.

[0076] Furthermore, the layout of the NAND gate circuit also includes a sixth metal wire 306 and a seventh metal wire 307. Among them, the first end of the sixth metal wire 306 is connected to the first polysilicon through a connection hole, and the second end of the sixth metal wire 306 is connected to the first signal input terminal A; the first end of the seventh metal wire 307 is connected to the second polysilicon through a connection hole, and the second end of the seventh metal wire 307 is connected to the second signal input terminal B; the fourth metal wire 304 is connected to the signal output terminal Z. It should be pointed out that although there is a second signal input terminal B in the embodiment of the present application, since the second PMOS tube PM2 and the second NMOS tube NM2 fail, the input signal of the second signal input terminal B will no longer affect the output signal of the signal output terminal Z.

[0077] For ease of understanding, the following Figure 3 The equivalent circuit diagram of the inverter circuit shown explains the working principle of the inverter circuit.

[0078] See also Figure 4 ,for Figure 3The equivalent circuit diagram of the digital circuit shown in FIG. 1 is a circuit diagram of a digital circuit of FIG. 1 . Since the second PMOS tube PM2 and the second NMOS tube NM2 fail, the inverter circuit only includes the first PMOS tube PM1 and the first NMOS tube NM1. In addition, the failed second NMOS tube NM2 will generate a parasitic resistor (i.e., the first resistor) in the inverter circuit, so the inverter circuit also includes the first resistor. Specifically, the gate of the first PMOS tube PM1 is used to connect to the first signal input terminal A, the source of the first PMOS tube PM1 is used to connect to the power supply terminal VS, and the drain of the first PMOS tube PM1 is used to connect to the signal output terminal Z; the gate of the first NMOS tube NM1 is used to connect to the first signal input terminal A, the drain of the first NMOS tube NM1 is used to connect to the signal output terminal Z, and the source of the first NMOS tube NM1 is used to connect to the ground terminal GS through the first resistor.

[0079] Below Figure 3 and Figure 4 The input and output signals of the inverter circuit shown are analyzed:

[0080] First, when the first signal input terminal A and the second signal input terminal B are both at a high level (logic "1"), the first PMOS transistor PM1 is turned off, blocking the path from the power supply terminal VS to the signal output terminal Z. At the same time, the first NMOS transistor NM1 is turned on, connecting the signal output terminal Z to the ground terminal GS, so that the signal output terminal Z is at a low level (logic "0").

[0081] Second, when the first signal input terminal A is at a high level (logic "1") and the second signal input terminal B is at a low level (logic "0"), the first PMOS transistor PM1 is turned off, blocking the path from the power supply terminal VS to the signal output terminal Z. At the same time, the first NMOS transistor NM1 is turned on, connecting the signal output terminal Z to the ground terminal GS, so that the signal output terminal Z is at a low level (logic "0").

[0082] Third, when the first signal input terminal A is at a low level (logic "0") and the second input terminal is at a high level (logic "1"), the first NMOS transistor NM1 is turned off, blocking the path from the ground terminal GS to the signal output terminal Z. At the same time, the first PMOS transistor PM1 is turned on, and the signal output terminal Z can be connected to the power supply terminal VS through the first PMOS transistor PM1, so that the signal output terminal Z outputs a high level (logic "1").

[0083] Fourth, when the first signal input terminal A and the second signal input terminal B are both at a low level (logic "0"), the first NMOS transistor NM1 is turned off, blocking the path from the ground terminal GS to the signal output terminal Z. At the same time, the first PMOS transistor PM1 is turned on, and the signal output terminal Z can be connected to the power supply terminal VS through the first PMOS transistor PM1, so that the signal output terminal Z outputs a high level (logic "1").

[0084] In summary, Figure 3 and Figure 4 The truth table corresponding to the inverter circuit shown is shown in Table 2.

[0085] Table 2:

[0086] The first signal input terminal A The second signal input terminal B Signal output terminal Z 1 X 0 0 X 1

[0087] Among them, "X" represents any signal. It can be understood that the output signal of the signal output terminal Z is opposite to the input signal of the first signal input terminal A, and is not affected by the second signal input terminal B. Therefore, Figure 3 and Figure 4 The inverter circuit shown can implement the logical operation of "NOT".

[0088] By comparison Figure 1 and Figure 3 It can be found that Figure 3 The inverter circuit shown is Figure 1 The NAND gate circuit shown has basically no difference in physical appearance (the change in doping type is difficult to distinguish in physical appearance). Therefore, the inverter circuit provided in the embodiment of the present application has a strong camouflage feature and can better protect the digital circuit and prevent the digital circuit from being copied or plagiarized.

[0089] It should be noted that, in addition to Figure 1 In addition to the layout structure shown, the NAND gate circuit may also have other layout structures. Those skilled in the art can also adjust the NAND gate circuit to an inverter circuit by adjusting the doping type of the corresponding area in other layout structures. In addition, in addition to disguising the inverter circuit by the NAND gate circuit, other types of circuits can also be disguised, and the embodiments of the present application do not specifically limit this.

[0090] Corresponding to the above embodiment, the embodiment of the present application also provides a microprocessor chip.

[0091] See also Figure 5 , is a schematic diagram of the structure of a microprocessor chip provided in an embodiment of the present application. Figure 5 As shown, the microprocessor chip includes at least one digital circuit, which is the digital circuit described in the above embodiment. For the specific content of the digital circuit, please refer to the description of the above embodiment, and for the sake of simplicity, it will not be repeated here.

[0092] In a specific implementation, the microprocessor chip may be a micro central control chip or system-on-chip chip such as MCU, DSP, MPU, micro CPU, etc., which can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions, etc. The embodiment of the present application does not impose specific restrictions on its product form.

[0093] See also Figure 6 , is a schematic diagram of the structure of another microprocessor chip provided in an embodiment of the present application. Figure 6 As shown, in an embodiment of the present application, the microprocessor chip also includes a processing module, and at least one digital circuit is configured in the processing module to execute logical operations in the processing module.

[0094] In a possible implementation, the "logical operation" is a specific logical operation in the processing module, that is, not all logical operations in the processing module are implemented by the digital circuit in the embodiment of the present application. Among them, the "specific logical operation" is usually a more important or more sensitive logical operation in the processing module, so as to avoid third parties from cracking the circuit structure of this part as much as possible, thereby improving the overall circuit security.

[0095] In a specific implementation, when the digital circuit in the processing module is an inverter circuit, the logical operations that can be performed by the digital circuit include but are not limited to signal inversion, data processing and logic control.

[0096] See also Figure 7 , is a schematic diagram of the structure of another microprocessor chip provided in an embodiment of the present application. Figure 7 As shown, in an embodiment of the present application, the microprocessor chip also includes a security module, and at least one digital circuit is configured in the security module for performing security protection on the target signal path in the microprocessor chip to enhance the ability of the microprocessor chip to resist external attacks and reverse engineering.

[0097] In a possible implementation, the "target signal path" is a specific signal path in the microprocessor chip, that is, not all signal paths in the microprocessor chip are protected by the digital circuit in the embodiment of the present application. Among them, the "specific signal path" is usually a more important or more sensitive signal path in the microprocessor chip, so as to avoid third parties from cracking the circuit structure of this part, thereby improving the overall circuit security.

[0098] In a specific implementation, the digital circuit in the security module may be an inverter circuit, that is, the target signal path is safely protected by the inverter circuit.

[0099] See also Figure 8 , is a schematic diagram of the structure of another microprocessor chip provided in an embodiment of the present application. Figure 8As shown, in the embodiment of the present application, the microprocessor chip also includes a processing module and a security module. Among them, at least one digital circuit is configured in the processing module to perform logical operations in the processing module; at least one digital circuit is configured in the security module to perform security protection on the target signal path in the microprocessor chip.

[0100] For the specific contents of the processing module and the security module, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0101] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0102] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0103] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0104] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0105] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A digital circuit, characterized in that: include: One or more transistors, at least one of the one or more transistors fails, so that the digital circuit is adjusted from a first functional circuit to a second functional circuit.

2. The digital circuit according to claim 1, characterized in that: The at least one transistor fails, comprising: The doping type of a partial region of the at least one transistor changes, so that the at least one transistor fails.

3. The digital circuit according to claim 2, characterized in that: The doping type changes include: Adjust from P-type doping to N-type doping; or, adjust from N-type doping to P-type doping.

4. The digital circuit according to claim 3, characterized in that: The at least one transistor comprises: A PMOS tube, wherein the source of the PMOS tube is adjusted from P-type doping to N-type doping, so that the PMOS tube fails; and / or, NMOS tube, the drain of the NMOS tube is adjusted from N-type doping to P-type doping, so that the NMOS tube fails.

5. The digital circuit according to any one of claims 1 to 4, characterized in that: The first functional circuit is a NAND gate circuit, and the second functional circuit is an inverter circuit.

6. The digital circuit according to claim 5, characterized in that: The digital circuit comprises: a first PMOS tube, wherein a gate of the first PMOS tube is used to connect to a first signal input terminal, a source of the first PMOS tube is used to connect to a power supply terminal, and a drain of the first PMOS tube is used to connect to a signal output terminal; a second PMOS tube, wherein the gate of the second PMOS tube is used to connect to the second signal input terminal, the source of the second PMOS tube is used to connect to the power supply terminal, and the drain of the second PMOS tube is used to connect to the signal output terminal; a first NMOS transistor, wherein a gate of the first NMOS transistor is used to connect to the first signal input terminal, and a drain of the first NMOS transistor is used to connect to the signal output terminal; a second NMOS transistor, wherein the gate of the second NMOS transistor is used to connect to the second signal input terminal, the drain of the second NMOS transistor is electrically connected to the source of the first NMOS transistor, and the source of the first NMOS transistor is used to connect to the ground terminal; The source of the second PMOS tube is adjusted from P-type doping to N-type doping and the drain of the second NMOS tube is adjusted from N-type doping to P-type doping, so that the digital circuit is adjusted from a NAND gate circuit to an inverter circuit.

7. The digital circuit according to claim 6, characterized in that: The layout structure of the digital circuit includes: An N-well region, wherein a first N-type doping region, a first P-type doping region, and a second P-type doping region are sequentially arranged in a first direction and extend in a second direction, and the first direction is perpendicular to the second direction; A P-well region, wherein a second N-type doping region, a third P-type doping region, a third N-type doping region and a fourth N-type doping region are sequentially arranged along the first direction and extend along the second direction; a first polysilicon region, wherein the first polysilicon region extends along the second direction, a first end of the first polysilicon region is located between the first N-type doping region and the first P-type doping region, and a second end of the first polysilicon region is located between the second N-type doping region and the third P-type doping region; a second polysilicon region, wherein the second polysilicon region extends along the second direction, a first end of the second polysilicon region is located between the first P-type doping region and the second P-type doping region, and a second end of the second polysilicon region is located between the third N-type doping region and the fourth N-type doping region; a first metal wire, wherein a first end of the first metal wire is connected to the first N-type doping region through a connecting hole, and a second end of the first metal wire is connected to a power supply terminal; a second metal wire, wherein a first end of the second metal wire is connected to the second P-type doping region through a connecting hole, and a second end of the second metal wire is connected to a power supply terminal; a third metal wire, wherein a first end of the third metal wire is connected to the second N-type doping region through a connecting hole, and a second end of the third metal wire is connected to a ground terminal; a fourth metal wire, wherein a first end of the fourth metal wire is connected to the first P-type doping region through a connection hole, a second end of the fourth metal wire is connected to the fourth N-type doping region through a connection hole, and the fourth metal wire is connected to the signal output terminal; a fifth metal wire, wherein a first end of the fifth metal wire is connected to the third P-type doping region through a connection hole, and a second end of the fifth metal wire is connected to the third N-type doping region through a connection hole; a sixth metal wire, wherein a first end of the sixth metal wire is connected to the first polysilicon through a connection hole, and a second end of the sixth metal wire is connected to the first signal input terminal; A seventh metal wire, wherein a first end of the seventh metal wire is connected to the second polysilicon through a connection hole, and a second end of the seventh metal wire is connected to the second signal input end.

8. A microprocessor chip, characterized in that: include: At least one digital circuit as claimed in any one of claims 1 to 7.

9. The microprocessor chip according to claim 8, characterized in that: Also includes: A processing module, wherein at least one of the digital circuits is configured within the processing module to execute logic operations in the processing module.

10. The microprocessor chip according to claim 8 or 9, characterized in that: Also includes: A security module, wherein at least one of the digital circuits is configured within the security module for providing security protection for a target signal path in the microprocessor chip.

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