Incremental encoder universal counting method and device based on programmable logic unit, electronic equipment and storage medium

Abstract

The application discloses a kind of general counting methods, devices, electronic equipment and storage medium based on programmable logic unit incremental encoder, the general counting methods of incremental encoder are processed into increment counting pulse and decrement counting pulse by PLU different types of encoder signal, increment counting pulse and decrement counting pulse are captured by MCU timing counter, and the number of increment counting pulse and the number of decrement counting pulse are obtained by MCU by software reading the register of timing counter, the final count value can be obtained by subtraction operation to the number of increment counting pulse and the number of decrement counting pulse;Secondly, the application utilizes the characteristics that PLU unit in MCU can be dynamically configured, designs a variety of types of encoder decoding logic circuit, and realizes the function of dynamic switching decoding system, so that the scheme can be compatible with a variety of different signal system, and the encoder counting method of the application is compatible, low in cost, good in real-time performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of encoder detection, in particular, relates to a general counting method and device of incremental encoder based on programmable logic unit, electronic equipment and storage medium. BACKGROUND

[0002] At present, the encoder is widely used in engineering machinery, manufacturing production line and automatic control system for mechanical speed measurement, speed and acceleration measurement and mechanical operation control. The encoder is a sensor for converting displacement into electrical signal, which can measure and detect the rotation angle, linear displacement, speed, acceleration and other parameters of the object. According to the working principle, the encoder can be divided into incremental encoder and absolute value encoder, wherein the incremental encoder can be divided into AB orthogonal pulse signal, A pulse signal B direction signal, A increment counting pulse B decrement counting pulse and A pulse signal B disable according to the pulse signal format. By counting the pulse signal output by the encoder, the pulse number and direction information can be obtained.

[0003] At present, the encoder counting mainly has the following two implementation schemes: 1. Software scheme, counting through the external interrupt function of microcontroller MCU and the method of querying the input pin level, specifically, inputting a pulse signal to the interrupt function pin to trigger rising edge and falling edge interrupt, in the interrupt processing program, executing software code to query the high and low level of another pulse signal to judge the direction or increment counting processing; 2. Hardware scheme, using a special decoding chip, or using FPGA plus custom designed processing circuit to phase demodulate and pulse capture the signal to obtain the direction and number of the current input pulse signal, according to the direction signal and pulse number to calculate the final counting value, finally the special chip or FPGA custom circuit transmits the counting value to MCU through the communication interface.

[0004] At present, the above two methods still have some problems: 1. The response time is uncertain and the real-time performance is poor. In the software implementation scheme, there is a certain software delay from the signal edge reaching the MCU pin to the MCU entering the interrupt processing task. The priority of the task and the complexity of the program processing will affect the actual delay length, which affects the real-time response performance of the counting. In addition, when the encoder rotation speed is fast, the MCU will frequently enter the interrupt and execute the interrupt processing function, which will cause the interrupt processing to occupy a large amount of MCU running time or resources, affecting the running of other software tasks; 2. The upper limit of the counting frequency is low. Due to the limitation of the MCU main frequency, the MCU needs time to execute the interrupt processing function after entering the interrupt. When the encoder output signal frequency is high and the interrupt generation interval time is less than the interrupt processing time, the MCU interrupt response is covered, and the counting number loss phenomenon occurs; 3. The compatibility is not strong, and the cost is high. Since the hardware decoding chips on the market are often designed only for specific signal formats, if you want to realize decoding of multiple signal formats, you need to use multiple special chips in the circuit, which increases the design cost and circuit complexity. SUMMARY

[0005] The preferred embodiment of the present application provides a general counting method for incremental encoder based on programmable logic unit, to solve the technical problems of weak compatibility, high cost and poor real-time performance when the existing encoder counts.

[0006] The technical scheme adopted by the present application is as follows:

[0007] A general counting method for incremental encoder based on programmable logic unit, comprising the steps of:

[0008] S1, the microcontroller with programmable logic unit PLU is logically configured according to the encoder type selected by the user to obtain the signal logic processing circuit of the corresponding decoding format to form a signal processing unit, and realizes the dynamic switching of the decoding format;

[0009] S2, the microcontroller initializes and configures the two built-in timing counters according to the frequency multiplication relationship required by the user, including rising edge counting / double edge counting selection, non-frequency division / 2 frequency division selection, and capture configuration of the two timing counters to obtain the corresponding configured pulse capture unit;

[0010] S3, after the A / B signals of the incremental encoder are input into the counting device of the present application, the signal processing unit processes them to obtain the increment counting pulse and the decrement counting pulse respectively;

[0011] S4, the pulse capture unit captures the increment counting pulse and the decrement counting pulse, processes them to obtain the increment counting value and the decrement counting value respectively, and stores them in the registers of the two timing counters of the microcontroller.

[0012] S5. Obtain the corresponding increment count value and decrement count value in the registers of the two timing counters of the microcontroller, obtain the final incremental encoder count value through subtraction operation, and send the detected encoder count value to the user in real time through the communication interface and communication processing module;

[0013] S6. After receiving the Z signal pulse from the incremental encoder, the microcontroller generates an external interrupt response and executes the interrupt service subroutine to clear the final incremental encoder count value.

[0014] Furthermore, in step S1, the encoder types include AB orthogonal type encoder, A increase B decrease type encoder, A pulse B direction type encoder, and A pulse B disable type encoder.

[0015] Furthermore, when the encoder type is an AB orthogonal encoder, the signal logic processing circuit includes input terminals IN0 and IN1, a D flip-flop, an XOR gate, a first multiplexer and a first multiplexer, and output terminals OTU0 and OTU1, wherein:

[0016] Input terminals IN0 and IN1 correspond to input A and input B of the signal processing unit, respectively. Output terminals OTU0 and OTU1 correspond to the up-count pulse and down-count pulse of the signal processing unit, respectively. The D flip-flop is composed of six NAND gates. The logic processing circuit is used to perform phase detection and waveform processing on AB quadrature signals with a phase difference of 90°, determine the direction of the AB quadrature pulses based on their phase using the D flip-flop, and integrate the waveforms of the AB quadrature signals using an exclusive-OR gate. When the AB quadrature pulse is determined to be forward, the multiplexer selects input pin 1 as the output, i.e., output terminal OTU0 outputs the pulse integrated by the exclusive-OR gate as the up-count pulse. When the AB quadrature pulse is determined to be reverse, the multiplexer selects input pin 1 as the output, i.e., output terminal OTU1 outputs the pulse integrated by the exclusive-OR gate as the down-count pulse.

[0017] Furthermore, when the encoder type is an A increase B decrease type encoder, the signal logic processing circuit includes input terminals IN0 and IN1, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, and output terminals OTU0 and OTU1, wherein:

[0018] The first NOT gate and the second NOT gate are connected in series between the input end IN0 and the output end OTU0, the third NOT gate and the fourth NOT gate are connected in series between the input end IN1 and the output end OTU1, and the output ends OTU0 and OTU1 correspond to the counting-up pulse and the counting-down pulse of the signal processing unit, respectively. The logic processing circuit is configured to output the A signal input from the input end IN0 to the output end OTU0 as the counting-up pulse after twice NOT operations, and output the B signal input from the input end IN1 to the output end OTU1 as the counting-down pulse after twice NOT operations.

[0019] Further, when the encoder type is an A-pulse B-direction type encoder, the signal logic processing circuit comprises the input ends IN0 and IN1, a fifth NOT gate, a first AND gate, a third multiplexer 403, a fourth multiplexer, the output ends OTU0 and OTU1, wherein:

[0020] The input ends IN0 and IN1 correspond to the input A and the input B of the signal processing unit, respectively, and the output ends OTU0 and OTU1 correspond to the counting-up pulse and the counting-down pulse of the signal processing unit, respectively. The input end of the fifth NOT gate is connected to the input end IN1, and the output end is connected to the input end of the first AND gate and the control end of the third multiplexer, respectively. The other input end of the first AND gate is connected to the input end IN1, and the output end is connected to the input ends of the third multiplexer and the fourth multiplexer, respectively. The output ends of the third multiplexer and the fourth multiplexer are connected to the output ends OTU1 and OTU0, respectively. The other input ends of the third multiplexer and the fourth multiplexer are connected to the input end IN1. The control end of the fourth multiplexer is connected to the input end IN1. When the B signal input from the input end IN1 is at a high level, the fourth multiplexer selects the input pin 1 as the output, that is, the output end OTU0 outputs the signal of the input end IN0 channel as the counting-up pulse. When the B signal input from the input end IN1 is at a low level, the third multiplexer selects the input pin 1 as the output, that is, the output end OTU1 outputs the signal of the input end IN0 channel as the counting-down pulse.

[0021] Further, when the encoder type is an A-pulse B-direction type encoder, the signal logic processing circuit comprises the input ends IN0 and IN1, a fifth NOT gate, a first AND gate, a third multiplexer 403, a fourth multiplexer, the output ends OTU0 and OTU1, wherein:

[0022] The input end IN0 and IN1 correspond to the input A and input B of the signal processing unit in sequence, the output end OTU0 and OTU1 correspond to the up-counting pulse and down-counting pulse of the signal processing unit in sequence, the sixth and seventh non-gate are connected in sequence between the input end IN0 and the output end OTU0, the input end of the eighth non-gate is connected with the input end IN1, the output end is connected with the input end of the second AND gate, the other input end of the second AND gate is connected with the input end IN1, the output end is connected with the output end OTU1, and the logic processing circuit is used for: outputting the A signal input by the input end IN0 to the output end OTU0 as the up-counting pulse, inputting the signal input by the input end IN1 and the negation signal thereof to the second AND gate, and always outputting low level, and disabling the B signal.

[0023] Further, the microprocessor adopts an MCU with a programmable logic unit, such as LPC55S16, PIC24FJ1024 or HPM6240.

[0024] Another preferred embodiment of the present application also provides a general counting device of an incremental encoder based on a programmable logic unit, comprising:

[0025] The signal logic processing circuit configuration module is used for configuring the programmable logic unit PLU to obtain a signal logic processing circuit forming a signal processing unit of a corresponding decoding system, so as to realize dynamic switching of the decoding system.

[0026] The pulse capture configuration module is used for initializing and configuring the two self-provided timing counters of the microcontroller according to the frequency multiplication relationship required by the user, including rising edge counting / double edge counting selection, non-frequency division / 2 frequency division selection and capture configuration of the two timing counters, so as to obtain a corresponding configured pulse capture unit.

[0027] The up-down pulse processing module is used for inputting the A / B signal of the incremental encoder into the counting device, and processing the signal to obtain an up-counting pulse and a down-counting pulse respectively.

[0028] The up-down counting processing module is used for capturing the up-counting pulse and the down-counting pulse by the pulse capture unit, and processing the up-counting pulse and the down-counting pulse to obtain an up-counting value and a down-counting value respectively and store the up-counting value and the down-counting value in the registers of the two timing counters of the microcontroller.

[0029] The counting value processing module is used for obtaining the corresponding up-counting value and down-counting value in the registers of the two timing counters of the microcontroller, obtaining the final counting value of the incremental encoder through subtraction operation, and sending the detected counting value of the encoder in real time through the communication interface and the communication processing module for the user to use.

[0030] The zero clearing module is configured to clear the final incremental encoder count value after the microcontroller generates an external interrupt response to a pulse generated by the Z signal of the incremental encoder.

[0031] Another preferred embodiment of the present application also provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the general counting method for the incremental encoder based on the programmable logic unit when executing the computer program.

[0032] Another preferred embodiment of the present application also provides a storage medium comprising a stored program, wherein the program controls the device where the storage medium is located to implement the steps of the general counting method for the incremental encoder based on the programmable logic unit when the program is executed.

[0033] Compared with the prior art, the present application has the following beneficial effects:

[0034] (1) The general counting method for the incremental encoder has good compatibility, and a counting device can support multiple types of incremental encoders by configuring the PLU into a logic circuit of different decoding systems.

[0035] (2) The counting method has high real-time performance. Although the PLU is part of the MCU, it is essentially a configurable hardware circuit, and its decoding accuracy and real-time performance are comparable to that of a dedicated decoding chip, and it does not occupy the computing resources of the MCU. The software running in the MCU only needs to read the value in the incremental / decremental timing counter and perform subtraction to obtain the final count value with directionality.

[0036] (3) Compared with a hardware implementation scheme with the same compatibility, the present application does not need to use multiple dedicated chips and does not have a corresponding complex peripheral circuit, and the development and manufacturing costs are low.

[0037] (4) The counting method has a high upper limit of counting frequency and is not restricted by the main frequency or response speed of the MCU.

[0038] In addition to the purposes, features and advantages described above, the present application has other purposes, features and advantages. The present application will be further described in detail below with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings, which form a part of the present application, are intended to provide further understanding of the present application, and the illustrative embodiments of the present application and their description serve the purpose of explaining the present application. The accompanying drawings should not be construed as an inappropriate limitation on the present application. In the drawings:

[0040] Figure 1is a general counting method flowchart of the incremental encoder based on the programmable logic unit of the preferred embodiment of the present application;

[0041] Figure 2 is a general scheme design diagram of the incremental encoder general counting method;

[0042] Figure 3 is a general counting method flowchart of the incremental encoder based on the programmable logic unit of another preferred embodiment of the present application;

[0043] Figure 4 is a signal logic processing circuit schematic diagram of the preferred embodiment of the present application;

[0044] Figure 5 is a signal logic processing circuit schematic diagram of another preferred embodiment of the present application;

[0045] Figure 6 is a signal logic processing circuit schematic diagram of another preferred embodiment of the present application;

[0046] Figure 7 is a signal logic processing circuit schematic diagram of another preferred embodiment of the present application;

[0047] Figure 8 is a general counting device module schematic diagram of the incremental encoder based on the programmable logic unit of the preferred embodiment of the present application;

[0048] Figure 9 is an electronic device entity schematic diagram of the preferred embodiment of the present application;

[0049] Figure 10 is an internal structure diagram of the computer device of the preferred embodiment of the present application. DETAILED DESCRIPTION

[0050] The embodiments of the present application are described in detail below with reference to the accompanying drawings, but the present application can be implemented in various different ways as defined and covered by the following.

[0051] As shown in Figure 1 , the preferred embodiment of the present application provides a general counting method of the incremental encoder based on the programmable logic unit, comprising the steps of:

[0052] S1, the microcontroller with programmable logic unit PLU is logically configured according to the encoder type selected by the user to obtain the corresponding signal logic processing circuit of the decoding system to form a signal processing unit, and realize the dynamic switching of the decoding system;

[0053] S2, the microcontroller initializes and configures the two built-in timing counter peripherals according to the user's demand for frequency multiplication, including rising edge count / double edge count selection, undivided / 2 division selection, and capture configuration of the two timing counters to obtain the corresponding configured pulse capture unit;

[0054] S3, the A / B signals of the incremental encoder are input to the counting device, and the signal processing unit processes the signals to obtain the incremental count pulse and the decremental count pulse, respectively;

[0055] S4, the pulse capture unit captures the incremental count pulse and the decremental count pulse, and processes them to obtain the incremental count value and the decremental count value, respectively, which are stored in the registers of the two timing counters of the microcontroller;

[0056] S5, the corresponding incremental count value and the decremental count value are obtained in the registers of the two timing counters of the microcontroller, and the final incremental encoder count value is obtained through subtraction operation, and the detected encoder count value is sent in real time through the communication interface and the communication processing module for the user to use;

[0057] S6, when receiving the Z signal pulse of the incremental encoder, the microcontroller generates an external interrupt response, and executes an interrupt service sub-function to clear the final incremental encoder count value.

[0058] The embodiment is implemented on a microcontroller (MCU) with a programmable logic unit (PLU) (such as LPC55S16), and the embodiment will be further described below in combination with the drawings and the embodiment.

[0059] Figure 2 The overall scheme design diagram of the incremental encoder general counting method based on the programmable logic unit is provided for the embodiment, which includes an encoder output 101, a signal processing unit 102, a pulse capture unit 103, and a software processing unit 104.

[0060] As Figure 2As shown, the encoder output 101 includes three signals of A / B / Z, wherein the A / B signal is a pulse signal for counting, and the Z signal is a transient pulse signal for counting clear; the signal processing unit 102 includes input A and input B for receiving the A / B signal of the encoder output, and outputs the increment counting pulse signal and the decrement counting pulse signal after processing; the pulse capture unit 103 includes two pulse input captures 01 and 02, and outputs the increment counting value and the decrement counting value after processing; the software processing unit 104 includes capture configuration, logic configuration, counting processing, clear processing and system running, wherein the capture configuration and the logic configuration are used for initializing the working mode configuration of the signal processing unit 102 and the pulse capture unit 103, the counting processing is used for receiving the increment / decrement counting value output by the pulse capture unit and performing operation to obtain the final counting result, the clear processing is used for receiving the Z signal output by the encoder output 101 for counting clear processing, and the system running is mainly used for controlling the running of the whole system.

[0061] Compared with the prior art, the embodiment has the following beneficial effects:

[0062] (1) The incremental encoder universal counting method of the embodiment has good compatibility, and one counting device can support the functions of multiple different types of incremental encoders by configuring the PLU into different decoding systems.

[0063] (2) The counting method adopted in the embodiment has high real-time performance. Although the PLU is part of the MCU, it is essentially a configurable hardware circuit, and the decoding accuracy and real-time performance thereof are comparable to those of a dedicated decoding chip, and the MCU computing resources are not occupied. The software running in the MCU only needs to read the values in the increment / decrement timing counters at regular intervals and perform subtraction operation to obtain the final counting value with direction property.

[0064] (3) Compared with the hardware implementation scheme with the same compatibility, the embodiment does not need to use multiple dedicated chips, and there is no corresponding complex peripheral circuit, so the development and manufacturing cost is low.

[0065] (4) The counting method adopted in the embodiment has high upper limit of counting frequency and is not restricted by the main frequency or response speed of the MCU.

[0066] Preferably, in step S1, the encoder type includes an AB quadrature type encoder, an A increment B decrement type encoder, an A pulse B direction type encoder and an A pulse B disable type encoder. Thus, the counting needs of different types of encoders are met, and the applicability is wide and flexible and reliable.

[0067] Figure 3 is a flowchart of another embodiment of the incremental encoder universal counting method based on the programmable logic unit.

[0068] like Figure 4 As shown, in a preferred embodiment of the present application, when the encoder type is an AB orthogonal encoder, the signal logic processing circuit includes input terminals IN0 and IN1, a D flip-flop 201, an XOR gate 202, a first multiplexer 203 and a first multiplexer 204, and output terminals OTU0 and OTU1, wherein:

[0069] Input terminals IN0 and IN1 correspond to input A and input B of the signal processing unit, respectively. Output terminals OTU0 and OTU1 correspond to the up-count pulse and down-count pulse of the signal processing unit, respectively. D flip-flop 201 is a D flip-flop composed of six NAND gates. The logic processing circuit is used to perform phase detection and waveform processing on AB quadrature signals with a 90° phase difference, determine the direction of the AB quadrature pulses based on their phases using D flip-flop 201, and integrate the waveforms of the AB quadrature signals using exclusive-OR gate 202. When the AB quadrature pulses are determined to be forward-directed, multiplexer 203 selects input pin 1 as output, i.e., output terminal OTU0 outputs the pulse integrated by exclusive-OR gate 202 as an up-count pulse. When the AB quadrature pulses are determined to be reverse-directed, multiplexer 204 selects input pin 1 as output, i.e., output terminal OTU1 outputs the pulse integrated by exclusive-OR gate 202 as a down-count pulse.

[0070] The advantage of the signal logic processing circuit of this embodiment is that the designed logic processing circuit is used to process the AB quadrature signal into up-counting pulses and down-counting pulses, which saves MCU software running resources and improves the real-time performance and compatibility of pulse counting.

[0071] like Figure 5 As shown, in a preferred embodiment of the present application, when the encoder type is an A increase B decrease type encoder, the signal logic processing circuit includes input terminals IN0 and IN1, a first NOT gate 301, a second NOT gate 302, a third NOT gate 303, a fourth NOT gate 304, and output terminals OTU0 and OTU1, wherein:

[0072] The first NOT gate 301 and the second NOT gate 302 are connected in series between the input terminal IN0 and the output terminal OTU0, respectively. The third NOT gate 303 and the fourth NOT gate 304 are connected in series between the input terminal IN1 and the output terminal OTU1, and the output terminals OTU0 and OTU1 correspond to the up-count pulse and down-count pulse of the signal processing unit, respectively. The logic processing circuit is used to: after performing two negation operations on the A signal inputted from the input terminal IN0, output it to OTU0 as an up-count pulse; and after performing two negation operations on the B signal inputted from the input terminal IN1, output it to OTU1 as a down-count pulse.

[0073] The signal logic processing circuit of the embodiment has the advantages that the A pulse signal and the B direction signal are processed into the increment counting pulse and the decrement counting pulse by using the designed logic processing circuit, MCU software running resources are saved, and the real-time performance and compatibility of the pulse counting are improved.

[0074] As shown in Figure 6 the preferred embodiment of the present application, when the encoder type is an A pulse B direction type encoder, the signal logic processing circuit comprises an input terminal IN0 and an input terminal IN1, a fifth NOT gate 401, a first AND gate 402, a third multiplexer 403 and a fourth multiplexer 404, and output terminals OTU0 and OTU1, wherein:

[0075] The input terminals IN0 and IN1 correspond to the input A and the input B of the signal processing unit 102 in sequence, the output terminals OTU0 and OTU1 correspond to the increment counting pulse and the decrement counting pulse of the signal processing unit in sequence, the input terminal of the fifth NOT gate 401 is connected to the input terminal IN1, the output terminals are respectively connected to the input terminal of the first AND gate 402 and the control terminal of the third multiplexer 403, the other input terminal of the first AND gate 402 is connected to the input terminal IN1, the output terminals are respectively connected to the input terminals of the third multiplexer 403 and the fourth multiplexer 404, the output terminals of the third multiplexer 403 and the fourth multiplexer 404 are respectively connected to the output terminals OTU1 and OTU0, the other input terminals of the third multiplexer 403 and the fourth multiplexer 404 are connected to the input terminal IN1, the control terminal of the fourth multiplexer 404 is connected to the input terminal IN1, and the logic processing circuit is used for: when the B signal input by the input terminal IN1 is at a high level, the fourth multiplexer 404 selects the input pin 1 as the output, that is, the output terminal OTU0 outputs the signal of the input terminal IN0 channel as the increment counting pulse; when the B signal input by the input terminal IN1 is at a low level, the third multiplexer 403 selects the input pin 1 as the output, that is, the output terminal OTU1 outputs the signal of the IN0 channel as the decrement counting pulse.

[0076] The signal logic processing circuit of the embodiment has the advantages that the A pulse signal and the B direction signal are processed into the increment counting pulse and the decrement counting pulse by using the designed logic processing circuit, MCU software running resources are saved, and the real-time performance and compatibility of the pulse counting are improved.

[0077] As shown in Figure 7 the preferred embodiment of the present application, when the encoder type is an A pulse B direction type encoder, the signal logic processing circuit comprises an input terminal IN0 and an input terminal IN1, a fifth NOT gate 401, a first AND gate 402, a third multiplexer 403 and a fourth multiplexer 404, and output terminals OTU0 and OTU1, wherein:

[0078] Input terminals IN0 and IN1 correspond to input A and input B of the signal processing unit 102, respectively. Output terminals OTU0 and OTU1 correspond to the up-count pulse and down-count pulse of the signal processing unit, respectively. The sixth NOT gate 501 and the seventh NOT gate 502 are connected in series between the input terminal IN0 and the output terminal OTU0, respectively. The input terminal of the eighth NOT gate 503 is connected to the input terminal IN1, and the output terminal is connected to the input terminal of the second AND gate 504. The other input terminal of the second AND gate 504 is connected to the input terminal IN1, and the output terminal is connected to the output terminal OTU1. The logic processing circuit is configured to: output the A signal inputted at the input terminal IN0 to the output terminal OTU0 as an up-count pulse; input the signal inputted at the input terminal IN1 and its negated signal to the second AND gate 504, and output it as a low level, thereby disabling the B signal.

[0079] The advantage of the signal logic processing circuit of this embodiment is that the designed logic processing circuit is used to process the A pulse signal B disabled into an increase count pulse and a decrease count pulse, which saves MCU software running resources and improves the real-time performance and compatibility of pulse counting.

[0080] Preferably, the microprocessor is an MCU with a programmable logic unit such as LPC55S16, PIC24FJ1024 or HPM6240.

[0081] In summary, the above embodiments of the present application have the following features:

[0082] (1) In this application, an MCU timing counter and a programmable logic unit PLU or a programmable logic device FPGA are used to count encoder signals of different formats.

[0083] (2) The present application outputs the encoder signal into a unified up-count pulse and down-count pulse through different logic circuits.

[0084] (3) The logic processing circuit design shown in this application includes but is not limited to the encoder PLU logic processing design of AB orthogonal mode, the encoder PLU logic processing design of A increase B decrease mode, the encoder PLU logic processing design of A pulse B direction mode and the encoder PLU logic processing design of A pulse B disable mode.

[0085] like Figure 8 As shown, another preferred embodiment of the present application further provides a universal counting device for an incremental encoder based on a programmable logic unit, comprising:

[0086] The signal logic processing circuit configuration module is used to configure the microcontroller provided with the programmable logic unit (PLU) to obtain a signal logic processing circuit of the corresponding decoding format according to the encoder type selected by the user, thereby forming a signal processing unit and realizing dynamic switching of the decoding format;

[0087] Pulse capture configuration module, for the microcontroller to initialize and configure the two timing counter peripherals according to the user's demand for frequency multiplication relationship, including rising edge count / double edge count selection, undivided / 2 division selection and enabling the capture configuration of the two timing counters to obtain the corresponding configured pulse capture unit;

[0088] Increment and decrement pulse processing module, for the A / B signal of the incremental encoder to be input to the counting device, and the increment count pulse and the decrement count pulse are obtained after being processed by the signal processing unit respectively;

[0089] Increment and decrement count processing module, for the pulse capture unit to capture the increment count pulse and the decrement count pulse, and to obtain the increment count value and the decrement count value respectively and store them in the registers of the two timing counters of the microcontroller;

[0090] Count value processing module, for obtaining the corresponding increment count value and decrement count value in the registers of the two timing counters of the microcontroller, obtaining the final incremental encoder count value through subtraction operation, and sending the detected encoder count value in real time through the communication interface and the communication processing module for the user to use;

[0091] Clearing processing module, for the microcontroller to generate an external interrupt response after receiving the Z signal pulse of the incremental encoder, and to execute the interrupt service sub-function to clear the final incremental encoder count value.

[0092] As shown in Figure 9 Another preferred embodiment of the present application also provides an electronic device, which includes a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the incremental encoder general counting method based on the programmable logic unit in the above embodiment when executing the computer program.

[0093] As shown in Figure 10 Another preferred embodiment of the present application also provides a computer device, which can be a terminal or a living body detection server, and its internal structure diagram can be as shown in Figure 10The computer device shown in the figure includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computer device is used to communicate with other computer devices outside through network connection. The computer program is executed by the processor to implement the steps of the general counting method of the programmable logic unit-based incremental encoder described above.

[0094] Those skilled in the art can understand that, Figure 10 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0095] The preferred embodiment of the present application also provides a storage medium including a stored program, which, when executed, controls the device where the storage medium is located to perform the steps of the general counting method of the programmable logic unit-based incremental encoder in the above-described embodiments.

[0096] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0097] When the functions of the method of the present embodiment are realized in the form of software function units and sold or used as independent products, they can be stored in one or more computer readable storage media. Based on such understanding, the part of the prior art that the present embodiment contributes to or part of the technical solution can be embodied in the form of a software product stored in a storage medium, including a number of instructions for causing a computer device (which can be a personal computer, a server, a mobile computing device or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0098] Those skilled in the art will appreciate that embodiments of the application can be readily used as software, hardware, or a combination of software and hardware. In one embodiment, the application can be implemented in software and / or firmware. In addition, the software implementation can be implemented by one or more computer programs.

[0099] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart

[0100] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart

[0101] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart

[0102] While the preferred embodiments of the application have been described, additional variations and modifications can be employed. Therefore, the terms and expressions

[0103] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A universal counting method for incremental encoders based on programmable logic units, characterized in that: Including steps: S1. A microcontroller provided with a programmable logic unit (PLU) performs logic configuration on the programmable logic unit (PLU) according to the encoder type selected by the user to obtain a signal logic processing circuit of the corresponding decoding format to form a signal processing unit, thereby realizing dynamic switching of the decoding format. S2. The microcontroller initializes and configures the two built-in timer counter peripherals according to the frequency multiplication relationship required by the user, including the rising edge counting / double edge counting selection, the non-division / divide-by-2 selection, and the capture configuration of the two timer counters to obtain the corresponding pulse capture unit; S3, after the A / B signal of the incremental encoder is input into the signal processing unit, it is processed by the signal processing unit to obtain an increase count pulse and a decrease count pulse respectively; S4, the pulse capture unit captures the up-count pulse and the down-count pulse, processes the up-count value and the down-count value respectively, and stores them in the registers of the two timing counters of the microcontroller; S5. Obtain the corresponding increment count value and decrement count value in the registers of the two timing counters of the microcontroller, obtain the final incremental encoder count value through subtraction operation, and send the detected encoder count value to the user in real time through the communication interface and communication processing module; S6. After receiving the Z signal pulse from the incremental encoder, the microcontroller generates an external interrupt response and executes the interrupt service subroutine to clear the final incremental encoder count value.

2. The universal counting method of incremental encoder based on programmable logic unit according to claim 1, characterized in that: In step S1, the encoder types include AB orthogonal type encoder, A increase B decrease type encoder, A pulse B direction type encoder, and A pulse B disable type encoder.

3. The universal counting method of incremental encoder based on programmable logic unit according to claim 2, characterized in that: When the encoder type is an AB orthogonal encoder, the signal logic processing circuit includes input terminals IN0 and IN1, a D flip-flop (201), an XOR gate (202), a first multiplexer (203) and a second multiplexer (204), and output terminals OTU0 and OTU1, wherein: The input terminals IN0 and IN1 correspond to input A and input B of the signal processing unit in sequence, and the output terminals OTU0 and OTU1 correspond to count-up pulses and count-down pulses of the signal processing unit in sequence. The D flip-flop (201) is a D flip-flop composed of 6 NAND gates. The logic processing circuit is used to perform phase discrimination and waveform processing on the AB quadrature signals with a phase difference of 90°, determine the direction of the AB quadrature pulse according to its phase using the D flip-flop (201), and integrate the waveform of the AB quadrature signal using the exclusive OR gate (202). When the AB quadrature pulse is determined to be in the forward direction, the first multiplexer (203) selects input pin 1 as the output, i.e., the output terminal OTU0 outputs the pulse integrated by the exclusive OR gate (202) as the count-up pulse. When the AB quadrature pulse is determined to be in the reverse direction, the second multiplexer (204) selects input pin 1 as the output, i.e., the output terminal OTU1 outputs the pulse integrated by the exclusive OR gate (202) as the count-down pulse.

4. The universal counting method of incremental encoder based on programmable logic unit according to claim 2, characterized in that: When the encoder type is an A increase B decrease type encoder, the signal logic processing circuit includes input terminals IN0 and IN1, a first NOT gate (301), a second NOT gate (302), a third NOT gate (303), a fourth NOT gate (304), and output terminals OTU0 and OTU1, wherein: The first NOT gate (301) and the second NOT gate (302) are sequentially connected in series between the input terminal IN0 and the output terminal OTU0, the third NOT gate (303) and the fourth NOT gate (304) are sequentially connected in series between the input terminal IN1 and the output terminal OTU1, and the output terminals OTU0 and OTU1 correspond to the increase count pulse and the decrease count pulse of the signal processing unit respectively. The logic processing circuit is used to: output the A signal input from the input terminal IN0 to OTU0 as the increase count pulse after two negation operations, and output the B signal input from the input terminal IN1 to OTU1 as the decrease count pulse after two negation operations.

5. The universal counting method of incremental encoder based on programmable logic unit according to claim 2, characterized in that: When the encoder type is an A pulse B direction type encoder, the signal logic processing circuit includes input terminals IN0 and IN1, a fifth NOT gate (401), a first AND gate (402), a third multiplexer (403) and a fourth multiplexer (404), and output terminals OTU0 and OTU1, wherein: The input terminals IN0 and IN1 correspond to the input A and input B of the signal processing unit (102) in sequence, and the output terminals OTU0 and OTU1 correspond to the increase count pulse and decrease count pulse of the signal processing unit in sequence. The input terminal of the fifth NOT gate (401) is connected to the input terminal IN1, and the output terminals are respectively connected to the input terminal of the first AND gate (402) and the control terminal of the third multiplexer (403). The other input terminal of the first AND gate (402) is connected to the input terminal IN1, and the output terminals are respectively connected to the input terminals of the third multiplexer (403) and the fourth multiplexer (404). The output terminals of the third multiplexer (403) and the fourth multiplexer (404) are respectively connected to the control terminal of the third multiplexer (403). The output terminals OTU1 and OTU0 are connected, the other input terminals of the third multiplexer (403) and the fourth multiplexer (404) are connected to the input terminal IN1, and the control terminal of the fourth multiplexer (404) is connected to the input terminal IN1. The logic processing circuit is used for: when the B signal inputted by the input terminal IN1 is at a high level, the fourth multiplexer (404) selects the input pin 1 as the output, that is, the output terminal OTU0 outputs the signal of the input terminal IN0 channel as an increase count pulse; when the B signal inputted by the input terminal IN1 is at a low level, the third multiplexer (403) selects the input pin 1 as the output, that is, the output terminal OTU1 outputs the signal of the IN0 channel as a decrease count pulse.

6. The universal counting method of incremental encoder based on programmable logic unit according to claim 2, characterized in that: When the encoder type is an A pulse B disabled type encoder, the signal logic processing circuit includes input terminals IN0 and IN1, a sixth NOT gate (501), a seventh NOT gate (502), an eighth NOT gate (503), a second AND gate (504), and output terminals OTU0 and OTU1, wherein: The input terminals IN0 and IN1 correspond to input A and input B of the signal processing unit (102) in sequence, and the output terminals OTU0 and OTU1 correspond to the increase count pulse and decrease count pulse of the signal processing unit in sequence. The sixth NOT gate (501) and the seventh NOT gate (502) are serially connected between the input terminal IN0 and the output terminal OTU0 in sequence. The input terminal of the eighth NOT gate (503) is connected to the input terminal IN1, and the output terminal is connected to the input terminal of the second AND gate (504). The other input terminal of the second AND gate (504) is connected to the input terminal IN1, and the output terminal is connected to the output terminal OTU1. The logic processing circuit is used to: output the A signal inputted from the input terminal IN0 to the output terminal OTU0 as an increase count pulse, and after the signal inputted from the input terminal IN1 and its negation signal are inputted into the second AND gate (504), the output is always low level, thereby disabling the B signal.

7. The universal counting method of incremental encoder based on programmable logic unit according to claim 1, characterized in that: The microcontroller adopts LPC55S16, PIC24FJ1024 or HPM6240.

8. A universal counting device for an incremental encoder based on a programmable logic unit, characterized in that: include: The signal logic processing circuit configuration module is used to configure the microcontroller provided with the programmable logic unit (PLU) to obtain a signal logic processing circuit of the corresponding decoding format according to the encoder type selected by the user, thereby forming a signal processing unit and realizing dynamic switching of the decoding format; The pulse capture configuration module is used to initialize the configuration of the two built-in timer counter peripherals of the microcontroller according to the frequency multiplication relationship required by the user, including the selection of rising edge counting / double edge counting, non-division / divide-by-2 selection, and the activation of the capture configuration of the two timer counters to obtain the corresponding pulse capture unit; An increase / decrease pulse processing module is used to process the A / B signal of the incremental encoder into the signal processing unit, and then obtain an increase count pulse and a decrease count pulse respectively after the signal processing unit processes the signal; The up-down counting processing module is used for the pulse capture unit to capture the up-counting pulse and the down-counting pulse, and respectively process the up-counting value and the down-counting value to be stored in the registers of the two timing counters of the microcontroller; The count value processing module is used to obtain the corresponding up-count value and down-count value in the registers of the two timing counters of the microcontroller, and obtain the final incremental encoder count value through subtraction operation. The detected encoder count value is sent to the user in real time through the communication interface and the communication processing module; The reset processing module is used to generate an external interrupt response when the microcontroller receives a pulse from the Z signal of the incremental encoder and execute the interrupt service sub-function to reset the final incremental encoder count value.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the processor implements the steps of the universal counting method of the incremental encoder based on the programmable logic unit according to any one of claims 1 to 7.

10. A storage medium comprising a stored program, which controls a device where the storage medium is located to execute the steps of the universal counting method for incremental encoders based on programmable logic units as claimed in any one of claims 1 to 7 when the program is executed.

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