Rail transit broadcast dual-power-amplifier redundant playing system

Abstract

The invention discloses a dual-power-amplifier redundant playing system for rail transit broadcasting. The dual-power-amplifier redundant playing system comprises a first sound player, a second sound player and two dual-power-amplifier playing modules, wherein the two dual-power-amplifier playing modules have the same structure and are redundant to each other; the double-power-amplifier playing module comprises an audio input circuit, a CPU, a controller, two power amplifier control channels and two power amplifier monitoring circuits. The two CPUs are in communication connection with each other; in each dual-power amplifier playing module, the CPU is electrically connected with the controller and the two power amplifier control channels, the controller is electrically connected with the audio input circuit, the two power amplifier control channels and the two power amplifier monitoring circuits, the audio input circuit is electrically connected with the two power amplifier control channels, and the two power amplifier monitoring circuits are electrically connected with the two power amplifier monitoring circuits. The two power amplifier control channels are electrically connected with the two power amplifier monitoring circuits in a one-to-one correspondence manner, and the two power amplifier control channels are electrically connected with the two sound players respectively. According to the invention, redundant playing in a rail transit broadcast dual-power-amplifier playing mode is realized, and the situation that only one side is broadcasted is effectively avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of rail transit, and in particular to a rail transit broadcasting dual-power amplifier redundant playback system. Background Art

[0002] In rail transit vehicles, it is usually necessary to install a sound playback device (such as a speaker) on the left and right sides of the carriage to play broadcasts, such as train arrival information, etc. Therefore, in order to facilitate passengers to better receive broadcasts and ensure the normal travel of passengers, it is very important to ensure that the sound playback devices on both sides can play the broadcasts normally.

[0003] At present, the sound playback devices on both sides of rail transit vehicles are controlled by different power amplifier chips. When an abnormality occurs in the path where one of the power amplifier chips is located (such as communication abnormality, output data abnormality, etc.), the corresponding sound playback device will not be able to play normally, and there will be a situation where only one side has broadcasting while the other side is silent. This situation will cause passengers to miss important broadcast information and seriously affect their travel.

[0004] Therefore, there is an urgent need for a redundant playback system that can avoid the situation where only one side of the existing dual-amplifier broadcasting is broadcasting, so as to ensure the normal travel of passengers. Summary of the invention

[0005] In view of this, the present invention provides a rail transit broadcast dual-amplifier redundant playback system to solve the problem that only one side of the existing rail transit dual-amplifier playback system is prone to broadcasting, thereby affecting the normal travel of passengers.

[0006] The present invention provides a rail transit broadcast dual-power amplifier redundant playback system, comprising a first sound player, a second sound player and two dual-power amplifier playback modules with the same structure and being redundant to each other;

[0007] Each of the dual-power amplifier playback modules includes an audio input circuit, a CPU, a controller, a two-way power amplifier control path, and a two-way power amplifier monitoring circuit; the CPUs in the two dual-power amplifier playback modules are connected to communicate with each other;

[0008] In each of the dual-power amplifier playback modules, the CPU is electrically connected to the controller and the two power amplifier control paths, the controller is electrically connected to the audio input circuit, the two power amplifier control paths and the two power amplifier monitoring circuits, the audio input circuit is electrically connected to the two power amplifier control paths, the two power amplifier control paths are electrically connected to the two power amplifier monitoring circuits in a one-to-one correspondence, one of the power amplifier control paths is electrically connected to the first sound player, and the other power amplifier control path is electrically connected to the second sound player;

[0009] In any of the dual-power amplifier playback modules, the two power amplifier monitoring circuits are used to monitor the working state of the corresponding electrically connected power amplifier control path in real time, and send the working state to the corresponding electrically connected controller; the controller is used to determine whether the corresponding power amplifier control path is abnormal according to the received working states of the two paths; when at least one of the power amplifier control paths is abnormal, a first control instruction is sent to the two power amplifier control paths respectively to control the two power amplifier control paths to be disconnected; and path disconnection information is generated, and the path disconnection information is sent to the corresponding electrically connected CPU; the CPU sends the path disconnection information to the CPU in another dual-power amplifier playback module;

[0010] In another dual-amplifier playback module, the CPU is used to send a second control instruction to the two corresponding electrically connected power amplifier control paths according to the received path disconnection information, so as to control the corresponding two power amplifier control paths to be turned on, so as to use one of the turned-on power amplifier control paths to control the first sound player to play the broadcast transmitted by the audio input circuit, and to use the other turned-on power amplifier control path to control the second sound player to play the broadcast transmitted by the audio input circuit.

[0011] Optionally, in each of the dual-power amplifier playback modules, the two power amplifier control paths include a power amplifier processing subcircuit, a filtering subcircuit and a switch control subcircuit; the input ends of the two power amplifier processing subcircuits are electrically connected to the output ends of the audio input circuits in the corresponding dual-power amplifier playback modules, and the input ends of the two power amplifier processing subcircuits are also electrically connected to the output ends of the controllers in the corresponding dual-power amplifier playback modules; the output ends of the two power amplifier processing subcircuits are electrically connected to the input ends of the corresponding switch control subcircuits through the corresponding filtering subcircuits; the input ends of the two switch control subcircuits are also electrically connected to the corresponding CPUs, wherein the output end of one switch control subcircuit is electrically connected to the first sound player, and the output end of the other switch control subcircuit is electrically connected to the second sound player;

[0012] In each of the dual-power amplifier playback modules, the input ends of the two power amplifier processing sub-circuits are also electrically connected to the power amplifier monitoring circuit in the corresponding dual-power amplifier playback module, and the output ends of the two power amplifier processing sub-circuits are also electrically connected to the power amplifier monitoring circuit in the corresponding dual-power amplifier playback module through the corresponding filtering sub-circuit.

[0013] Optionally, each power amplifier processing sub-circuit includes a power amplifier chip U61, a first Schottky diode D23, a fuse F8, a first diode D6, a first resistor R33, a second resistor R173, a fourth resistor R333, a fifth resistor R336, a sixth resistor R367, an eighth resistor R369, a ninth resistor R370, a tenth resistor R371, an eleventh resistor R372, a twelfth resistor R373, a thirteenth resistor R374, a fourteenth resistor R376, a fifteenth resistor R378, a sixteenth resistor R386, a seventeenth resistor R387, an eighteenth resistor R989, a first polarity Capacitor C25, second polarized capacitor C346, third polarized capacitor C347, fourth polarized capacitor C349, first capacitor C21, second capacitor C23, third capacitor C32, fourth capacitor C36, fifth capacitor C331, sixth capacitor C332, seventh capacitor C333, eighth capacitor C334, ninth capacitor C335, tenth capacitor C341, eleventh capacitor C342, twelfth capacitor C343, thirteenth capacitor C344, fourteenth capacitor C345, fifteenth capacitor C348, sixteenth capacitor C350, seventeenth capacitor C351 and eighteenth capacitor C352;

[0014] In each of the power amplifier processing sub-circuits, the shutdown logic input pin #SD of the power amplifier chip U61 is electrically connected to the corresponding controller through the second resistor R173; the first end of the fifteenth resistor R378 and the cathode of the first diode D6 are electrically connected to the 3.3V power supply end, the second end of the fifteenth resistor R378, the anode of the first diode D6 and the first end of the ninth capacitor C335 are all connected to the common connection end between the shutdown logic input pin #SD of the power amplifier chip U61 and the second resistor R173, and the ninth capacitor C335 The second end of the power amplifier chip U61 is grounded; the fault detection pin #FAULT of the power amplifier chip U61 is electrically connected to the corresponding power amplifier monitoring circuit; the right channel positive input pin RINP of the power amplifier chip U61 is electrically connected to the corresponding controller through the fifth capacitor C331 and the sixteenth resistor R386 in sequence, and the right channel negative input pin RINN of the power amplifier chip U61 is grounded through the sixth capacitor C332 and the seventeenth resistor R387 in sequence; the mute pin MUTE of the power amplifier chip U61 is electrically connected to the corresponding controller through the eighteenth resistor R989;

[0015] The right channel positive output pin OUTPR and the right channel negative output pin OUTNR of the power amplifier chip U61 are connected together, and are electrically connected to the first input end of the corresponding filtering sub-circuit; the right channel positive output bootstrap pin BSPR of the power amplifier chip U61 is electrically connected to the right channel positive output pin OUTPR of the power amplifier chip U61 through the third capacitor C32, and the right channel negative output bootstrap pin BSNR of the power amplifier chip U61 is electrically connected to the right channel negative output pin OUTNR of the power amplifier chip U61 through the tenth capacitor C341; The left channel positive output pin OUTPL and the left channel negative output pin OUTNL of the power amplifier chip U61 are connected together, and are electrically connected to the corresponding second input end of the filtering sub-circuit; the left channel positive output bootstrap pin BSPL of the power amplifier chip U61 is electrically connected to the left channel positive output pin OUTPL of the power amplifier chip U61 through the eleventh capacitor C342, and the left channel negative output bootstrap pin BSNL of the power amplifier chip U61 is electrically connected to the left channel negative output pin OUTNL of the power amplifier chip U61 through the twelfth capacitor C343;

[0016] The first power supply pin PVCC0 and the second power supply pin PVCC1 of the power amplifier chip U61 are connected together and electrically connected to the 24V power amplifier power supply terminal; the cathode of the first Schottky diode D23 is connected to the common connection terminal between the first power supply pin PVCC0 of the power amplifier chip U61 and the 24V power amplifier power supply terminal, and the anode of the first Schottky diode D23 is electrically connected to the 24V power supply terminal through the fuse F8; the anode of the first polarized capacitor C25, the anode of the second polarized capacitor C346, and the cathode of the first capacitor C The first end of the first capacitor C21, the first end of the second capacitor C23, the first end of the thirteenth capacitor C344 and the first end of the fourteenth capacitor C345 are all connected to the common connection end between the first power supply pin PVCC0 of the power amplifier chip U61 and the 24V power amplifier power supply end, and the negative electrode of the first polarized capacitor C25, the negative electrode of the second polarized capacitor C346, the second end of the first capacitor C21, the second end of the second capacitor C23, the second end of the thirteenth capacitor C344 and the second end of the fourteenth capacitor C345 are all grounded;

[0017] The third power supply pin PVCC2, the fourth power supply pin PVCC3 and the analog power supply pin AVCC of the power amplifier chip U61 are all connected together and electrically connected to the 24V power amplifier power supply terminal; the positive electrode of the third polar capacitor C347, the positive electrode of the fourth polar capacitor C349, the first end of the fifteenth capacitor C348, the first end of the sixteenth capacitor C350, the first end of the seventeenth capacitor C351 and the first end of the eighteenth capacitor C352 are all connected to the common connection terminal between the third power supply pin PVCC3 of the power amplifier chip U61 and the 24V power amplifier power supply terminal, and the negative electrode of the third polar capacitor C347, the negative electrode of the fourth polar capacitor C349, the second end of the fifteenth capacitor C348, the second end of the sixteenth capacitor C350, the second end of the seventeenth capacitor C351 and the second end of the eighteenth capacitor C352 are all grounded;

[0018] The mode logic input pin MODSEL, the first ground pin GND0, the second ground pin GND1, the third ground pin GND2, the fourth ground pin GND3, the left channel positive input pin LINP and the left channel negative input pin LINN of the power amplifier chip U61 are all grounded; the power limit level pin PLMIT of the power amplifier chip U61 is grounded through the eighth capacitor C334; the upper tube gate drive voltage pin GVDD of the power amplifier chip U61 is grounded through the fourteenth resistor R376 and the fourth resistor R333 in turn, and the power limit level pin PLMIT of the power amplifier chip U61 is also connected to the fourteenth resistor R376 and the fourth resistor R333. The first end of the fourth capacitor C36 and the first end of the sixth resistor R367 are both connected to the common connection end between the upper tube gate drive voltage pin GVDD of the power amplifier chip U61 and the fourteenth resistor R376, the second end of the fourth capacitor C36 is grounded, and the second end of the sixth resistor R367 is grounded through the first resistor R33; the gain pin GAIN / SLV of the power amplifier chip U61 is connected to the common connection end between the sixth resistor R367 and the first resistor R33; the pins of the power amplifier chip U61 are grounded in sequence through the thirteenth resistor R374 and the seventh capacitor C333;

[0019] The first end of the tenth resistor R371, the first end of the eleventh resistor R372 and the first end of the twelfth resistor R373 are all electrically connected to the 3.3V power supply end, the second end of the tenth resistor R371 is grounded through the fifth resistor R336, the second end of the eleventh resistor R372 is grounded through the eighth resistor R369, and the second end of the twelfth resistor R373 is grounded through the ninth resistor R370; the first frequency modulation pin AM0 of the power amplifier chip U61 is connected to the common connection end between the twelfth resistor R373 and the ninth resistor R370, the second frequency modulation pin AM1 of the power amplifier chip U61 is connected to the common connection end between the eleventh resistor R372 and the eighth resistor R369, and the third frequency modulation pin AM2 of the power amplifier chip U61 is connected to the common connection end between the tenth resistor R371 and the fifth resistor R336.

[0020] Optionally, each of the filtering sub-circuits includes a second Schottky diode D22, a third Schottky diode D24, a first inductor L15, a second inductor L16, a nineteenth resistor R379, a twentieth resistor R380, a twenty-first resistor R382, a nineteenth capacitor C34, a twentieth capacitor C35, a twenty-first capacitor C336, a twenty-second capacitor C337, a twenty-third capacitor C338, a twenty-fourth capacitor C339 and a twenty-fifth capacitor C340;

[0021] In each filtering subcircuit, the first end of the first inductor L15 is connected to the common connection end between the right channel positive output pin OUTPR and the right channel negative output pin OUTNR of the corresponding power amplifier chip U61, the first end of the first inductor L15 is also connected to the common connection end between the first power supply pin PVCC0 of the corresponding power amplifier chip U61 and the 24V power amplifier power supply terminal through the second Schottky diode D22, and the second end of the first inductor L15 is electrically connected to the corresponding switch control subcircuit;

[0022] The first end of the second inductor L16 is connected to the common connection end between the left channel positive output pin OUTPL and the left channel negative output pin OUTNL of the corresponding power amplifier chip U61, the first end of the second inductor L16 is also connected to the common connection end between the third power supply pin PVCC2 of the corresponding power amplifier chip U61 and the 24V power amplifier power supply terminal through the third Schottky diode D24, and the second end of the second inductor L16 is electrically connected to the corresponding switch control subcircuit through the twenty-first resistor R382;

[0023] The first end of the nineteenth resistor R379, the first end of the nineteenth capacitor C34, the first end of the twentieth capacitor C35 and the first end of the twenty-third capacitor C338 are all connected to the common connection end between the second end of the first inductor L15 and the corresponding switch control subcircuit; the second end of the nineteenth resistor R379 is electrically connected to the first end of the twenty-first capacitor C336, the second end of the twenty-first capacitor C336 is grounded, the second end of the twenty-first capacitor C336 is also electrically connected to the first end of the twentieth resistor C380 through the twenty-second capacitor C337, and the second end of the twentieth resistor C380 is connected to the second inductor L16. and the common connection end between the second inductor L16 and the twenty-first resistor R382; the second end of the nineteenth capacitor C34 and the second end of the twentieth capacitor C35 are both grounded, the second end of the nineteenth capacitor C34 is also connected to the common connection end between the second inductor L16 and the twenty-first resistor R382 through the twenty-fifth capacitor C340, the second end of the twentieth capacitor C35 is also connected to the common connection end between the second inductor L16 and the twenty-first resistor R382 through the twenty-fourth capacitor C339; the second end of the twenty-third capacitor C338 is connected to the common connection end between the second inductor L16 and the twenty-first resistor R382.

[0024] Optionally, in each of the dual-power amplifier playback modules, the two power amplifier monitoring circuits each include an input fault detection subcircuit and an output current detection subcircuit;

[0025] In each dual-power amplifier playback module, the two input fault detection subcircuits are electrically connected to the input ends of the two power amplifier processing subcircuits in a one-to-one correspondence, and the two output current detection subcircuits are electrically connected to the output ends of the two filtering subcircuits in a one-to-one correspondence.

[0026] Optionally, each of the input fault detection sub-circuits includes a third resistor R328 and a fourth resistor R368;

[0027] In each input fault detection sub-circuit, the first end of the third resistor R328 is electrically connected to the 3.3V power supply end, the second end of the third resistor R328 is electrically connected to the fault detection pin #FAULT of the corresponding power amplifier chip U61, the first end of the fourth resistor R368 is connected to the common connection end between the third resistor R328 and the corresponding fault detection pin #FAULT of the power amplifier chip U61, and the second end of the fourth resistor R368 is electrically connected to the corresponding controller.

[0028] Optionally, each output current detection subcircuit includes a current detection chip U55, a magnetic bead B23, a twenty-second resistor R938, a twenty-third resistor R939, a twenty-fourth resistor R972, a twenty-sixth capacitor C49, a twenty-seventh capacitor C50, a twenty-eighth capacitor C993 and a twenty-ninth capacitor C1022;

[0029] In each output current detection sub-circuit, the positive input pin IN+ of the current detection chip U55 is connected to the common connection end between the second inductor L16 and the twenty-first resistor R382 in the corresponding filtering sub-circuit through the twenty-third resistor R939, and the negative input pin IN- of the current detection chip U55 is connected to the common connection end between the twenty-first resistor R382 and the switch control sub-circuit in the corresponding filtering sub-circuit through the twenty-second resistor R938; the first end of the twenty-eighth capacitor C993 is connected to the common connection end between the positive input pin IN+ of the current detection chip U55 and the twenty-third resistor R939, and the second end of the twenty-eighth capacitor C993 is connected to the common connection end between the negative input pin IN- of the current detection chip U55 and the twenty-second resistor R938; the current detection chip The first reference voltage pin REF1 and the power supply pin VS of the chip U55 are connected together, and are electrically connected to the 3.3V power supply end through the magnetic bead B23; the first end of the twenty-sixth capacitor C49 and the first end of the twenty-seventh capacitor C50 are both connected to the common connection end between the power supply pin VS of the current detection chip U55 and the magnetic bead, and the second end of the twenty-sixth capacitor C49 and the second end of the twenty-seventh capacitor C50 are both grounded; the output pin OUT of the current detection chip U55 is electrically connected to the corresponding controller through the twenty-fourth resistor R972, the first end of the twenty-ninth capacitor C1022 is connected to the common connection end between the twenty-fourth resistor R972 and the corresponding controller, and the second end of the twenty-ninth capacitor C1022 is grounded; the second reference voltage pin REF2 and the ground pin GND of the current detection chip U55 are both grounded.

[0030] Optionally, each of the switch control sub-circuits includes a monitoring chip U32, a transistor Q7, a second diode D59, a third diode D60, a double-pole double-throw relay U63, a connector J1, a fifth polarized capacitor C984, a sixth polarized capacitor C985, a twenty-fifth resistor R925, a twenty-sixth resistor R929, a twenty-seventh resistor R932, a twenty-eighth resistor R933, a twenty-ninth resistor R934, a thirtieth resistor R935, a thirty-first resistor R381, a thirtieth capacitor C135, a thirty-first capacitor C990, a thirty-second capacitor C991 and a thirty-third capacitor C992; the connector J1 has 5 pins;

[0031] In each of the switch control sub-circuits, the enable pin EN of the monitoring chip U32 is electrically connected to the corresponding CPU through the twenty-ninth resistor R934, the first end of the twenty-eighth resistor R933 is connected to the common connection end between the enable pin EN of the monitoring chip U32 and the twenty-ninth resistor R934, and the second end of the twenty-eighth resistor R933 is grounded; the input pin IN of the monitoring chip U32 is electrically connected to the corresponding controller through the twenty-eighth resistor R935, the first end of the twenty-seventh resistor R932 is connected to the common connection end between the input pin IN of the monitoring chip U32 and the twenty-eighth resistor R935, and the second end of the twenty-seventh resistor R932 is grounded; the ground pin of the monitoring chip U32 is electrically connected to the corresponding controller through the twenty-eighth resistor R935, the first end of the twenty-seventh resistor R932 is connected to the common connection end between the input pin IN of the monitoring chip U32 and the twenty-eighth resistor R935, and the second end of the twenty-seventh resistor R932 is grounded; The external capacitor pin CDELAY of the monitoring chip U32 is grounded through the thirty-second capacitor C991, the first end of the thirty-third capacitor C992 is connected to the common connection end between the external capacitor pin CDELAY of the monitoring chip U32 and the thirty-second capacitor C991, and the second end of the thirty-third capacitor C992 is grounded; the power supply pin VCC of the monitoring chip U32 is electrically connected to the 3.3V power supply end, the first end of the 30th capacitor C135 and the first end of the thirty-first capacitor C990 are both connected to the common connection end between the power supply pin VCC of the monitoring chip U32 and the 3.3V power supply end, and the second end of the 30th capacitor C135 and the second end of the thirty-first capacitor C990 are both grounded;

[0032] The output pin OUT of the monitoring chip U32 is electrically connected to the base of the transistor Q9 through the twenty-sixth resistor R929; the anode of the third diode D60, the anode of the sixth polarized capacitor C985 and the first end of the twenty-fifth resistor R925 are all connected to the common connection end between the twenty-sixth resistor R929 and the base of the transistor Q9, the cathode of the third diode D60 is connected to the common connection end between the output pin OUT of the monitoring chip U32 and the twenty-sixth resistor R929, and the cathode of the sixth polarized capacitor C985 and the second end of the twenty-fifth resistor R925 are both grounded;

[0033] The emitter of the transistor Q9 is grounded, the collector of the transistor Q9 is electrically connected to the 5V power supply terminal through the second diode D59, the collector of the transistor Q9 is also electrically connected to the first connection end of the coil in the double-pole double-throw relay U63, the positive electrode of the fifth polar capacitor C984 and the second connection end of the coil in the double-pole double-throw relay U63 are both connected to the common connection end between the second diode D59 and the 5V power supply terminal, and the negative electrode of the fifth polar capacitor C984 is grounded; the first moving contact and the second moving contact of the double-pole double-throw relay U63 are both connected to the filter The output end of the wave sub-circuit is electrically connected, the first normally closed static contact of the double-pole double-throw relay U63 is electrically connected to the second normally closed static contact of the double-pole double-throw relay U63 through the thirty-first resistor R381, the first normally open static contact of the double-pole double-throw relay U63 is electrically connected to pin No. 1 of the connector J1, and the second normally open static contact of the double-pole double-throw relay U63 is electrically connected to pin No. 2 of the connector J1; pin No. 4 and pin No. 5 of the connector J1 are connected together and grounded and left suspended; the 5 pins of the connector J1 are also electrically connected to the first sound player.

[0034] Optionally, each of the dual-power amplifier playback modules further includes a watchdog reset circuit;

[0035] In each of the dual-power amplifier playback modules, the input end of the watchdog reset circuit is electrically connected to the corresponding controller, and the output end of the watchdog reset circuit is electrically connected to the input ends of the two switch control sub-circuits.

[0036] Optionally, each of the switch control sub-circuits further includes a dual-input AND gate chip U67, a thirty-second resistor R931, a thirty-third resistor R936, a thirty-fourth resistor R937, a thirty-fourth capacitor C988 and a thirty-fifth capacitor C989;

[0037] In each of the switch control sub-circuits, the first logic input terminal A of the dual-input AND gate chip U67 is electrically connected to the output terminal of the watchdog reset circuit through the thirty-fourth resistor R937, the second logic input terminal B of the dual-input AND gate chip U67 is electrically connected to the output pin OUT of the monitoring chip U32, the first end of the thirty-third resistor R936 is connected to the common connection terminal between the second logic input terminal B of the dual-input AND gate chip U67 and the output pin OUT of the monitoring chip U32, and the second end of the thirty-third resistor R936 is grounded; the ground pin G of the dual-input AND gate chip U67 is electrically connected to the ground pin G of the dual-input AND gate chip U67. ND is grounded; the power supply pin VCC of the dual-input AND gate chip U67 is electrically connected to the 3.3V power supply terminal, the first end of the thirty-fourth capacitor C988 and the first end of the thirty-fifth capacitor C989 are both connected to the common connection terminal between the power supply pin VCC of the dual-input AND gate chip U67 and the 3.3V power supply terminal, the second end of the thirty-fourth capacitor C988 and the second end of the thirty-fifth capacitor C989 are both grounded; the output pin Y of the dual-input AND gate chip U67 is electrically connected to the base of the transistor Q9 through the thirty-second resistor R931 and the twenty-sixth resistor R929 in sequence.

[0038] Optionally, in each of the dual-power amplifier playback modules, the watchdog reset circuit includes a watchdog chip U59, a dip switch S2, a reset button S3, a thirty-fifth resistor R997, a thirty-sixth capacitor C150 and a thirty-seventh capacitor C186;

[0039] In each of the dual-power amplifier playback modules, the reset button S3 has four contacts, contact No. 1 and contact No. 3 of the reset button S3 are connected together and grounded, contact No. 2 and contact No. 4 of the reset button S3 are also connected together and electrically connected to the manual reset pin MR of the watchdog chip U59, and contact No. 2 and contact No. 4 of the reset button S3 are also grounded through the thirty-seventh capacitor C186; the power supply pin VCC of the watchdog chip U59 is electrically connected to the 3.3V power supply end, the first end of the thirty-sixth capacitor C150 is connected to the common connection end between the power supply pin VCC of the watchdog chip U59 and the 3.3V power supply end, and the second end of the thirty-sixth capacitor C150 is grounded; the ground pin GND of the watchdog chip U59 and the electrical The source fault detection input pins PFI are all grounded; the reset output signal pin WDO of the watchdog chip U59 is electrically connected to the input ends of the two switch control sub-circuits, the static contact of the dip switch S2 is electrically connected to the manual reset pin MR of the watchdog chip U59, and the moving contact of the dip switch S2 is electrically connected to the reset output signal pin WDO of the watchdog chip U59; the reset pin RESET and the dog feeding signal input pin WDI of the watchdog chip U59 are both electrically connected to the corresponding controller, the first end of the thirty-fifth resistor R997 is electrically connected to the dog feeding signal input pin WDI of the watchdog chip U59, and the second end of the thirty-fifth resistor R997 is grounded; the power fault detection output pin PFO of the watchdog chip U59 is suspended.

[0040] The beneficial effects of the present invention are as follows: since the two dual-power amplifier playback modules have the same structure and are redundant with each other, any dual-power amplifier playback module can be used as a main playback module to control the first sound player and the second sound player to play rail transit broadcasts respectively, while the other dual-power amplifier playback module is used as a backup to achieve dual-power amplifier redundant playback; in any dual-power amplifier playback module, the audio input circuit is electrically connected to the controller and the two-way power amplifier control path, and the audio emitted by the external audio transmitting end can be input into the two-way power amplifier control path under the control of the controller, and the two-way power amplifier control path is electrically connected to the two sound players respectively, so that the broadcast input and playback of the dual-power amplifier mode can be achieved; the two-way power amplifier monitoring circuit is electrically connected to the two-way power amplifier control path in a one-to-one correspondence, and the two-way power amplifier monitoring circuit is also electrically connected to the corresponding controller, so that the status monitoring and abnormal analysis of the two-way power amplifier control path can be realized. When at least one power amplifier When the amplifier control path is abnormal, the corresponding dual-power amplifier playback module is abnormal, and the first control instruction is sent to the two power amplifier control paths in the corresponding dual-power amplifier playback module respectively, so as to cut off the two power amplifier control paths; at the same time, path disconnection information is generated, and the communication connection between the CPUs in the two dual-power amplifier playback modules is used to send the path disconnection information to the CPU in another dual-power amplifier playback module, and the electrical connection between the CPU and the corresponding two power amplifier control paths is used to control the corresponding two power amplifier control paths to be turned on, and the two turned-on power amplifier control paths are used to control the first sound player and the second sound player to play the input broadcast respectively; redundant playback in the dual-power amplifier playback mode of rail transit broadcasting is realized, so as to effectively avoid the situation that only one side of the existing dual-power amplifier broadcasting system is prone to broadcasting when a fault occurs, so as to avoid passengers missing important broadcasting information, and truly and effectively guarantee the normal travel of passengers. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The features and advantages of the present invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the present invention in any way. In the accompanying drawings:

[0042] Figure 1 A structural diagram of a rail transit broadcast dual-power amplifier redundant playback system according to an embodiment of the present invention is shown;

[0043] Figure 2 A structural diagram of a dual-power amplifier playback module in an embodiment of the present invention is shown;

[0044] Figure 3 The design diagram of the power amplifier processing subcircuit, the filtering subcircuit and part of the switch control subcircuit in the embodiment of the present invention is shown;

[0045] Figure 4 shows a design diagram of an output current detection subcircuit in an embodiment of the present invention;

[0046] Figure 5shows a partial design diagram of a switch control subcircuit in an embodiment of the present invention;

[0047] Figure 6 A partial design diagram of another switch control subcircuit in an embodiment of the present invention is shown;

[0048] Figure 7 The design diagram of the watchdog reset circuit in the embodiment of the present invention is shown. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0050] Example

[0051] like Figure 1 As shown, a rail transit broadcast dual-power amplifier redundant playback system includes a first sound player, a second sound player, and two dual-power amplifier playback modules with the same structure and being redundant to each other;

[0052] Each of the dual-power amplifier playback modules includes an audio input circuit, a CPU, a controller, a two-way power amplifier control path, and a two-way power amplifier monitoring circuit; the CPUs in the two dual-power amplifier playback modules are connected to communicate with each other;

[0053] In each of the dual-power amplifier playback modules, the CPU is electrically connected to the controller and the two power amplifier control paths, the controller is electrically connected to the audio input circuit, the two power amplifier control paths and the two power amplifier monitoring circuits, the audio input circuit is electrically connected to the two power amplifier control paths, the two power amplifier control paths are electrically connected to the two power amplifier monitoring circuits in a one-to-one correspondence, one of the power amplifier control paths is electrically connected to the first sound player, and the other power amplifier control path is electrically connected to the second sound player;

[0054] In any of the dual-power amplifier playback modules, the two power amplifier monitoring circuits are used to monitor the working state of the corresponding electrically connected power amplifier control path in real time, and send the working state to the corresponding electrically connected controller; the controller is used to determine whether the corresponding power amplifier control path is abnormal according to the received working states of the two paths; when at least one of the power amplifier control paths is abnormal, a first control instruction is sent to the two power amplifier control paths respectively to control the two power amplifier control paths to be disconnected; and path disconnection information is generated, and the path disconnection information is sent to the corresponding electrically connected CPU; the CPU sends the path disconnection information to the CPU in another dual-power amplifier playback module;

[0055] In another dual-amplifier playback module, the CPU is used to send a second control instruction to the two corresponding electrically connected power amplifier control paths according to the received path disconnection information, so as to control the corresponding two power amplifier control paths to be turned on, so as to use one of the turned-on power amplifier control paths to control the first sound player to play the broadcast transmitted by the audio input circuit, and to use the other turned-on power amplifier control path to control the second sound player to play the broadcast transmitted by the audio input circuit.

[0056] In this embodiment, since the two dual-power amplifier playback modules have the same structure and are redundant to each other, any dual-power amplifier playback module can be used as a main playback module to control the first sound player and the second sound player to play the rail transit broadcast respectively, while the other dual-power amplifier playback module is used as a backup to achieve dual-power amplifier redundant playback; in any dual-power amplifier playback module, the audio input circuit is electrically connected to the controller and the two-way power amplifier control path, and the audio emitted by the external audio transmitting end can be input into the two-way power amplifier control path under the control of the controller, and the two-way power amplifier control path is electrically connected to the two sound players respectively, so that the broadcast input and playback of the dual-power amplifier mode can be realized; the two-way power amplifier monitoring circuit is electrically connected to the two-way power amplifier control path in a one-to-one correspondence, and the two-way power amplifier monitoring circuit is also electrically connected to the corresponding controller, which can realize the status monitoring and abnormal analysis of the two-way power amplifier control path, when at least one power amplifier When the control path is abnormal, the corresponding dual-power amplifier playback module is abnormal, and the first control instruction is sent to the two power amplifier control paths in the corresponding dual-power amplifier playback module respectively, and the two power amplifier control paths are cut off; at the same time, the path disconnection information is generated, and the communication connection between the CPUs in the two dual-power amplifier playback modules is used to send the path disconnection information to the CPU in the other dual-power amplifier playback module, and the electrical connection between the CPU and the corresponding two power amplifier control paths is used to control the corresponding two power amplifier control paths to be turned on, and the two turned-on power amplifier control paths are used to control the first sound player and the second sound player to play the input broadcast respectively; redundant playback in the dual-power amplifier playback mode of rail transit broadcasting is realized, effectively avoiding the situation in which only one side of the existing dual-power amplifier broadcasting system is prone to broadcasting when a fault occurs, avoiding passengers from missing important broadcasting information, and truly and effectively ensuring the normal travel of passengers.

[0057] In this embodiment, rail transit includes transportation tools such as buses, subways, trains, and high-speed trains.

[0058] Each component of the rail transit broadcast dual-power amplifier redundant playback system of this embodiment is described in detail below.

[0059] The first audio player and the second audio player both include but are not limited to loudspeakers, amplifiers, sound boxes, and the like.

[0060] In each dual-amplifier playback module, the audio input circuit can be appropriately designed according to actual conditions and is not limited here.

[0061] In each dual-amplifier playback module, the CPU is specifically a central processing unit arranged in the chassis of the rail transit vehicle, which can execute instructions and process data, and is electrically connected to the controller and the amplifier control path through the backplane connector, and is connected to the CPU communication in other dual-amplifier playback modules through Ethernet. The controller is specifically a microprocessor (i.e., MCU) of the STM32 series, which is electrically connected to the CPU through the backplane connector, and is electrically connected to the audio input circuit, the amplifier control path, and the amplifier monitoring circuit through the peripheral interface.

[0062] It should be understood that the rail transit broadcasting dual-amplifier redundant playback system of this embodiment includes two dual-amplifier playback modules, and each dual-amplifier playback module includes two power amplifier control paths and two power amplifier monitoring circuits. Therefore, the entire system includes four power amplifier control paths and four power amplifier monitoring circuits.

[0063] Preferably, in each of the dual-amplifier playback modules, Figure 2 As shown, the two power amplifier control paths both include a power amplifier processing subcircuit, a filtering subcircuit and a switch control subcircuit; the input ends of the two power amplifier processing subcircuits are both electrically connected to the output ends of the audio input circuits in the corresponding dual power amplifier playback modules, and the input ends of the two power amplifier processing subcircuits are also electrically connected to the output ends of the controllers in the corresponding dual power amplifier playback modules; the output ends of the two power amplifier processing subcircuits are both electrically connected to the input ends of the corresponding switch control subcircuits through the corresponding filtering subcircuits; the input ends of the two switch control subcircuits are also electrically connected to the corresponding CPUs, wherein the output end of one switch control subcircuit is electrically connected to the first sound player, and the output end of the other switch control subcircuit is electrically connected to the second sound player;

[0064] In each of the dual-power amplifier playback modules, the input ends of the two power amplifier processing sub-circuits are also electrically connected to the power amplifier monitoring circuit in the corresponding dual-power amplifier playback module, and the output ends of the two power amplifier processing sub-circuits are also electrically connected to the power amplifier monitoring circuit in the corresponding dual-power amplifier playback module through the corresponding filtering sub-circuit.

[0065] In each power amplifier control path, the power amplifier processing subcircuit is used to receive audio signals and provide signal amplification, control and protection functions for the audio signals, ensuring the final output of high-quality audio signals; at the same time, it is also convenient to connect the corresponding power amplifier monitoring circuits to the input and output ends of the power amplifier processing subcircuit respectively to realize the status monitoring of the power amplifier control path; the filtering subcircuit can be used to filter the audio signals processed by the power amplifier processing subcircuit to reduce noise interference and further improve the quality of the audio signal; the switch control subcircuit can realize independent switch switching of each power amplifier control path, which is convenient for realizing redundant playback in the dual-power amplifier playback mode of rail transit broadcasting.

[0066] Preferably, if Figure 3 As shown, each power amplifier processing sub-circuit includes a power amplifier chip U61, a first Schottky diode D23, a fuse F8, a first diode D6, a first resistor R33, a second resistor R173, a fourth resistor R333, a fifth resistor R336, a sixth resistor R367, an eighth resistor R369, a ninth resistor R370, a tenth resistor R371, an eleventh resistor R372, a twelfth resistor R373, a thirteenth resistor R374, a fourteenth resistor R376, a fifteenth resistor R378, a sixteenth resistor R386, a seventeenth resistor R387, an eighteenth resistor R989, a first polarity Capacitor C25, second polarized capacitor C346, third polarized capacitor C347, fourth polarized capacitor C349, first capacitor C21, second capacitor C23, third capacitor C32, fourth capacitor C36, fifth capacitor C331, sixth capacitor C332, seventh capacitor C333, eighth capacitor C334, ninth capacitor C335, tenth capacitor C341, eleventh capacitor C342, twelfth capacitor C343, thirteenth capacitor C344, fourteenth capacitor C345, fifteenth capacitor C348, sixteenth capacitor C350, seventeenth capacitor C351 and eighteenth capacitor C352;

[0067] In each of the power amplifier processing sub-circuits, the shutdown logic input pin #SD of the power amplifier chip U61 is electrically connected to the corresponding controller through the second resistor R173; the first end of the fifteenth resistor R378 and the cathode of the first diode D6 are electrically connected to the 3.3V power supply end, the second end of the fifteenth resistor R378, the anode of the first diode D6 and the first end of the ninth capacitor C335 are all connected to the common connection end between the shutdown logic input pin #SD of the power amplifier chip U61 and the second resistor R173, and the ninth capacitor C335 The second end of the power amplifier chip U61 is grounded; the fault detection pin #FAULT of the power amplifier chip U61 is electrically connected to the corresponding power amplifier monitoring circuit; the right channel positive input pin RINP of the power amplifier chip U61 is electrically connected to the corresponding controller through the fifth capacitor C331 and the sixteenth resistor R386 in sequence, and the right channel negative input pin RINN of the power amplifier chip U61 is grounded through the sixth capacitor C332 and the seventeenth resistor R387 in sequence; the mute pin MUTE of the power amplifier chip U61 is electrically connected to the corresponding controller through the eighteenth resistor R989;

[0068] The right channel positive output pin OUTPR and the right channel negative output pin OUTNR of the power amplifier chip U61 are connected together, and are electrically connected to the first input end of the corresponding filtering sub-circuit; the right channel positive output bootstrap pin BSPR of the power amplifier chip U61 is electrically connected to the right channel positive output pin OUTPR of the power amplifier chip U61 through the third capacitor C32, and the right channel negative output bootstrap pin BSNR of the power amplifier chip U61 is electrically connected to the right channel negative output pin OUTNR of the power amplifier chip U61 through the tenth capacitor C341; The left channel positive output pin OUTPL and the left channel negative output pin OUTNL of the power amplifier chip U61 are connected together, and are electrically connected to the corresponding second input end of the filtering sub-circuit; the left channel positive output bootstrap pin BSPL of the power amplifier chip U61 is electrically connected to the left channel positive output pin OUTPL of the power amplifier chip U61 through the eleventh capacitor C342, and the left channel negative output bootstrap pin BSNL of the power amplifier chip U61 is electrically connected to the left channel negative output pin OUTNL of the power amplifier chip U61 through the twelfth capacitor C343;

[0069] The first power supply pin PVCC0 and the second power supply pin PVCC1 of the power amplifier chip U61 are connected together and electrically connected to the 24V power amplifier power supply terminal; the cathode of the first Schottky diode D23 is connected to the common connection terminal between the first power supply pin PVCC0 of the power amplifier chip U61 and the 24V power amplifier power supply terminal, and the anode of the first Schottky diode D23 is electrically connected to the 24V power supply terminal through the fuse F8; the anode of the first polarized capacitor C25, the anode of the second polarized capacitor C346, and the cathode of the first capacitor C The first end of the first capacitor C21, the first end of the second capacitor C23, the first end of the thirteenth capacitor C344 and the first end of the fourteenth capacitor C345 are all connected to the common connection end between the first power supply pin PVCC0 of the power amplifier chip U61 and the 24V power amplifier power supply end, and the negative electrode of the first polarized capacitor C25, the negative electrode of the second polarized capacitor C346, the second end of the first capacitor C21, the second end of the second capacitor C23, the second end of the thirteenth capacitor C344 and the second end of the fourteenth capacitor C345 are all grounded;

[0070] The third power supply pin PVCC2, the fourth power supply pin PVCC3 and the analog power supply pin AVCC of the power amplifier chip U61 are all connected together and electrically connected to the 24V power amplifier power supply terminal; the positive electrode of the third polar capacitor C347, the positive electrode of the fourth polar capacitor C349, the first end of the fifteenth capacitor C348, the first end of the sixteenth capacitor C350, the first end of the seventeenth capacitor C351 and the first end of the eighteenth capacitor C352 are all connected to the common connection terminal between the third power supply pin PVCC3 of the power amplifier chip U61 and the 24V power amplifier power supply terminal, and the negative electrode of the third polar capacitor C347, the negative electrode of the fourth polar capacitor C349, the second end of the fifteenth capacitor C348, the second end of the sixteenth capacitor C350, the second end of the seventeenth capacitor C351 and the second end of the eighteenth capacitor C352 are all grounded;

[0071] The mode logic input pin MODSEL, the first ground pin GND0, the second ground pin GND1, the third ground pin GND2, the fourth ground pin GND3, the left channel positive input pin LINP and the left channel negative input pin LINN of the power amplifier chip U61 are all grounded; the power limit level pin PLMIT of the power amplifier chip U61 is grounded through the eighth capacitor C334; the upper tube gate drive voltage pin GVDD of the power amplifier chip U61 is grounded through the fourteenth resistor R376 and the fourth resistor R333 in turn, and the power limit level pin PLMIT of the power amplifier chip U61 is also connected to the fourteenth resistor R376 and the fourth resistor R333. The first end of the fourth capacitor C36 and the first end of the sixth resistor R367 are both connected to the common connection end between the upper tube gate drive voltage pin GVDD of the power amplifier chip U61 and the fourteenth resistor R376, the second end of the fourth capacitor C36 is grounded, and the second end of the sixth resistor R367 is grounded through the first resistor R33; the gain pin GAIN / SLV of the power amplifier chip U61 is connected to the common connection end between the sixth resistor R367 and the first resistor R33; the pins of the power amplifier chip U61 are grounded in sequence through the thirteenth resistor R374 and the seventh capacitor C333;

[0072] The first end of the tenth resistor R371, the first end of the eleventh resistor R372 and the first end of the twelfth resistor R373 are all electrically connected to the 3.3V power supply end, the second end of the tenth resistor R371 is grounded through the fifth resistor R336, the second end of the eleventh resistor R372 is grounded through the eighth resistor R369, and the second end of the twelfth resistor R373 is grounded through the ninth resistor R370; the first frequency modulation pin AM0 of the power amplifier chip U61 is connected to the common connection end between the twelfth resistor R373 and the ninth resistor R370, the second frequency modulation pin AM1 of the power amplifier chip U61 is connected to the common connection end between the eleventh resistor R372 and the eighth resistor R369, and the third frequency modulation pin AM2 of the power amplifier chip U61 is connected to the common connection end between the tenth resistor R371 and the fifth resistor R336.

[0073] In the power amplifier processing subcircuit of the above structure, the right channel positive input pin RINP of the power amplifier chip is electrically connected to the corresponding controller through the fifth capacitor C331 and the sixteenth resistor R386 in sequence, and the controller is electrically connected to the audio input circuit, so the right channel positive input pin RINP of the power amplifier chip can be connected to the audio signal through the controller (i.e. Figure 3 The signal output by the Amp_Aduio port in the power amplifier chip); wherein, adding the fifth capacitor can isolate the DC signal and avoid interference from the DC signal; the right channel positive output pin OUTPR of the power amplifier chip is connected with the right channel negative output pin OUTNR, and is electrically connected to the first input end of the filter subcircuit, and can output the first audio signal processed by the power amplifier to the subsequent stage; the left channel positive output pin OUTPL of the power amplifier chip is connected with the left channel negative output pin OUTNL, and is electrically connected to the second input end of the filter subcircuit, and can output the second audio signal processed by the power amplifier to the subsequent stage.

[0074] Among them, the fault detection pin #FAULT of the power amplifier chip is electrically connected to the power amplifier monitoring circuit, which can collect the fault level signal at the input end of the power amplifier control path, so as to facilitate the status monitoring of the power amplifier control path.

[0075] The first power supply pin PVCC0 and the second power supply pin PVCC1 of the power amplifier chip are connected together and electrically connected to the 24V power amplifier power terminal, and then electrically connected to the 24V power supply through the first Schottky diode D23 and the fuse F1, and connected to the 24V working voltage required for the normal operation of the power amplifier chip. Among them, adding the first Schottky diode can achieve anti-reverse, preventing the voltage from flowing back and burning other circuit chips after the power amplifier chip is damaged.

[0076] This embodiment can ensure the output of high-quality audio signals to the subsequent stage and achieve high-quality broadcasting through the power amplifier processing sub-circuit of the above structure.

[0077] Preferably, if Figure 3 As shown, each filtering sub-circuit includes a second Schottky diode D22, a third Schottky diode D24, a first inductor L15, a second inductor L16, a nineteenth resistor R379, a twentieth resistor R380, a twenty-first resistor R382, a nineteenth capacitor C34, a twentieth capacitor C35, a twenty-first capacitor C336, a twenty-second capacitor C337, a twenty-third capacitor C338, a twenty-fourth capacitor C339 and a twenty-fifth capacitor C340;

[0078] In each filtering subcircuit, the first end of the first inductor L15 is connected to the common connection end between the right channel positive output pin OUTPR and the right channel negative output pin OUTNR of the corresponding power amplifier chip U61, the first end of the first inductor L15 is also connected to the common connection end between the first power supply pin PVCC0 of the corresponding power amplifier chip U61 and the 24V power amplifier power supply terminal through the second Schottky diode D22, and the second end of the first inductor L15 is electrically connected to the corresponding switch control subcircuit;

[0079] The first end of the second inductor L16 is connected to the common connection end between the left channel positive output pin OUTPL and the left channel negative output pin OUTNL of the corresponding power amplifier chip U61, the first end of the second inductor L16 is also connected to the common connection end between the third power supply pin PVCC2 of the corresponding power amplifier chip U61 and the 24V power amplifier power supply terminal through the third Schottky diode D24, and the second end of the second inductor L16 is electrically connected to the corresponding switch control subcircuit through the twenty-first resistor R382;

[0080] The first end of the nineteenth resistor R379, the first end of the nineteenth capacitor C34, the first end of the twentieth capacitor C35 and the first end of the twenty-third capacitor C338 are all connected to the common connection end between the second end of the first inductor L15 and the corresponding switch control subcircuit; the second end of the nineteenth resistor R379 is electrically connected to the first end of the twenty-first capacitor C336, the second end of the twenty-first capacitor C336 is grounded, the second end of the twenty-first capacitor C336 is also electrically connected to the first end of the twentieth resistor C380 through the twenty-second capacitor C337, and the second end of the twentieth resistor C380 is connected to the second inductor L16. and the common connection end between the second inductor L16 and the twenty-first resistor R382; the second end of the nineteenth capacitor C34 and the second end of the twentieth capacitor C35 are both grounded, the second end of the nineteenth capacitor C34 is also connected to the common connection end between the second inductor L16 and the twenty-first resistor R382 through the twenty-fifth capacitor C340, the second end of the twentieth capacitor C35 is also connected to the common connection end between the second inductor L16 and the twenty-first resistor R382 through the twenty-fourth capacitor C339; the second end of the twenty-third capacitor C338 is connected to the common connection end between the second inductor L16 and the twenty-first resistor R382.

[0081] The filtering subcircuit of the above structure realizes low-pass filtering of the audio signal output by the power amplifier processing subcircuit, eliminates high-frequency noise, and further improves the quality of the audio signal output to the subsequent stage.

[0082] It should be understood that Figure 3 Only the specific circuit design diagram of one power amplifier processing subcircuit and one filtering subcircuit is shown. The specific circuit designs of the other three power amplifier processing subcircuits and filtering subcircuits are the same and will not be listed here. The power amplifier chip in the power amplifier processing subcircuit uses the TPA3116D2QDADRQ1 model power amplifier chip. The other electronic components can be selected according to the actual situation. The appropriate specifications or product models are not listed here.

[0083] Preferably, in each of the dual-amplifier playback modules, Figure 2 As shown, the two power amplifier monitoring circuits each include an input fault detection subcircuit and an output current detection subcircuit;

[0084] In each dual-power amplifier playback module, the two input fault detection subcircuits are electrically connected to the input ends of the two power amplifier processing subcircuits in a one-to-one correspondence, and the two output current detection subcircuits are electrically connected to the output ends of the two filtering subcircuits in a one-to-one correspondence.

[0085] In each power amplifier monitoring circuit, the input fault detection subcircuit is electrically connected to the input end of the corresponding power amplifier processing subcircuit, so as to realize fault detection at the input end of the entire power amplifier control path; the output current subcircuit is electrically connected to the output end of the corresponding power amplifier processing subcircuit through the filtering subcircuit, so as to realize current detection at the output end of the entire power amplifier control path; based on the two state monitorings of fault detection and current detection, the state of the dual power amplifier playback module can be monitored in all directions, so as to facilitate switching to another dual power amplifier playback module when an abnormality occurs in one of the dual power amplifier playback modules, so as to realize dual power amplifier redundant playback of rail transit broadcasting.

[0086] Preferably, if Figure 3 As shown, each input fault detection sub-circuit includes a third resistor R328 and a fourth resistor R368;

[0087] In each input fault detection sub-circuit, the first end of the third resistor R328 is electrically connected to the 3.3V power supply end, the second end of the third resistor R328 is electrically connected to the fault detection pin #FAULT of the corresponding power amplifier chip U61, the first end of the fourth resistor R368 is connected to the common connection end between the third resistor R328 and the corresponding fault detection pin #FAULT of the power amplifier chip U61, and the second end of the fourth resistor R368 is electrically connected to the corresponding controller.

[0088] In the input fault detection subcircuit of the above structure, by leading out a level signal at the fault detection pin #FAULT of the power amplifier chip U61 and then connecting it to the controller through the fourth resistor, fault detection at the input end of the power amplifier control path can be realized; specifically, when the power amplifier chip in the power amplifier control path is normal, the level signal led out by the fault detection pin #FAULT is a high-level signal, and when the power amplifier chip is abnormal, the level signal led out by the fault detection pin #FAULT is pulled down and a low-level signal is output. The corresponding controller can determine that the power amplifier control path is abnormal, send a first control instruction to the switch control subcircuit in the two power amplifier control paths, cut off the two power amplifier control paths, and generate path disconnection information synchronized to the corresponding CPU, and then the CPU sends the path disconnection information to the CPU in the other dual-power amplifier playback module.

[0089] Preferably, if Figure 3 and Figure 4 As shown, each output current detection sub-circuit includes a current detection chip U55, a magnetic bead B23, a twenty-second resistor R938, a twenty-third resistor R939, a twenty-fourth resistor R972, a twenty-sixth capacitor C49, a twenty-seventh capacitor C50, a twenty-eighth capacitor C993 and a twenty-ninth capacitor C1022;

[0090] In each output current detection sub-circuit, the positive input pin IN+ of the current detection chip U55 is connected to the common connection end between the second inductor L16 and the twenty-first resistor R382 in the corresponding filtering sub-circuit through the twenty-third resistor R939, and the negative input pin IN- of the current detection chip U55 is connected to the common connection end between the twenty-first resistor R382 and the switch control sub-circuit in the corresponding filtering sub-circuit through the twenty-second resistor R938; the first end of the twenty-eighth capacitor C993 is connected to the common connection end between the positive input pin IN+ of the current detection chip U55 and the twenty-third resistor R939, and the second end of the twenty-eighth capacitor C993 is connected to the common connection end between the negative input pin IN- of the current detection chip U55 and the twenty-second resistor R938; the current detection chip The first reference voltage pin REF1 and the power supply pin VS of the chip U55 are connected together, and are electrically connected to the 3.3V power supply end through the magnetic bead B23; the first end of the twenty-sixth capacitor C49 and the first end of the twenty-seventh capacitor C50 are both connected to the common connection end between the power supply pin VS of the current detection chip U55 and the magnetic bead, and the second end of the twenty-sixth capacitor C49 and the second end of the twenty-seventh capacitor C50 are both grounded; the output pin OUT of the current detection chip U55 is electrically connected to the corresponding controller through the twenty-fourth resistor R972, the first end of the twenty-ninth capacitor C1022 is connected to the common connection end between the twenty-fourth resistor R972 and the corresponding controller, and the second end of the twenty-ninth capacitor C1022 is grounded; the second reference voltage pin REF2 and the ground pin GND of the current detection chip U55 are both grounded.

[0091] In the above output current detection subcircuit, current sampling is performed at both ends of the twenty-first resistor R382 at the output end of the filter subcircuit (ie Figure 3 The output signals of AMP1_P port and AMP1_N port are sent to the positive input pin IN+ and negative input pin IN- of the current detection chip U55 respectively. After being processed by the current detection chip, the corresponding current detection signal (i.e. Figure 4 The signal output by the AMP_I1 port in the power amplifier is sent to the corresponding controller for current detection signal analysis. When the current detection signal exceeds the preset threshold, it is determined that the corresponding power amplifier control path is abnormal.

[0092] It should be understood that Figure 3 and Figure 4Only the specific circuit design diagram of one power amplifier monitoring circuit is shown. The specific circuit designs of the other three power amplifier monitoring circuits are the same and will not be listed here. The current detection chip of the output current detection subcircuit in the power amplifier monitoring circuit uses the INA240A1QDRQ1 current detection chip. The other electronic components can be selected according to the actual situation. The appropriate specifications or product models are not listed here.

[0093] Preferably, if Figure 3 and Figure 5 As shown, each of the switch control sub-circuits includes a monitoring chip U32, a transistor Q7, a second diode D59, a third diode D60, a double-pole double-throw relay U63, a connector J1, a fifth polarized capacitor C984, a sixth polarized capacitor C985, a twenty-fifth resistor R925, a twenty-sixth resistor R929, a twenty-seventh resistor R932, a twenty-eighth resistor R933, a twenty-ninth resistor R934, a thirtieth resistor R935, a thirty-first resistor R381, a thirtieth capacitor C135, a thirty-first capacitor C990, a thirty-second capacitor C991 and a thirty-third capacitor C992; the connector J1 has 5 pins;

[0094] In each of the switch control sub-circuits, the enable pin EN of the monitoring chip U32 is electrically connected to the corresponding CPU through the twenty-ninth resistor R934, the first end of the twenty-eighth resistor R933 is connected to the common connection end between the enable pin EN of the monitoring chip U32 and the twenty-ninth resistor R934, and the second end of the twenty-eighth resistor R933 is grounded; the input pin IN of the monitoring chip U32 is electrically connected to the corresponding controller through the twenty-eighth resistor R935, the first end of the twenty-seventh resistor R932 is connected to the common connection end between the input pin IN of the monitoring chip U32 and the twenty-eighth resistor R935, and the second end of the twenty-seventh resistor R932 is grounded; the ground pin of the monitoring chip U32 is electrically connected to the corresponding controller through the twenty-eighth resistor R935, the first end of the twenty-seventh resistor R932 is connected to the common connection end between the input pin IN of the monitoring chip U32 and the twenty-eighth resistor R935, and the second end of the twenty-seventh resistor R932 is grounded; The external capacitor pin CDELAY of the monitoring chip U32 is grounded through the thirty-second capacitor C991, the first end of the thirty-third capacitor C992 is connected to the common connection end between the external capacitor pin CDELAY of the monitoring chip U32 and the thirty-second capacitor C991, and the second end of the thirty-third capacitor C992 is grounded; the power supply pin VCC of the monitoring chip U32 is electrically connected to the 3.3V power supply end, the first end of the 30th capacitor C135 and the first end of the thirty-first capacitor C990 are both connected to the common connection end between the power supply pin VCC of the monitoring chip U32 and the 3.3V power supply end, and the second end of the 30th capacitor C135 and the second end of the thirty-first capacitor C990 are both grounded;

[0095] The output pin OUT of the monitoring chip U32 is electrically connected to the base of the transistor Q9 through the twenty-sixth resistor R929; the anode of the third diode D60, the anode of the sixth polarized capacitor C985 and the first end of the twenty-fifth resistor R925 are all connected to the common connection end between the twenty-sixth resistor R929 and the base of the transistor Q9, the cathode of the third diode D60 is connected to the common connection end between the output pin OUT of the monitoring chip U32 and the twenty-sixth resistor R929, and the cathode of the sixth polarized capacitor C985 and the second end of the twenty-fifth resistor R925 are both grounded;

[0096] The emitter of the transistor Q9 is grounded, the collector of the transistor Q9 is electrically connected to the 5V power supply terminal through the second diode D59, the collector of the transistor Q9 is also electrically connected to the first connection end of the coil in the double-pole double-throw relay U63, the positive electrode of the fifth polar capacitor C984 and the second connection end of the coil in the double-pole double-throw relay U63 are both connected to the common connection end between the second diode D59 and the 5V power supply terminal, and the negative electrode of the fifth polar capacitor C984 is grounded; the first moving contact and the second moving contact of the double-pole double-throw relay U63 are both connected to the filter The output end of the wave sub-circuit is electrically connected, the first normally closed static contact of the double-pole double-throw relay U63 is electrically connected to the second normally closed static contact of the double-pole double-throw relay U63 through the thirty-first resistor R381, the first normally open static contact of the double-pole double-throw relay U63 is electrically connected to pin No. 1 of the connector J1, and the second normally open static contact of the double-pole double-throw relay U63 is electrically connected to pin No. 2 of the connector J1; pin No. 4 and pin No. 5 of the connector J1 are connected together and grounded and left suspended; the 5 pins of the connector J1 are also electrically connected to the first sound player.

[0097] In the above switch control subcircuit, the enable pin of the monitoring chip receives the control signal of the CPU (ie Figure 5 The signal output by the AMP_CPU_CTL port in the CPU can control the working state of the monitoring chip. For example, when the signal output by the AMP_CPU_CTL port is a high-level signal, the monitoring chip works normally, otherwise it stops working; the input pin IN of the monitoring chip receives the control signal of the controller (i.e. Figure 5The first control instruction can be sent to the monitoring chip, and transmitted to the transistor and double-pole double-throw relay of the subsequent stage through the monitoring chip to realize the driving and switch control of the double-pole double-throw relay, and then realize the on-off of the corresponding power amplifier control path. Among them, the driving signal of the double-pole double-throw relay is transmitted from the collector of the transistor, and the driving signal is transmitted to the coil of the double-pole double-throw relay, and then the contact of the double-pole double-throw relay is switched to realize the on-off of the path.

[0098] Specifically, in Figure 3 In the figure, the first connection end and the second connection end of the coil of the double-pole double-throw relay U63 are pin 8 and pin 1 respectively, the first moving contact and the second moving contact are pin 6 and pin 3 respectively, the first normally closed static contact and the second normally closed static contact are pin 7 and pin 2 respectively, and the first normally open static contact and the second normally open static contact are pin 5 and pin 4 respectively; the double-pole double-throw relay U63 is a normally closed relay, that is, in the default state, pin 6 is connected to pin 7, pin 3 is connected to pin 4, and the corresponding power amplifier control path is in the on state.

[0099] Specifically, for Figure 5 In the switch control subcircuit shown, when the power amplifier control path is normal, the signal output by the AMP_MCU_CTL1 port is a high-level signal, the corresponding transistor Q7 is turned on, and the double-pole double-throw relay is in a normally closed state, that is, Figure 5 The 6th pin of the double-pole double-throw relay U63 is connected to the 7th pin, and the 3rd pin is connected to the 4th pin, and the corresponding power amplifier control path is in the on state; when the power amplifier control path is abnormal, the signal output by the AMP_MCU_CTL1 port is a low-level signal, the corresponding transistor Q7 is cut off, and the double-pole double-throw relay is switched from the normally closed state to the normally open state, that is, Figure 5 The 6th pin of the double-pole double-throw relay U63 is connected to the 5th pin, and the 3rd pin is connected to the 2nd pin, and the corresponding power amplifier control path is in the disconnected state.

[0100] Preferably, if Figure 2 As shown, each of the dual-power amplifier playback modules also includes a watchdog reset circuit;

[0101] In each of the dual-power amplifier playback modules, the input end of the watchdog reset circuit is electrically connected to the corresponding controller, and the output end of the watchdog reset circuit is electrically connected to the input ends of the two switch control sub-circuits.

[0102] In order to prevent the dual-amplifier playback module from abnormalities, a watchdog reset circuit is usually configured for the dual-amplifier playback module. The watchdog reset circuit can perform periodic status monitoring of the system. When the system crashes, shuts down, or other abnormalities occur, it can automatically detect and trigger the system reset operation by sending a reset control signal to restore the system abnormality and ensure the reliability and stability of the system. Therefore, whether the power amplifier control path receives the reset control signal sent by the watchdog reset circuit can also reflect the working status of the power amplifier control path. When the reset control signal is not received, it indicates that the power amplifier control path has a communication abnormality, and when the reset control signal is received, it indicates that the power amplifier control path is communicating normally. Therefore, the output end of the watchdog reset circuit is also electrically connected to the input end of the two-way switch control subcircuit, and the signal output by the watchdog reset circuit can also be used as the basis for path switch control, which can further effectively prevent the dual-amplifier playback module from abnormalities, and further avoid the situation where only one side is broadcast in the rail transit dual-amplifier playback system.

[0103] Preferably, if Figure 6 As shown, each of the switch control sub-circuits further includes a dual-input AND gate chip U67, a thirty-second resistor R931, a thirty-third resistor R936, a thirty-fourth resistor R937, a thirty-fourth capacitor C988 and a thirty-fifth capacitor C989;

[0104] In each of the switch control sub-circuits, the first logic input terminal A of the dual-input AND gate chip U67 is electrically connected to the output terminal of the watchdog reset circuit through the thirty-fourth resistor R937, the second logic input terminal B of the dual-input AND gate chip U67 is electrically connected to the output pin OUT of the monitoring chip U32, the first end of the thirty-third resistor R936 is connected to the common connection terminal between the second logic input terminal B of the dual-input AND gate chip U67 and the output pin OUT of the monitoring chip U32, and the second end of the thirty-third resistor R936 is grounded; the ground pin G of the dual-input AND gate chip U67 is electrically connected to the ground pin G of the dual-input AND gate chip U67. ND is grounded; the power supply pin VCC of the dual-input AND gate chip U67 is electrically connected to the 3.3V power supply terminal, the first end of the thirty-fourth capacitor C988 and the first end of the thirty-fifth capacitor C989 are both connected to the common connection terminal between the power supply pin VCC of the dual-input AND gate chip U67 and the 3.3V power supply terminal, the second end of the thirty-fourth capacitor C988 and the second end of the thirty-fifth capacitor C989 are both grounded; the output pin Y of the dual-input AND gate chip U67 is electrically connected to the base of the transistor Q9 through the thirty-second resistor R931 and the twenty-sixth resistor R929 in sequence.

[0105] In the above switch control subcircuit, a dual-input AND gate chip is added to the output end of the monitoring chip to convert the output signal of the monitoring chip and the output signal of the watchdog reset circuit (i.e. Figure 7 The signal output by the 706_WDO port in the output) is used as the two logic inputs of the dual-input AND gate chip respectively, which can be combined with the fault level signal at the input end of the power amplifier control path, the current sampling signal at the output end, and the reset signal to comprehensively control the on and off of the power amplifier control path, comprehensively consider the working status of the power amplifier control path, and truly and effectively avoid the situation where only one side has sound in the dual-amplifier playback mode.

[0106] Specifically, when the fault level signal at the input end of the power amplifier control path and the current sampling signal at the output end are both normal, the output signal of the monitoring chip is a high-level signal; when the power amplifier control path communicates normally, it receives the output signal of the watchdog reset circuit, and the output signal of the watchdog reset circuit is a high-level signal, then the dual-input AND gate chip outputs a high-level signal; correspondingly, the double-pole double-throw relay of the switch control subcircuit is in a normally closed state, that is, the corresponding power amplifier control path is in a conducting state. When at least one of the fault level signal at the input end of the power amplifier control path and the current sampling signal at the output end is abnormal, or when the power amplifier control path communicates abnormally, it does not receive the output signal of the watchdog reset circuit, then the dual-input AND gate chip outputs a low-level signal; correspondingly, the double-pole double-throw relay of the switch control subcircuit switches from a normally closed state to a normally open state, that is, the corresponding power amplifier control path is in a disconnected state.

[0107] It should be understood that Figure 3 , Figure 5 and Figure 6 Only one switch control subcircuit is shown in the specific circuit design diagram. The specific circuit designs of other switch control subcircuits are the same and will not be listed here. The monitoring chip in the switch control subcircuit uses the MAX16053 monitoring chip, the dual-input AND gate chip uses the SGM7SZ08YN5G / TR AND gate chip, the transistor uses the 1AM-MMBT3904 transistor, the double-pole double-throw relay uses the HF115F_005_2ZS4AF relay, and other electronic components can be selected according to the actual situation. Appropriate specifications or product models are not listed here.

[0108] Preferably, in each of the dual-amplifier playback modules, Figure 7 As shown, the watchdog reset circuit includes a watchdog chip U59, a dip switch S2, a reset button S3, a thirty-fifth resistor R997, a thirty-sixth capacitor C150 and a thirty-seventh capacitor C186;

[0109] In each of the dual-power amplifier playback modules, the reset button S3 has four contacts, contact No. 1 and contact No. 3 of the reset button S3 are connected together and grounded, contact No. 2 and contact No. 4 of the reset button S3 are also connected together and electrically connected to the manual reset pin MR of the watchdog chip U59, and contact No. 2 and contact No. 4 of the reset button S3 are also grounded through the thirty-seventh capacitor C186; the power supply pin VCC of the watchdog chip U59 is electrically connected to the 3.3V power supply end, the first end of the thirty-sixth capacitor C150 is connected to the common connection end between the power supply pin VCC of the watchdog chip U59 and the 3.3V power supply end, and the second end of the thirty-sixth capacitor C150 is grounded; the ground pin GND of the watchdog chip U59 and the electrical The source fault detection input pins PFI are all grounded; the reset output signal pin WDO of the watchdog chip U59 is electrically connected to the input ends of the two switch control sub-circuits, the static contact of the dip switch S2 is electrically connected to the manual reset pin MR of the watchdog chip U59, and the moving contact of the dip switch S2 is electrically connected to the reset output signal pin WDO of the watchdog chip U59; the reset pin RESET and the dog feeding signal input pin WDI of the watchdog chip U59 are both electrically connected to the corresponding controller, the first end of the thirty-fifth resistor R997 is electrically connected to the dog feeding signal input pin WDI of the watchdog chip U59, and the second end of the thirty-fifth resistor R997 is grounded; the power fault detection output pin PFO of the watchdog chip U59 is suspended.

[0110] The watchdog reset circuit of the above structure has two reset modes: manual reset and automatic reset. When the system crashes, shuts down, etc., the system reset operation is triggered to recover the system abnormality and ensure the reliability and stability of the system.

[0111] It should be understood that Figure 7 Only the specific circuit design diagram of the watchdog reset circuit in one dual-power amplifier playback module is shown. The specific circuit design of the watchdog reset circuit in another dual-power amplifier playback module is the same as this, which is not listed here. The watchdog chip in the watchdog reset circuit uses the ADM706SAR watchdog chip, and the other electronic components can be selected according to the actual situation. Appropriate specifications or product models are not listed here.

[0112] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A rail transit broadcast dual-power amplifier redundant playback system, characterized in that: It includes a first sound player, a second sound player and two dual-power amplifier playback modules with the same structure and redundancy; Each of the dual-power amplifier playback modules includes an audio input circuit, a CPU, a controller, a two-way power amplifier control path, and a two-way power amplifier monitoring circuit; the CPUs in the two dual-power amplifier playback modules are connected to communicate with each other; In each of the dual-power amplifier playback modules, the CPU is electrically connected to the controller and the two power amplifier control paths, the controller is electrically connected to the audio input circuit, the two power amplifier control paths and the two power amplifier monitoring circuits, the audio input circuit is electrically connected to the two power amplifier control paths, the two power amplifier control paths are electrically connected to the two power amplifier monitoring circuits in a one-to-one correspondence, one of the power amplifier control paths is electrically connected to the first sound player, and the other power amplifier control path is electrically connected to the second sound player; In any of the dual-power amplifier playback modules, the two power amplifier monitoring circuits are used to monitor the working status of the corresponding electrically connected power amplifier control path in real time, and send the working status to the corresponding electrically connected controller; The controller is used to determine whether the corresponding power amplifier control path is abnormal according to the received working states of the two paths; when at least one of the power amplifier control paths is abnormal, send a first control instruction to the two power amplifier control paths respectively to control the two power amplifier control paths to be disconnected; and generating path disconnection information, and sending the path disconnection information to the CPU of the corresponding electrical connection; the CPU sends the path disconnection information to the CPU in another dual-power amplifier playback module; In another dual-amplifier playback module, the CPU is used to send a second control instruction to the two corresponding electrically connected power amplifier control paths according to the received path disconnection information, so as to control the corresponding two power amplifier control paths to be turned on, so as to use one of the turned-on power amplifier control paths to control the first sound player to play the broadcast transmitted by the audio input circuit, and to use the other turned-on power amplifier control path to control the second sound player to play the broadcast transmitted by the audio input circuit.

2. The rail transit broadcast dual-power amplifier redundant playback system according to claim 1 is characterized in that: In each of the dual-power amplifier playback modules, the two power amplifier control paths include a power amplifier processing subcircuit, a filtering subcircuit and a switch control subcircuit; the input ends of the two power amplifier processing subcircuits are electrically connected to the output ends of the audio input circuits in the corresponding dual-power amplifier playback modules, and the input ends of the two power amplifier processing subcircuits are also electrically connected to the output ends of the controllers in the corresponding dual-power amplifier playback modules; the output ends of the two power amplifier processing subcircuits are electrically connected to the input ends of the corresponding switch control subcircuits through the corresponding filtering subcircuits; the input ends of the two switch control subcircuits are also electrically connected to the corresponding CPUs, the output end of one of the switch control subcircuits is electrically connected to the first sound player, and the output end of the other switch control subcircuit is electrically connected to the second sound player; In each of the dual-power amplifier playback modules, the input ends of the two power amplifier processing sub-circuits are also electrically connected to the power amplifier monitoring circuit in the corresponding dual-power amplifier playback module, and the output ends of the two power amplifier processing sub-circuits are also electrically connected to the power amplifier monitoring circuit in the corresponding dual-power amplifier playback module through the corresponding filtering sub-circuit.

3. The rail transit broadcasting dual-power amplifier redundant playback system according to claim 2 is characterized in that: Each power amplifier processing sub-circuit includes a power amplifier chip U61, a first Schottky diode D23, a fuse F8, a first diode D6, a first resistor R33, a second resistor R173, a fourth resistor R333, a fifth resistor R336, a sixth resistor R367, an eighth resistor R369, a ninth resistor R370, a tenth resistor R371, an eleventh resistor R372, a twelfth resistor R373, a thirteenth resistor R374, a fourteenth resistor R376, a fifteenth resistor R378, a sixteenth resistor R386, a seventeenth resistor R387, an eighteenth resistor R989, a first polarized capacitor C25, a second polarized capacitor C346, a third polarized capacitor C347, a fourth polarized capacitor C349, a first capacitor C21, a second capacitor C23, a third capacitor C32, a fourth capacitor C36, a fifth capacitor C331, a sixth capacitor C332, a seventh capacitor C333, an eighth capacitor C334, a ninth capacitor C335, a tenth capacitor C341, an eleventh capacitor C342, a twelfth capacitor C343, a thirteenth capacitor C344, a fourteenth capacitor C345, a fifteenth capacitor C348, a sixteenth capacitor C350, a seventeenth capacitor C351 and an eighteenth capacitor C352; In each of the power amplifier processing sub-circuits, the shutdown logic input pin #SD of the power amplifier chip U61 is electrically connected to the corresponding controller through the second resistor R173; the first end of the fifteenth resistor R378 and the cathode of the first diode D6 are electrically connected to the 3.3V power supply end, the second end of the fifteenth resistor R378, the anode of the first diode D6 and the first end of the ninth capacitor C335 are all connected to the common connection end between the shutdown logic input pin #SD of the power amplifier chip U61 and the second resistor R173, and the ninth capacitor C335 The second end of the power amplifier chip U61 is grounded; the fault detection pin #FAULT of the power amplifier chip U61 is electrically connected to the corresponding power amplifier monitoring circuit; the right channel positive input pin RINP of the power amplifier chip U61 is electrically connected to the corresponding controller through the fifth capacitor C331 and the sixteenth resistor R386 in sequence, and the right channel negative input pin RINN of the power amplifier chip U61 is grounded through the sixth capacitor C332 and the seventeenth resistor R387 in sequence; the mute pin MUTE of the power amplifier chip U61 is electrically connected to the corresponding controller through the eighteenth resistor R989; The right channel positive output pin OUTPR and the right channel negative output pin OUTNR of the power amplifier chip U61 are connected together, and are electrically connected to the first input end of the corresponding filtering sub-circuit; the right channel positive output bootstrap pin BSPR of the power amplifier chip U61 is electrically connected to the right channel positive output pin OUTPR of the power amplifier chip U61 through the third capacitor C32, and the right channel negative output bootstrap pin BSNR of the power amplifier chip U61 is electrically connected to the right channel negative output pin OUTNR of the power amplifier chip U61 through the tenth capacitor C341; The left channel positive output pin OUTPL and the left channel negative output pin OUTNL of the power amplifier chip U61 are connected together, and are electrically connected to the corresponding second input end of the filtering sub-circuit; the left channel positive output bootstrap pin BSPL of the power amplifier chip U61 is electrically connected to the left channel positive output pin OUTPL of the power amplifier chip U61 through the eleventh capacitor C342, and the left channel negative output bootstrap pin BSNL of the power amplifier chip U61 is electrically connected to the left channel negative output pin OUTNL of the power amplifier chip U61 through the twelfth capacitor C343; The first power supply pin PVCC0 and the second power supply pin PVCC1 of the power amplifier chip U61 are connected together and electrically connected to the 24V power amplifier power supply terminal; the cathode of the first Schottky diode D23 is connected to the common connection terminal between the first power supply pin PVCC0 of the power amplifier chip U61 and the 24V power amplifier power supply terminal, and the anode of the first Schottky diode D23 is electrically connected to the 24V power supply terminal through the fuse F8; the anode of the first polarized capacitor C25, the anode of the second polarized capacitor C346, and the cathode of the first capacitor C The first end of the first capacitor C21, the first end of the second capacitor C23, the first end of the thirteenth capacitor C344 and the first end of the fourteenth capacitor C345 are all connected to the common connection end between the first power supply pin PVCC0 of the power amplifier chip U61 and the 24V power amplifier power supply end, and the negative electrode of the first polarized capacitor C25, the negative electrode of the second polarized capacitor C346, the second end of the first capacitor C21, the second end of the second capacitor C23, the second end of the thirteenth capacitor C344 and the second end of the fourteenth capacitor C345 are all grounded; The third power supply pin PVCC2, the fourth power supply pin PVCC3 and the analog power supply pin AVCC of the power amplifier chip U61 are all connected together and electrically connected to the 24V power amplifier power supply terminal; the positive electrode of the third polar capacitor C347, the positive electrode of the fourth polar capacitor C349, the first end of the fifteenth capacitor C348, the first end of the sixteenth capacitor C350, the first end of the seventeenth capacitor C351 and the first end of the eighteenth capacitor C352 are all connected to the common connection terminal between the third power supply pin PVCC3 of the power amplifier chip U61 and the 24V power amplifier power supply terminal, and the negative electrode of the third polar capacitor C347, the negative electrode of the fourth polar capacitor C349, the second end of the fifteenth capacitor C348, the second end of the sixteenth capacitor C350, the second end of the seventeenth capacitor C351 and the second end of the eighteenth capacitor C352 are all grounded; The mode logic input pin MODSEL, the first ground pin GND0, the second ground pin GND1, the third ground pin GND2, the fourth ground pin GND3, the left channel positive input pin LINP and the left channel negative input pin LINN of the power amplifier chip U61 are all grounded; the power limit level pin PLMIT of the power amplifier chip U61 is grounded through the eighth capacitor C334; the upper tube gate drive voltage pin GVDD of the power amplifier chip U61 is grounded through the fourteenth resistor R376 and the fourth resistor R333 in turn, and the power limit level pin PLMIT of the power amplifier chip U61 is also connected to the fourteenth resistor R376 and the fourth resistor R333. The first end of the fourth capacitor C36 and the first end of the sixth resistor R367 are both connected to the common connection end between the upper tube gate drive voltage pin GVDD of the power amplifier chip U61 and the fourteenth resistor R376, the second end of the fourth capacitor C36 is grounded, and the second end of the sixth resistor R367 is grounded through the first resistor R33; the gain pin GAIN / SLV of the power amplifier chip U61 is connected to the common connection end between the sixth resistor R367 and the first resistor R33; the pins of the power amplifier chip U61 are grounded in sequence through the thirteenth resistor R374 and the seventh capacitor C333; The first end of the tenth resistor R371, the first end of the eleventh resistor R372 and the first end of the twelfth resistor R373 are all electrically connected to the 3.3V power supply end, the second end of the tenth resistor R371 is grounded through the fifth resistor R336, the second end of the eleventh resistor R372 is grounded through the eighth resistor R369, and the second end of the twelfth resistor R373 is grounded through the ninth resistor R370; the first frequency modulation pin AM0 of the power amplifier chip U61 is connected to the common connection end between the twelfth resistor R373 and the ninth resistor R370, the second frequency modulation pin AM1 of the power amplifier chip U61 is connected to the common connection end between the eleventh resistor R372 and the eighth resistor R369, and the third frequency modulation pin AM2 of the power amplifier chip U61 is connected to the common connection end between the tenth resistor R371 and the fifth resistor R336.

4. The rail transit broadcasting dual-power amplifier redundant playback system according to claim 3 is characterized in that: Each of the filtering sub-circuits includes a second Schottky diode D22, a third Schottky diode D24, a first inductor L15, a second inductor L16, a nineteenth resistor R379, a twentieth resistor R380, a twenty-first resistor R382, a nineteenth capacitor C34, a twentieth capacitor C35, a twenty-first capacitor C336, a twenty-second capacitor C337, a twenty-third capacitor C338, a twenty-fourth capacitor C339 and a twenty-fifth capacitor C340; In each filtering subcircuit, the first end of the first inductor L15 is connected to the common connection end between the right channel positive output pin OUTPR and the right channel negative output pin OUTNR of the corresponding power amplifier chip U61, the first end of the first inductor L15 is also connected to the common connection end between the first power supply pin PVCC0 of the corresponding power amplifier chip U61 and the 24V power amplifier power supply terminal through the second Schottky diode D22, and the second end of the first inductor L15 is electrically connected to the corresponding switch control subcircuit; The first end of the second inductor L16 is connected to the common connection end between the left channel positive output pin OUTPL and the left channel negative output pin OUTNL of the corresponding power amplifier chip U61, the first end of the second inductor L16 is also connected to the common connection end between the third power supply pin PVCC2 of the corresponding power amplifier chip U61 and the 24V power amplifier power supply terminal through the third Schottky diode D24, and the second end of the second inductor L16 is electrically connected to the corresponding switch control subcircuit through the twenty-first resistor R382; The first end of the nineteenth resistor R379, the first end of the nineteenth capacitor C34, the first end of the twentieth capacitor C35 and the first end of the twenty-third capacitor C338 are all connected to the common connection end between the second end of the first inductor L15 and the corresponding switch control subcircuit; the second end of the nineteenth resistor R379 is electrically connected to the first end of the twenty-first capacitor C336, the second end of the twenty-first capacitor C336 is grounded, the second end of the twenty-first capacitor C336 is also electrically connected to the first end of the twentieth resistor C380 through the twenty-second capacitor C337, and the second end of the twentieth resistor C380 is connected to the second inductor L16. and the common connection end between the second inductor L16 and the twenty-first resistor R382; the second end of the nineteenth capacitor C34 and the second end of the twentieth capacitor C35 are both grounded, the second end of the nineteenth capacitor C34 is also connected to the common connection end between the second inductor L16 and the twenty-first resistor R382 through the twenty-fifth capacitor C340, the second end of the twentieth capacitor C35 is also connected to the common connection end between the second inductor L16 and the twenty-first resistor R382 through the twenty-fourth capacitor C339; the second end of the twenty-third capacitor C338 is connected to the common connection end between the second inductor L16 and the twenty-first resistor R382.

5. The rail transit broadcast dual-power amplifier redundant playback system according to claim 4 is characterized in that: In each of the dual-power amplifier playback modules, the two power amplifier monitoring circuits each include an input fault detection subcircuit and an output current detection subcircuit; In each dual-power amplifier playback module, the two input fault detection subcircuits are electrically connected to the input ends of the two power amplifier processing subcircuits in a one-to-one correspondence, and the two output current detection subcircuits are electrically connected to the output ends of the two filtering subcircuits in a one-to-one correspondence.

6. The rail transit broadcast dual-power amplifier redundant playback system according to claim 5 is characterized in that: Each of the input fault detection sub-circuits includes a third resistor R328 and a fourth resistor R368; In each input fault detection sub-circuit, the first end of the third resistor R328 is electrically connected to the 3.3V power supply end, the second end of the third resistor R328 is electrically connected to the fault detection pin #FAULT of the corresponding power amplifier chip U61, the first end of the fourth resistor R368 is connected to the common connection end between the third resistor R328 and the corresponding fault detection pin #FAULT of the power amplifier chip U61, and the second end of the fourth resistor R368 is electrically connected to the corresponding controller.

7. The rail transit broadcasting dual-power amplifier redundant playback system according to claim 5 is characterized in that: Each output current detection subcircuit includes a current detection chip U55, a magnetic bead B23, a twenty-second resistor R938, a twenty-third resistor R939, a twenty-fourth resistor R972, a twenty-sixth capacitor C49, a twenty-seventh capacitor C50, a twenty-eighth capacitor C993 and a twenty-ninth capacitor C1022; In each output current detection sub-circuit, the positive input pin IN+ of the current detection chip U55 is connected to the common connection end between the second inductor L16 and the twenty-first resistor R382 in the corresponding filtering sub-circuit through the twenty-third resistor R939, and the negative input pin IN- of the current detection chip U55 is connected to the common connection end between the twenty-first resistor R382 and the switch control sub-circuit in the corresponding filtering sub-circuit through the twenty-second resistor R938; the first end of the twenty-eighth capacitor C993 is connected to the common connection end between the positive input pin IN+ of the current detection chip U55 and the twenty-third resistor R939, and the second end of the twenty-eighth capacitor C993 is connected to the common connection end between the negative input pin IN- of the current detection chip U55 and the twenty-second resistor R938; the current detection chip The first reference voltage pin REF1 and the power supply pin VS of the chip U55 are connected together, and are electrically connected to the 3.3V power supply end through the magnetic bead B23; the first end of the twenty-sixth capacitor C49 and the first end of the twenty-seventh capacitor C50 are both connected to the common connection end between the power supply pin VS of the current detection chip U55 and the magnetic bead, and the second end of the twenty-sixth capacitor C49 and the second end of the twenty-seventh capacitor C50 are both grounded; the output pin OUT of the current detection chip U55 is electrically connected to the corresponding controller through the twenty-fourth resistor R972, the first end of the twenty-ninth capacitor C1022 is connected to the common connection end between the twenty-fourth resistor R972 and the corresponding controller, and the second end of the twenty-ninth capacitor C1022 is grounded; the second reference voltage pin REF2 and the ground pin GND of the current detection chip U55 are both grounded.

8. The rail transit broadcast dual-power amplifier redundant playback system according to claim 2 is characterized in that: Each of the switch control subcircuits includes a monitoring chip U32, a transistor Q7, a second diode D59, a third diode D60, a double-pole double-throw relay U63, a connector J1, a fifth polarized capacitor C984, a sixth polarized capacitor C985, a twenty-fifth resistor R925, a twenty-sixth resistor R929, a twenty-seventh resistor R932, a twenty-eighth resistor R933, a twenty-ninth resistor R934, a thirtieth resistor R935, a thirty-first resistor R381, a thirtieth capacitor C135, a thirty-first capacitor C990, a thirty-second capacitor C991 and a thirty-third capacitor C992; the connector J1 has 5 pins; In each of the switch control sub-circuits, the enable pin EN of the monitoring chip U32 is electrically connected to the corresponding CPU through the twenty-ninth resistor R934, the first end of the twenty-eighth resistor R933 is connected to the common connection end between the enable pin EN of the monitoring chip U32 and the twenty-ninth resistor R934, and the second end of the twenty-eighth resistor R933 is grounded; the input pin IN of the monitoring chip U32 is electrically connected to the corresponding controller through the twenty-eighth resistor R935, the first end of the twenty-seventh resistor R932 is connected to the common connection end between the input pin IN of the monitoring chip U32 and the twenty-eighth resistor R935, and the second end of the twenty-seventh resistor R932 is grounded; the ground pin of the monitoring chip U32 is electrically connected to the corresponding controller through the twenty-eighth resistor R935, the first end of the twenty-seventh resistor R932 is connected to the common connection end between the input pin IN of the monitoring chip U32 and the twenty-eighth resistor R935, and the second end of the twenty-seventh resistor R932 is grounded; The external capacitor pin CDELAY of the monitoring chip U32 is grounded through the thirty-second capacitor C991, the first end of the thirty-third capacitor C992 is connected to the common connection end between the external capacitor pin CDELAY of the monitoring chip U32 and the thirty-second capacitor C991, and the second end of the thirty-third capacitor C992 is grounded; the power supply pin VCC of the monitoring chip U32 is electrically connected to the 3.3V power supply end, the first end of the 30th capacitor C135 and the first end of the thirty-first capacitor C990 are both connected to the common connection end between the power supply pin VCC of the monitoring chip U32 and the 3.3V power supply end, and the second end of the 30th capacitor C135 and the second end of the thirty-first capacitor C990 are both grounded; The output pin OUT of the monitoring chip U32 is electrically connected to the base of the transistor Q9 through the twenty-sixth resistor R929; the anode of the third diode D60, the anode of the sixth polarized capacitor C985 and the first end of the twenty-fifth resistor R925 are all connected to the common connection end between the twenty-sixth resistor R929 and the base of the transistor Q9, the cathode of the third diode D60 is connected to the common connection end between the output pin OUT of the monitoring chip U32 and the twenty-sixth resistor R929, and the cathode of the sixth polarized capacitor C985 and the second end of the twenty-fifth resistor R925 are both grounded; The emitter of the transistor Q9 is grounded, the collector of the transistor Q9 is electrically connected to the 5V power supply terminal through the second diode D59, the collector of the transistor Q9 is also electrically connected to the first connection end of the coil in the double-pole double-throw relay U63, the positive electrode of the fifth polar capacitor C984 and the second connection end of the coil in the double-pole double-throw relay U63 are both connected to the common connection end between the second diode D59 and the 5V power supply terminal, and the negative electrode of the fifth polar capacitor C984 is grounded; the first moving contact and the second moving contact of the double-pole double-throw relay U63 are both connected to the filter The output end of the wave sub-circuit is electrically connected, the first normally closed static contact of the double-pole double-throw relay U63 is electrically connected to the second normally closed static contact of the double-pole double-throw relay U63 through the thirty-first resistor R381, the first normally open static contact of the double-pole double-throw relay U63 is electrically connected to pin No. 1 of the connector J1, and the second normally open static contact of the double-pole double-throw relay U63 is electrically connected to pin No. 2 of the connector J1; pin No. 4 and pin No. 5 of the connector J1 are connected together and grounded and left suspended; the 5 pins of the connector J1 are also electrically connected to the first sound player.

9. The rail transit broadcasting dual-power amplifier redundant playback system according to claim 8 is characterized in that: Each of the dual-power amplifier playback modules also includes a watchdog reset circuit; In each of the dual-power amplifier playback modules, the input end of the watchdog reset circuit is electrically connected to the corresponding controller, and the output end of the watchdog reset circuit is electrically connected to the input ends of the two switch control sub-circuits.

10. The rail transit broadcasting dual-power amplifier redundant playback system according to claim 9 is characterized in that: Each of the switch control sub-circuits further includes a dual-input AND gate chip U67, a thirty-second resistor R931, a thirty-third resistor R936, a thirty-fourth resistor R937, a thirty-fourth capacitor C988 and a thirty-fifth capacitor C989; In each of the switch control sub-circuits, the first logic input terminal A of the dual-input AND gate chip U67 is electrically connected to the output terminal of the watchdog reset circuit through the thirty-fourth resistor R937, the second logic input terminal B of the dual-input AND gate chip U67 is electrically connected to the output pin OUT of the monitoring chip U32, the first end of the thirty-third resistor R936 is connected to the common connection terminal between the second logic input terminal B of the dual-input AND gate chip U67 and the output pin OUT of the monitoring chip U32, and the second end of the thirty-third resistor R936 is grounded; the ground pin G of the dual-input AND gate chip U67 is electrically connected to the ground pin G of the dual-input AND gate chip U67. ND is grounded; the power supply pin VCC of the dual-input AND gate chip U67 is electrically connected to the 3.3V power supply terminal, the first end of the thirty-fourth capacitor C988 and the first end of the thirty-fifth capacitor C989 are both connected to the common connection terminal between the power supply pin VCC of the dual-input AND gate chip U67 and the 3.3V power supply terminal, the second end of the thirty-fourth capacitor C988 and the second end of the thirty-fifth capacitor C989 are both grounded; the output pin Y of the dual-input AND gate chip U67 is electrically connected to the base of the transistor Q9 through the thirty-second resistor R931 and the twenty-sixth resistor R929 in sequence.

11. The rail transit broadcasting dual-power amplifier redundant playback system according to claim 9, characterized in that: In each of the dual-power amplifier playback modules, the watchdog reset circuit includes a watchdog chip U59, a dip switch S2, a reset button S3, a thirty-fifth resistor R997, a thirty-sixth capacitor C150 and a thirty-seventh capacitor C186; In each of the dual-power amplifier playback modules, the reset button S3 has four contacts, contact No. 1 and contact No. 3 of the reset button S3 are connected together and grounded, contact No. 2 and contact No. 4 of the reset button S3 are also connected together and electrically connected to the manual reset pin MR of the watchdog chip U59, and contact No. 2 and contact No. 4 of the reset button S3 are also grounded through the thirty-seventh capacitor C186; the power supply pin VCC of the watchdog chip U59 is electrically connected to the 3.3V power supply end, the first end of the thirty-sixth capacitor C150 is connected to the common connection end between the power supply pin VCC of the watchdog chip U59 and the 3.3V power supply end, and the second end of the thirty-sixth capacitor C150 is grounded; the ground pin GND of the watchdog chip U59 and the electrical The source fault detection input pins PFI are all grounded; the reset output signal pin WDO of the watchdog chip U59 is electrically connected to the input ends of the two switch control sub-circuits, the static contact of the dip switch S2 is electrically connected to the manual reset pin MR of the watchdog chip U59, and the moving contact of the dip switch S2 is electrically connected to the reset output signal pin WDO of the watchdog chip U59; the reset pin RESET and the dog feeding signal input pin WDI of the watchdog chip U59 are both electrically connected to the corresponding controller, the first end of the thirty-fifth resistor R997 is electrically connected to the dog feeding signal input pin WDI of the watchdog chip U59, and the second end of the thirty-fifth resistor R997 is grounded; the power fault detection output pin PFO of the watchdog chip U59 is suspended.

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