Design detection method of imaging system

Abstract

The invention relates to the technical field of imaging system design and detection, in particular to a design and detection method of an imaging system, which describes functional modules of the imaging system, formulates different detection strategies for a topology level from the aspects of a top-layer system and specific modules of a bottom layer, and improves the detection accuracy of the imaging system. Specific content and key points of design review and a corresponding detection method are formulated; for a design process stage, measures are formulated for each detection item from the perspective of a schematic diagram stage and a circuit board stage, and auxiliary detection is carried out by fully utilizing electrical rule detection of the schematic diagram and grouping equal-length detection and simulation work of the circuit board.

Description

Technical Field

[0001] The invention belongs to the technical field of imaging system design and detection, and in particular relates to a design and detection method for an imaging system. Background Art

[0002] The imaging system consists of multiple functional modules. To achieve stable and reliable operation of the imaging system, each functional module needs to work properly, and the interfaces between the functional modules need to be correctly designed and have sufficient compatibility. If any functional module in the imaging system has a design error or the connection between the functional modules has an error, it will cause errors in the application of the imaging system and even cause the entire design to fail.

[0003] In the first version of the imaging system design, errors in the principle design stage are often prone to occur, resulting in circuit breaks, short circuits, incorrect signal connection positions, insufficient design margins, signal reversals, etc., causing the circuit board to fly or fail.

[0004] In the process of circuit board design, due to the lack of understanding of power integrity and signal integrity, the working current is estimated incorrectly, resulting in too narrow line width, the working voltage difference is not carefully checked, resulting in insufficient safety spacing, or the lack of attention to the process leads to welding and assembly difficulties.

[0005] For programmable logic devices, most pins are exchangeable, but some dedicated pins are not exchangeable or occupied. If these dedicated pins are occupied or connected to other signals, it will cause abnormal operation. Summary of the invention

[0006] In view of this, the present invention aims to provide a design and detection method for an imaging system to solve the problems of large detection workload and low detection efficiency.

[0007] To achieve the above object, the technical solution created by the present invention is implemented as follows:

[0008] A design and testing method for an imaging system includes principle stage testing and circuit board stage testing, wherein the principle stage testing includes testing of common parts of the imaging system principle design and testing of special parts of the imaging system principle design, and the circuit board stage testing includes testing of common parts of the imaging system circuit board design and testing of special parts of the imaging system circuit board; wherein,

[0009] The common part of the imaging system principle design test includes the consistency test of the device pin number and name with the device manufacturer's information, the correctness test of the device pin connection signal, the consistency test of the positive and negative power supply and the positive and negative poles of the polarized capacitor, the voltage margin test of the filter capacitor, the single-point test of the electrical rules, the allowable range test of the total amount of the filter capacitor in the power chip, the consistency test of the number and capacity of the decoupling capacitors in the device with the manufacturer's requirements, the consistency test of the node definition of the connector and the signed interface file, and the processing method test of the idle pins;

[0010] The special part of the imaging system principle design test content includes the power-on sequence test of the loading configuration, the consistency test of the interface circuit and the construction specification, the matching test of the power supply range and input voltage range of the power chip and the design margin test, the matching test of the output voltage range of the power chip and the application, the test of the initial state of power-on, and the test of the power supply power-on delay margin;

[0011] The common part detection of the imaging system circuit board design includes the impedance diagram planning detection of the imaging system circuit board, the line width setting detection of the imaging system circuit board, the routing spacing setting detection of the imaging system circuit board, the placement direction of the device on the imaging system circuit board and the consistency detection of the interface constraints, the packaging and manual of the device on the imaging system circuit board and the consistency detection of the molding tooling, the teardrop detection of the non-power signal routing of the direct-insertion device on the imaging system circuit board, the design connectivity and short circuit detection of the imaging system circuit board, the consistency detection of the imaging system circuit board and the structural constraint file, the copper digging detection of multiple ground layers of the direct-insertion device on the imaging system circuit board, the detection of no vias and routing at the bottom of the power chip on the imaging system circuit board, the reference plane and via detection of the imaging system circuit board, the dispensing position detection of the device on the imaging system circuit board, the distance detection of the small capacitor around the direct-insertion array device on the imaging system circuit board, the topological link detection of the multi-point connection signal on the imaging system circuit board, and the priority order detection of the placement of the filter capacitor and the power supply chip on the imaging system circuit board;

[0012] The inspection contents of the special part of the imaging system circuit board include the inspection of the equal-length constraint group of the imaging system circuit board, the interference inspection of the binding wire and the device on the imaging system circuit board, the grounding anti-tear wire inspection of the rigid-flex board and the flexible belt on the imaging system circuit board, the device opening inspection of the protruding structural parts on the imaging system circuit board, the configuration level correctness inspection of the refresh chip on the imaging system circuit board, the key clock signal inspection of the imaging system circuit board, the routing inspection of the MGT correction signal on the imaging system circuit board, the lengthening inspection of the bottom pad of the high-power power chip on the imaging system circuit board, the rationality inspection of the LDO current limiting on the imaging system circuit board, the configuration pin inspection of the imaging system circuit board, the stamp hole setting inspection of the imaging system circuit board, the mounting hole spacing inspection of the molded device on the imaging system circuit board, and the insertion loss and return loss inspection of the high-frequency signal on the imaging system circuit board.

[0013] Furthermore, the consistency test contents of the device pin number and name with the device manufacturer's information are as follows:

[0014] Check whether the pin numbers and names of the components in the schematic diagram of the imaging system are consistent with the information provided by the component manufacturer;

[0015] Contents of correctness detection of device pin connection signals:

[0016] Check whether the signal names connected to the pins of each device in the imaging system are consistent with the pin names;

[0017] The consistency test contents of positive and negative power supply and positive and negative poles of polarized capacitors:

[0018] Check whether the high voltage end of the detector power supply chip and related power supply circuits outside the detector is connected to the positive pole of the polarity capacitor, and whether the low voltage end is connected to the negative pole of the polarity capacitor;

[0019] The voltage margin detection content of the filter capacitor is as follows:

[0020] Check whether the withstand voltage of the filter capacitors of each component of the imaging system is between 2 and 3 times the maximum voltage;

[0021] Single point inspection content of electrical rules:

[0022] Check whether there are isolated single points on the pins of each device in the imaging system that are not connected to other devices;

[0023] The allowable range of the total amount of filter capacitors in the power chip is tested as follows:

[0024] Check whether the capacitive load driven by the detector power supply chip and some power supply chips in the related power supply circuits outside the detector is within the allowable range;

[0025] Contents of consistency test between the number and capacity of decoupling capacitors in the device and the manufacturer's requirements:

[0026] Check whether the number and capacity of decoupling capacitors in each device of the imaging system are consistent with the manufacturer's requirements;

[0027] The consistency check content of the connector's node definition and the signed interface file is as follows:

[0028] Check whether the connector node definitions in the imaging system are consistent with the requirements of the signed interface document

[0029] Idle pin processing method detection content:

[0030] Check whether the unused pins of the imaging system components are grounded.

[0031] Furthermore, the grounding methods include external direct grounding, resistor grounding, and internal grounding set by software.

[0032] Furthermore, the signed interface document includes data transmission and power supply parts.

[0033] Furthermore, the power-on sequence detection content of the load configuration is as follows:

[0034] Check whether the power-on sequence of related power supply circuits, except the detectors related to FPGA loading configuration, is consistent with the manual;

[0035] Contents of consistency test between interface circuit and construction specification:

[0036] Check whether the level of the initial state of the interface circuit is stable and whether the voltage threshold of the corresponding interface chip meets the construction specifications;

[0037] The matching of the power supply range and input voltage range of the power chip and the design margin detection content:

[0038] Check whether the input voltage range allowed by the detector power supply chip and related power supply circuits outside the detector is greater than the actual input voltage range, whether the maximum output voltage range allowed is greater than the voltage range required by the application, whether the input-output voltage difference is greater than the voltage difference requirement of the power supply chip, and whether the difference between the input bias power supply voltage and the output voltage is greater than the voltage requirement allowed by the data provided by the manufacturer;

[0039] The output voltage range of the power chip and the matching test content of the application:

[0040] Check whether the power supply chip of the detector, the related power supply circuit outside the detector, the data transmission interface, and the power-on initial state level set by the controller interface make the output in a prohibited state;

[0041] Detection of the initial state of power-on and the power-on delay margin:

[0042] Check whether the rising edge time of each power supply in the detector power supply chip and related power supply circuits outside the detector is within the allowable range of the manual, and whether the relative delay time of each power supply is within the allowable range of the manual.

[0043] Furthermore, the impedance diagram of the imaging system circuit board is planned to detect the following:

[0044] Check the impedance of the single-ended signal of the imaging system circuit board and whether the impedance of the differential signal is consistent with the internal impedance of the imaging system device;

[0045] Imaging system circuit board line width setting detection content:

[0046] Check whether the trace width on the imaging system circuit board, the trace width of the detector power supply chip and related power supply circuits outside the detector, and other non-power and impedance control signals meet the trace width requirements;

[0047] Imaging system circuit board trace spacing setting test content:

[0048] Check whether the safety distance between the components and structural parts on the imaging system circuit board and the safety distance determined by the processing accuracy and the pressure difference of the adjacent networks meet the safety distance requirements;

[0049] Contents of consistency test of device placement direction and interface constraints on imaging system circuit boards:

[0050] Check whether the direction of the angled connector on the imaging system circuit board and the size of the board frame are consistent with the interface constraint file;

[0051] The packaging and manual of the components on the imaging system circuit board and the consistency test content with the molding tooling:

[0052] Check whether the high-stacked devices on the imaging system circuit board have pads at the contact position between the device pin heel and the pad, whether the total length of the pads of all devices is 3.5-4mm, and whether the distance between the inner side of the pad and the device body is not less than 0.5mm;

[0053] Teardrop detection content of non-power signal traces of plug-in devices on imaging system circuit boards:

[0054] Check whether teardrops are added to the plug-in devices on the imaging system circuit board for reinforcement;

[0055] Design connectivity and short circuit detection content of imaging system circuit board:

[0056] By confirming the connectivity of the entire link, it is detected whether the pseudo single point on the imaging system circuit board is connected to two device pins, and by confirming the number of nodes and signal names connected at the same time, it is detected whether the prohibited pins are disconnected;

[0057] Contents of consistency test between imaging system circuit board and structural constraint file:

[0058] Check whether the relative positions of the components on the imaging system circuit board are consistent with the constraint file;

[0059] Copper digging detection content of multiple ground layers of direct-insertion devices on the circuit board of the imaging system:

[0060] Check whether the grounding holes of through-hole devices with multiple ground layers are connected to the large ground area using hot air pads or cross connections, and check whether the specified ground layer is dug at the pin position of the through-hole device;

[0061] The inspection contents of no vias and traces at the bottom of the power chip on the imaging system circuit board are as follows:

[0062] Check whether non-grounded vias and traces appear in the bottom package of the device;

[0063] Imaging system circuit board reference plane and via detection content:

[0064] Check whether the key signals of the imaging system circuit board have at least one complete ground reference plane, whether they cross the partition area of ​​another reference plane, and whether the number of link vias exceeds 3; whether the low-frequency signal has at least one complete ground reference plane, and whether the number of times it crosses the partition area of ​​another reference plane exceeds 3;

[0065] Imaging system circuit board device dispensing position detection content:

[0066] Check whether there are vias and pads at the four corners of the glue spots on each device on the imaging system circuit board;

[0067] Distance detection content of small capacitors around the plug-in array devices on the imaging system circuit board:

[0068] Check whether the lateral spacing between the DIP array device and the surrounding small capacitors on the imaging system circuit board is less than 0.63mm, and whether the spacing in other directions is less than 1.5mm;

[0069] Topology link detection content of multi-point connection signals on the imaging system circuit board:

[0070] Check whether the multi-point connection signals on the imaging system circuit board are designed according to the daisy chain topology;

[0071] Priority order of placement of filter capacitors and power supply chips on the imaging system circuit board Inspection content:

[0072] Check whether the priority order of placing the detector filter capacitor and the power supply chip on the imaging system circuit board is: small capacitor first, then large capacitor, pixel first, then digital power supply; Check whether the priority order of placing the imaging controller filter capacitor on the imaging system circuit board is: small capacitor first, then large capacitor.

[0073] Furthermore, the detection content of the equal length constraint group of the imaging system circuit board is as follows:

[0074] Check whether the signals on the imaging system circuit board that change synchronously with temperature are set as equal-length constraint groups, and whether the number of vias and the position of the distribution layer of the signals in the equal-length constraint groups are the same;

[0075] Interference detection content of binding wires and devices on the imaging system circuit board:

[0076] Check whether the devices near the binding wires in the relevant power supply circuits other than the detector on the imaging system circuit board are away from the binding wires;

[0077] Inspection contents of grounding anti-tear wire of rigid-flex board and flex tape on imaging system circuit board:

[0078] Check whether to set an anti-tear line if the layers of the rigid-flex PCB are all wide power signals; check whether to set an anti-tear line if the edges of the rigid-flex PCB are non-power signal lines; check whether to ensure that external interference is superimposed on the anti-tear line if the anti-tear line is grounded;

[0079] Contents of device opening inspection of protruding structural parts on imaging system circuit boards:

[0080] Devices for detecting whether the imaging system circuit board avoids protruding structural parts;

[0081] Contents of the configuration level correctness test of the refresh chip on the imaging system circuit board:

[0082] Check whether the flash capacity, flash quantity, and FPGA type connected to the refresh chip on the imaging system circuit board are configured according to the actual situation;

[0083] Key clock signal detection content of imaging system circuit board:

[0084] Check whether the power supply on the imaging system circuit board is low-noise, and whether the low-jitter clock uses a clock splitter or a separate bank of the FPGA;

[0085] Contents of the MGT correction signal routing test on the imaging system circuit board:

[0086] Check whether the MGT correction signal and reference signal of the imaging controller are separately routed and connected between the two pads of the resistor and the FPGA pad;

[0087] Lengthening test contents of the bottom pad of the high-power power chip on the imaging system circuit board:

[0088] Check whether the detector power supply chip and related power supply circuits outside the detector have lengthened the bottom pad;

[0089] Reasonableness test contents of LDO current limiting on imaging system circuit board:

[0090] Check the LDO in the detector power supply chip and related power supply circuits outside the detector. Check whether the setting of the current limiting resistor takes into account the peak current of the load startup in the case of filter capacitance, and whether at least 20% margin is left;

[0091] Configuration pin detection content of imaging system circuit board:

[0092] Check whether the dedicated configuration pins of the imaging controller and the refresh chip are connected according to the configuration pins specified in the information provided by the chip manufacturer;

[0093] Imaging system circuit board stamp hole setting detection content:

[0094] Check whether the stamp holes on the imaging system circuit board are arranged at a pitch of 70 mm;

[0095] Contents of the inspection of the mounting hole spacing of the molded components on the imaging system circuit board:

[0096] Check whether the spacing between the mounting holes of the molded components on the imaging system circuit board meets the requirement that the total length from both sides of the molded component body to the pads at both ends does not exceed 25.4mm;

[0097] Insertion loss and return loss test contents of high frequency signals on imaging system circuit boards:

[0098] Check whether the insertion loss and return loss of high-frequency signals on the imaging system circuit board meet industry standards.

[0099] Compared with the prior art, the invention can achieve the following beneficial effects:

[0100] 1. Split the design test into principle stage test and circuit board stage test. There are different test focuses at different stages. The principle stage test focuses on the test of design principles, while the circuit board stage test focuses on the specific implementation process test. This can greatly reduce the workload of testing and improve the testing efficiency.

[0101] 2. For the numerous test items in the two test stages, they are further differentiated according to the characteristics of the common parts and specific functional modules. First, each test item is described from a universal perspective, and then the special requirements of the specific functional modules are explained according to their characteristics, which can greatly reduce the workload of the test and improve the test efficiency.

[0102] 3. In the schematic design stage, make full use of the electrical rule detection of the schematic to eliminate a large number of single-point errors; for pseudo-single-point errors where the number of connection points has reached 2 but the system is not fully connected, the single-point statistics of the electrical rule detection of the schematic cannot detect errors, especially in the process of schematic optimization and modification, which may cause pseudo-single-point errors if the modification is incomplete; in the circuit board design stage, use the manually designed detection rules to count whether the number of nodes connected to the signal network meets the requirements, and whether it is connected with the expected input and output signals; in addition, use the grouping equal length rule to further detect whether the required signal is connected. You can also use the insertion loss and return loss simulation between nodes in the circuit board for auxiliary detection, which can detect errors that existing tools cannot detect and reduce the probability of errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0103] The drawings constituting part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments and descriptions of the present invention are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0104] Figure 1 It is a schematic diagram of the structure of an imaging system according to an embodiment of the invention. DETAILED DESCRIPTION

[0105] In order to make the purpose, technical solution and advantages of the invention more clear, the invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the invention and do not constitute a limitation of the invention.

[0106] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0107] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0108] In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0109] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0110] The design and detection method of the imaging system provided by the embodiment of the present invention is used for Figure 1 The various functional modules of the imaging system shown are tested.

[0111] like Figure 1 As shown, the imaging system includes an imaging controller, a detector, a detector power supply chip, a detector driver chip, a local reference crystal, a data transmission interface, a flash 2 for storing configuration data, a refresh chip, a flash 1 for storing configuration data, an interface of the controller, related power supply circuits outside the detector, a correction coefficient flash, a correction coefficient MRAM, a temperature processing chip, a local reference clock crystal, and a connector.

[0112] The power supply circuit outside the detector provides power to chips other than the detector.

[0113] The local reference clock crystal provides the system reference clock for the imaging controller, samples the master-slave identification signal in the interface of the controller, and performs master-slave switching. Under the synchronous control of the system reference clock and the master-slave identification signal, the master-slave homologous clock in the interface of the controller is switched as the system clock of the imaging controller; the three-mode redundant master-slave identification signal, the master-slave 422 communication signal, the master-slave line synchronization and second pulse signal, the master-slave camera start and stop, the detector power on and off, and the timing reset signal are also connected to the program controller by the master-slave switch.

[0114] The imaging controller provides the detector with a high-frequency clock synchronized with the detector; outputs a power supply control signal to control the detector power supply chip, and outputs the required power supply according to the detector power-on sequence; outputs the detector's SPI signal to configure the detector's internal registers, and receives the debug signal returned by the detector; outputs the detector's drive control signal, which is then level-converted by the detector drive chip and sent to the detector. The parallel data and accompanying clock output by the detector are sent to the imaging controller for serial image data conditioning, including non-uniform correction using correction coefficients; the imaging controller outputs the digital transmission signal and configuration signal to the digital transmission interface. The imaging controller configures the temperature sensor; the analog temperature signal output by the detector is converted into a digital signal by the temperature processing chip and sent to the imaging processor. The local reference crystal provides a reference clock for the digital transmission-related circuits inside the imaging controller.

[0115] Both the correction coefficient RAM and the correction coefficient flash are used to store the correction coefficients, and the imaging controller selects one of the correction coefficients to use according to the application needs. Flash1 storing configuration data and flash2 storing configuration data are both used to store the configuration data of the imaging controller. The configuration data in flash1 storing configuration data can be read out under the control of the refresh chip to load the configuration of the imaging controller, and the configuration data can also be updated; there is a refresh control signal between the refresh chip and the controller interface; the configuration falsh address, data and control signal 1 of flash1 storing configuration data are generated by the refresh chip. The configuration data in flash2 storing configuration data can only be read out in the imaging controller in master-parallel or master-serial mode, and after the data is written, it can only be updated through the JTAG port of the imaging controller; the configuration falsh address, data and control signal 2 of flash1 storing configuration data are generated by the imaging controller.

[0116] In a specific embodiment of the present invention, (1) the imaging controller uses the FPGA of Shanghai Fudan Microelectronics Co., Ltd.; (2) the detector uses the TDICMOS detector of Changguang Chenxin Co., Ltd.; (3) the detector power supply chip mainly uses the TPS7H1101 of TI of the United States; (4) the detector driver chip is mainly based on the level conversion chip 164245; (5) the local reference crystal and the local reference clock crystal use the crystal products of Wuhan Haichuang Co., Ltd.; (6) the flash2 for storing configuration data, the flash1 for storing configuration data, and the correction coefficient flash use the flash products of Shanghai The flash chip of Fudan Microelectronics Co., Ltd.; (7) The related power supply circuit outside the detector adopts the RSW1101 chip of Beijing Shengyu Co., Ltd.; (8) The correction coefficient MRAM adopts the MRAM of 3DPLUS Co., Ltd.; (9) The temperature processing chip adopts the temperature sensor chip of Beijing Shengyu Co., Ltd.; (10) The refresh chip adopts the refresh chip JFMRS01RH of Fudan Micro; (11) The interface of the controller mainly adopts 54AC14, DS26LV31 and DS26LV32; (12) The data transmission interface adopts the TLK2711 chip or the optical fiber module chip.

[0117] The design and detection method of the imaging system provided by the embodiment of the invention includes principle stage detection and circuit board stage detection. The principle stage detection includes detection of common parts of the imaging system principle design and detection of special parts of the imaging system principle design. The circuit board stage detection includes detection of common parts of the imaging system circuit board design and detection of special parts of the imaging system circuit board.

[0118] The following is a detailed description of the four major inspection contents: the common part inspection of the imaging system principle design, the special part inspection of the imaging system principle design, the common part inspection of the imaging system circuit board design and the special part inspection of the imaging system circuit board.

[0119] 1. The common part of the imaging system principle design is tested, including the following 9 parts:

[0120] 1. Check the consistency between the device pin number and name and the device manufacturer's information

[0121] The imaging system includes imaging controller, detector, detector power supply chip, detector driver chip, local reference crystal, data transmission interface, flash2 for storing configuration data, refresh chip, flash1 for storing configuration data, controller interface, related power supply circuit outside the detector, correction coefficient flash, correction coefficient MRAM, temperature processing chip, local reference clock crystal, etc. Check whether the pin numbers and names of these components in the schematic diagram are consistent with the information provided by the component manufacturer.

[0122] 2. Check the signal correctness of device pin connection

[0123] The detection requires whether the signal name connected to the imaging system device pin is consistent with the pin name; including the detector pin with differential signal, whether the positive and negative polarity of the connected signal is consistent with the device pin; in addition, the single-ended clock signal can only be connected to the positive end. If the positive end is already connected to the single-ended clock, the corresponding differential signal n-end can only be left floating and cannot be connected to other signals.

[0124] 3. Check the consistency of the positive and negative power supply and the positive and negative poles of the polarized capacitor

[0125] It is required that the high voltage terminal of the detector power supply chip and related power supply circuits outside the detector be connected to the positive pole of the polarity capacitor, and the low voltage terminal be connected to the negative pole of the polarity capacitor.

[0126] 4. Voltage tolerance test of filter capacitor

[0127] The filter capacitor of the imaging system device is required to withstand a voltage no less than 2 times the maximum voltage, and should not be higher than 3 times the maximum voltage.

[0128] 5. Single point detection of electrical rules

[0129] Check whether there are isolated single points on the imaging system device pins that are not connected to other devices.

[0130] 6. Detection of the allowable range of the total amount of filter capacitance of the power chip

[0131] The detector power supply chip and some power supply chips such as LDO in the related power supply circuit outside the detector can carry limited capacitive load. Insufficient filter capacitor capacity will lead to unstable output voltage. Excessive filter capacitor may also cause changes in the designed zero poles and instability. Excessive filter capacitor capacity may also cause excessive startup current of the power supply chip and current limiting protection. In this case, it is necessary to power on the subsequent load in time or reduce the total capacity of the filter capacitor.

[0132] 7. Check the consistency between the number and capacity of the device's decoupling capacitors and the manufacturer's requirements

[0133] Check whether the number and capacity of decoupling capacitors of the imaging controller, detector, local reference crystal, data transmission interface, flash2 for storing configuration data, refresh chip, flash1 for storing configuration data, controller interface, related power supply circuits outside the detector, correction factor flash, correction factor MRAM, temperature processing chip, and local reference clock crystal are consistent with the manufacturer's requirements.

[0134] 8. Check the consistency between the connector's node definition and the signed interface file

[0135] Check whether the connector node definition in the imaging system is consistent with the interface document requirements signed by the power supply, data transmission and other parts.

[0136] 9. Detection of processing methods without pins

[0137] Detect unused pins of imaging system components, such as unused input power supplies, which need to be directly grounded externally, or grounded through resistors, or internally grounded through software settings.

[0138] 2. Special part inspection of imaging system principle design, including the following 5 parts:

[0139] 1. Power-on sequence detection for loading configuration

[0140] Whether the power-on sequence of related power supply circuits other than the detectors related to FPGA loading configuration is consistent with the manual; evaluate whether potential paths in interface circuits such as the controller interface will cause FPGA loading configuration failure.

[0141] 2. Whether the interface circuit is consistent with the construction specifications

[0142] Check whether the initial state level of the interface circuit, such as the controller interface, data transmission interface, etc., is stable, and whether the voltage threshold of the corresponding interface chip meets the construction specifications, such as the satellite construction specifications.

[0143] 3. Check the matching of the power supply range and input voltage range of the power chip and the design margin; check the matching of the output voltage range of the power chip and the application

[0144] The test objects are the detector power supply chip and related power supply circuits outside the detector. The allowed input voltage range should be larger than the actual input voltage range; the allowed maximum output voltage range should be larger than the voltage range required by the application; the input-output voltage difference should be larger than the voltage difference requirement of the power supply chip; the difference between the input bias power supply voltage and the output voltage should be larger than the voltage requirement allowed by the data provided by the manufacturer;

[0145] 4. Detection of power-on initial state

[0146] The detection objects are the detector power supply chip, related power supply circuits outside the detector, data transmission interface, and controller interface. The power-on initial state level is required to be set to make the output in a disabled state.

[0147] 5. Detection of power-on delay margin

[0148] The detection objects are the detector power supply chip and related power supply circuits outside the detector. The rising edge time of each power supply is required to be within the allowable range of the manual; the relative delay time of each power supply is required to be within the allowable range of the manual.

[0149] 3. Common part detection of imaging system circuit board design, including the following 15 parts:

[0150] 1. Impedance diagram planning of imaging system circuit board

[0151] The impedance of the single-ended signal of the imaging system circuit board is required to be 40-50 ohms, and the impedance of the differential signal is required to be 80-100 ohms, which should be consistent with the internal impedance of the imaging system device. At the same time, the line width should not be less than 4 mils.

[0152] 2. Line width setting of imaging system circuit board

[0153] The trace width on the imaging system circuit board depends on the impedance diagram. The trace width of the detector power supply chip and related power supply circuits outside the detector depends on the current carrying size and the thickness of the copper layer; the remaining non-power and impedance control signals only need to meet the minimum line width.

[0154] 3. Setting the trace spacing of the imaging system circuit board

[0155] Including the safe distance between devices and structural parts on the imaging system circuit board; the safe distance determined by the processing accuracy and the pressure difference of adjacent networks; the processing accuracy requires a minimum spacing of 4 mils.

[0156] 4. Whether the placement direction of the imaging system circuit board components is consistent with the interface constraints

[0157] The direction of the angled connector on the imaging system circuit board and the size of the board frame must be consistent with the interface constraint file.

[0158] 5. The packaging of the imaging system circuit board components is consistent with the manual and consistent with the molding tooling.

[0159] The pad design of high-stack devices such as correction factor MRAM on the imaging system circuit board must ensure that there are pads in the front and back range of the device pin toe contact position; the total length of all device pads is 3.5 to 4 mm, and the distance between the inner side of the pad and the device body is not less than 0.5 mm.

[0160] 6. Teardrop detection of non-power signal lines of plug-in devices on imaging system circuit boards

[0161] During installation and vibration experiments, thin wires on the imaging system circuit board, such as connectors, are prone to breakage without teardrop reinforcement, so teardrops need to be added for reinforcement.

[0162] 7. Design connectivity detection and short circuit detection of imaging system circuit boards

[0163] The imaging system circuit board has two device pins connected at a pseudo-single point, and the single-ended detection rule does not apply. In fact, they are still not connected, and it is easy to detect by confirming the connectivity of the entire link. For pins that do not want to be connected, they cannot be detected by the electrical rule detection of the schematic diagram after being connected together. They need to be confirmed by confirming the number of nodes connected at the same time and the signal name.

[0164] 8. Consistency test between imaging system circuit board and structural constraint file

[0165] Check whether the relative positions of the components on the imaging system circuit board are consistent with the constraint file, and perform simulated assembly confirmation through the three-dimensional diagram on the circuit board.

[0166] 9. Copper digging detection of multiple ground layers of direct-insertion devices on circuit boards of imaging systems

[0167] For through-hole devices with multiple grounding layers, such as detectors, some detector power supply chips, connectors, etc., in order to avoid too much equivalent heat dissipation area caused by connecting too many bottom layers and resulting in cold soldering, hot air pads or cross connections are used between the grounding holes and the large ground area. At the same time, only connections with three grounding layers are retained, such as the top, bottom and middle ground layers. The remaining ground layers are copper-dug at the pin positions of the through-hole devices.

[0168] 10. Detection of no vias and traces at the bottom of the power chip on the imaging system circuit board

[0169] For high-power devices with heat dissipation requirements, the detector power supply chip of the imaging system circuit board and related power supply circuits outside the detector are usually provided with a grounded thermal pad at the bottom of the device. In order to avoid short circuits or insufficient safety distance between the thermal pad at the bottom of the device and the vias and traces, non-grounded vias and traces are not allowed to appear in the bottom package of the device.

[0170] 11. Imaging system circuit board reference plane and via detection

[0171] Key signals of the imaging system circuit board, such as signals and clocks with a frequency exceeding 1 GHz in the data transmission interface, need to have at least one complete ground reference plane and cannot cross the partition of another reference plane. The number of link vias should not exceed 3. Low-frequency signals, such as signals of the controller interface, need to have at least one complete ground reference plane and cannot cross the partition of another reference plane more than 3 times.

[0172] 12. Detection of dispensing position of high components on circuit boards of imaging systems

[0173] In the imaging system circuit board, there are places for glue dots at the four corners of the imaging controller, detector, refresh chip, correction coefficient MRAM and other devices, without vias and pads; the distance between the detection and the devices on the same layer should be kept at 3-5mm.

[0174] 13. Distance detection of small capacitors around direct-insertion array devices on imaging system circuit boards

[0175] The array devices directly plugged into the imaging system circuit board, such as detectors and some detector power supply chips, are required to have a lateral spacing of no less than 0.63mm from the surrounding small capacitors, and a spacing of no less than 1.5mm in other directions.

[0176] 14. Topology link detection of multi-point connection signals on imaging system circuit boards

[0177] Multi-point connection signals on the imaging system circuit board, such as some signals on the control interface, need to be designed according to the daisy chain topology.

[0178] 15. Priority detection of filter capacitors and power supply chip placement on imaging system circuit boards

[0179] The priority of placing the detector filter capacitor and power supply chip on the imaging system circuit board is: small capacitor first, then large capacitor, pixel first, then digital power supply, pixel power supply first; the filter capacitor should be as close to the load end as possible. The priority of placing the imaging controller filter capacitor is: small capacitor first, then large capacitor.

[0180] 4. Inspection of dedicated parts of imaging system circuit board, including the following 13 parts:

[0181] 1. Detection of equal length constraint groups of imaging system circuit boards

[0182] For signals on the imaging system circuit board that are required to change synchronously with temperature, such as signals related to the detector and imaging controller, they need to be set as equal-length constraint groups and routed with equal lengths. The number of vias and the position of the distribution layer of the signals within the group must be the same.

[0183] 2. Imaging system circuit board binding wire and device interference detection

[0184] In the related power supply circuits other than the detector on the imaging system circuit board, the devices near the binding wires are required to be arranged away from the binding wires.

[0185] 3. Grounding anti-tear wire detection of rigid-flex board and flex tape

[0186] In the imaging system circuit board, if the flex tape layer is full of wide power signals, there is no need to set an anti-tear wire; if the edge of the flex tape is a non-power signal line, an anti-tear wire is required; the anti-tear wire is grounded to ensure that external interference will not be superimposed on the anti-tear wire to interfere with the signal.

[0187] 4. Opening notches on protruding structural parts

[0188] In the imaging system circuit board, if there are devices with protruding structural parts in the data transmission interface, it is necessary to avoid the protruding structural parts on the circuit board.

[0189] 5. Check the correctness of the configuration level of the refresh chip

[0190] The capacity, number of flash memories, FPGA type, etc. of the flash memory connected to the refresh chip in the imaging system circuit board need to be configured according to actual conditions.

[0191] 6. Detection of key clock signals

[0192] The high-speed clock in the digital transmission interface of the imaging system circuit board is connected in a point-to-point manner. The power supply requires low noise and low-jitter clocks. The clock splitter or a separate bank of the FPGA is used to provide it.

[0193] 7. Routing detection of MGT correction signal MGTVTTRCAL of imaging system circuit board

[0194] The imaging system circuit board requires that the imaging controller's MGT correction signal MGTVTTRCAL and reference signal MGTRREF be separately routed and connected between the two pads of the resistor and the FPGA pad.

[0195] 8. Lengthen the bottom pad of the high-power power chip on the imaging system circuit board

[0196] For high-power power chips with heat dissipation pads at the bottom of the imaging system circuit board, such as the detector power supply chip of the imaging system circuit board and related power supply circuits outside the detector, the bottom pads are lengthened to facilitate manual soldering and rework.

[0197] 9. Rationality test of LDO current limiting on imaging system circuit board

[0198] For imaging system circuit board LDO, such as the detector power supply chip of the imaging system circuit board and the LDO in the related power supply circuit outside the detector, the current limiting resistor cannot be set according to the rated current of the load. It is necessary to consider the peak current of the load startup in the case of filter capacitor and leave at least 20% margin.

[0199] 10. Detection of configuration pins on imaging system circuit board

[0200] Confirm the connection relationship between the dedicated configuration pins of the imaging controller and the refresh chip in the imaging system circuit board, such as checking whether the configuration pins specified in the information provided by the chip manufacturer are connected.

[0201] 11. Inspection of stamp hole settings on circuit boards of imaging systems

[0202] The stamp holes on the imaging system circuit board are arranged at a spacing of 70 mm.

[0203] 12. Detection of mounting hole spacing of molding components on circuit boards of imaging systems

[0204] The mounting hole spacing requirements of molded components such as through-hole diodes in the control interface of the imaging system circuit board must be met, and the total length from both sides of the component body to the pads at both ends shall not exceed 25.4mm.

[0205] 13. Insertion loss and return loss detection of high-frequency signals on imaging system circuit boards

[0206] The insertion loss and return loss of high-frequency signals in the digital transmission interface of the imaging system circuit board are required to meet industry standards such as PCIE4.0.

[0207] The advantages of the imaging system design and detection method provided by the embodiment of the present invention are as follows:

[0208] 1. Split the design test into principle stage test and circuit board stage test. There are different test focuses at different stages. The principle stage test focuses on the test of design principles, while the circuit board stage test focuses on the specific implementation process test. This can greatly reduce the workload of testing and improve the testing efficiency.

[0209] 2. For the numerous test items in the two test stages, they are further differentiated according to the characteristics of the common parts and specific functional modules. First, each test item is described from a universal perspective, and then the special requirements of the specific functional modules are explained according to their characteristics, which can greatly reduce the workload of the test and improve the test efficiency.

[0210] 3. In the schematic design stage, make full use of the electrical rule detection of the schematic to eliminate a large number of single-point errors; for pseudo-single-point errors where the number of connection points has reached 2 but the system is not fully connected, the single-point statistics of the electrical rule detection of the schematic cannot detect errors, especially in the process of schematic optimization and modification, which may cause pseudo-single-point errors if the modification is incomplete; in the circuit board design stage, use the manually designed detection rules to count whether the number of nodes connected to the signal network meets the requirements, and whether it is connected with the expected input and output signals; in addition, use the grouping equal length rule to further detect whether the required signal is connected. You can also use the insertion loss and return loss simulation between nodes in the circuit board for auxiliary detection, which can detect errors that existing tools cannot detect and reduce the probability of errors.

[0211] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the disclosure of the present invention can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0212] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A design and detection method for an imaging system, characterized in that: It includes principle stage detection and circuit board stage detection. The principle stage detection includes the detection of the common parts of the imaging system principle design and the detection of the special parts of the imaging system principle design. The circuit board stage detection includes the detection of the common parts of the imaging system circuit board design and the detection of the special parts of the imaging system circuit board; among them, The common part of the imaging system principle design test includes the consistency test of the device pin number and name with the device manufacturer's information, the correctness test of the device pin connection signal, the consistency test of the positive and negative power supply and the positive and negative poles of the polarized capacitor, the voltage margin test of the filter capacitor, the single-point test of the electrical rules, the allowable range test of the total amount of the filter capacitor in the power chip, the consistency test of the number and capacity of the decoupling capacitors in the device with the manufacturer's requirements, the consistency test of the node definition of the connector and the signed interface file, and the processing method test of the idle pins; The special part of the imaging system principle design test content includes the power-on sequence test of the loading configuration, the consistency test of the interface circuit and the construction specification, the matching test of the power supply range and input voltage range of the power chip and the design margin test, the matching test of the output voltage range of the power chip and the application, the test of the initial state of power-on, and the test of the power supply power-on delay margin; The common part detection of the imaging system circuit board design includes the impedance diagram planning detection of the imaging system circuit board, the line width setting detection of the imaging system circuit board, the routing spacing setting detection of the imaging system circuit board, the placement direction of the device on the imaging system circuit board and the consistency detection of the interface constraints, the packaging and manual of the device on the imaging system circuit board and the consistency detection of the molding tooling, the teardrop detection of the non-power signal routing of the direct-insertion device on the imaging system circuit board, the design connectivity and short circuit detection of the imaging system circuit board, the consistency detection of the imaging system circuit board and the structural constraint file, the copper digging detection of multiple ground layers of the direct-insertion device on the imaging system circuit board, the detection of no vias and routing at the bottom of the power chip on the imaging system circuit board, the reference plane and via detection of the imaging system circuit board, the dispensing position detection of the device on the imaging system circuit board, the distance detection of the small capacitor around the direct-insertion array device on the imaging system circuit board, the topological link detection of the multi-point connection signal on the imaging system circuit board, and the priority order detection of the placement of the filter capacitor and the power supply chip on the imaging system circuit board; The inspection contents of the special part of the imaging system circuit board include the inspection of the equal-length constraint group of the imaging system circuit board, the interference inspection of the binding wire and the device on the imaging system circuit board, the grounding anti-tear wire inspection of the rigid-flex board and the flexible belt on the imaging system circuit board, the device opening inspection of the protruding structural parts on the imaging system circuit board, the configuration level correctness inspection of the refresh chip on the imaging system circuit board, the key clock signal inspection of the imaging system circuit board, the routing inspection of the MGT correction signal on the imaging system circuit board, the lengthening inspection of the bottom pad of the high-power power chip on the imaging system circuit board, the rationality inspection of the LDO current limiting on the imaging system circuit board, the configuration pin inspection of the imaging system circuit board, the stamp hole setting inspection of the imaging system circuit board, the mounting hole spacing inspection of the molded device on the imaging system circuit board, and the insertion loss and return loss inspection of the high-frequency signal on the imaging system circuit board.

2. The design and detection method of the imaging system according to claim 1, characterized in that: Contents of the consistency test of device pin numbers and names with device manufacturer's information: Check whether the pin numbers and names of the components in the schematic diagram of the imaging system are consistent with the information provided by the component manufacturer; Contents of correctness detection of device pin connection signals: Check whether the signal names connected to the pins of each device in the imaging system are consistent with the pin names; The consistency test contents of positive and negative power supply and positive and negative poles of polarized capacitors: Check whether the high voltage end of the detector power supply chip and related power supply circuits outside the detector is connected to the positive pole of the polarity capacitor, and whether the low voltage end is connected to the negative pole of the polarity capacitor; The voltage margin detection content of the filter capacitor is as follows: Check whether the withstand voltage of the filter capacitors of each component of the imaging system is between 2 and 3 times the maximum voltage; Single point inspection content of electrical rules: Check whether there are isolated single points on the pins of each device in the imaging system that are not connected to other devices; The allowable range of the total amount of filter capacitors in the power chip is tested as follows: Check whether the capacitive load driven by the detector power supply chip and some power supply chips in the related power supply circuits outside the detector is within the allowable range; Contents of consistency test between the number and capacity of decoupling capacitors in the device and the manufacturer's requirements: Check whether the number and capacity of decoupling capacitors in each device of the imaging system are consistent with the manufacturer's requirements; The consistency check content of the connector's node definition and the signed interface file is as follows: Check whether the connector node definitions in the imaging system are consistent with the requirements of the signed interface document Idle pin processing method detection content: Check whether the unused pins of the imaging system components are grounded.

3. The design and detection method of the imaging system according to claim 2, characterized in that: The grounding methods include external direct grounding, grounding through a resistor, and internal grounding set by software.

4. The design and detection method of the imaging system according to claim 2, characterized in that: The signed interface document includes data transmission and power supply parts.

5. The design and detection method of the imaging system according to claim 1, characterized in that: Load the configuration power-on sequence detection content: Check whether the power-on sequence of related power supply circuits, except the detectors related to FPGA loading configuration, is consistent with the manual; Contents of consistency test between interface circuit and construction specification: Check whether the level of the initial state of the interface circuit is stable and whether the voltage threshold of the corresponding interface chip meets the construction specifications; The matching of the power supply range and input voltage range of the power chip and the design margin detection content: Check whether the input voltage range allowed by the detector power supply chip and related power supply circuits outside the detector is greater than the actual input voltage range, whether the maximum output voltage range allowed is greater than the voltage range required by the application, whether the input-output voltage difference is greater than the voltage difference requirement of the power supply chip, and whether the difference between the input bias power supply voltage and the output voltage is greater than the voltage requirement allowed by the data provided by the manufacturer; The output voltage range of the power chip and the matching test content of the application: Check whether the power supply chip of the detector, the related power supply circuit outside the detector, the data transmission interface, and the power-on initial state level set by the controller interface make the output in a prohibited state; Detection of the initial state of power-on and the power-on delay margin: Check whether the rising edge time of each power supply in the detector power supply chip and related power supply circuits outside the detector is within the allowable range of the manual, and whether the relative delay time of each power supply is within the allowable range of the manual.

6. The design and detection method of the imaging system according to claim 1, characterized in that: Impedance diagram planning and detection content of imaging system circuit board: Check the impedance of the single-ended signal of the imaging system circuit board and whether the impedance of the differential signal is consistent with the internal impedance of the imaging system device; Imaging system circuit board line width setting detection content: Check whether the trace width on the imaging system circuit board, the trace width of the detector power supply chip and related power supply circuits outside the detector, and other non-power and impedance control signals meet the trace width requirements; Imaging system circuit board trace spacing setting test content: Check whether the safety distance between the components and structural parts on the imaging system circuit board and the safety distance determined by the processing accuracy and the pressure difference of the adjacent networks meet the safety distance requirements; Contents of consistency test of device placement direction and interface constraints on imaging system circuit boards: Check whether the direction of the angled connector on the imaging system circuit board and the size of the board frame are consistent with the interface constraint file; The packaging and manual of the components on the imaging system circuit board and the consistency test content with the molding tooling: Check whether the high-stacked devices on the imaging system circuit board have pads at the contact position between the device pin heel and the pad, whether the total length of the pads of all devices is 3.5-4mm, and whether the distance between the inner side of the pad and the device body is not less than 0.5mm; Teardrop detection content of non-power signal traces of plug-in devices on imaging system circuit boards: Check whether teardrops are added to the plug-in devices on the imaging system circuit board for reinforcement; Design connectivity and short circuit detection content of imaging system circuit board: By confirming the connectivity of the entire link, it is detected whether the pseudo single point on the imaging system circuit board is connected to two device pins, and by confirming the number of nodes and signal names connected at the same time, it is detected whether the prohibited pins are disconnected; Contents of consistency test between imaging system circuit board and structural constraint file: Check whether the relative positions of the components on the imaging system circuit board are consistent with the constraint file; Copper digging detection content of multiple ground layers of direct-insertion devices on the circuit board of the imaging system: Check whether the grounding holes of through-hole devices with multiple ground layers are connected to the large ground area using hot air pads or cross connections, and check whether the specified ground layer is dug at the pin position of the through-hole device; The inspection contents of no vias and traces at the bottom of the power chip on the imaging system circuit board are as follows: Check whether non-grounded vias and traces appear in the bottom package of the device; Imaging system circuit board reference plane and via detection content: Check whether the key signals of the imaging system circuit board have at least one complete ground reference plane, whether they cross the partition area of ​​another reference plane, and whether the number of link vias exceeds 3; whether the low-frequency signal has at least one complete ground reference plane, and whether the number of times it crosses the partition area of ​​another reference plane exceeds 3; Imaging system circuit board device dispensing position detection content: Check whether there are vias and pads at the four corners of the glue spots on each device on the imaging system circuit board; Distance detection content of small capacitors around the plug-in array devices on the imaging system circuit board: Check whether the lateral spacing between the DIP array device and the surrounding small capacitors on the imaging system circuit board is less than 0.63mm, and whether the spacing in other directions is less than 1.5mm; Topology link detection content of multi-point connection signals on the imaging system circuit board: Check whether the multi-point connection signals on the imaging system circuit board are designed according to the daisy chain topology; Priority order of placement of filter capacitors and power supply chips on the imaging system circuit board Inspection content: Check whether the priority order of placing the detector filter capacitor and the power supply chip on the imaging system circuit board is: small capacitor first, then large capacitor, pixel first, then digital power supply; Check whether the priority order of placing the imaging controller filter capacitor on the imaging system circuit board is: small capacitor first, then large capacitor.

7. The design and detection method of the imaging system according to claim 1, characterized in that: The detection content of the equal length constraint group of the imaging system circuit board is as follows: Check whether the signals on the imaging system circuit board that change synchronously with temperature are set as equal-length constraint groups, and whether the number of vias and the position of the distribution layer of the signals in the equal-length constraint groups are the same; Interference detection content of binding wires and devices on the imaging system circuit board: Check whether the devices near the binding wires in the relevant power supply circuits other than the detector on the imaging system circuit board are away from the binding wires; Inspection contents of grounding anti-tear wire of rigid-flex board and flex tape on imaging system circuit board: Check whether to set an anti-tear line if the layers of the rigid-flex PCB are all wide power signals; check whether to set an anti-tear line if the edges of the rigid-flex PCB are non-power signal lines; check whether to ensure that external interference is superimposed on the anti-tear line if the anti-tear line is grounded; Contents of device opening inspection of protruding structural parts on imaging system circuit boards: Devices for detecting whether the imaging system circuit board avoids protruding structural parts; Contents of the configuration level correctness test of the refresh chip on the imaging system circuit board: Check whether the flash capacity, flash quantity, and FPGA type connected to the refresh chip on the imaging system circuit board are configured according to the actual situation; Key clock signal detection content of imaging system circuit board: Check whether the power supply on the imaging system circuit board is low-noise, and whether the low-jitter clock uses a clock splitter or a separate bank of the FPGA; Contents of the MGT correction signal routing test on the imaging system circuit board: Check whether the MGT correction signal and reference signal of the imaging controller are separately routed and connected between the two pads of the resistor and the FPGA pad; Lengthening test contents of the bottom pad of the high-power power chip on the imaging system circuit board: Check whether the detector power supply chip and related power supply circuits outside the detector have lengthened the bottom pad; Reasonableness test contents of LDO current limiting on imaging system circuit board: Check the LDO in the detector power supply chip and related power supply circuits outside the detector. Check whether the setting of the current limiting resistor takes into account the peak current of the load startup in the case of filter capacitance, and whether at least 20% margin is left; Configuration pin detection content of imaging system circuit board: Check whether the dedicated configuration pins of the imaging controller and the refresh chip are connected according to the configuration pins specified in the information provided by the chip manufacturer; Imaging system circuit board stamp hole setting detection content: Check whether the stamp holes on the imaging system circuit board are arranged at a pitch of 70 mm; Contents of the inspection of the mounting hole spacing of the molded components on the imaging system circuit board: Check whether the spacing between the mounting holes of the molded components on the imaging system circuit board meets the requirement that the total length from both sides of the molded component body to the pads at both ends does not exceed 25.4mm; Insertion loss and return loss test contents of high frequency signals on imaging system circuit boards: Check whether the insertion loss and return loss of high-frequency signals on the imaging system circuit board meet industry standards.

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