Printed wiring board

Abstract

A printed wiring board having high quality. The printed wiring board includes: a mounting conductor layer having a first electrode and a second electrode; a connection conductor layer that is located under the mounting conductor layer and has a connection wiring that electrically connects the first electrode and the second electrode; a second resin insulating layer disposed between the mounting conductor layer and the connecting conductor layer, the second resin insulating layer having a plurality of openings including a first opening and a second opening; a first resin insulating layer which is located under the conductor layer for connection and supports the conductor layer for connection; a first connection via conductor formed in the first opening and electrically connecting the first electrode and the connection wiring; and a second connection via conductor formed in the second opening and electrically connecting the second electrode and the connection wiring. The conductor layer for connection is formed of a seed layer and a plating layer, the seed layer is composed of a first layer and a second layer on the first layer, and in a cross section of the connection wiring, the width of the first layer is larger than the width of the second layer, and the width of the plating layer is larger than the width of the first layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a printed wiring board. Background Art

[0002] Patent Document 1 discloses forming a roughened layer made of Cu—Ni—P on a conductor circuit.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2000-114719

[0004] [Problem of Patent Document 1]

[0005] Patent document 1 records that the needle-shaped alloy composed of Cu-Ni-P on the conductor circuit can ensure the close contact between the conductor circuit and the interlayer resin insulating layer formed on the conductor circuit. The width of the conductor circuit is small. Alternatively, if the thickness of the conductor circuit is small, it is considered difficult to ensure the close contact between the conductor circuit and the interlayer resin insulating layer formed on the conductor circuit using only the roughening layer. In the case of transmitting high-speed signals, it is preferred that the surface roughness of the conductor circuit is small. The surface roughness of the conductor circuit is small. Alternatively, it is considered difficult to ensure the close contact between the conductor circuit and the interlayer resin insulating layer formed on the conductor circuit if the surface of the conductor circuit is smooth. Summary of the invention

[0006] The printed wiring board of the present invention comprises: a mounting conductor layer having a first electrode for mounting a first electronic component and a second electrode for mounting a second electronic component; a connecting conductor layer located below the mounting conductor layer and having a connecting wiring electrically connecting the first electrode to the second electrode; a second resin insulating layer arranged between the mounting conductor layer and the connecting conductor layer and having a plurality of openings including a first opening and a second opening; a first resin insulating layer located below the connecting conductor layer and supporting the connecting conductor layer; a first connecting via conductor formed in the first opening and electrically connecting the first electrode to the connecting wiring; and a second connecting via conductor formed in the second opening and electrically connecting the second electrode to the connecting wiring. The connecting conductor layer is formed of a seed layer and a plating layer on the seed layer, the seed layer being composed of a first layer formed on the first resin insulating layer and a second layer on the first layer, and in a cross section of the connecting wiring, the width of the first layer is greater than the width of the second layer, and the width of the plating layer is greater than the width of the first layer.

[0007] In a printed wiring board of an embodiment of the present invention, in a cross section of the connecting wiring, the width of the second layer is smaller than the width of the first layer and the width of the electroplating layer. The side wall of the connecting wiring is not formed straight. The side wall has a depression. The stress generated by the thermal cycle is difficult to be transmitted to the first resin insulating layer along the side wall of the connecting wiring. It is considered that the stress is dispersed by the depressed portion. It is difficult to generate a crack along the extension line of the interface between the side wall of the connecting wiring and the second resin insulating layer in the first resin insulating layer. Since the side wall of the connecting wiring has a depression, the contact area between the side wall of the connecting wiring and the second resin insulating layer is large. The second resin insulating layer is difficult to peel off from the side wall of the connecting wiring. The embodiment can provide a printed wiring board with high quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a plan view schematically showing a printed wiring board according to the embodiment.

[0009] Figure 2 yes Figure 1 Cross-sectional view between II-II.

[0010] Figure 3 yes Figure 1 Cross-sectional view between III-III.

[0011] Figure 4 This is an enlarged cross-sectional view schematically showing a part of the printed wiring board according to the embodiment.

[0012] Figure 5 This is an enlarged cross-sectional view schematically showing a part of the printed wiring board according to the embodiment.

[0013] Figure 6 This is an enlarged cross-sectional view schematically showing a part of the printed wiring board according to the embodiment.

[0014] Figure 7 It is a cross-sectional view schematically showing a printed wiring board according to a modified example of the embodiment.

[0015] Fig. 8A It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0016] Figure 8B It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0017] Figure 8C It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0018] Fig.8D It is an enlarged cross-sectional view schematically showing the method for manufacturing a printed wiring board according to the embodiment.

[0019] Fig. 8E It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0020] Figure 8F It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0021] Figure 8G It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0022] Figure 8H It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0023] Fig. 9 It is a cross-sectional view schematically showing a printed wiring board having three connecting internal conductor layers.

[0024] Description of symbols

[0025] 2: printed wiring board; 30: conductor layer for connection; 36: connection wiring; 37: space; 38: depression; 90: inorganic particles; 91: first inorganic particles; 91a: flat portion; 91b: exposed surface; 92: second inorganic particles; 93: third inorganic particles; 100: adhesive layer; 102: smooth film; 104: protrusion; 120: resin insulating layer; 121: first opening; 122: second opening; 125: inner wall surface; 126: inner wall surface; 130: conductor layer for mounting; 131: first electrode; 132: second electrode; 141: first connecting via conductor; 142: second connecting via conductor; 150: adhesive layer; 241: first protrusion; 242: second protrusion; E1: first electronic component; E2: second electronic component. DETAILED DESCRIPTION

[0027] Figure 1 It is a top view which shows the printed wiring board 2 which concerns on embodiment. Figure 2 yes Figure 1 Cross-sectional view between II-II. Figure 3 yes Figure 1 Cross-sectional view between III-III. Figures 4 to 6 2 is an enlarged cross-sectional view showing a portion of the printed wiring board 2 according to the embodiment. Figure 1 and Figure 2 As shown, the printed wiring board 2 has an upper surface 2a and a lower surface 2b on the opposite side of the upper surface 2a. The printed wiring board 2 has a first mounting area A1 for mounting a first electronic component E1 and a second mounting area A2 for mounting a second electronic component E2. The first mounting area A1 is located directly below the first electronic component E1. The second mounting area A2 is located directly below the second electronic component E2. Figure 1The circles indicated by solid lines represent bumps (metal pillars) 241, 242, 243, 244 for mounting electronic components. The wirings drawn by dotted lines represent connection wirings 36 embedded in the printed wiring board 2. Examples of the first electronic component E1 and the second electronic component E2 are electronic components such as logic ICs and memories.

[0028] like Figure 1 to Figure 3 As shown, the printed wiring board 2 includes a conductor layer 10, a resin insulating layer (first resin insulating layer) 20, a connecting conductor layer 30, via conductors 41, 42, 141, 142, 143, 144, a resin insulating layer (second resin insulating layer) 120, a mounting conductor layer 130, and bumps 241, 242, 243, 244. Figure 2 As shown, via-hole conductors 41, 141, 143 are arranged directly below the first mounting area A1. Bumps 241, 243 are arranged directly above the first mounting area A1. Via-hole conductors 42, 142, 144 are arranged directly below the second mounting area A2. Bumps 242, 244 are arranged directly above the second mounting area A2.

[0029] The connecting conductor layer 30 includes a connecting wiring 36. Data is transmitted from the first electronic component E1 to the second electronic component E2 via the connecting wiring 36. The connecting wiring 36 is a part of the path for sending data from the first electronic component E1 to the second electronic component E2. The mounting conductor layer 130 includes electrodes 131, 132, 133, and 134. A protrusion 241, an electrode 131, and a via conductor 141 are arranged in the path (first path) between the first electronic component E1 and the connecting wiring 36. The first path is located directly below the first electronic component E1. A protrusion 242, an electrode 132, and a via conductor 142 are arranged in the path (second path) between the second electronic component E2 and the connecting wiring 36. The second path is located directly below the second electronic component E2. The protrusion 241 and the electrode 131, the via conductor 141, the protrusion 242, the electrode 132, and the via conductor 142 are also part of the path. The protrusions 241 and 242 can be called connecting protrusions (connecting metal pillars). The connection protrusion 241 located directly below the first electronic component E1 is a first connection protrusion (first connection metal column), and the connection protrusion 242 located directly below the second electronic component E2 is a second connection protrusion (second connection metal column). The electrodes 131 and 132 can be referred to as connection electrodes. The connection electrode 131 located directly below the first electronic component E1 is a first connection electrode, and the connection electrode 132 located directly below the second electronic component E2 is a second connection electrode. The via conductors 141 and 142 can be referred to as connection via conductors. The connection via conductor 141 located directly below the first electronic component E1 is a first connection via conductor, and the connection via conductor 142 located directly below the second electronic component E2 is a second connection via conductor. The first connection protrusion can also be referred to as a first protrusion (first metal column). The first connection electrode can also be referred to as a first electrode. The first connection via conductor can also be referred to as a first via conductor. The second connection protrusion can also be referred to as a second protrusion (second metal column). The second connection electrode can also be referred to as a second electrode. The second connection via conductor can also be referred to as a second via conductor. The first bump, first electrode and first via conductor located directly below the first electronic component E1 and electrically connected to the connection wiring 36 form a first path. The second bump, second electrode and second via conductor located directly below the second electronic component E2 and electrically connected to the connection wiring 36 form a second path.

[0030] The via-hole conductors 41, 42, 143, 144, the electrodes 133, 134, and the protrusions 243, 244 do not form a path. These via-hole conductors 41, 42, 143, 144, the electrodes 133, 134, and the protrusions 243, 244 are electrically connected to the power supply line or the ground line in the electronic component. These via-hole conductors 41, 42, 143, 144, the electrodes 133, 134, and the protrusions 243, 244 are independent of the connection wiring 36. These via-hole conductors 41, 42, 143, 144, the electrodes 133, 134, and the protrusions 243, 244 are not electrically connected to the connection wiring 36.

[0031] like Figure 2 As shown, the conductor layer 10 includes pads 12 and 14. The pads 12 and 14 are exposed from the lower surface 2b of the printed wiring board 2. The pads 12 and 14 are used for connection with other printed wiring boards and electronic components. The conductor layer 10 is mainly formed of copper.

[0032] The resin insulating layer (first resin insulating layer) 20 is formed on the conductor layer 10. The resin insulating layer 20 has a first surface 20a and a second surface 20b on the opposite side to the first surface 20a. The second surface 20b of the resin insulating layer 20 forms the lower surface 2b of the printed wiring board 2. The second surface 20b of the resin insulating layer 20 is opposite to the conductor layer 10. The resin insulating layer 20 has openings (openings for via conductors) 21 and 22 that expose the conductor layer 10. The opening 21 is located directly below the first mounting area A1 and exposes the pad 12. The opening 21 reaches the pad 12 from the first surface 20a of the resin insulating layer 20. The opening 22 is located directly below the second mounting area A2 and exposes the pad 14. The opening 22 reaches the pad 14 from the first surface 20a of the resin insulating layer 20. The resin insulating layer 20 is formed of a resin 80 and a plurality of inorganic particles 90 dispersed in the resin 80. The resin 80 is an epoxy resin. Examples of the resin include thermosetting resins and photocurable resins. The inorganic particles 90 are glass particles. The inorganic particles 90 may also be aluminum oxide.

[0033] like Figure 2 and Figure 4 As shown, the inorganic particles 90 include first inorganic particles 91 and second inorganic particles 92. The second inorganic particles 92 are buried in the resin insulation layer (the first resin insulation layer 20, the second resin insulation layer 120, etc.). The first inorganic particles 91 form the inner wall surface of the opening (the opening for the via conductor). The second inorganic particles 92 are in the shape of a sphere. The shape of the first inorganic particle 91 is obtained by cutting the sphere in a plane. The shape of the first inorganic particle 91 is obtained by cutting the second inorganic particle 92 in a plane. The shape of the first inorganic particle 91 is different from the shape of the second inorganic particle 92.

[0034] The first surface 20a of the resin insulating layer 20 is formed only of the resin 80. The inorganic particles 90 (second inorganic particles 92) are not exposed from the first surface 20a. The first surface 20a does not include the surface of the second inorganic particles 92. No concavities and convexities are formed on the first surface 20a of the resin insulating layer 20. The first surface 20a is not roughened. The first surface 20a is formed smoothly.

[0035] like Figure 4 As shown in FIG. 1 , the inner wall surface 23 of the opening (opening for the via conductor) is formed by the resin 80 and the first inorganic particles 91. Figure 4 , the opening 21 is shown as a representative example of the opening. The first inorganic particle 91 has a flat portion 91a. The flat portion 91a forms the inner wall surface 23. The inner wall surface 23 is formed by the resin 80 and the flat portion 91a. The flat portion 91a and the surface of the resin 80 forming the inner wall surface 23 form a substantially common surface. No irregularities are formed on the resin 80 forming the inner wall surface 23. The surface of the resin 80 forming the inner wall surface 23 is smooth. No irregularities are formed on the exposed surface 91b of the flat portion 91a (the surface forming the inner wall surface 23). The exposed surface 91b of the flat portion 91a is smooth. The inner wall surface 23 is smoothly formed. The arithmetic mean roughness (Ra) of the inner wall surface 23 is less than 1.0 μm.

[0036] The flat portion 91a of the first inorganic particle 91 substantially coincides with a surface obtained by extending a surface 80a of the resin 80 formed around the first inorganic particle 91 (a surface forming the inner wall surface 23). Figure 2 and Figure 4 The flat portion 91a depicted by a substantially straight line in FIG. 1 is a plane. Figure 2 and Figure 4 In the cross section shown, the flat portion 91a is a plane. The flat portion 91a may not be a completely flat surface. The flat portion 91a is a substantially flat surface and is a substantially smooth surface.

[0037] like Figure 4 As shown, the inner wall surface 23 of the opening 21 is inclined. The angle (inclination angle) θ1 between the upper surface of the pad 12 and the inner wall surface 23 is greater than 70° and less than 85°. The upper surface of the pad 12 is included in the upper surface of the conductor layer 10. The angle (inclination angle) θ2 between the first surface 20a of the resin insulating layer 20 and the inner wall surface 23 is greater than 95° and less than 110°.

[0038] exist Figure 2 and Figure 4 In the cross section shown, the shape of the opening for the via conductor, such as the opening 21, is shown as a roughly inverted trapezoid. However, the shape of the actual opening for the via conductor is roughly an inverted truncated cone. Therefore, the inner wall surface (side wall) of the actual opening for the via conductor is a roughly curved surface. That is, the common surface formed by the flat portion 91a and the resin 80 includes the inner wall surface (side wall) formed by a roughly curved surface.

[0039] The inner wall surface may have a step between the exposed surface 91b of the first inorganic particle 91 and the surface 80a of the resin 80 surrounding the first inorganic particle 91 having the exposed surface 91b. The exposed surface 91b is recessed from the surface 80a of the resin 80. Alternatively, the exposed surface 91b protrudes from the surface 80a of the resin 80. For example, there is a step between the exposed surface 91b and the surface 80a of the resin 80. The amount of the step (the distance between the exposed surface 91b and the surface 80a of the resin 80) is less than 5μm. The amount of the step is preferably less than 3μm. The amount of the step is more preferably less than 1.5μm. Even if a step is formed, since the step is small, the exposed surface 91b and the surface 80a of the resin 80 form a roughly common surface.

[0040] The openings 21 and 22 formed in the resin insulating layer 20 are identical. The openings 21 and 22 formed in the resin insulating layer 20 have identical inner wall surfaces 23 and 24. The inner wall surfaces 23 and 24 of each opening 21 and 22 are formed by the surface 80a of the resin 80 and the exposed surface 91b of the first inorganic particle 91.

[0041] like Figure 2 and Figure 3 As shown in FIG. 1 , the connection conductor layer (first connection conductor layer) 30 is formed on the first surface 20a of the resin insulating layer 20. Figure 2 As shown, the connecting conductor layer 30 includes pads 32, 34 and a connecting wiring 36. The connecting wiring 36 has one end and the other end opposite to the one end. The pad 32 is a first pad 32, and is directly connected to one end of the connecting wiring 36. The pad 34 is a second pad 34, and is directly connected to the other end of the connecting wiring 36. The first pad 32 is formed directly below the first mounting area A1. The second pad 34 is formed directly below the second mounting area A2. Figure 3 As shown, one connecting conductor layer 30 includes a plurality of connecting wirings 36. Although not shown, one connecting conductor layer 30 includes a plurality of first pads 32 and a plurality of second pads 34. A first pad 32 and a second pad 34 are connected at both ends of each connecting wiring 36. The connecting wiring 36 in the connecting conductor layer 30 can include a first pad 32 and a second pad 34. The first pad 32 is included in the first path. The second pad 34 is included in the second path. The pads (first pad 32, second pad 34, etc.) directly connected to the connecting wiring 36 can also be called connecting pads. The first pad 32 can be called a first connecting pad. The second pad 34 can be called a second connecting pad. The first pad 32 located directly below the first electronic component E1 and directly connected to the connecting wiring 36 forms a first path. The second pad 34 located directly below the second electronic component E2 and directly connected to the connecting wiring 36 forms a second path.

[0042] The connection wirings 36 are arranged substantially in parallel. The connection wiring 36 having the smallest width W1 among the plurality of connection wirings 36 is the smallest connection wiring 36a. The width W1 of the smallest connection wiring 36a is 1 μm or more and 3 μm or less. Spaces 37 exist between adjacent connection wirings 36. Among the plurality of spaces 37, the space 37 having the smallest width G1 is the smallest space 37a. The width G1 of the smallest space 37a is 1 μm or more and 3 μm or less.

[0043] The connection wiring 36 having the largest width W2 among the plurality of connection wirings 36 is the largest connection wiring 36b. The width W2 of the largest connection wiring 36b is 5 μm or less. The width W2 of the largest connection wiring 36b is preferably 3 μm or less. Among the plurality of spaces 37, the space having the largest width G2 is the largest space 37b. The width G2 of the largest space 37b is 5 μm or less. The width G2 of the largest space 37b is preferably 3 μm or less.

[0044] The width of each connection wiring 36 is preferably not less than 1 μm and not more than 3 μm. The width of each space 37 is preferably not less than 1 μm and not more than 3 μm.

[0045] Each of the connection wirings 36 has an aspect ratio (thickness / width). The aspect ratio is 2.0 or more and 4.0 or less. The thickness of the connection wiring 36 is preferably 3 μm or more and 7 μm or less.

[0046] The conductor layer 30 for connection is mainly formed of copper. The conductor layer 30 for connection is formed by a seed layer 30a on the first surface 20a of the resin insulating layer 20 and a plating layer 30b on the seed layer 30a. The seed layer 30a is formed by sputtering. The seed layer 30a is formed by a first layer 31a on the first surface 20a of the resin insulating layer 20 and a second layer 31b on the first layer 31a. The first layer 31a is in contact with the first surface 20a of the resin insulating layer 20. For example, the seed layer 30a and the first layer 31a are formed of a copper alloy, and the second layer 31b is formed of copper. The second layer 31b is not necessary. The first layer 31a and the second layer 31b are formed by sputtering. Both are sputtering films.

[0047] The first layer 31a is composed of an alloy containing copper, aluminum and a specific metal. Examples of specific metals are nickel, zinc, gallium, silicon, and magnesium. The alloy preferably contains one specific metal, or two specific metals, or three specific metals. The aluminum content in the alloy is greater than 1.0 at% and less than 15.0 at%. An example of a specific metal is silicon. The content of the specific metal in the alloy is greater than 0.5 at% and less than 10.0 at%. The first layer 31a may also contain impurities. Examples of impurities are oxygen and carbon. The first layer 31a may contain oxygen or carbon. The first layer 31a may contain oxygen and carbon. In an embodiment, the alloy also contains carbon. The carbon content in the alloy is less than 50 ppm. The alloy also contains oxygen. The oxygen content in the alloy is less than 100 ppm. The values ​​of the contents of the above-mentioned elements are examples. Among the elements forming the first layer 31a, the amount of copper is the largest. Next, the amount of aluminum is large. The amount of the specific metal is less than the amount of aluminum. Therefore, copper is the primary metal, aluminum is the first secondary metal, and the specific metal is the second secondary metal. The amount of the impurity is smaller than the amount of the specific metal.

[0048] The second layer 31b is formed of copper. The content of copper forming the second layer 31b is 99.9at% or more. The content of copper in the second layer 31b is preferably 99.95at% or more. The electroplating layer 30b is formed of copper. The content of copper forming the electroplating layer 30b is 99.9at% or more. The content of copper in the electroplating layer 30b is preferably 99.95at% or more.

[0049] Figure 5 FIG. 2 shows an enlarged cross-sectional view of the connection wiring 36. Figure 5 As shown, the connection wiring 36 is formed by the seed layer 30a on the first surface 20a of the resin insulation layer 20 and the electroplating layer 30b on the seed layer 30a. The seed layer 30a is formed by the first layer 31a on the first surface 20a and the second layer 31b on the first layer 31a. The first layer 31a is in contact with the first surface 20a. The surface of the first layer 31a opposite to the first surface 20a is formed along the surface shape of the first surface 20a. The electroplating layer 30b is formed directly above the second layer 31b. The second layer 31b is in contact with the first layer 31a, and the electroplating layer 30b is in contact with the second layer 31b.

[0050] The width of the seed layer 30a of the connection wiring 36 is smaller than the width of the electroplating layer 30b. The width of the connection wiring 36 has a minimum value at the boundary portion B between the seed layer 30a and the electroplating layer 30b. The width D2 of the first layer 31a is larger than the width D3 of the second layer 31b, and the width D1 of the electroplating layer 30b is larger than the width D2 of the first layer 31a. The widths D1, D2, and D3 are Figure 5 The cross section used for measurement is perpendicular to the first surface. The cross section used for measurement is perpendicular to the side surface of the connection wiring of the measurement object.

[0051] Width D1 is the distance between two faces of the electroplating layer 30b extending from the upper surface of the electroplating layer 30b and facing the first face 20a. The upper surface of the electroplating layer 30b is the face away from the seed layer 30a. The face used to measure width D1 forms the side (side wall) of the electroplating layer 30b. The width of the connecting wiring 36 can also be represented by width D1. Width D1 is measured near the upper surface of the conductor circuit. Width D2 is measured on the first face 20a. Width D3 is measured at the interface between the second layer 31b and the electroplating layer 30b.

[0052] like Figure 5 As shown, an example of the cross-sectional shape of the electroplating layer 30b is a roughly hexagonal shape. If the cross-sectional shape is a roughly hexagonal shape, the side that contacts the seed layer 30a among the sides forming the hexagon is the lower side BL. The side opposite to the lower side BL is the upper side UL. The sides extending from the upper side UL are the first side SL1 and the second side SL2. The first side SL1 and the second side SL2 are the two sides used to measure the width D1. The sides extending from the lower side BL are the third side SL3 and the fourth side SL4. The third side SL3 is connected to the first side SL1. The third side SL3 is formed between the first side SL1 and the lower side BL. The fourth side SL4 is connected to the second side SL2. The fourth side SL4 is formed between the second side SL2 and the lower side BL. The surface including the first side SL1 forms a side wall (side) of the electroplating layer 30b. The surface including the second side SL2 forms another side wall (side) of the electroplating layer 30b.

[0053] By making the width D3 of the second layer 31b smaller than the width D1 of the electroplating layer 30b and the width D2 of the first layer 31a, the side wall of the connection wiring 36 has a recess 38. Both side walls (side surfaces) of the connection wiring 36 have recesses 38. The recess 38 is formed by the area surrounded by the surface including the side surface of the electroplating layer 30b, the first surface 20a, and the actual side surface of the connection wiring 36. The actual side surface includes the side surface of the seed layer 30a. The recess 38 is filled with the resin insulating layer 120. The resin insulating layer 120 is formed of a resin 80 and inorganic particles 90 (first inorganic particles 91, second inorganic particles 92) in the same manner as the resin insulating layer 20 ( Figure 2 ).like Figure 5 As shown, the resin insulating layer 120 filling the recess 38 is referred to as a specific portion S. The specific portion S includes the third inorganic particles 93. The diameter of the third inorganic particles 93 included in the specific portion S is smaller than the diameter of the second inorganic particles 92 included in the other portions. The diameter of the third inorganic particles 93 included in the specific portion S is, for example, 1.0 μm or less. The width of the specific portion S is equivalent to Figure 5 C. The width of the specific portion S is about 1.0 μm. The content of the resin 80 in the specific portion S is greater than the content of the resin 80 contained in other portions. Therefore, the stress generated at the interface between the seed layer 30 a and the plating layer 30 b is relaxed.

[0054] The other conductor circuits (pads 32, 34, etc.) in the connection conductor layer 30 are the same as the connection wiring 36. The conductor circuits (first electrode 131, second electrode 132, etc.) in the mounting conductor layer 130 are the same as the connection wiring 36. The conductor circuits other than the connection wiring 36 may also have Figure 5 The recess 38 is as shown. With respect to the width D1, the width D2, the width D3, and the specific portion S, the connection wiring 36 and the conductor circuits other than the connection wiring 36 are the same. The conductor circuits (second connection wiring, etc.) in the conductor layers (mounting conductor layer 130, etc.) other than the connection conductor layer 30 are included in the conductor circuits other than the connection wiring 36. With respect to the relationship between the width D1, the width D2, and the width D3, the connection wiring 36 and the conductor circuits other than the connection wiring 36 have the same relationship.

[0055] In an embodiment, an adhesive layer 100 can be formed on the surface (upper surface and side surface) of the connecting conductor layer 30. The adhesive layer 100 is not essential. The surface of the connecting conductor layer 30 is formed by a first surface and a second surface. The first surface of the surface is a portion exposed through an opening for a via conductor. The second surface is a portion other than the first surface. The first surface is not covered by the adhesive layer 100, and the second surface is covered by the adhesive layer 100. The adhesive layer 100 is in contact with the connecting conductor layer 30. The adhesive layer 100 is in contact with the second surface of the connecting conductor layer 30. The adhesive layer 100 is formed of a resin. The adhesive layer 100 is formed of an organic material (organic resin). An example of an organic material is a nitrogen-based organic compound. An example of a nitrogen-based organic compound is a tetrazole compound. Examples of nitrogen-based organic compounds are disclosed in Japanese Patent Publication No. 2015-54987. The adhesive layer 100 does not cover the first surface 20a of the resin insulating layer 20 exposed from the connecting conductor layer 30. The adhesive layer 100 is formed between the connecting conductor layer 30 and the second resin insulating layer 120. The adhesive layer 100 is sandwiched between the connecting conductor layer 30 and the resin insulating layer (second resin insulating layer) 120. The adhesive layer 100 bonds the connecting conductor layer 30 and the resin insulating layer 120. The connecting wiring 36 may have only the second surface.

[0056] Figure 6 1 is an enlarged cross-sectional view showing a portion of the adhesive layer 100 formed on the second surface of the connection wiring 36. Figure 6 As shown, the adhesive layer 100 is formed of a substantially smooth smooth film 102 and a plurality of protrusions 104 protruding from the smooth film 102. The adhesive layer 100 formed on the second surface of the pad (pads 32, 34, etc.) is formed of a plurality of protrusions 104 protruding from the smooth film 102. Figure 6 The same smoothing film 102 and a plurality of protrusions 104 are formed. The shapes are also the same.

[0057] The smooth film 102 has a substantially uniform thickness T. The thickness T of the smooth film 102 is not less than 10 nm and not more than 120 nm. The ratio (S1 / S2) of the area (S1) of the smooth film 102 exposed from the protrusion 104 to the area (S2) of the adhesive layer 100 is not less than 0.1 and not more than 0.5. The smooth film 102 on the second surface of the connecting conductor layer 30 is formed substantially along the shape of the second surface of the connecting conductor layer 30. In the case where undulations are formed on the upper surface and the side surface of the connecting conductor layer 30, the smooth film 102 follows the undulations.

[0058] The protrusion 104 is formed by a plurality of protrusions 106. The plurality of protrusions 106 form irregularities on the upper surface of the protrusion 104. 2 The number of protrusions 106 is 5 or more and 15 or less. The protrusion 104 has heights H1 and H2 between the upper surface of the smooth film 102 and the top of the protrusion 104. The maximum value of the heights H1 and H2 is 10 or more and 30 or less times the thickness T of the smooth film 102. The heights H1 and H2 are 200 nm or more and 450 nm or less.

[0059] like Figure 2 As shown, via conductors 41 and 42 are formed in the openings (openings 21 and 22 for via conductors). The via conductors 41 and 42 electrically connect the conductor layer 10 and the connecting conductor layer 30. The via conductors 41 and 42 and the connecting conductor layer 30 are formed at the same time. The via conductors 41 and 42 are formed by a seed layer 30a and a plating layer 30b on the seed layer 30a. The seed layer 30a forming the via conductors 41 and 42 and the seed layer 30a forming the connecting conductor layer 30 are common. The plating layer 30b forming the via conductors 41 and 42 and the plating layer 30b forming the connecting conductor layer 30 are common. The seed layer 30a forming the via-hole conductors 41 and 42 is formed of a first layer 31a formed on the inner wall surfaces 23 and 24 of the openings 21 and 22 for the via-hole conductors and on the pads 12 and 14 exposed from the openings 21 and 22 for the via-hole conductors, and a second layer 31b on the first layer 31a. The first layer 31a is in contact with the pads 12 and 14 and the inner wall surfaces 23 and 24. The resin insulating layer (first resin insulating layer) 20 supports the connecting conductor layer (first connecting conductor layer) 30. The connecting conductor layer (first connecting conductor layer) 30 in contact with the first surface 20a of the resin insulating layer (first resin insulating layer) 20 and the via-hole conductors 41 and 42 penetrating the resin insulating layer (first resin insulating layer) 20 are formed simultaneously. The embodiment can reduce the thickness of the seed layer 30a forming the via-hole conductors 41 and 42. The embodiment can reduce the thickness of the first layer 31a forming the via-hole conductors 41 and 42. The embodiment can reduce the thickness of the second layer 31b forming the via-hole conductors 41 and 42. Therefore, the embodiment can form the connection conductor layer 30 having fine connection wirings 36.

[0060] A resin insulating layer (second resin insulating layer) 120 having a first surface 120a and a second surface 120b on the side opposite to the first surface 120a is formed on the connecting conductor layer 30 and the resin insulating layer 20 via the adhesive layer 100. The resin insulating layer 120 is bonded to the connecting conductor layer 30 via the adhesive layer 100. The resin insulating layer 120 is in contact with the adhesive layer 100. The second surface 120b of the resin insulating layer 120 is opposite to the connecting conductor layer 30. The material of the resin insulating layer (second resin insulating layer) 120 is the same as that of the resin insulating layer (first resin insulating layer) 20. The first surface 120a of the resin insulating layer 120 is the same as the first surface 20a of the resin insulating layer 20.

[0061] The resin insulating layer 120 has openings (openings for via conductors) 121, 122, 123, 124. The opening 121 is a first opening 121 that exposes the first pad 32. The opening 122 is a second opening 122 that exposes the second pad 34. The first opening 121 and the opening 123 are formed directly below the first mounting area A1. The second opening 122 and the opening 124 are formed directly below the second mounting area A2. The first opening 121 and the second opening 122 reach the pads 32 and 34 that are directly connected to the connecting wiring 36. Such openings (the first opening 121, the second opening 122, etc.) can also be called openings for connecting via conductors. The first opening 121 located directly below the first electronic component E1 is an opening for a first connecting via conductor, and the second opening 122 located directly below the second electronic component E2 is an opening for a second connecting via conductor. The first opening 121 and the second opening 122, the openings 123 and 124 are Figure 4 Therefore, the inner wall surface 125 of the first opening 121, the inner wall surface 126 of the second opening 122, and the inner wall surfaces of the openings 123 and 124 are the same as Figure 4 The inner wall surface 23 of the opening 21 shown is the same. The inner wall surface of the opening for the via conductor penetrating the resin insulating layer (second resin insulating layer) 120 is the same as the inner wall surface of the opening for the via conductor penetrating the resin insulating layer (first resin insulating layer) 20. The openings for the via conductor penetrating each resin insulating layer have substantially the same inner wall surface.

[0062] The mounting conductor layer 130 is formed on the first surface 120a of the resin insulating layer 120. The resin insulating layer 120 supporting the mounting conductor layer 130 is the uppermost resin insulating layer. The mounting conductor layer 130 contacts the first surface of the uppermost resin insulating layer. The mounting conductor layer 130 includes a plurality of first electrodes 131 and a plurality of second electrodes 132. The mounting conductor layer 130 includes electrodes 133 and 134 other than the first electrode 131 and the second electrode 132. The first electrode 131 and the electrode 133 are formed in the first mounting area A1. The first electronic component E1 is mounted on the printed wiring board 2 via the first electrode 131 and the electrode 133. The second electrode 132 and the electrode 134 are formed in the second mounting area A2. The second electronic component E2 is mounted on the printed wiring board 2 via the second electrode 132 and the electrode 134. The mounting conductor layer 130 may also have a plurality of connection wirings (second connection wirings). In this case, the second connection wiring has one end and the other end on the opposite side of the one end. One end of the second connection wiring is directly connected to one first electrode 131. The other end of the second connection wiring is directly connected to one second electrode 132. The second connection wiring electrically connects the first electrode 131 and the second electrode 132. Data is transmitted from the first electronic component E1 to the second electronic component E2 via the second connection wiring. The connection wiring in the mounting conductor layer 130 is not essential. The connection wiring in the mounting conductor layer 130 may include the first electrode 131 and the second electrode 132.

[0063] The mounting conductor layer 130 is identical to the connecting conductor layer 30. Therefore, the mounting conductor layer 130 is formed of a seed layer 130a and a plating layer 130b on the seed layer 130a. The seed layer 130a is formed of a first layer 131a and a second layer 131b on the first layer 131a. The seed layer 130a forming the mounting conductor layer 130 is identical to the seed layer 30a forming the connecting conductor layer 30. The first layer 131a forming the mounting conductor layer 130 is identical to the first layer 31a forming the connecting conductor layer 30. The second layer 131b forming the mounting conductor layer 130 is identical to the second layer 31b forming the connecting conductor layer 30. The plating layer 130b forming the mounting conductor layer 130 is identical to the plating layer 30b forming the connecting conductor layer 30.

[0064] When the mounting conductor layer 130 includes a connection wiring, the connection wiring in the mounting conductor layer 130 is the same as the connection wiring 36 in the connection conductor layer 30. Therefore, the widths W1, G1, W2, and G2 related to the connection wiring in the mounting conductor layer 130 are respectively the same as the widths W1, G1, W2, and G2 related to the connection wiring 36 in the connection conductor layer 30. The aspect ratio (thickness / width) of the connection wiring in the mounting conductor layer 130 is greater than or equal to 2.0 and less than or equal to 4.0. The widths D1, D2, and D3 of the connection wiring in the mounting conductor layer 130 are respectively the same as the widths D1, D2, and D3 of the connection wiring 36 in the connection conductor layer 30.

[0065] In an embodiment, an adhesive layer 150 may be formed on the surface (upper surface and side surface) of the mounting conductor layer 130. The adhesive layer 150 is not essential. The surface of the mounting conductor layer 130 is formed of a third surface and a fourth surface. The third surface of the surface is a portion exposed by an opening. An example of an opening is an opening for forming a protrusion. The fourth surface is a portion other than the third surface. The third surface is not covered by the adhesive layer 150, and the fourth surface is covered by the adhesive layer 150. The adhesive layer 150 covering the fourth surface of the mounting conductor layer 130 is the same as the adhesive layer 100 covering the second surface of the connecting conductor layer 30. Therefore, the adhesive layer 150 is formed of a substantially smooth smooth film 102 and a protrusion 104 protruding from the smooth film 102 (refer to Figure 6 ). The adhesive layer 150 does not cover the first surface 120a of the resin insulating layer 120 exposed from the mounting conductor layer 130. The adhesive layer 150 bonds the mounting conductor layer 130 and the insulating layer 220. When the mounting conductor layer 130 includes a connection wiring, the connection wiring may have only the fourth surface.

[0066] Via conductors 141, 142, 143, 144 are formed in the respective openings (openings for via conductors) 121, 122, 123, 124 penetrating the resin insulating layer 120. The via conductor 141 formed in the first opening 121 is a first connecting via conductor 141. The first connecting via conductor 141 is connected to the first pad 32 extending from one end of the connecting wiring 36. The via conductor 142 formed in the second opening 122 is a second connecting via conductor 142. The second connecting via conductor 142 is connected to the second pad 34 extending from the other end of the connecting wiring 36. The first connecting via conductor 141 and the second connecting via conductor 142 electrically connect the connecting conductor layer 30 and the mounting conductor layer 130. The first connecting via conductor 141 electrically connects the first pad 32 to the first electrode 131. The second connecting via conductor 142 electrically connects the second pad 34 to the second electrode 132. The first connecting via conductor 141 electrically connects the first electrode 131 and the connecting wiring 36. The second connecting via conductor 142 electrically connects the second electrode 132 and the connecting wiring 36. The inner wall surfaces 125, 126 of the openings 121, 122 for the connecting via conductors 141, 142 are formed by the exposed surface 91b of the first inorganic particle 91 and the surface 80a of the resin 80. The exposed surface 91b of the first inorganic particle 91 forms a substantially common surface with the surface 80a of the resin 80. The inner wall surface of the opening for the connecting via conductor is substantially flat. Therefore, when the data from the first electrode 131 to the second electrode 132 passes through the connecting via conductors 141, 142, the data is difficult to degrade. The connecting via conductor of the embodiment is suitable for a via conductor for transmitting high-speed data. The printed wiring board 2 of the embodiment can transmit large-capacity data via the connecting via conductor.

[0067] The connecting via conductor is formed by the seed layer 130a and the electroplating layer 130b on the seed layer 130a. The first connecting via conductor 141 and the second connecting via conductor 142 are examples of connecting via conductors. The seed layer 130a forming the connecting via conductors 141 and 142 is common to the seed layer 130a forming the mounting conductor layer 130. The first layer 131a forming the connecting via conductors 141 and 142 is common to the first layer 131a forming the mounting conductor layer 130. The second layer 131b forming the connecting via conductors 141 and 142 is common to the second layer 131b forming the mounting conductor layer 130. The electroplating layer 130b forming the connecting via conductors 141 and 142 is common to the electroplating layer 130b forming the mounting conductor layer 130. The seed layer 130a for forming the connecting via conductors 141 and 142 is formed of the inner wall surfaces 125 and 126 of the openings 121 and 122 for the connecting via conductors and the first layer 131a formed on the pads 32 and 34 exposed from the openings 121 and 122 for the connecting via conductors, and the second layer 131b on the first layer 131a. The first layer 131a is in contact with the inner wall surfaces 125 and 126 and the pads 32 and 34. The via conductors 143 and 144 are formed in the openings 123 and 124 other than the openings 121 and 122 for the connecting via conductors.

[0068] The mounting conductor layer is formed directly above the resin insulating layer (mounting resin insulating layer) supporting the mounting conductor layer. The mounting conductor layer is in contact with the mounting resin insulating layer. The seed layer for forming the mounting conductor layer and the seed layer for forming the via conductor penetrating the mounting resin insulating layer are common. Both are formed at the same time. The first layer for forming the mounting conductor layer and the first layer for forming the via conductor penetrating the mounting resin insulating layer are common. Both are formed at the same time. The second layer for forming the mounting conductor layer and the second layer for forming the via conductor penetrating the mounting resin insulating layer are common. Both are formed at the same time. The first layer and the second layer form the seed layer. The electroplating layer for forming the mounting conductor layer and the electroplating layer for forming the via conductor penetrating the mounting resin insulating layer are common. Both are formed at the same time. The inner wall surface of the opening for the via conductor penetrating the mounting resin insulating layer and Figure 4 The inner wall surface 23 of the opening 21 shown is the same. Therefore, in the embodiment, the thickness of the seed layer forming the mounting conductor layer can be reduced. The mounting conductor layer can have fine connection wiring.

[0069] The insulating layer 220 having a first surface 220a and a second surface 220b on the opposite side of the first surface 220a is formed on the first surface 120a of the mounting conductor layer 130 and the resin insulating layer 120. In the embodiment, the adhesive layer 150 may be formed on the mounting conductor layer 130. In this case, the insulating layer 220 is formed on the mounting conductor layer 130 via the adhesive layer 150. The adhesive layer 150 formed on the mounting conductor layer 130 is the same as the adhesive layer 100 on the connecting conductor layer 30. The insulating layer 220 is bonded to the mounting conductor layer 130 through the adhesive layer 150. The second surface 220b of the insulating layer 220 is opposite to the mounting conductor layer 130. The insulating layer 220 is used as a solder resist. It is preferred that the material of the insulating layer 220 is different from the material of the resin insulating layers 20 and 120. The insulating layer 220 is formed using, for example, an epoxy resin or a polyimide resin containing a photosensitive agent.

[0070] The insulating layer 220 has openings (openings for projections) 221, 222, 223, 224 that expose the electrodes 131, 132, 133, 134. The opening 221 is a first opening (first opening for projections) 221 that exposes the first electrode 131. The opening 222 is a second opening (second opening for projections) 222 that exposes the second electrode 132. The first opening 221 and the opening 223 are formed directly above the first mounting area A1. The second opening 222 and the opening 224 are formed directly above the second mounting area A2.

[0071] The projections 241, 242, 243, 244 are formed on the electrodes 131, 132, 133, 134 exposed from the openings (openings for projections) 221, 222, 223, 224. The projection 241 formed on the first electrode 131 exposed from the first opening (first opening for projections) 221 is the first projection 241. The projection 242 formed on the second electrode 132 exposed from the second opening (second opening for projections) 222 is the second projection 242. The projections 241, 242, 243, 244 are examples of projections for mounting electronic components (first electronic component E1, second electronic component E2, etc.) on the printed wiring board 2. The first projection 241 and the projection 243 are located on the first mounting area A1, and the first electronic component E1 is mounted on the printed wiring board 2 via these projections 241, 243. The second protrusions 242 and 244 are located in the second mounting area A2 , and the second electronic component E2 is mounted on the printed wiring board 2 via these protrusions 242 , 244 .

[0072] Each protrusion 241, 242, 243, 244 is formed by a portion (first portion) filling the openings 221, 222, 223, 224 and a second portion (pad) on the first portion. The second portion is formed on the first surface 220a of the insulating layer 220 just above the first portion and around the openings 221, 222, 223, 224. The first portion and the second portion are formed integrally. The first portion and the second portion are formed continuously. The second portion protrudes from the first surface 220a of the insulating layer 220. The first electronic component E1 is electrically connected to the first electrode 131 through the first protrusion 241. The second electronic component E2 is electrically connected to the second electrode 132 through the second protrusion 242. The first electronic component E1 and the second electronic component E2 are connected via the first protrusion 241, the first connecting via conductor 141, the connecting wiring 36, the second connecting via conductor 142 and the second protrusion 242. When data is transmitted from the first electronic component E1 to the second electronic component E2, the data is transmitted via a path including a connecting via conductor and a connecting wiring. The connecting via conductor and the connecting wiring include a sputtering seed layer formed on a substantially flat surface, so the printed wiring board 2 of the embodiment can transmit a large amount of data from the first electronic component E1 to the second electronic component E2 at high speed. When data is transmitted, data degradation is not likely to occur.

[0073] The projections 241, 242, 243, 244 are formed by the seed layer 230a and the electroplating layer 230b on the seed layer 230a. The seed layer 230a is formed by the first layer 231a and the second layer 231b on the first layer 231a. The seed layer 230a forming the projections (the first projection 241, the second projection 242, etc.) is the same as the seed layer 30a forming the connecting conductor layer 30. The first layer 231a forming the projections is the same as the first layer 31a forming the connecting conductor layer 30. The second layer 231b forming the projections is the same as the second layer 31b forming the connecting conductor layer 30. The electroplating layer 230b forming the projections is the same as the electroplating layer 30b forming the connecting conductor layer 30. In the modified example, the projections 241, 242, 243, 244 can also be formed by solder.

[0074] A functional layer 260 is formed on the top of the protrusions 241, 242, 243, and 244. The functional layer 260 is, for example, a plated film of nickel, tin, palladium, or gold. The functional layer 260 is not essential.

[0075] [Modifications of the Embodiments]

[0076] Figure 7 2 is a cross-sectional view showing a printed wiring board 3 according to a modified example of the embodiment. Figure 7As shown, the printed wiring board 3 has the printed wiring board 2 of the embodiment and a support 4. The support 4 is attached to the lower surface 2b of the printed wiring board 2 of the embodiment. The support 4 includes a substrate 5, a first metal layer 6 laminated on both sides of the substrate 5, a peeling layer 7 formed on the first metal layer 6, and a second metal layer 8 laminated on the peeling layer 7. The printed wiring board 2 of the embodiment is laminated on the second metal layer 8.

[0077] An example of the base material 5 is a substrate containing a reinforcing material such as glass, silicon, or glass fiber. The rigidity of the base material 5 is higher than that of the printed wiring board 2. Therefore, in the printed wiring board 3 of the modified example, the connection reliability between the printed wiring board and the electronic components (the first electronic component E1, the second electronic component E2, etc.) can be improved.

[0078] [Method for Manufacturing Printed Wiring Board 2 According to Embodiment]

[0079] Figure 8A to Figure 8H A method for manufacturing the printed wiring board 2 according to the embodiment will be described. Figure 8A to Figure 8C , Figure 8E to Figure 8H It is a cross-sectional view. Fig.8D is an enlarged cross-sectional view. Fig. 8A The support body 4 and the conductor layer 10 formed on the support body 4 are shown. Figure 7 The support body 4 is the same as that of the second metal layer 8. A plating resist is formed on the second metal layer 8. A conductor layer 10 including pads 12 and 14 is formed on the second metal layer 8 exposed from the plating resist. The second metal layer 8 functions as a seed layer for forming the conductor layer 10. Thereafter, the plating resist is removed. In an embodiment, the upper surface of the conductor layer 10 can be polished by, for example, CMP (Chemical Mechanical Polishing) before removing the plating resist.

[0080] like Figure 8B As shown, a resin insulating layer (first resin insulating layer) 20 and a protective film 50 are formed on the second metal layer 8 and the conductor layer 10. The second surface 20b of the resin insulating layer 20 is opposite to the second metal layer 8. The protective film 50 is formed on the first surface 20a of the resin insulating layer 20. The resin insulating layer 20 has a resin 80 and inorganic particles 90 (second inorganic particles 92). The inorganic particles 90 are buried in the resin 80. The first surface 20a of the resin insulating layer 20 is formed only by the resin 80. The inorganic particles 90 are not exposed from the first surface 20a of the resin insulating layer 20. The first surface 20a of the resin insulating layer 20 does not include the surface of the inorganic particles 90. No concavo-convex is formed on the first surface 20a of the resin insulating layer 20.

[0081] like Figure 8CAs shown, laser light L is irradiated from above the protective film 50. The laser light L penetrates through the protective film 50 and the resin insulating layer 20 at the same time. The openings 21 and 22 for the via conductors that reach the pads 12 and 14 of the conductor layer 10 are formed. The laser light L is, for example, a UV laser or a CO2 laser. The pads 12 and 14 are exposed through the openings 21 and 22. When the openings 21 and 22 for the via conductors are formed, the first surface 20a of the resin insulating layer 20 is covered by the protective film 50. Therefore, even if the resin scatters when the openings 21 and 22 for the via conductors are formed, it is possible to suppress the resin from adhering to the first surface 20a of the resin insulating layer 20.

[0082] Fig.8D The inner wall surface 23b of the opening (opening for via conductor) after laser irradiation is shown. As a representative example of the opening for via conductor, opening 21 is depicted. Opening 22 is the same as opening 21. The inner wall surface 24b of opening 22 is the same as the inner wall surface 23b of opening 21. The inner wall surface 23b is formed by resin 80 and inorganic particles 90 protruding from the resin 80. In order to control the shape of the inner wall surface, the inner wall surface 23b after laser irradiation is treated. It is preferred to selectively remove the inorganic particles 90 protruding from the resin 80. Thus, the first inorganic particles 91 are formed from the inorganic particles 90. For example, by treating the inner wall surface 23b after laser irradiation with a chemical, the inorganic particles 90 protruding from the resin 80 are selectively removed. Alternatively, by treating the inner wall surface 23b after laser irradiation with plasma, the inorganic particles 90 protruding from the resin 80 are selectively removed. The etching rate of the selective removal of the inorganic particles 90 is greater than the etching rate of the resin 80. For example, the difference in etching speed between the two is more than 10 times. Or, the difference in etching speed between the two is more than 50 times. Or, the difference in etching speed between the two is more than 100 times. By treating the inner wall surface 23b after laser irradiation, a first inorganic particle 91 having a flat portion 91a is obtained. By controlling the conditions for treating the inner wall surface 23b after laser irradiation, in an embodiment, the shape of the inner wall surface 23 can be controlled. Examples of conditions are temperature, concentration, time, type of gas, and pressure. Control the etching speed of the inorganic particle 90 and the etching speed of the resin.

[0083] By irradiating the resin insulating layer 20 with laser light L, a portion of the second inorganic particle 92 embedded in the resin 80 forms the inner wall surface 23b after laser irradiation. The second inorganic particle 92 forming the inner wall surface 23b after laser irradiation is formed by a protruding portion P protruding from the resin 80 and a portion E embedded in the resin 80. The inner wall surface 23b after laser irradiation is treated. For example, the inner wall surface 23b is treated with a plasma of a gas containing tetrafluoromethane. The protruding portion P is selectively removed to form the inner wall surface 23 of the embodiment. The first inorganic particle 91 is formed by the second inorganic particle 92. By selectively removing the protruding portion P, the first inorganic particle 91 having a flat portion 91a is formed. The flat portion 91a is a plane. When the second inorganic particle 92 having a spherical shape is cut by a plane, the shape of the first inorganic particle 91 is obtained. The inner wall surface 23 is formed by the flat portion 91a and the surface 80a of the resin 80, and the exposed surface 91b of the flat portion 91a and the surface 80a of the resin 80 are located on approximately the same plane. For example, when a seed layer 30a is formed on the inner wall surface 23b by sputtering, the protrusion P hinders the growth of the sputtered film (sputtering film). For example, a continuous seed layer 30a is not formed on the inner wall surface 23b. Alternatively, it is necessary to thicken the thickness of the seed layer 30a. If there is a protrusion P, it is difficult to form a fine conductor circuit. In an embodiment, the protrusion P is removed. The embodiment can thin the thickness of the seed layer 30a formed by sputtering. Even if the thickness of the seed layer 30a formed by sputtering is thin, a continuous seed layer 30a can be obtained. The width of the connecting wiring 36 meets the target value. The embodiment can easily control the width D1, the width D2, and the width D3. The width D1, the width D2, and the width D3 are formed according to the target. The width of the space 37 between adjacent connecting wirings 36 meets the target value. The via conductor formed on the inner wall surface 23b having the protrusion P is the via conductor of the reference example. If the via conductor of the reference example exists in the path, data moving from the first electronic component E1 to the second electronic component E2 must pass through the via conductor of the reference example. In this case, it is considered that the data is degraded due to the influence of the protrusion P. In the embodiment, the protrusion P is removed. The embodiment can suppress the degradation of data.

[0084] Forming an opening (opening for a via conductor) includes forming inorganic particles (second inorganic particles 92) 90 having a protruding portion P. The opening 21 is a representative example of an opening (opening for a via conductor). The protruding portion P protrudes from the resin 80 forming the inner wall surface 23b of the opening 21. The first inorganic particle 91 is formed by removing the protruding portion P of the inorganic particle (second inorganic particle 92) 90. The inner wall surface 23 of the opening 21 includes an exposed surface 91b of the first inorganic particle 91. The exposed surface 91b of the first inorganic particle 91 is formed by removing the protruding portion P.

[0085] The shape of the first inorganic particle 91 obtained by cutting the second inorganic particle 92 having a spherical shape in a plane includes removing the protruding portion P of the inorganic particle 90. The inner wall surface 23 of the actual opening 21 is a substantially curved surface. The flat portion 91a is formed by removing the protruding portion P, so the exposed surface 91b of the flat portion 91a includes a curved surface. That is, the flat portion 91a and the resin 80 form a common surface, including forming the inner wall surface 23 formed by a substantial curved surface.

[0086] No irregularities are formed on the inner wall surface 23. The inner wall surface 23 is formed smoothly. The size of the irregularities is controlled by controlling the conditions for processing the inner wall surface 23b after laser irradiation.

[0087] The opening 21 is cleaned. By cleaning the opening 21, the resin residue generated when the opening 21 is formed is removed. The cleaning of the opening 21 is performed by plasma. That is, the cleaning is performed by a dry process. The cleaning includes a desmear treatment.

[0088] When cleaning the opening 21, the first surface 20a of the resin insulating layer 20 is covered by the protective film 50. The first surface 20a is not affected by the plasma. The first surface 20a is formed only by the resin 80. The inorganic particles 90 are not exposed from the first surface 20a. The first surface 20a does not include the surface of the inorganic particles 90. The first surface 20a has no unevenness. The first surface 20a is formed smoothly.

[0089] When the processing of the inner wall surface 23 b after the laser irradiation includes cleaning the inside of the opening 21 , in the embodiment, the step of cleaning the inside of the opening 21 can be eliminated.

[0090] like Fig. 8E As shown, after cleaning the inside of the openings 21 and 22 for the via conductors, the protective film 50 is removed from the resin insulating layer 20. When the processing of the inner wall surfaces 23b and 24b after laser irradiation includes cleaning the inside of the openings for the via conductors, the protective film 50 is removed from the resin insulating layer 20 after processing the inner wall surfaces 23b and 24b after laser irradiation. When the inner wall surfaces 23b and 24b after laser irradiation are processed, the protective film 50 covers the first surface 20a of the resin insulating layer 20. After removing the protective film 50, the first surface 20a is not roughened.

[0091] like Figure 8FAs shown, a seed layer 30a is formed on the first surface 20a. The seed layer 30a is formed by sputtering. The formation of the seed layer 30a is performed by a dry process. The seed layer 30a is also formed on the inner wall surfaces 23, 24 of the opening for the via conductor and the pads 12, 14 exposed from the openings 21, 22 for the via conductor. The seed layer 30a is mainly formed of copper. The first layer 31a is formed on the first surface 20a by sputtering. The first layer 31a is also formed on the inner wall surfaces 23, 24 of the opening for the via conductor and the pads 12, 14 exposed from the openings 21, 22 for the via conductor. The second layer 31b is formed on the first layer 31a by sputtering. The inner wall surfaces 23, 24 of the opening for the via conductor are formed by the exposed surface 91b of the first inorganic particle 91 and the surface 80a of the resin 80. Moreover, the exposed surface 91b and the surface 80a of the resin 80 are substantially located on the same surface. The inner wall surface of the opening for the via conductor is substantially flat. Therefore, in the embodiment, the thickness of the first layer 31a and the thickness of the second layer 31b on the inner wall surface can be thinned. Due to the thin thickness, in the embodiment, the deviation of the thickness of the seed layer 30a can be reduced. The first layer 31a on the inner wall surfaces 23 and 24 and the first layer 31a on the first surface 20a of the resin insulation layer 20 are formed at the same time. The second layer 31b on the inner wall surfaces 23 and 24 and the second layer 31b on the first surface 20a of the resin insulation layer 20 are formed at the same time. Therefore, in the embodiment, the thickness of the first layer 31a on the first surface 20a of the resin insulation layer 20 and the thickness of the second layer 31b can be reduced. In the embodiment, the thickness deviation of the first layer 31a on the first surface 20a of the resin insulation layer 20 and the thickness deviation of the second layer 31b can be reduced. The width of the connection wiring 36 on the first surface 20a of the resin insulation layer 20 meets the target value. The width of the space 37 between adjacent connection wirings 36 meets the target value. In the embodiment, it is possible to reduce the variation in the width of the connection wiring 36. In the embodiment, it is possible to reduce the variation in the width of the space 37. Even if a plurality of connection wirings 36 are formed on the first surface 20a of the resin insulating layer 20, data transmitted via each connection wiring 36 reaches the electronic component with almost no delay.

[0092] For example, the first layer 31a is formed of a copper alloy. The first layer 31a of the seed layer 30a is formed of an alloy containing copper, aluminum and silicon. Aluminum has high ductility and high ductility. Therefore, the adhesion between the resin insulating layer 20 and the first layer 31a is high. It is believed that even if the resin insulating layer 20 expands and contracts due to thermal cycles, the seed layer 30a containing aluminum can follow the expansion and contraction. Even if the first surface 20a of the resin insulating layer 20 is smooth, the seed layer 30a is difficult to peel off from the resin insulating layer 20. It is believed that aluminum is easily oxidized. It is believed that if the first inorganic particle 91 is an inorganic particle 90 containing oxygen (oxygen element), the first layer 31a formed on the inner wall surface 23, 24 is closely attached to the first inorganic particle 91 through the oxygen in the inorganic particle 90 forming the inner wall surface 23, 24. The first layer 31a is firmly bonded to the inner wall surface 23, 24. In an embodiment, the adhesion between the inner wall surface 23, 24 and the first layer 31a can be improved. The seed layer 30a is difficult to be peeled off from the inner wall surfaces 23 and 24. The inorganic particles 90 forming the inner wall surfaces 23 and 24 preferably contain oxygen.

[0093] The thickness of the seed layer 30a is greater than 0.02μm and less than 1.0μm. A more preferred example is greater than 0.03μm and less than 0.5μm. A further preferred example is greater than 0.05μm and less than 0.3μm. The arithmetic mean roughness (Ra) of the first surface 20a is greater than 0.02μm and less than 0.06μm. If the thickness of the seed layer 30a is less than 0.02μm, it is difficult to uniformly form the seed layer 30a on the entire first surface 20a of the resin insulating layer 20. If the thickness is greater than 1.0μm, it is difficult to control the width of the electroplating layer 30b when the seed layer 30a is removed. The thickness of the first layer 31a is greater than 0.01μm and less than 0.5μm. A more preferred example is greater than 0.02μm and less than 0.3μm. A further preferred example is greater than 0.03μm and less than 0.1μm. If the thickness of the first layer 31a is less than 0.01 μm, the adhesion between the first layer 31a and the resin insulating layer 20 is reduced. If the thickness of the first layer 31a is greater than 0.5 μm, the resistance of the connection wiring 36 becomes high. The thickness of the second layer 31b is greater than 0.01 μm and less than 0.9 μm. A more preferred example is greater than 0.02 μm and less than 0.3 μm. A further preferred example is greater than 0.03 μm and less than 0.2 μm. If the thickness of the second layer 31b is less than 0.01 μm, the resistance of the connection wiring 36 becomes high. If the thickness of the second layer 31b is greater than 0.9 μm, it is difficult to control the width of the electroplating layer 30b when the seed layer 30a is removed. The seed layer 30a is formed along the surface shape of the first surface 20a. The seed layer 30a forming the connection wiring 36 in the connection conductor layer 30 does not enter the inner side of the resin insulating layer 20. The embodiment can reduce the etching amount when removing the seed layer 30a. The connection wiring 36 is less likely to be excessively removed. The width of the connection wiring 36 has a value close to the designed value.

[0094] A plating resist is formed on the seed layer 30 a and has openings for forming the via conductors 41 and 42 , the connection wiring 36 , and the pads 32 and 34 extending from the connection wiring 36 .

[0095] The electroplating layer 30b is formed on the seed layer 30a exposed from the plating resist. The electroplating layer 30b fills the opening of the plating resist. The electroplating layer 30b fills the openings 21 and 22. A portion of the electroplating layer 30b protrudes upward from the upper surface of the plating resist. In this case, the electroplating layer 30b partially covers the upper surface of the plating resist. Alternatively, the electroplating layer 30b completely covers the upper surface of the plating resist.

[0096] The electroplating layer 30b is ground. The thickness of the electroplating layer 30b is reduced by grinding. The total thickness of the electroplating layer 30b and the thickness of the seed layer 30a reaches a predetermined value. The plating resist is also ground together with the electroplating layer 30b. An example of a grinding method is CMP. The arithmetic mean roughness (Ra) of the upper surface of the electroplating layer 30b after grinding is less than 0.3 μm.

[0097] After the electroplating layer 30b is polished, the plating resist is removed. The seed layer 30a exposed from the electroplating layer 30b is removed. Figure 8G As shown, pads 32, 34 and connection wiring 36 are formed by using seed layer 30a and plating layer 30b on resin insulating layer 20. Connecting conductor layer 30 is formed. Via conductors 41, 42 are formed by seed layer 30a and plating layer 30b in openings 21, 22 for via conductors. Connecting conductor layer 30 and via conductors 41, 42 are formed at the same time.

[0098] The etching rate R2 of the second layer 31b is greater than the etching rate R1 of the first layer 31a. The etching rate R1 of the first layer 31a is greater than the etching rate RE of the electroplating layer 30b. The etching rate RS of the seed layer 30a is greater than the etching rate RE of the electroplating layer 30b. For example, the ratio of the etching rate R2 of the second layer 31b to the etching rate RE of the electroplating layer 30b (R2 / RE) is greater than 1.2 and less than 1.5. The ratio of the etching rate R1 of the first layer 31a to the etching rate RE of the electroplating layer 30b (R1 / RE) is greater than 1.1 and less than 1.4. The ratio of the etching rate R2 of the second layer 31b to the etching rate R1 of the first layer 31a (R2 / R1) is greater than 1.1 and less than 1.5. Therefore, as Figure 5As shown, the width D2 of the first layer 31a is greater than the width D3 of the second layer 31b. The width D1 of the electroplating layer 30b is greater than the width D2 of the first layer 31a. When the seed layer 30a is removed, the etching amount of the electroplating layer 30b is small. It is difficult for the conductor circuit to be excessively removed. The width of the conductor circuit is formed roughly according to the design value. As an etching solution for removing the seed layer 30a, an etching solution that dissolves the second layer 31b more than the first layer 31a is preferred. The width of the wiring (the distance between the side walls of the wiring) has a minimum value ( Figure 5 ). In the boundary portion B, the stress easily exhibits a maximum value, so the adhesion between the first layer 31a and the resin insulating layer 20 is improved.

[0099] The etching speed is different between the layers 31a, 31b, and 30b that form the connecting conductor layer 30. It is speculated that the structural ratio (amorphous structure / crystalline structure) of each layer 31a, 31b, and 30b is related to the difference in etching speed. This is because amorphous structures are prone to lattice defects. Therefore, a layer with a large structural ratio is prone to have a large etching speed. Examples of devices for calculating the structural ratio are transmission electron microscopes and X-ray diffraction. For example, the structural ratio is calculated using the volumes of the two. Alternatively, the structural ratio is calculated using the areas of the two contained in the cross section. When using area, the area ratio (area of ​​amorphous structure / area of ​​crystal structure) is used as a representative value of the structural ratio.

[0100] It is believed that if the structural ratio is large, the etching speed is large. Therefore, the structural ratio of the second layer 31b should be greater than the structural ratio of the first layer 31a. The structural ratio of the first layer 31a should be greater than the structural ratio of the electroplating layer 30b. It is believed that heat, composition, thickness, time, formation method, density, crystallinity, etc. affect the structural ratio. The heat applied to the first layer 31a is greater than the heat applied to the second layer 31b. The thickness of the first layer 31a is approximately equal to the thickness of the second layer 31b. The thickness of the electroplating layer 30b is much thicker than the thickness of the first layer 31a. The second layer 31b and the electroplating layer 30b are formed of copper, and the first layer 31a is formed of a copper alloy. The first layer 31a is formed on a resin. The second layer 31b is formed on the first layer 31a composed of a copper alloy. The electroplating layer 30b is formed on the second layer 31b composed of copper. Among the first layer 31a, the second layer 31b, and the electroplating layer 30b, the first layer 31a is formed first. The first layer 31a and the second layer 31b are formed by sputtering. The electroplating layer 30b is formed by electroplating. There are commonalities and differences between the layers 31a, 31b, 30b forming the connecting conductor layer 30. It is considered that the etching speed of each layer 31a, 31b, 30b is controlled by controlling the factors affecting the structural ratio.

[0101] Since the flat portion 91a of the first inorganic particle 91 forms the inner wall surface 23, 24, the embodiment can reduce the thickness of the first layer 31a. The thickness of the first layer 31a is sufficiently thinner than the thickness of the electroplating layer 30b. Therefore, the orientation of the particles forming the first layer 31a is likely to be smaller than the orientation of the particles forming the electroplating layer 30b. Alternatively, the density of the first layer 31a is likely to be smaller than the density of the electroplating layer 30b. Alternatively, the crystallinity of the first layer 31a is likely to be smaller than the crystallinity of the electroplating layer 30b. Since the flat portion 91a of the first inorganic particle 91 forms the inner wall surface 23, 24, the embodiment can reduce the thickness of the second layer 31b. The thickness of the second layer 31b is sufficiently thinner than the thickness of the electroplating layer 30b. Therefore, the orientation of the particles forming the second layer 31b is likely to become smaller than the orientation of the particles forming the electroplating layer 30b. Alternatively, the density of the second layer 31b is likely to be smaller than the density of the electroplating layer 30b. Alternatively, the crystallinity of the second layer 31b is likely to be less than that of the plating layer 30b. Therefore, the etching rate of the first layer 31a and the second layer 31b is greater than the etching rate of the plating layer 30b. When the seed layer 30a exposed from the plating layer 30b is removed, the width D1 of the plating layer 30b is greater than the width D2 of the first layer 31a. The width D1 of the plating layer 30b is greater than the width D3 of the second layer 31b. The etching rate of the plating layer 30b is less than the etching rate of the seed layer 30a. Therefore, the amount of dissolved components in the etching solution consumed to dissolve the plating layer 30b is small. According to an embodiment, the dissolved components fully reach the seed layer 30a. The seed layer 30a is effectively dissolved. The embodiment can form a connection wiring 36 with a width of a target value. The first layer 31a is covered by the second layer 31b. The dissolved components are consumed to dissolve the second layer 31b. Therefore, the amount of dissolved first layer 31a can be made less than the amount of dissolved second layer 31b. When the seed layer 30 a exposed from the plating layer 30 b is removed, the width D2 of the first layer 31 a is greater than the width D3 of the second layer 31 b .

[0102] The first layer 31a forming the connection wiring 36 is formed on the insulating layer, and the second layer 31b is formed on the metal layer. The first layer 31a is formed of a copper alloy, and the second layer 31b is formed of copper. Figure 4 The first layer 31a on the inner wall surface 23 shown is formed at the same time. If they are intertwined with each other, it is considered that the etching rate of the first layer 31a is different from the etching rate of the second layer 31b.

[0103] like Figure 8H As shown in FIG. 1 , an adhesive layer 100 is formed on the upper surface and the side surface of the connecting conductor layer 30. The adhesive layer 100 is formed by Figure 8GThe intermediate substrate shown is formed by immersing it in a chemical solution containing a nitrogen-based organic compound. The pH of the chemical solution is 7 or less. By immersing the intermediate substrate in the chemical solution, an adhesive layer 100 having a smooth film 102 and a protrusion 104 is formed on the upper surface and side surfaces of the connecting conductor layer 30. Before the intermediate substrate is immersed in the chemical solution, the oxide film covering the upper surface and side surfaces of the connecting conductor layer 30 is removed. In a modified example, the adhesive layer 100 is formed by applying a chemical solution on the connecting conductor layer 30. When the adhesive layer 100 is formed, the intermediate substrate is removed from the chemical solution. The adhesive layer 100 is dried. The upper surface of the adhesive layer 100 before drying may be smooth. In this case, a part of the adhesive layer condenses by drying. By condensing, the adhesive layer 100 including the smooth film 102 and the protrusion 104 is formed.

[0104] A resin insulating layer (second resin insulating layer) 120, a mounting conductor layer 130, and via conductors 141, 142, 143, 144 are formed on the connecting conductor layer 30 and the resin insulating layer 20. The via conductors include connecting via conductors. Examples of connecting via conductors are the first connecting via conductor 141 and the second connecting via conductor 142. The resin insulating layer 120 and the resin insulating layer 20 are formed by the same method. The mounting conductor layer 130 and the connecting conductor layer 30 are formed by the same method. The via conductors 141, 142, 143, 144 and the via conductors 41, 42 are formed by the same method. When the openings 121, 122, 123, 124 for the via conductors are formed in the resin insulating layer 120 by using the laser L, the laser L removes the adhesive layer 100 covering the connecting conductor layer 30. Alternatively, the adhesive layer 100 is not completely removed by the laser L. In this case, the adhesive layer 100 at the bottom of the openings 121, 122, 123, 124 for the via conductors is removed by cleaning the inside of the openings 121, 122, 123, 124 for the via conductors. The connecting conductor layer 30 is exposed through the openings 121, 122, 123, 124 for the via conductors. The openings for the via conductors include the openings for the connecting via conductors. Examples of the openings for the connecting via conductors are the first opening (the first connecting via conductor opening) 121 and the second opening (the second connecting via conductor opening) 122.

[0105] The embodiment can make the thickness of the first layer forming the connecting via conductor thinner. The embodiment can make the thickness of the second layer forming the connecting via conductor thinner. The first layer and the second layer form a seed layer. The embodiment can increase the volume of the opening for the connecting via conductor after the seed layer is formed. The opening for the connecting via conductor after the seed layer is formed can be referred to as an opening after the seed layer is formed. By forming an electroplating layer in the opening after the seed layer is formed, a connecting via conductor composed of a seed layer and an electroplating layer is formed. Even if the diameter of the opening for the connecting via conductor is small, the plating solution can easily enter the opening for the connecting via conductor after the seed layer is formed. The electroplating layer forming the connecting via conductor is unlikely to contain voids. A low-resistance connecting via conductor is formed. Even if the path includes a connecting via conductor, the printed wiring board 2 of the embodiment can transmit high-speed data. Examples of openings 210 and 211 after the seed layer is formed are as follows Figure 8F As shown, after the seed layer is formed, the openings 210 and 211 are surrounded by the seed layer, and the bottom and side surfaces of the openings 210 and 211 are in contact with the seed layer.

[0106] Adhesive layer 150 is formed on the upper surface and side surface of mounting conductor layer 130. Adhesive layer 150 is the same as adhesive layer 100. Insulating layer 220 is formed on mounting conductor layer 130 and resin insulating layer 120. Insulating layer 220 has openings 221, 222, 223, 224 for exposing electrodes (first electrode 131, second electrode 132, etc.). Protrusions (first protrusion 241, second protrusion 242, etc.) are formed on electrodes 131, 132, 133, 134 exposed through openings 221, 222, 223, 224. Functional layer 260 is formed on protrusions 241, 242, 243, 244. Printed wiring board 3 of a modified example is obtained.

[0107] The support 4 is removed. For example, by heating or ultraviolet irradiation, the peeling layer 7 of the support 4 is softened or brittle. The first metal layer 6 and the second metal layer 8 are separated. Thereafter, the second metal layer 8 is removed by etching. The lower surface 2b of the printed wiring board 2 is exposed. The printed wiring board 2 of the embodiment is obtained.

[0108] By making the width D3 of the second layer 31b smaller than the width D1 of the plating layer 30b and the width D2 of the first layer 31a, the side wall of the connection wiring 36 has the recess 38 ( Figure 5 ). Stress is difficult to be transmitted to the resin insulating layer 20 along the side wall of the connection wiring 36. The stress is dispersed by the recess 38. It is difficult to generate cracks along the extension line of the interface between the side wall of the connection wiring 36 and the resin insulating layer 120 in the resin insulating layer 20. Since the side wall of the connection wiring 36 has the recess 38, the contact area between the connection wiring 36 and the resin insulating layer 120 is large. The resin insulating layer 120 is difficult to be peeled off from the connection wiring 36.

[0109] The surface of the connecting conductor layer 30 that is opposite to the first surface 20a is formed along the surface shape of the first surface 20a. Therefore, the seed layer 30a that forms the connecting wiring 36 in the connecting conductor layer 30 does not enter the inner side of the first surface 20a of the first resin insulating layer 20. A thin seed layer 30a is formed. The deviation of the thickness of the seed layer 30a is small. When the seed layer 30a is removed, the etching amount is small. The connecting wiring 36 is difficult to be excessively removed. The width of the connecting wiring 36 is approximately close to the design value.

[0110] The width of the connection wiring 36 is small. The thickness of the connection wiring 36 is small. The width of the space 37 between the connection wirings 36 is small. Therefore, the resin insulation layer 120 formed between the adjacent connection wirings 36 is easily peeled off from the connection wiring 36. The connection wirings 36 are densely formed. Therefore, cracks along the sides of the connection wirings 36 are easily generated in the first resin insulation layer 20 supporting the connection wirings 36. However, since the connection wirings 36 of the embodiment have the recesses 38, the second resin insulation layer 120 filling the spaces between the connection wirings 36 is difficult to peel off from the connection wirings 36. The second resin insulation layer 120 covering the connection wirings 36 is difficult to peel off from the connection wirings 36. Cracks along the sides of the connection wirings 36 are not easily generated in the first resin insulation layer 20 supporting the connection wirings 36. Since the connection wirings 36 have the recesses 38, the embodiment can configure the connection wirings 36 at a high density.

[0111] For example, by making the width D2 smaller than the width D1 and the width D3, the side wall of the connection wiring can be made to have a recess. In this case, the contact area between the first layer 31a and the first surface 20a is small. Therefore, the connection wiring 36 is easily peeled off from the first surface 20a. However, in the embodiment, the width D1 and the width D2 are larger than the width D3. Therefore, in the embodiment, the connection wiring 36 is difficult to peel off from the first surface 20a.

[0112] The connection wiring formed at one end of the plurality of connection wirings 36 is the first connection wiring 36F. The first connection wiring 36F is as shown in FIG. Figure 1 and Figure 3 As shown. Figure 3 As shown, the first connection wiring 36F has a first side wall F1 opposite to the adjacent connection wiring (second connection wiring) and a second side wall F2 on the opposite side to the first side wall F1. There is no connection wiring 36 next to the second side wall F2. The first connection wiring 36F has recesses 38 on both sides, and the size of the recess 38 formed on the first side wall F1 (first recess 38F1) is smaller than the size of the recess 38 formed on the second side wall F2 (second recess 38F2). Figure 5The first recess 38F1 and the second recess 38F2 are depicted in FIG. The size of the recess 38 is represented by the distance X between the surface including the side of the electroplated layer 30b and the side of the second layer 31b. The distance X is represented by Figure 5 The side of the second layer 31b is represented by the position of the boundary portion B.

[0113] In the printed wiring board 2 of the embodiment, the inner wall surface of the opening for the via conductor is formed by the flat portion 91a of the first inorganic particle 91 and the resin 80. The flat portion 91a and the surface 80a of the resin 80 forming the inner wall surface form a substantially common surface. The inner wall surface is formed smoothly. Therefore, a seed layer 30a of uniform thickness is formed on the inner wall surface of the opening. The seed layer 30a is formed thinner. When the seed layer 30a is removed, the etching amount is small. Therefore, the etching amount of the electroplating layer 30b is small. Each conductor circuit in the connecting conductor layer 30 and the mounting conductor layer 130 has a width as designed. Provided is a printed wiring board 2 with high quality.

[0114] Data is transmitted from the first electronic component E1 to the second electronic component E2 via the connecting wiring 36. When data is transmitted, low loss is preferred. When the connecting conductor layer is the conductor layer of the inner layer, the path for data transmission between the first electronic component E1 and the second electronic component E2 includes a via conductor connected to the connecting wiring. The via conductor forming the path is a connecting via conductor. Even if the path includes a via conductor (connecting via conductor), the inner wall surface of the opening for the connecting via conductor of the printed wiring board 2 of the embodiment is formed by the exposed surface 91b of the first inorganic particle 91 and the surface 80a of the resin 80. The inner wall surface is roughly flat. According to the embodiment, when data passes through the via conductor, the printed wiring board 2 of the embodiment can suppress loss. The conductor layer of the inner layer is sandwiched by adjacent resin insulation layers. When there are multiple connecting conductor layers (connecting internal conductor layers) formed by the conductor layer of the inner layer, the number of connecting internal conductor layers CI is preferably more than 3. The number of connecting internal conductor layers CI is preferably less than 7. Furthermore, the number of connecting internal conductor layers CI is preferably less than 5. An example of a printed wiring board 200 having three connecting internal conductor layers CI is shown in FIG. Fig. 9 As shown. Fig. 9 As shown, when the path connecting the first connection pad P1 and the first connection electrode D1 has a plurality of via-hole conductors V1, V2, and V3, all the via-hole conductors V1, V2, and V3 in the path are formed at the same position as Figure 4The via conductor V1, the via conductor V2 and the via conductor V3 are first connection via conductors and form a first path. The via conductor V1, the via conductor V2 and the via conductor V3 are formed in different resin insulating layers. When the path connecting the second connection pad P2 and the second connection electrode D2 has a plurality of via conductors V4, V5 and V6, all the via conductors V4, V5 and V6 in the path are formed in the same resin insulating layer as the second connection pad P2 and the second connection electrode D2. Figure 4 The opening 21 shown is also an opening for a via conductor. The via conductor V4, the via conductor V5, and the via conductor V6 are second connection via conductors and form a second path. The via conductor V4, the via conductor V5, and the via conductor V6 are formed in different resin insulating layers.

[0115] The connecting internal conductor layer is preferably sandwiched by a resin insulating layer containing the first inorganic particles 91 and the second inorganic particles 92. The resin insulating layers sandwiching the connecting internal conductor layer each have an opening for a via conductor. Moreover, the inner wall surface of the opening for the via conductor is formed by the exposed surface 91b of the first inorganic particle 91 and the surface 80a of the resin 80. Each connecting wiring forming the connecting internal conductor layer has a width close to the design value. The embodiment can form a high-density connecting wiring group.

[0116] The inner wall surface of each via hole opening is formed by the exposed surface 91b of the first inorganic particle 91 and the surface 80a of the resin 80, so the inner wall surface of each via hole has substantially the same shape. Even if there are multiple paths including connecting via hole conductors, the embodiment can reduce the difference in transmission speed between the paths.

[0117] In the printed wiring board 2 of the embodiment, the first surface 20a of the resin insulating layer 20 is formed of the resin 80. The inorganic particles 90 are not exposed on the first surface 20a. No concavoconvexity is formed on the first surface 20a. The standard deviation of the relative dielectric constant of the portion near the first surface 20a of the resin insulating layer 20 is suppressed from becoming larger. The relative dielectric constant of the first surface 20a of the resin insulating layer 20 does not vary greatly depending on the location. Even if a plurality of connection wirings 36 are in contact with the first surface 20a of the resin insulating layer 20, in the embodiment, the difference in propagation speed of the electrical signal between the connection wirings 36 can be reduced. Therefore, noise is suppressed in the printed wiring board 2 of the embodiment. Even if a logic IC is mounted on the printed wiring board 2 of the embodiment, the data transmitted by each connection wiring 36 reaches the logic IC almost at the same time. In the embodiment, malfunction of the logic IC can be suppressed. Even if the length of each connection wiring 36 is 5 mm or more, in the embodiment, the difference in propagation speed can be reduced. Even if the length of each connection wiring 36 is 10 mm or more and 20 mm or less, in the embodiment, malfunction of the logic IC can be suppressed. The first surface 120a of the resin insulating layer 120 is also the same as the first surface 20a of the resin insulating layer 20. Therefore, the connection wiring in the mounting conductor layer 130 also has the same effect as the connection wiring 36 in the connection conductor layer 30. A high-quality printed wiring board 2 is provided.

[0118] The printed wiring board 2 of the embodiment has an adhesive layer 100 between the connecting conductor layer 30 and the resin insulating layer 120. The adhesive layer 100 bonds the connecting conductor layer 30 to the resin insulating layer 120. Therefore, even if the upper surface and the side surface of the connecting wiring 36 are smooth, the resin insulating layer 120 is difficult to peel off from the connecting wiring 36. It is preferable not to roughen the upper surface and the side surface of the connecting wiring 36. The adhesive layer 100 is formed by a substantially smooth smooth film 102 and a protrusion 104 protruding from the smooth film 102. The adhesive layer 100 has concavities and convexities formed by the protrusion 104 and the smooth film 102. The adhesive layer 100 has concavities and convexities formed by a plurality of protrusions 106. Therefore, the connecting conductor layer 30 and the resin insulating layer 120 are sufficiently adhered to each other via the adhesive layer 100. A printed wiring board 2 with high quality is provided. For example, even if the length of each side of the printed wiring board 2 is 50 mm or more, the resin insulating layer 120 is difficult to peel off from the connecting conductor layer 30. Even when the length of each side of the printed wiring board 2 is 100 mm or more, cracks caused by the adhesive layer 100 are unlikely to occur in the resin insulating layer 120. Even when the connecting conductor layer 30 includes a conductor circuit having a width of 5 μm or less, the resin insulating layer 120 is unlikely to be peeled off from the connecting conductor layer 30. Even when the connecting conductor layer 30 includes a conductor circuit having a width of 3 μm or less, cracks caused by the adhesive layer 100 are unlikely to occur in the resin insulating layer 120. The adhesive layer 150 formed between the mounting conductor layer 130 and the insulating layer 220 also has the same effect as the adhesive layer 100. A printed wiring board 2 having high quality is provided.

[0119] When the first layer contains silicon as the specific metal and the inorganic particles are glass particles, the first layer and the first inorganic particles on the inner wall surface contain silicon. It is believed that the two are firmly bonded via silicon. The seed layer is difficult to peel off from the inner wall surface.

[0120] It is believed that if the first layer contains aluminum and the inorganic particles contain oxygen, the first layer and the first inorganic particles (inorganic particles containing oxygen such as glass particles) are firmly bonded. In the case where the first layer contains aluminum and the inorganic particles contain oxygen, the first layer may not contain the specific metal. In this case, the first layer is formed of copper, aluminum and impurities.

[0121] [Another Example 1 of Implementation]

[0122] In another example 1 of the embodiment, the specific metal contained in the alloy forming the first layer is at least one of nickel, zinc, gallium, silicon, and magnesium.

[0123] [Another Example 2 of Implementation Method]

[0124] In another embodiment example 2, the alloy forming the first layer does not contain carbon.

[0125] [Another Example 3 of Implementation]

[0126] In another example 3 of the embodiment, the alloy forming the first layer does not contain oxygen.

[0127] In this specification, the term "plane" is used to refer to the shape of the inner wall surface, the shape of the flat portion 91a, and the shape of the first inorganic particle 91. The plane used in these terms means Figure 2 and Figure 4 That is, in Figure 2 and Figure 4 In the figure, the inner wall surface is drawn roughly straight. Figure 2 and Figure 4 The shape of the inner wall surface in the cross section is generally a straight line. The plane in this specification includes the substantial straight line shown in the cross section. Figure 2 and Figure 4 As shown in the cross section of the first inorganic particle 91, in the cross section, cutting with a plane includes cutting with a straight line. The plane in this specification does not mean a complete plane, but includes a substantial plane. The substantial plane may also include small concave and convex.

Claims

1. A printed wiring board comprising: a mounting conductor layer having a first electrode for mounting a first electronic component and a second electrode for mounting a second electronic component; a connecting conductor layer, located below the mounting conductor layer, having a connecting wiring that electrically connects the first electrode and the second electrode; a second resin insulating layer disposed between the mounting conductor layer and the connecting conductor layer and having a plurality of openings including a first opening and a second opening; a first resin insulating layer, which is located below the connecting conductor layer and supports the connecting conductor layer; a first connection via conductor formed in the first opening and electrically connecting the first electrode and the connection wiring; as well as a second connecting via conductor formed in the second opening and electrically connecting the second electrode and the connecting wiring, in, The connecting conductor layer is formed of a seed layer and a plating layer on the seed layer, wherein the seed layer is composed of a first layer formed on the first resin insulating layer and a second layer on the first layer. In a cross section of the connection wiring, the width of the first layer is greater than the width of the second layer, and the width of the electroplating layer is greater than the width of the first layer.

2. The printed wiring board according to claim 1, wherein The width of the connection wiring has a minimum value at a boundary portion between the seed layer and the plating layer.

3. The printed wiring board according to claim 1, wherein The second resin insulating layer is formed of inorganic particles and resin, The inorganic particles include first inorganic particles forming the inner wall surface of the opening and second inorganic particles buried in the second resin insulating layer, The shape of the first inorganic particles is different from the shape of the second inorganic particles.

4. The printed wiring board according to claim 1, wherein The side wall of the connection wiring has a recess.

5. The printed wiring board according to claim 3, wherein The inner wall surface is formed by the first inorganic particles and the resin, The first inorganic particle has a flat portion, The flat portion forms the inner wall surface.

6. The printed wiring board according to claim 5, wherein The flat portion and a surface of the resin forming the inner wall surface form a substantially common surface.

7. The printed wiring board according to claim 5, wherein The second inorganic particles are in the shape of spheres, The shape of the first inorganic particle is obtained by cutting the second inorganic particle along a plane.

8. The printed wiring board according to claim 3, wherein In the process of forming the opening, the inorganic particles are formed to have a protruding portion protruding from the resin forming the inner wall surface of the opening, and the first inorganic particles are formed by removing the protruding portion of the inorganic particles.

9. The printed wiring board according to claim 3, wherein In the process of forming the opening, the inorganic particles having the protruding portion are formed from the second inorganic particles, The inner wall surface of the opening includes an exposed surface of the first inorganic particles formed by removing the protruding portion.

10. The printed wiring board according to claim 1, wherein An adhesive layer is further provided between the connecting conductor layer and the second resin insulating layer. The adhesive layer is in contact with the connecting conductor layer, The second resin insulation layer is in contact with the adhesive layer.

11. The printed wiring board according to claim 10, wherein The adhesive layer is formed of a substantially smooth smooth film and a protrusion protruding from the smooth film.

12. The printed wiring board according to claim 1, wherein The number of the first electrodes, the number of the second electrodes, and the number of the connecting wirings are plural, The connecting wirings are arranged substantially in parallel. The connection wiring having the smallest width among the plurality of connection wirings is the smallest connection wiring, The minimum width of the connection wiring is not less than 1 μm and not more than 3 μm, There is a space between adjacent connecting wirings, The space with the smallest width among the plurality of spaces is the smallest space, The minimum space has a width of 1 μm or more and 3 μm or less.

13. The printed wiring board according to claim 1, wherein The first layer and the second layer are formed by sputtering. The first layer is composed of an alloy containing copper, aluminum and a specific metal. The second layer is formed of copper.

14. The printed wiring board according to claim 13, wherein The specific metal is silicon.

15. The printed wiring board according to claim 3, wherein The first inorganic particles contain oxygen.

16. The printed wiring board according to claim 5, wherein The inner wall surface has a step.

17. The printed wiring board according to claim 1, wherein There are multiple connecting wires. The connection wiring formed at one end of the plurality of connection wirings is a first connection wiring, The first connection wiring has a first side wall and a second side wall opposite to the first side wall, and other connection wirings are formed beside the first side wall. The connection wiring is not formed beside the second side wall, The size of the recess formed on the first side wall is smaller than the size of the recess formed on the second side wall.

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