Circuit board and manufacturing method thereof

Abstract

A circuit board includes a first circuit structure, a second circuit structure and an internal structure. The internal structure is disposed between the first line structure and the second line structure, wherein the first line structure, the second line structure and the internal structure are stacked in the first direction. The internal structure and the first circuit structure protrude out of the side wall of the second circuit structure in a second direction perpendicular to the first direction. The first circuit structure comprises a plurality of first connecting pads, the plurality of first connecting pads protrude out of the side wall of the second circuit structure in the second direction, each of the plurality of first connecting pads is provided with a first top and a first bottom, and the width of the first top is larger than that of the first bottom. The wider top part can increase the surface contact area between the connecting pads so as to improve the connecting capability between the connecting pads.

Description

Technical Field

[0001] The present invention relates to a circuit board and a method for manufacturing the circuit board, and in particular to a circuit board with a pad having a larger area and a method for manufacturing the circuit board. Background Art

[0002] In existing display technology, a circuit board can be connected (pressed) to a display through an anisotropic conductive film (ACF). The ACF connection method can be applied to various displays. However, with the trend of electronic products becoming lighter and smaller, the size of the pads in the circuit board and the display (or electronic components) is getting smaller and smaller, and the contact area between the pads of the circuit board and the pads of the display is also getting smaller. As a result, the ACF connection method is limited by the reduced size of the pads, and it is difficult to meet the trend of existing electronic products becoming lighter and smaller. Summary of the invention

[0003] At least one embodiment of the present invention provides a circuit board and a manufacturing method thereof, wherein the pads are formed with a wider top by electroplating. The wider top can increase the surface contact area between the pads of the circuit board and the pads of the display (or electronic component), thereby improving the connection capability between the pads.

[0004] A circuit board provided in at least one embodiment of the present invention comprises a first circuit structure, a second circuit structure and an internal structure. The internal structure is disposed between the first circuit structure and the second circuit structure, wherein the first circuit structure, the second circuit structure and the internal structure are stacked in a first direction. The internal structure and the first circuit structure protrude from a side wall of the second circuit structure in a second direction perpendicular to the first direction. The first circuit structure comprises a plurality of first pads, and the plurality of first pads protrude from a side wall of the second circuit structure in the second direction, wherein each of the plurality of first pads has a first top and a first bottom, and the width of the first top is greater than the width of the first bottom.

[0005] In at least one embodiment of the present invention, the circuit board further includes a flexible circuit substrate, wherein the flexible circuit substrate is disposed on the plurality of first pads.

[0006] In at least one embodiment of the present invention, a top surface of the first top portion of each of the plurality of first pads is a curved surface or a flat surface.

[0007] In at least one embodiment of the present invention, the circuit board further includes a first external circuit structure, wherein the first external circuit structure is disposed on the first circuit structure, wherein the first circuit structure protrudes from a side wall of the first external circuit structure in the second direction.

[0008] In at least one embodiment of the present invention, the second circuit structure includes a plurality of second pads, wherein each of the plurality of second pads has a second top portion and a second bottom portion, and a width of the second top portion is greater than a width of the second bottom portion.

[0009] In at least one embodiment of the present invention, the circuit board further includes an electronic component, wherein the electronic component is disposed on the plurality of second pads.

[0010] In at least one embodiment of the present invention, the circuit board further includes a second external circuit structure, wherein the second external circuit structure is disposed on the second circuit structure, wherein the second external circuit structure includes an opening, and the electronic component is disposed in the opening.

[0011] A method for manufacturing a circuit board provided by at least one embodiment of the present invention comprises the following steps. A substrate is provided. A first mask layer is formed on the substrate. The substrate is electroplated using the first mask layer as a mask to form an initial circuit layer on the substrate, wherein the initial circuit layer comprises a plurality of initial pads and a plurality of routing lines, and a plurality of gaps are formed between the plurality of initial pads and the plurality of routing lines. The plurality of gaps are filled with dielectric material. A second mask layer is formed on the initial circuit layer and the dielectric material, wherein the second mask layer covers the routing lines and exposes the plurality of initial pads. The plurality of initial pads are electroplated using the second mask layer as a mask to form a plurality of pads, wherein each of the plurality of pads has a top and a bottom, and the width of the top is greater than the width of the bottom. The second mask layer is removed.

[0012] In at least one embodiment of the present invention, the step of filling the plurality of gaps with the dielectric material comprises the following steps: forming an initial dielectric material to fill the plurality of gaps and cover the top surface of the initial circuit layer; and removing a portion of the initial dielectric material covering the top surface of the initial circuit layer to expose the top surface of the initial circuit layer.

[0013] In at least one embodiment of the present invention, the method for manufacturing a circuit board further comprises the following steps: After electroplating a plurality of initial pads, forming a third mask layer to cover the pads; using the third mask layer as a mask, removing the substrate to expose the plurality of pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] When read in conjunction with the accompanying drawings, the various aspects of the present application can be best understood according to the following detailed description. It should be understood that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features can be arbitrarily increased or reduced for clarity.

[0015] Figures 1A to 1H Schematic cross-sectional view of a circuit board in various stages of a process according to at least one embodiment of the present invention.

[0016] FIG. 2A to FIG. 2CSchematic cross-sectional views of pads according to various embodiments of the present invention.

[0017] FIG. 3A to FIG. 3D Schematic cross-sectional view of a circuit board in various stages of a process according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0018] In the following text, in order to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the components (e.g., circuit layers, adhesive layers, and pads, etc.) in the accompanying drawings will be enlarged in unequal proportions, and the number of some components will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of components in the accompanying drawings and the dimensions and shapes presented by the components, but should cover the dimensions, shapes, and deviations thereof caused by actual processes and / or tolerances. For example, the flat surface shown in the accompanying drawings may have rough and / or nonlinear features, while the acute angles shown in the accompanying drawings may be rounded. Therefore, the components presented in the accompanying drawings of the present invention are mainly for illustration, and are not intended to accurately depict the actual shape of the components, nor are they intended to limit the scope of the patent application of the present invention.

[0019] In addition, spatially relative terms such as "below," "below," "below," "above," "above," and other similar terms are used to facilitate describing the relationship between one element or feature and another element or feature in the figure. In addition to the orientation depicted in the figure, the spatially relative terms also cover other orientations of the device when in use or operation. That is, when the orientation of the device is different from the figure (rotated 90 degrees or in other orientations), the spatially relative terms used in this disclosure can also be interpreted accordingly.

[0020] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the embodiment, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] It should be noted that the first direction D1 and the second direction D2 are marked in the drawings of the present case to show the configuration relationship of each component in the drawings, and the first direction D1 and the second direction D2 are substantially perpendicular to each other.

[0022] Figures 1A to 1H Schematic diagram of the cross-section of the circuit board 100 in various stages of the process of at least one embodiment of the present invention. Figure 1A, a first mask layer 120 is formed on the substrate 110. In some embodiments, the substrate 110 may be a copper substrate, such as a copper foil. In some embodiments, the first mask layer 120 may include a photoresist, such as a dry film photoresist, a wet photoresist, some other suitable mask material, or any combination thereof. In some embodiments, the first mask layer 120 may be formed on the substrate 110 by a coating process. Then, after the photoresist is exposed and developed, a first mask layer 120 having a pattern is formed, such as Figure 1A shown.

[0023] Please refer to Figure 1A and Figure 1B , using the first mask layer 120 as a mask, electroplating the substrate 110 to form an initial circuit layer 130 on the substrate 110. In some embodiments, when the substrate 110 is a copper substrate (e.g., copper foil), the initial circuit layer 130 is formed by electroplating. It is understood that the thickness of the initial circuit layer 130 can be adjusted by the electroplating time. In some embodiments, the material of the initial circuit layer 130 includes copper.

[0024] Since the first mask layer 120 is used as a mask, the initial circuit layer 130 is formed in the gap of the first mask layer 120, and the initial circuit layer 130 is connected to the substrate 110. After the initial circuit layer 130 is formed, the first mask layer 120 is removed from between the substrate 110 and the initial circuit layer 130 to form a circuit board 110. Figure 1B The initial circuit layer 130 includes a plurality of initial pads 132 and a plurality of routing lines 134 , and a plurality of gaps 136 are formed between the plurality of initial pads 132 and the plurality of routing lines 134 .

[0025] Please refer to Figures 1B to 1D , the plurality of gaps 136 are filled with dielectric material 140a. In detail, Figure 1B and Figure 1C As shown, an initial dielectric material 140 is formed to fill the gaps 136 between the plurality of initial pads 132 and between the plurality of traces 134. Figure 1C As shown, the initial dielectric material 140 covers the top surface 132s1 of the initial pad 132 and the top surface 134s1 of the trace 134. In some embodiments, the initial dielectric material 140 and the dielectric material 140a may include epoxy, liquid crystal polymer (LCP), polypropylene (PP), polyimide (PI), but are not limited thereto.

[0026] Please refer to Figure 1C and Figure 1D , removing the initial dielectric material 140 covering the top surface of the initial circuit layer 130 (ie, the top surface 132s1 of the initial pad 132 and the top surface 134s1 of the trace 134) to expose the top surface of the initial circuit layer 130, forming Figure 1D Dielectric material 140a is shown.

[0027] Please refer to Figure 1D and Figure 1E , forming a second mask layer 150 on the initial circuit layer 130 and the dielectric material 140a, wherein the second mask layer 150 covers the traces 134 and exposes a plurality of initial pads 132. Specifically, the second mask layer 150 has an opening 152, and the opening 152 exposes a plurality of initial pads 132, such as Figure 1E In some embodiments, the material of the second mask layer 150 may be the same as or similar to the material of the first mask layer 120. In some embodiments, the method of forming the second mask layer 150 may be the same as or similar to the method of forming the first mask layer 120.

[0028] Please refer to Figure 1E and Figure 1F , using the second mask layer 150 as a mask, electroplating the plurality of initial pads 132 to form a plurality of pads 132a. Specifically, since the initial pads 132 are made of metal material (e.g., copper metal), and the dielectric material 140a has dielectric properties, when the electroplating process is performed, only the surface of the initial pads 132 will form an electroplated metal layer, and the surface of the dielectric material 140a will not form an electroplated metal layer. Figure 1F As shown, the pad 132a has a top portion 132at and a bottom portion 132ab, and a width W1 of the top portion 132at is greater than a width W2 of the bottom portion 132ab. In some embodiments, the width W2 is less than 20 micrometers.

[0029] It should be understood that for the purpose of discussing the method of forming the pad, the "bottom 132ab" is substantially the same as the "initial pad 132", and the "top 132at" is a protrusion formed above the "initial pad 132" by electroplating. In some embodiments, the top 132at is formed above the initial pad 132 by electroplating to form the pad 132a. In some embodiments, the top 132at and the initial pad 132 have the same material. In some embodiments, the thickness and morphology of the top 132at can be adjusted by the electroplating time. The embodiment of the change of the top 132at will be described in detail. FIG. 2A to FIG. 2C Detailed description.

[0030] Please refer to Figure 1F and Figure 1G, remove the second mask layer 150, and form a third mask layer 160 to cover the pad 132a. In detail, the third mask layer 160 covers the top 132at of the pad 132a and a portion of the top of the dielectric material 140a. In some embodiments, the material of the third mask layer 160 may be the same as or similar to the material of the first mask layer 120. In some embodiments, the method of forming the third mask layer 160 may be the same as or similar to the method of forming the first mask layer 120.

[0031] Please refer to Figure 1G and Figure 1H , using the third mask layer 160 as a mask, the substrate 110 is removed to expose the plurality of pads 132a and the plurality of traces 134. Specifically, after removing the substrate 110, the bottom surface 132s2 of the bottom 132ab of the pad 132a is exposed. In addition, the bottom surface 134s2 of the trace 134 is also exposed after removing the substrate 110. In some embodiments, the substrate 110 is removed by an etching process.

[0032] After removing the substrate 110, the third mask layer 160 is removed, so that the top surface 133 of the top 132at of the pad 132a and the top surface 134s1 of the trace 134 are exposed, and then the circuit board 100 having the circuit layer 130a and the dielectric material 140a is formed. Figure 1H In other words, the top 132at of the pad 132a is completely exposed, and the bottom 132ab of the pad 132a is embedded in the dielectric material 140a.

[0033] exist Figure 1H In the embodiment, the top surface 134s1 of the trace 134 is substantially coplanar with the top surface of the dielectric material 140a, and the bottom surface 134s2 of the trace 134 is also substantially coplanar with the bottom surface 132s2 of the bottom 132ab and the bottom surface of the dielectric material 140a.

[0034] FIG. 2A to FIG. 2C 1 is a cross-sectional view of the pad 132a of various embodiments of the present invention. Since the thickness and morphology of the top 132at of the pad 132a can be changed by, for example, adjusting the electroplating time, FIG. 2A to FIG. 2C Various aspects of the top portion 132at are shown.

[0035] Please refer to Figure 2A , the top surface 133 of the top portion 132at is a plane, and the side surface 137 of the top portion 132at is a curved surface. Figure 2A The cross-sectional structure of the pad 132 a has a T-shaped structure.

[0036] Please refer to Figure 2B, the top surface 133 and the side surface 137 of the top portion 132at are both curved surfaces. Figure 2B The top portion 132at has a hat-like shape.

[0037] Please refer to Figure 2C The top surface 133 and the side surface 137 of the top portion 132at are also curved surfaces. Figure 2C The top portion 132at has a mushroom-like shape.

[0038] Due to the characteristics of the electroplating process, the top portion 132at grows in both the lateral direction (i.e., the second direction D2) and the longitudinal direction (i.e., the first direction D1). Therefore, the curvature of the top surface 133 decreases as the electroplating time increases, while the curvature of the side surface 137 increases as the electroplating time increases. As the electroplating time increases, the curvatures of the top surface 133 and the side surface 137 tend to be the same. In other words, the boundary between the top surface 133 and the side surface 137 tends to be blurred, as shown in FIG. Figure 2C shown.

[0039] It should be noted that this article Figure 1F to Figure 1H The pad 132a and the bottom FIG. 3A to FIG. 3D The first pad 322 and the second pad 332 shown in the figure can be replaced by FIG. 2A to FIG. 2C The pads shown.

[0040] FIG. 3A to FIG. 3D Schematic diagram of the cross section of the circuit board 300 in various stages of the process of at least one embodiment of the present invention. Figure 3A , the circuit board 300 includes an internal structure 310, a first circuit structure 320, and a second circuit structure 330. The internal structure 310 is disposed between the first circuit structure 320 and the second circuit structure 330. In other words, the first circuit structure 320 and the second circuit structure 330 are disposed on opposite sides of the internal structure 310. The first circuit structure 320, the second circuit structure 330, and the internal structure 310 are stacked in the first direction D1.

[0041] The inner structure 310 includes a core layer 312 and an adhesive layer 314, wherein the adhesive layers 314 are respectively located on opposite sides of the core layer 312. The core layer 312 and the adhesive layer 314 are stacked along a first direction D1, wherein the first direction D1 may be perpendicular to the second direction D2.

[0042] In some embodiments, the material of the core layer 312 may be an insulating material such as polyimide (PI), glass fiber epoxy resin (FR4), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or polyethylene (PE), but is not limited thereto. In some embodiments, the material of the adhesive layer 314 may be a low flow prepreg or a non-flow prepreg.

[0043] Each of the first circuit structure 320 and the second circuit structure 330 may be formed by Figures 1A to 1H The circuit board (also referred to as a circuit substrate) formed by the manufacturing method described above. The first circuit structure 320 includes a plurality of first pads 322, and each of the plurality of first pads 322 has a first top 322t and a first bottom 322b, and the width of the first top 322t is greater than the width of the first bottom 322b. In some embodiments, the top surface of the first top 322t of the first pad 322 can be a curved surface or a flat surface.

[0044] The second circuit structure 330 includes a plurality of second pads 332, and each of the plurality of second pads 332 has a second top 332t and a second bottom 332b, and the width of the second top 332t is greater than the width of the second bottom 332b. In some embodiments, the top surface of the second top 332t of the second pad 332 can be a curved surface or a flat surface.

[0045] The inner structure 310 and the first circuit structure 320 protrude from the sidewall SW1 of the second circuit structure 330 in the second direction D2. Figure 3A In the cross-sectional view of FIG. 3 , the width of the internal structure 310 and the width of the first circuit structure 320 are both greater than the width of the second circuit structure 330. In addition, the plurality of first pads 322 are arranged from the side wall SW1 of the second circuit structure 330 in the opposite direction of the second direction D2, such as Figure 3A shown.

[0046] Please refer to Figure 3A and Figure 3B The first external circuit structure 340 is formed on the first circuit structure 320, and the second external circuit structure 350 is formed on the second circuit structure 330. A solder mask 345 is formed on the first external circuit structure 340, and a solder mask 355 is formed on the second external circuit structure 350.

[0047] Please refer to Figure 3B, the first external circuit structure 340 includes an adhesive layer 342. The first external circuit structure 340 is disposed on the first circuit structure 320 through the adhesive layer 342. The first external circuit structure 340 does not cover the first pads 322 of the first circuit structure 320. The first circuit structure 320 protrudes from the sidewall SW2 of the first external circuit structure 340 in the second direction D2. In other words, Figure 3B In the cross-sectional schematic diagram of , the width of the first circuit structure 320 is greater than the width of the first external circuit structure 340.

[0048] The second external circuit structure 350 includes an adhesive layer 352. The second external circuit structure 350 is disposed on the second circuit structure 330 through the adhesive layer 352. The second external circuit structure 350 also includes an opening 354, and the opening exposes a plurality of second pads 332. The first circuit structure 320 protrudes from the sidewall SW3 of the second external circuit structure 350 in the second direction D2. In other words, Figure 3B In the cross-sectional view of FIG. 3 , the width of the first circuit structure 320 is greater than the width of the second outer circuit structure 350 . In some embodiments, the sidewall SW3 of the second outer circuit structure 350 is flush with the sidewall SW1 of the second circuit structure 330 .

[0049] Please refer to Figure 3B and Figure 3C , the first pad 322 and the second pad 332 are surface treated to form a surface treatment layer 360. The surface treatment layer 360 is used to prevent the first pad 322 and the second pad 332 from being oxidized due to exposure to air, thereby affecting their electrical properties. In detail, the surface treatment layer 360 is formed on the top surface and side surface of the first top 322t of the first pad 322 and the second top 332t of the second pad 332, respectively. In some embodiments, the material of the surface treatment layer 360 may include gold, nickel-plated gold, or nickel-palladium gold, but is not limited thereto. In some embodiments, the surface treatment layer 360 may be formed by an electroplating process.

[0050] Please refer to Figure 3C and Figure 3D The flexible printed circuit board 370 is formed on the first pads 322 of the first circuit structure 320, and the electronic component 380 is formed on the second pads 332. In other words, the electronic component 380 is disposed in the opening 354 of the second external circuit structure 350 (see Figure 3B )middle.

[0051] In some embodiments, the flexible circuit substrate 370 may be pressed onto the first pad 322 via an anisotropic conductive film (ACF) 374 , and the pad 372 of the flexible circuit substrate 370 may be electrically connected to the first pad 322 via conductive particles in the ACF.

[0052] In some embodiments, the pad 382 of the electronic component 380 can be electrically connected to the plurality of second pads 332 through a conductive paste 384. The conductive paste 384 can be, for example, copper paste or tin paste, but is not limited thereto. The electronic component 380 can be, for example, an integrated circuit component, but is not limited thereto.

[0053] In summary, the pads in the circuit board of the present invention are formed with a wider top by electroplating. The wider top can increase the surface contact area between the pads of the circuit board and the pads of the display (or electronic component), so that the pad connection capability can still be maintained well when the spacing between the pads is reduced.

[0054] The features of multiple embodiments are summarized above so that those skilled in the art can better understand the aspects of the present application. Those skilled in the art should understand that the present application can be easily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present application, and various changes, substitutions and modifications of the present application can be made without departing from the spirit and scope of the present application.

[0055]

Explanation of symbols

[0056] 100: Circuit board

[0057] 110: Substrate

[0058] 120: First mask layer

[0059] 130: Initial circuit layer

[0060] 130a: Circuit layer

[0061] 132: Initial pad

[0062] 132a: pad

[0063] 132at: Top

[0064] 132ab: bottom

[0065] 132s1: Top surface

[0066] 132s2: Bottom surface

[0067] 133: Top surface

[0068] 134: Routing

[0069] 134s1: Top surface

[0070] 134s2: Bottom surface

[0071] 136: Gap

[0072] 137: Side surface

[0073] 140: Initial dielectric material

[0074] 140a: Dielectric materials

[0075] 150: Second mask layer

[0076] 152: Opening

[0077] 300: Circuit board

[0078] 310: Internal structure

[0079] 312: Core layer

[0080] 314: Adhesive layer

[0081] 320: First line structure

[0082] 322: First pad

[0083] 322t: First Top

[0084] 322b: First bottom

[0085] 330: Second line structure

[0086] 332: Second pad

[0087] 332t: Second top

[0088] 332b: Second bottom

[0089] 340: First external line structure

[0090] 342: Adhesive layer

[0091] 345: Solder mask

[0092] 350: Second external line structure

[0093] 352: Adhesive layer

[0094] 354: Opening

[0095] 355: Solder mask

[0096] 360: Surface treatment layer

[0097] 370: Flexible circuit board

[0098] 372: Pad

[0099] 374: Anisotropic conductive film

[0100] 380: Electronic components

[0101] 382: Pad

[0102] 384: Conductive paste

[0103] D1: First direction

[0104] D2: Second direction

[0105] W1, W2: Width

[0106] SW1, SW2, SW3: side walls.

Claims

1. A circuit board, characterized in that: Include: First line structure; a second circuit structure; and an internal structure disposed between the first circuit structure and the second circuit structure, wherein the first circuit structure, the second circuit structure and the internal structure are stacked in a first direction, wherein the internal structure and the first circuit structure protrude from the side wall of the second circuit structure in a second direction perpendicular to the first direction, The first circuit structure includes a plurality of first pads, and the plurality of first pads protrude from the sidewall of the second circuit structure in the second direction, wherein each of the plurality of first pads has a first top and a first bottom, and the width of the first top is greater than the width of the first bottom.

2. The circuit board according to claim 1, wherein: Also includes: The flexible circuit substrate is disposed on the plurality of first pads. 3 . The circuit board according to claim 2 , wherein a top surface of the first top portion of each of the plurality of first pads is a curved surface or a flat surface.

4. The circuit board according to claim 1, wherein: Also includes: The first external circuit structure is disposed on the first circuit structure, wherein the first circuit structure protrudes from a side wall of the first external circuit structure in the second direction. 5 . The circuit board according to claim 1 , wherein the second circuit structure comprises a plurality of second pads, wherein each of the plurality of second pads has a second top portion and a second bottom portion, and a width of the second top portion is greater than a width of the second bottom portion.

6. The circuit board according to claim 5, wherein: Also includes: The electronic component is disposed on the plurality of second pads.

7. The circuit board according to claim 6, wherein: Also includes: The second external circuit structure is disposed on the second circuit structure, wherein the second external circuit structure comprises an opening, and the electronic component is disposed in the opening.

8. A method for manufacturing a circuit board, characterized in that: Include: providing a substrate; forming a first mask layer on the substrate; Using the first mask layer as a mask, electroplating the substrate to form an initial circuit layer on the substrate, wherein the initial circuit layer includes a plurality of initial pads and a plurality of routing lines, and a plurality of gaps are formed between the plurality of initial pads and the plurality of routing lines; filling the plurality of gaps with a dielectric material; forming a second mask layer on the initial circuit layer and the dielectric material, wherein the second mask layer covers the wiring and exposes the plurality of initial pads; Using the second mask layer as a mask, electroplating the plurality of initial pads to form a plurality of pads, wherein each of the plurality of pads has a top and a bottom, and the width of the top is greater than the width of the bottom; as well as Remove the second mask layer.

9. The method for manufacturing a circuit board according to claim 8, wherein the step of filling the plurality of gaps with the dielectric material comprises: forming an initial dielectric material to fill the plurality of gaps and cover a top surface of the initial wiring layer; and A portion of the initial dielectric material covering the top surface of the initial circuit layer is removed to expose the top surface of the initial circuit layer.

10. The method for manufacturing a circuit board according to claim 8, wherein: Also includes: After electroplating the plurality of initial pads, forming a third mask layer to cover the pads; and The substrate is removed using the third mask layer as a mask to expose the plurality of pads.

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