Semiconductor device

Abstract

A semiconductor device may include a lower wiring structure on a substrate, the lower wiring structure including a plurality of wirings. The plurality of wirings includes: a first wiring group having a first stacked structure including a metal pattern and a barrier metal pattern constituting a contact plug and a conductive pattern, and the barrier metal pattern surrounding a lower surface of the metal pattern; and a second wiring group having a second stacked structure different from the first stacked structure, the second stacked structure including a lower metal pattern constituting the contact plug and a lower barrier metal pattern surrounding a lower surface of the lower metal pattern, and an upper metal pattern constituting a conductive pattern, the upper metal pattern having a lower resistance than the lower metal pattern.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to semiconductor devices, and in particular, to semiconductor devices including vertical channel transistors. Background Art

[0002] Recently, semiconductor devices are manufactured in a highly integrated manner. Therefore, in order to achieve high integration, the semiconductor device may include a vertical channel transistor including a channel provided in a vertical direction perpendicular to the substrate surface. The semiconductor device may include wiring for electrically connecting a memory cell to a core / peripheral circuit. Summary of the invention

[0003] Example embodiments provide a semiconductor device including a vertical channel transistor and a wiring structure.

[0004] According to one aspect of the present invention, a semiconductor device is provided, which includes: a first wiring structure on a substrate, the first wiring structure including a plurality of wirings, each of the plurality of wirings including a contact plug and a conductive pattern stacked in a vertical direction perpendicular to a surface of the substrate; and a unit structure provided on the uppermost conductive pattern in the first wiring structure, the unit structure including a vertical channel transistor connected to the conductive pattern, wherein the plurality of wirings of the first wiring structure include: a first wiring group including one or more first wirings having a first stacking structure among the plurality of wirings, the first stacking structure including a metal pattern and a barrier metal pattern constituting a contact plug and a conductive pattern, and the barrier metal pattern surrounding a lower surface of the metal pattern; and a second wiring group including one or more second wirings having a second stacking structure different from the first stacking structure among the plurality of wirings, the second stacking structure including a lower metal pattern constituting a contact plug and a lower barrier metal pattern surrounding a lower surface of the lower metal pattern, and an upper metal pattern constituting a conductive pattern, the upper metal pattern having a lower resistance than the lower metal pattern.

[0005] According to another aspect of the present invention, a semiconductor device is provided, which includes: a first wiring structure on a substrate, the first wiring structure including a plurality of wirings, each of the plurality of wirings including a contact plug and a conductive pattern stacked in a vertical direction perpendicular to a surface of the substrate; a channel pattern provided on the first wiring structure, the channel pattern including two or more side walls extending in a vertical direction and a lower surface connecting lower portions of two opposite side walls among the two or more side walls in a horizontal direction, the lower surface of the channel pattern contacting the uppermost conductive pattern in the first wiring structure; a gate insulating layer pattern and a word line pattern, stacked laterally on an inner wall of the channel pattern; and a capacitor connected to the channel pattern. The upper surface of the channel pattern, wherein the multiple wirings of the first wiring structure include: a first wiring group, including one or more first wirings with a first stacking structure among the multiple wirings, the first stacking structure including a metal pattern and a barrier metal pattern constituting a contact plug and a conductive pattern, the barrier metal pattern surrounding the lower surface of the metal pattern; and a second wiring group, including one or more second wirings with a second stacking structure different from the first stacking structure among the multiple wirings, the second stacking structure including a lower metal pattern constituting a contact plug and a lower barrier metal pattern surrounding the lower surface of the lower metal pattern, and an upper metal pattern constituting a conductive pattern, the upper metal pattern being formed by a physical vapor deposition process.

[0006] According to another aspect of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a peripheral circuit structure comprising a plurality of peripheral circuits provided on a substrate; a first wiring structure comprising a plurality of wirings connected to the plurality of peripheral circuit structures, each of the plurality of wirings comprising a contact plug and a conductive pattern stacked in a vertical direction perpendicular to a surface of the substrate, the uppermost conductive pattern in the first wiring structure having a line shape extending in a first direction parallel to the surface of the substrate; a channel pattern provided on the first wiring structure, the channel pattern comprising two or more side walls extending in the vertical direction and a lower surface connecting lower portions of two opposite side walls among the two or more side walls in a horizontal direction, the channel patterns being regularly arranged in a first direction and in a second direction perpendicular to the first direction, the lower surface of the channel pattern contacting the uppermost conductive pattern in the first wiring structure; a word line pattern formed laterally on the channel pattern on an inner wall of the channel pattern, the word line pattern extending in the second direction; a gate insulating layer pattern between the channel pattern and the word line pattern, the gate insulating layer pattern extending in the second direction; and a capacitor connected to the upper surface of the channel pattern, wherein the multiple wirings of the first wiring structure include: a first wiring group, including one or more first wirings having a first stacking structure among the multiple wirings, the first stacking structure including a metal pattern and a barrier metal pattern constituting a contact plug and a conductive pattern, the barrier metal pattern surrounding the lower surface of the metal pattern; and a second wiring group, including one or more second wirings having a second stacking structure different from the first stacking structure among the multiple wirings, the second stacking structure including a lower metal pattern formed by a chemical vapor deposition process constituting a contact plug and a lower barrier metal pattern surrounding the lower surface of the lower metal pattern, and an upper metal pattern formed by a physical vapor deposition process constituting a conductive pattern.

[0007] In the semiconductor device according to example embodiments, the lower wiring structure may include at least one first group wiring and at least one second group wiring. Therefore, the lower wiring structure may have low resistance, and electrical characteristics of the semiconductor device may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 29 represents non-limiting example embodiments as described herein.

[0009] Figure 1 is a block diagram of a semiconductor device according to an example embodiment;

[0010] Figure 2 is a perspective view schematically illustrating a semiconductor device according to an example embodiment;

[0011] Figure 3is a cross-sectional view of a semiconductor device according to an example embodiment;

[0012] Figure 4 is a plan view of a unit structure in a semiconductor device according to an example embodiment;

[0013] Figure 5 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to an example embodiment;

[0014] Figure 6 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to an example embodiment;

[0015] Figure 7 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to an example embodiment;

[0016] Figure 8 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to an example embodiment;

[0017] Figures 9 to 27 is a cross-sectional view of a stage in a method of manufacturing a semiconductor device according to an example embodiment;

[0018] Fig.28 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to an example embodiment; and

[0019] Fig.29 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0020] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0021] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be apparent. For example, the order of operations described herein is only an example, and is not limited to those set forth herein, but can be changed as will be apparent after understanding the disclosure of the application, except for the operations that must occur in a specific order. In addition, for improved clarity and conciseness, the description of the features known after understanding the disclosure of the application can be omitted.

[0022] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways (which will be apparent after understanding the disclosure of this application) of implementing the methods, devices and / or systems described herein.

[0023] Throughout the specification, when a component is described as being "connected to" or "coupled to" another component, it may be directly "connected to" or "coupled to" the other component, or one or more other components may be present in between. Conversely, when an element is described as being "directly connected to" or "directly coupled to" another element, there may be no other elements in between. Similarly, similar expressions, for example, "between" and "immediately between" and "adjacent to" and "immediately adjacent to" should also be interpreted in the same manner. As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more.

[0024] Although terms such as "first", "second", and "third" may be used herein to describe various members, components, regions, layers, or parts, these members, components, regions, layers, or parts are not limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or part from another member, component, region, layer, or part. Therefore, without departing from the teachings of the examples described herein, the first member, component, region, layer, or part mentioned in the examples may also be referred to as the second member, component, region, layer, or part.

[0025] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are also intended to include plural forms. The terms "comprise", "include" and "have" indicate the presence of stated features, numbers, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or combinations thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs based on an understanding of the disclosure of the present application. Terms, such as those defined in commonly used dictionaries, will be interpreted as having a meaning consistent with their meaning in the context of the relevant art and in the disclosure of the present application, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein. The use of the term "may" here with respect to an example or implementation (e.g., with respect to what an example or implementation may include or implement) means that there is at least one example or implementation in the case of including or implementing such a feature, while all example implementations are not limited thereto.

[0027] Hereinafter, the direction parallel to the substrate surface is referred to as the first direction, and the direction parallel to the substrate surface and perpendicular to the first direction is referred to as the second direction. In addition, the direction perpendicular to the substrate surface is referred to as the vertical direction.

[0028] Figure 1 is a block diagram of a semiconductor device according to example embodiments.

[0029] Reference Figure 1 , a semiconductor device may include a memory cell array 1 , a row decoder 2 , a sense amplifier 3 , a column decoder 4 , and a control logic 5 .

[0030] The memory cell array 1 may include a plurality of memory cells MC. Each memory cell MC may be located at a cross point of a word line WL and a bit line BL, and may be connected to one of the word lines WL and one of the bit lines BL.

[0031] The unit memory cell MC may include a transistor TR and a capacitor C. A gate electrode included in the transistor TR may extend in a direction parallel to the upper surface of the substrate 100 and may serve as a word line WL. A drain region of the transistor TR may be electrically connected to the bit line BL, and a source region of the transistor TR may be electrically connected to the capacitor C.

[0032] The row decoder 2 may decode an input address and may select one of the word lines WL in the memory cell array 1. The address decoded in the row decoder 2 may be provided to a row driver. The row driver may apply predetermined voltages to the selected word line WL and the unselected word line WL, respectively, based on a signal of the control logic 5.

[0033] The sense amplifier 3 may detect and amplify a voltage difference between a selected bit line BL and a reference bit line according to an address decoded in the column decoder 4 , and may output the amplified voltage difference between the selected bit line BL and the reference bit line.

[0034] The column decoder 4 may be a data transmission path between the sense amplifier 3 and an external device (eg, a memory controller). The column decoder 4 may decode an external input address and thus may select one of the bit lines BL.

[0035] The control logic 5 may generate a control signal for writing data into the memory cell array 1 or reading data from the memory cell array 1. According to an embodiment, the control logic 5 may be implemented as a control logic circuit.

[0036] Figure 2 is a perspective view schematically illustrating a semiconductor device according to example embodiments.

[0037] Reference Figure 2 , the peripheral circuit structure 10, the lower wiring structure 20, and the unit structure 30 may be sequentially stacked on the semiconductor substrate 100. A wiring structure 22 electrically connected to the lower wiring structure 20 may be further provided outside the unit structure 30.

[0038] The peripheral circuit structure 10 may include a core circuit and a peripheral circuit formed on the semiconductor substrate 100. The core circuit and the peripheral circuit may include Figure 1 A row decoder 2, a column decoder 4, a sense amplifier 3 and a control logic 5 are shown.

[0039] The cell structure 30 may be provided on the peripheral circuit structure 10. The cell structure 30 may include a memory cell MC ( Figure 1 ). The memory cells may be arranged on a plane extending along the first direction and the second direction. Each memory cell MC may include a transistor TR and a capacitor C, such as Figure 1 shown.

[0040] The transistor included in each memory cell may include a vertical channel transistor (VCT). The vertical channel transistor may include a channel pattern extending in a vertical direction.

[0041] The lower wiring structure 20 may be provided between the peripheral circuit structure 10 and the cell structure 30 in a vertical direction. The lower wiring structure 20 may electrically connect the peripheral circuit structure 10 and the cell structure 30.

[0042] In example embodiments, the bit line may be located below a channel pattern of the vertical channel transistor. The word line may be located on a sidewall of the channel pattern of the vertical channel transistor.

[0043] The sense amplifier on the substrate 100 may be electrically connected to the bit line. In example embodiments, the sense amplifier and the bit line may be electrically connected through a portion of the lower wiring structure 20 on the substrate 100. In example embodiments, the uppermost conductive pattern included in the lower wiring structure 20 may serve as a bit line, and thus the lower wiring structure 20 may include a bit line.

[0044] In an example embodiment, a wiring structure is formed on the substrate 100, and the wiring structure may be electrically connected to a word line. Therefore, the wiring structure may be electrically connected to a peripheral circuit structure 10 of a row driver corresponding to a row decoder via a word line. In addition, a wiring structure connected to a control logic may be further formed on the substrate 100. In an example embodiment, at least one of the wiring structures may be provided outside the cell structure 30. According to an example embodiment, at least one of the wiring structures may not overlap with the cell structure 30 in a vertical direction.

[0045] As described above, the arrangement of the lower wiring structure 20 for connecting the peripheral circuit structure 10 and the memory cell may be complicated. Therefore, the lower wiring structure 20 may not be composed of a single-layer wiring, but the lower wiring structure 20 may be composed of a multi-layer wiring. In addition, the lower wiring structure 20 may be designed to have a low resistance.

[0046] Figure 3 is a cross-sectional view of a semiconductor device according to example embodiments. Figure 4 is a plan view of a unit structure in a semiconductor device according to example embodiments. Figure 5 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to example embodiments.

[0047] Figure 3 The semiconductor device shown may be a DRAM device. However, the present disclosure is not limited thereto, and as such, the semiconductor device may be another type of electronic device. Figure 3 Shown along Figure 4 The bit line intercepted by the line AA' and the cell structure provided on the bit line. Figure 4 In the figure, the capacitor and the elements formed on the capacitor are omitted to avoid complexity of the drawing.

[0048] according to Figures 3 to 5 In the example embodiment shown, the semiconductor device may include a peripheral circuit structure on a substrate 100. The peripheral circuit structure may include a peripheral transistor 110 constituting a peripheral circuit. The peripheral transistor 110 may include an NMOS transistor and a PMOS transistor. The peripheral transistor 110 may be a planar transistor. Figure 3 Only one peripheral transistor 110 is provided on the substrate 100 , but a plurality of peripheral transistors constituting a peripheral circuit may be provided on the substrate 100 .

[0049] According to example embodiments, a trench 102 may be formed on a substrate 100, and an isolation pattern 104 may be filled in the trench 102. A peripheral transistor 110 may be formed on the isolation pattern 104 and the substrate 100. The peripheral transistor 110 may include a lower gate structure and an impurity region. The lower gate structure may include a lower gate insulating layer, a lower gate electrode, and a hard mask pattern. The lower gate insulating layer, the lower gate electrode, and the hard mask pattern may be arranged in a stack. The impurity region may be formed at an upper portion of the substrate 100 adjacent to both sides of the lower gate structure.

[0050] The lower wiring structure may be provided on the peripheral circuit structure. The lower wiring structure may have a structure in which the wiring is stacked into a plurality of layers. For example, the lower wiring structure may include a first wiring 124, a second wiring 144, a third wiring 164, and a fourth wiring 184. However, the present disclosure is not limited to four wirings, so that, according to another embodiment, the lower wiring structure may include a plurality of wirings different from four. Each wiring included in the lower wiring structure may include a contact plug and a conductive pattern. Hereinafter, a lower wiring structure including the first to fourth wirings 124, 144, 164, and 184 may be described.

[0051] According to example embodiments, a first lower insulating interlayer 112 may be provided on the substrate 100. For example, the first lower insulating interlayer 112 may be provided on the peripheral transistor 110. For example, the first lower insulating interlayer 112 may be provided to cover the peripheral transistor 110 on the substrate 100. The first lower insulating interlayer 112 may include silicon oxide. However, the present disclosure is not limited thereto.

[0052] The first contact hole 114 may pass through the first lower insulating interlayer 112. The first contact hole 114 may pass through the first lower insulating interlayer 112 and contact the substrate 100. The first contact hole 114 may expose the impurity region of the peripheral transistor 110. The first contact hole 114 may also expose the upper surface of the substrate 100. The first wiring 124 may be provided on the first lower insulating interlayer 112. In addition, the first wiring 124 may be provided in the first contact hole 114, as such, the first wiring 124 may fill the first contact hole 114. The first wiring 124 may be the lowermost wiring that directly contacts the substrate 100.

[0053] The first wiring 124 may include a first contact plug C1 and a first conductive pattern L1. The first contact plug C1 may fill the first contact hole 114. The first conductive pattern L1 may be provided on the first contact plug C1 and the first lower insulating interlayer 112 and may be connected to the first contact plug C1. The first conductive pattern L1 may be in direct contact with the first contact plug C1. The first conductive pattern L1 may extend in a direction parallel to the upper surface of the substrate 100. For example, the first conductive pattern L1 may extend in one of the first direction and the second direction.

[0054] In example embodiments, a metal silicide pattern 116 may be further included between the first contact plug C1 and the substrate 100 .

[0055] The first wiring 124 may include a first barrier metal pattern 120a and a first metal pattern 122a provided on the first barrier metal pattern. The first barrier metal pattern 120a may be provided along the inner surface of the first contact hole 114 and the upper surface of the first lower insulating interlayer 112. The first metal pattern 122a may be provided in the first contact hole 114. For example, the first metal pattern 122a may fill the first contact hole 114.

[0056] The first metal pattern 122a may contact the entire upper surface of the first barrier metal pattern 120a. However, the present disclosure is not limited thereto, and as such, according to another embodiment, the first metal pattern 122a may contact at least a portion of the upper surface of the first barrier metal pattern 120a. According to an embodiment, the first contact plug C1 and the first conductive pattern L1 may include a first metal pattern 122a having one body. As such, an obvious connection portion (e.g., an interface) may not be provided between the first contact plug C1 and the first conductive pattern L1. That is, the first contact plug C1 and the first conductive pattern L1 including the first metal pattern 122a may be formed as a single-piece structure. The first barrier metal pattern 120a may be provided on the bottom of the first metal pattern 122a and may contact the bottom of the first metal pattern 122a.

[0057] Hereinafter, in each wiring including a contact plug and a conductive pattern, the first stacked structure may include a barrier metal pattern constituting the contact plug and the conductive pattern and a metal pattern having one body (ie, a single-piece structure). Figure 5 As shown, in the first stacked structure S1, the barrier metal pattern may surround the lower surface of the metal pattern. In the first stacked structure S1, the barrier metal pattern may extend to the surface of the contact hole and the upper surface of the lower insulating interlayer, and the connection portion between the contact plug and the conductive pattern is formed as the metal pattern having the one body. In the first stacked structure S1, the barrier metal pattern may be formed on the lower surface of the metal pattern and may contact the lower surface of the metal pattern.

[0058] In example embodiments, the first wiring 124 , which is a lowermost wiring directly contacting the substrate 100 , may have a first stack structure S1 .

[0059] The barrier metal pattern and the metal pattern included in the wiring having the first stacked structure S1 may be formed by a chemical vapor deposition process. The barrier metal pattern included in the wiring having the first stacked structure S1 may include but is not limited to titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, tungsten carbonitride, or the like.

[0060] The metal pattern included in the wiring having the first stacked structure S1 may include a metal material that can be patterned by an etching process and has a low thermal budget in a process for forming a cell structure thereon. The metal pattern included in the wiring having the first stacked structure S1 may include, but is not limited to, tungsten or aluminum. For example, the metal pattern included in the wiring having the first stacked structure S1 may include tungsten formed by a chemical vapor deposition process.

[0061] In example embodiments, a first etch stop layer 130 may be provided on the first lower insulating interlayer 112 and the first wiring 124. For example, the first etch stop layer 130 may conform to upper surfaces of the first lower insulating interlayer 112 and the first wiring 124 and cover surfaces of the first lower insulating interlayer 112 and the first wiring 124. The first etch stop layer 130 may include, but is not limited to, silicon nitride.

[0062] In example embodiments, a second lower insulating interlayer 132 and a third lower insulating interlayer 134 may be formed on the first etch stop layer 130. In example embodiments, the second lower insulating interlayer 132 may fill the gap between the first conductive patterns L1. The third lower insulating interlayer 134 may be provided on the second lower insulating interlayer 132 and the first etch stop layer 130.

[0063] The second lower insulating interlayer 132 may include silicon oxide. The third lower insulating interlayer 134 may include silicon nitride. However, the material included in each of the second lower insulating interlayer 132 and the third lower insulating interlayer 134 may not be limited thereto. For example, the second lower insulating interlayer 132 and the third lower insulating interlayer 134 may include the same material. In addition, the second lower insulating interlayer 132 and the third lower insulating interlayer 134 may include a material other than silicon oxide or silicon nitride.

[0064] In example embodiments, the second contact hole 136 may pass through the third lower insulating interlayer 134 and may expose an upper surface of the first wiring 124. A second wiring 144 may be provided on the third lower insulating interlayer 134 and fill the second contact hole 136.

[0065] The second wiring 144 may include a second contact plug C2 and a second conductive pattern L2. The second contact plug C2 may be provided in the second contact hole 136. The second contact plug C2 may fill the second contact hole 136. The second conductive pattern L2 may be provided on the second contact plug C2 and the third lower insulating interlayer 134 and may be electrically connected to the second contact plug C2. The second conductive pattern L2 may extend in a direction parallel to the upper surface of the substrate 100.

[0066] In example embodiments, the second wiring 144 may include a second barrier metal pattern 140a and a second metal pattern 142a provided on the second barrier metal pattern 140a. The second barrier metal pattern 140a may be formed along the inner surface of the second contact hole 136 and the upper surface of the third lower insulating interlayer 134. The second metal pattern 142a may be provided in the second contact hole 136. The second metal pattern 142a may fill the second contact hole 136, and the upper surface of the second metal pattern 142a may be located above the third lower insulating interlayer 134. In this case, the second wiring 144 may have a first stacked structure S1.

[0067] In example embodiments, a second etch stop layer 150 may be provided on the third lower insulating interlayer 134 and the second wiring 144. For example, the second etch stop layer 150 may conformally cover surfaces of the third lower insulating interlayer 134 and the second wiring 144. The second etch stop layer 150 may include, but is not limited to, silicon nitride.

[0068] In example embodiments, a fourth lower insulating interlayer 152 and a fifth lower insulating interlayer 154 may be formed on the second etch stop layer 150. In example embodiments, the fourth lower insulating interlayer 152 may fill the gap between the second conductive patterns L2. The fifth lower insulating interlayer 154 may be provided on the fourth lower insulating interlayer 152 and the second etch stop layer 150.

[0069] The fourth lower insulating interlayer 152 may include silicon oxide, and the fifth lower insulating interlayer 154 may include silicon nitride. However, the materials included in the fourth lower insulating interlayer 152 and the fifth lower insulating interlayer 154 may not be limited thereto. For example, the fourth lower insulating interlayer 152 and the fifth lower insulating interlayer 154 may include the same material. In addition, the fourth lower insulating interlayer 152 and the fifth lower insulating interlayer 154 may include a material other than silicon oxide or silicon nitride.

[0070] In example embodiments, the third contact hole 156 may pass through the fifth lower insulating interlayer 154 and may expose an upper surface of the second wiring 144. A third wiring 164 may be provided on the fifth lower insulating interlayer 154 and fill the third contact hole 156.

[0071] The third wiring 164 may include a third contact plug C3 and a third conductive pattern L3. The third contact plug C3 may be provided in the third contact hole 156. The third contact plug C3 may fill the third contact hole 156. The third conductive pattern L3 may be formed on the third contact plug C3 and the fifth lower insulating interlayer 154 and may be electrically connected to the third contact plug C3. The third conductive pattern L3 may extend in a direction parallel to the upper surface of the substrate 100.

[0072] The third contact plug C3 includes a third barrier metal pattern 160a and a third metal pattern 162a provided on the third barrier metal pattern 160a. The third barrier metal pattern 160a may be formed along the inner surface of the third contact hole 156. The third metal pattern 162a may be provided in the third contact hole 156. The third metal pattern 162a may fill the third contact hole 156. In an embodiment, the upper surface of the third metal pattern 162a and the upper surface of the fifth lower insulating interlayer 154 may be at the same level. However, the present disclosure is not limited thereto, and as such, according to another embodiment, the upper surface of the third metal pattern 162a may be located above the fifth lower insulating interlayer 154 or below the fifth lower insulating interlayer 154.

[0073] The third conductive pattern L3 may include a fourth metal pattern 166a. The fourth metal pattern 166a may be independent and / or distinct from the third metal pattern 162a. For example, the fourth metal pattern 166a may have a lower resistance than the third metal pattern 162a.

[0074] In the third wiring 164, the third barrier metal pattern 160a may be only on the sidewall and the bottom of the third contact hole 156. The third barrier metal pattern 160a may not be formed on the upper surface of the fifth lower insulating interlayer 154. In addition, a connection portion (e.g., an interface) between the third metal pattern 162a included in the third contact plug C3 and the fourth metal pattern 166a used as the third conductive pattern L3 may be generated. That is, the connection portion between the third metal pattern 162a and the fourth metal pattern 166a may be distinguished. For example, the third metal pattern 162a and the fourth metal pattern 166a may be independent and / or different from each other. For example, the third metal pattern 162a and the fourth metal pattern 166a may be formed as a two-piece structure.

[0075] like Figure 5 As shown, in the wiring including the contact plug and the conductive pattern, the second stacked structure S2 may include a lower metal pattern and a barrier metal pattern surrounding the lower surface of the lower metal pattern constituting the contact plug, and an upper metal pattern constituting the conductive pattern. In the second stacked structure S2, the barrier metal pattern may be formed only on the surface of the contact hole, and the connection portion between the contact plug and the conductive pattern may be distinguished. For example, the contact plug and the conductive pattern may be independent and / or distinct from each other. For example, the contact plug and the conductive pattern may be formed as a two-piece structure. The third wiring 164 may have a second stacked structure S2. In the second stacked structure S2, the material of the conductive pattern may have a lower resistance than the resistance of the material of the contact plug.

[0076] In the case where the wiring has the second stack structure S2 , the lower metal pattern included in the contact plug and the upper metal pattern included in the conductive pattern may be formed through different deposition processes.

[0077] The lower metal pattern included in the contact plug may be formed by a deposition process having excellent gap filling characteristics, and the upper metal pattern included in the conductive pattern may be formed by a deposition process for depositing a material having high purity and low resistance. In the case where the wiring has the second stacking structure S2, the upper metal pattern included in the conductive pattern may be formed by a physical vapor deposition process. In addition, in the case where the wiring has the second stacking structure S2, the lower metal pattern included in the contact plug may be formed by a chemical vapor deposition process. The wiring having the second stacking structure S2 may include a metal material formed by a physical vapor deposition process.

[0078] In the wiring having the second stacked structure S2, the barrier metal pattern included in the contact plug may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, tungsten nitride, or the like. The upper metal pattern and the lower metal pattern included in the wiring having the second stacked structure S2 may include a material that can be patterned by an etching process and has a low thermal budget in a process for forming a cell structure thereon. For example, the upper metal pattern and the lower metal pattern included in the wiring having the second stacked structure S2 may include tungsten or aluminum.

[0079] For example, in the wiring having the second stack structure S2 , the lower metal pattern included in the contact plug may include tungsten formed by a chemical vapor deposition process, and the upper metal pattern included in the conductive pattern may include tungsten formed by physical vapor deposition.

[0080] In example embodiments, in the wiring having the second stacked structure S2, the lower metal pattern included in the contact plug and the upper metal pattern included in the conductive pattern may include the same material. In this case, the lower metal pattern included in the contact plug and the upper metal pattern included in the conductive pattern may have different grain sizes because the lower metal pattern included in the contact plug and the upper metal pattern included in the conductive pattern are formed by different deposition processes. For example, in an example case where the upper metal pattern and the lower metal pattern include tungsten, the tungsten included in the contact plug may have a grain size larger than that of the tungsten included in the conductive pattern.

[0081] In example embodiments, in the wiring having the second stack structure S2 , the lower metal pattern included in the contact plug and the upper metal pattern included in the conductive pattern may include different materials.

[0082] In the example case where the wiring having the second stacking structure S2 and the wiring having the first stacking structure S1 include the same metal material (e.g., tungsten), the wiring having the second stacking structure S2 including the metal formed by a physical vapor deposition process may have a lower resistance than the wiring having the first stacking structure S1 including the metal formed only by a chemical vapor deposition process. The multilayer interconnect structure may include the wiring having the second stacking structure S2, so that the total resistance of the multilayer interconnect structure may be reduced.

[0083] In example embodiments, a third etch stop layer 170 may be provided on the fifth lower insulating interlayer 154 and the third wiring 164. For example, the third etch stop layer 170 may conformally cover surfaces of the fifth lower insulating interlayer 154 and the third wiring 164. A sixth lower insulating interlayer 172 and a seventh lower insulating interlayer 174 may be formed on the third etch stop layer 170. The sixth lower insulating interlayer 172 and the seventh lower insulating interlayer 174 may have structures similar to those of the fourth lower insulating interlayer 152 and the fifth lower insulating interlayer 154, respectively.

[0084] The fourth contact hole 176 may pass through the seventh lower insulating interlayer 174 and may expose an upper surface of the third wiring 164. A fourth wiring 184 may be provided on the seventh lower insulating interlayer 174 to fill the fourth contact hole 176.

[0085] The fourth wiring 184 may include a fourth contact plug C4 and a fourth conductive pattern. The fourth contact plug C4 may be provided in the fourth contact hole 176. For example, the fourth contact plug C4 may fill the fourth contact hole 176. The fourth conductive pattern L4 may be formed on the fourth contact plug C4 and the seventh lower insulating interlayer 174 and may be electrically connected to the fourth contact plug C4. The fourth conductive pattern L4 may extend in a direction parallel to the upper surface of the substrate 100.

[0086] The fourth wiring 184 may include a fourth barrier metal pattern 180a and a fifth metal pattern 182a provided on the fourth barrier metal pattern 180a. The fourth barrier metal pattern 180a may be formed along the inner surface of the fourth contact hole 176 and the upper surface of the seventh lower insulating interlayer 174. The fifth metal pattern 182a may be provided in the fourth contact hole 176. The fifth metal pattern 182a may fill the fourth contact hole 176. The upper surface of the fifth metal pattern 182a may be located above the seventh lower insulating interlayer 174. The fourth wiring 184 may have a first stacked structure S1.

[0087] The fourth wiring 184 may be the uppermost wiring of the lower wiring structure formed below the cell structure. Some conductive patterns (e.g., the fourth conductive pattern) included in the uppermost wiring may be used as a bit line. The fourth conductive pattern L4 located in the memory cell region may be used as a bit line. Hereinafter, the fourth conductive pattern L4 may also be referred to as a bit line. The bit line L4 may extend in the first direction. The bit lines L4 may be spaced apart from each other in the second direction.

[0088] In example embodiments, a fourth etch stop layer pattern 190a may be provided on the seventh lower insulating interlayer 174 and the fourth wiring 184. For example, the fourth etch stop layer pattern 190a may conformally cover the surfaces of the seventh lower insulating interlayer 174 and the fourth wiring 184. An eighth lower insulating interlayer 192 may be formed on the fourth etch stop layer pattern 190a to fill the gap between the bit lines L4. An upper surface of the eighth lower insulating interlayer 192 and an upper surface of the fourth etch stop layer pattern 190a on the bit line L4 may be coplanar with each other. The fourth etch stop layer pattern 190a may include silicon nitride, and the eighth lower insulating interlayer 192 may include silicon oxide.

[0089] As described above, the lower wiring structure may include multi-layer wirings, and some conductive patterns included in the uppermost wirings may be used as bit lines. At least one wiring included in the lower wiring structure may have a second stacking structure S2. At least one wiring included in the lower wiring structure may have a first stacking structure S1.

[0090] Since the wiring having the second stacking structure S2 has a lower resistance than the wiring having the first stacking structure S1, the total resistance of the multilayer interconnect structure (e.g., the lower wiring structure) including the wiring having the second stacking structure S2 can be reduced. Since the process for forming the wiring having the second stacking structure S2 is more complicated than the process for forming the wiring having the first stacking structure S1, the wiring having the second stacking structure S2 can be selectively provided in the multilayer interconnect structure.

[0091] In an example implementation, if Figure 5 As shown, one of the wirings provided below the uppermost wiring may have a second stacking structure S2. Figure 5 In the embodiment, the third wiring 164 may have the second stack structure S2, but it may not be limited thereto. For example, instead of the third wiring 164, the second wiring 144 or the first wiring 124 may have the second stack structure S2.

[0092] The unit structure may be formed on the lower wiring structure. The unit structure may include a vertical channel transistor and a capacitor 246. The vertical channel transistor may include a channel pattern 214 and a word line pattern 218. In addition, the vertical channel transistor may include a molded insulating structure 204, a filling insulating structure 226, a landing pad 230, a fifth etch stop layer 234, and a plate electrode layer 248. Hereinafter, an example of a unit structure formed on the lower wiring structure may be described.

[0093] The first and second mold insulating patterns 200 and 202 may be stacked on the bit line L4 and the eighth lower insulating interlayer 192. Hereinafter, a structure in which the fourth etch stop layer pattern 190a, the first and second mold insulating patterns 200 and 202 are stacked may be referred to as a mold insulating structure 204.

[0094] The molded insulating structure 204 may have a line shape extending in the second direction. The molded insulating structure 204 may be provided to intersect the bit line L4. A plurality of molded insulating structures 204 may be spaced apart from each other in the first direction. Therefore, the first trench 206 may be between the molded insulating structures 204. The upper surface of the bit line L4 may be exposed through the bottom of the first trench 206.

[0095] The first mold insulating pattern 200 may include silicon oxide, and the second mold insulating pattern 202 may include silicon nitride. However, the present disclosure is not limited thereto, and as such, the first mold insulating pattern and the second mold insulating pattern 202 may include materials other than silicon oxide or silicon nitride.

[0096] The channel pattern 214 may be provided conformally on the sidewall of the molded insulating structure 204 and the upper surface of the bit line L4 between the molded insulating structure 204. The channel pattern 214 may include two sidewalls extending in the vertical direction and a lower surface connecting the lower portions of the two sidewalls facing each other in the first direction. The lower surface of the channel pattern 214 may contact the upper surface of the bit line L4. Therefore, the channel pattern 214 may have a U-shape in a cross-sectional view cut along the first direction. The channel pattern 214 may be regularly arranged in each of the first direction and the second direction. The channel pattern 214 may be spaced apart from each other in the first direction and the second direction.

[0097] Hereinafter, the portion of the U-shaped structure extending in the vertical direction is referred to as a side wall. In addition, the horizontal portion connected to the lower portions of the two side walls is referred to as a lower portion.

[0098] The bottom of the channel pattern 214 may contact the upper surface of the bit line L4. The mold insulation structure 204 may be provided between the channel patterns 214 in the first direction, and the channel patterns 214 may be aligned in the first direction. The channel patterns 214 may be spaced apart from each other in the second direction.

[0099] The channel pattern 214 may include an oxide semiconductor material. In example embodiments, the channel pattern 214 may include InxGayZnzO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, or a combination thereof. For example, the channel pattern 214 may include InxGayZnzO. In example embodiments, the channel pattern 214 may be amorphous.

[0100] The gate insulation layer pattern 216 may be formed on inner walls of the channel pattern 214 and sidewalls of the mold insulation structure 204. The gate insulation layer pattern 216 may extend in the second direction.

[0101] In example embodiments, the gate insulating layer pattern 216 may not be formed on the inner lower surface of the channel pattern 214. In some example embodiments, the gate insulating layer pattern 216 may be formed on the inner sidewall and lower surface of the channel pattern 214 and thus may have a U-shape in a cross-sectional view.

[0102] The gate insulating layer pattern 216 may include a metal oxide having a higher dielectric constant than that of silicon nitride. The gate insulating layer pattern 216 may include, for example, aluminum oxide, zirconium oxide, hafnium oxide, titanium oxide, or the like.

[0103] The uppermost surface of the gate insulating layer pattern 216 may be higher than the uppermost surface of the channel pattern 214. Figure 3 As shown, both ends of the gate insulating layer pattern 216 may be higher than the uppermost surface of the channel pattern 214. The uppermost surface of the gate insulating layer pattern 216 may be substantially coplanar with the upper surface of the mold insulating structure 204.

[0104] The word line pattern 218 may be provided on the inner sidewall of the gate insulating layer pattern 216. The word line patterns 218 may be provided on both sidewalls of the channel pattern 214 having a U shape, respectively. In addition, the word line pattern 218 may not be formed on the lower surface of the channel pattern 214 having a U shape. Each word line pattern 218 may extend in the second direction.

[0105] The uppermost surface of the word line pattern 218 may be lower than the upper surface of the mold insulation structure 204. In addition, the uppermost surface of the word line pattern 218 may be lower than the uppermost surface of the gate insulation layer pattern 216.

[0106] The word line pattern 218 may include, but is not limited to, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The plurality of word line patterns 218 may include, but are not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof.

[0107] The word line pattern 218 may be used as a gate electrode of a vertical channel transistor. Each channel pattern 214 may be used as an active pattern. The gate insulating layer pattern 216 and the word line pattern 218 may be stacked laterally on each inner sidewall of the channel pattern 214. The gate insulating layer pattern 216 may be interposed between the channel pattern 214 and the word line pattern 218. Thus, two vertical channel transistors connected in series may be provided on one channel pattern 214.

[0108] A filling insulating structure 226 may be formed on the word line pattern 218 to fill the first trench 206. An upper surface of the filling insulating structure 226 may be substantially coplanar with an upper surface of the mold insulating structure 204. The filling insulating structure 226 may have a line shape extending in the second direction. The filling insulating structure 226 may face the mold insulating structure 204 in the first direction.

[0109] In example embodiments, the filling insulating structure 226 may include a liner insulating pattern 220, a first filling insulating pattern 222, and a second filling insulating pattern 224. The liner insulating pattern 220 may be conformally formed on the word line pattern 218 in the first trench 206, the lower surface of the channel pattern 214, and the surface of the gate insulating layer pattern 216. The first filling insulating pattern 222 may fill most of the first trench 206. The second filling insulating pattern 224 may fill the upper portion of the first trench 206. In example embodiments, the bottom of the second filling insulating pattern 224 may be coplanar with the uppermost surface of the word line pattern 218 or higher than the uppermost surface of the word line pattern 218. The liner insulating pattern 220 and the second filling insulating pattern 224 may include silicon nitride, and the first filling insulating pattern 222 may include silicon oxide. However, the present disclosure is not limited thereto.

[0110] The gate insulation layer pattern 216 and the mold insulation structure 204 contacting the inner and outer sidewalls of the channel pattern 214 may protrude from the uppermost surface of the channel pattern 214. Therefore, a groove 228 may be formed between the gate insulation layer pattern 216 and the mold insulation structure 204 contacting the inner and outer sidewalls of the channel pattern 214. The channel pattern 214 may be exposed through the bottom of the groove 228.

[0111] The landing pad 230 may fill the groove 228. The upper surface of the landing pad 230 may protrude from the upper surfaces of the molded insulating structure 204 and the filling insulating structure 226. The landing pads 230 may contact the uppermost surfaces of the channel patterns 214, respectively. The landing pad 230 may include a conductive material. In a plan view, the landing pad 230 may have a circular, oval, rectangular, square, diamond, or hexagonal shape.

[0112] The upper insulating pattern 232 may fill the gap between the landing pads 230. The upper insulating pattern 232 may include silicon nitride, but is not limited thereto.

[0113] A fifth etch stop layer 234 may be formed on the landing pad 230 and the upper insulating pattern 232. Capacitors 246 may pass through the fifth etch stop layer 234 and may respectively contact upper surfaces of the landing pads 230. Each capacitor 246 may include a lower electrode 240, a dielectric layer 242, and an upper electrode 244.

[0114] In example embodiments, a supporting layer pattern (not shown) connecting the sidewalls of the lower electrode 240 may be further included.

[0115] The planar electrode layer 248 may be formed on the upper electrode 244. The planar electrode layer 248 may include silicon germanium, but is not limited thereto.

[0116] The capacitor 246 and the plate electrode layer 248 may be formed only on the memory cell region. The upper insulating interlayer 250 may cover the plate electrode layer 248 and the upper insulating pattern 232 .

[0117] As described above, the lower wiring structure may include at least one of the wirings having the first stack structure S1 and at least one of the wirings having the second stack structure S2 .

[0118] The lower wiring structure included in the semiconductor device may have various structures including at least one of the wirings having the first stack structure S1 and at least one of the wirings having the second stack structure S2. Hereinafter, examples of the lower wiring structure may be described.

[0119] Figure 6 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to example embodiments.

[0120] Reference Figure 6 , the lower wiring structure may include first to fourth wirings 124, 144, 164, and 184 stacked in a vertical direction. Figure 6 In the example embodiment, at least two wires in the lower wire structure may have a second stack structure S2.

[0121] For example, the second wiring 144 and the third wiring 164 may have a second stack structure S2 .

[0122] The second wiring 144 may include a second contact plug C2 and a second conductive pattern L2, the second contact plug C2 includes a barrier metal pattern 140a and a lower metal pattern 142a, and the second conductive pattern L2 includes an upper metal pattern 146a. The third wiring 164 may include a third contact plug C3 and a third conductive pattern L3, the third contact plug C3 includes a barrier metal pattern 160a and a lower metal pattern 162a, and the third conductive pattern L3 includes an upper metal pattern 166a.

[0123] In each of the second wiring 144 and the third wiring 164, the barrier metal pattern may be formed only inside the contact hole. For example, in each of the second wiring 144 and the third wiring 164, the upper surface of the barrier metal pattern may not be provided above the contact hole. That is, in each of the second wiring 144 and the third wiring 164, the barrier metal pattern may be formed only on the inner surface of the contact hole, and the connection portion between the contact plug and the conductive pattern may be distinguished. For example, the contact plug and the conductive pattern may be independent and / or distinct from each other. For example, the contact plug and the conductive pattern may be formed as a two-piece structure. In addition, the conductive pattern may have a resistance lower than the resistance of the contact plug.

[0124] The semiconductor device may have a lower wiring structure as shown in FIG. Figure 3 and Figure 4 The unit structure.

[0125] Figure 7 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to example embodiments.

[0126] Reference Figure 7 , the lower wiring structure may include first to fourth wirings 124, 144, 164, and 184 stacked in a vertical direction. In the lower wiring structure, the uppermost wiring including the bit line L4 may have a second stacking structure S2. The first to third wirings 124, 144, and 164 located below the uppermost wiring may have a first stacking structure S1.

[0127] like Figure 7 As shown, the fourth wiring 184 may have a second stack structure S2. The fourth wiring 184 may include a fourth contact plug C4 including a barrier metal pattern 180a and a lower metal pattern 182a, and a fourth conductive pattern L4 including an upper metal pattern 186a.

[0128] The semiconductor device may have a lower wiring structure as shown in FIG. Figure 3 and Figure 4The unit structure.

[0129] Figure 8 is an enlarged cross-sectional view of a lower wiring structure in a semiconductor device according to example embodiments.

[0130] Reference Figure 8 , the lower wiring structure may include first to fourth wirings 124, 144, 164, and 184 stacked in a vertical direction. In the lower wiring structure, the uppermost wiring including the bit line L4 may have a second stacking structure S2. In the lower wiring structure, the lowermost first wiring 124 may have a first stacking structure S1. In addition, at least one of the second to third wirings 144 and 164 located between the uppermost wiring and the lowermost wiring may have a second stacking structure S2.

[0131] For example, Figure 8 As shown, the third wiring 164 and the fourth wiring 184 may have a second stack structure S2.

[0132] The third wiring 164 may include a third contact plug C3 and a third conductive pattern L3, the third contact plug C3 includes a barrier metal pattern 160a and a lower metal pattern 162a, and the third conductive pattern L3 includes an upper metal pattern 166a. The fourth wiring 184 may have a second stacked structure S2. The fourth wiring 184 may include a fourth contact plug C4 and a fourth conductive pattern L4, the fourth contact plug C4 includes a barrier metal pattern 180a and a lower metal pattern 182a, and the fourth conductive pattern L4 includes an upper metal pattern 186a.

[0133] The semiconductor device may have a lower wiring structure as shown in FIG. Figure 3 and Figure 4 The unit structure.

[0134] Figures 9 to 27 are cross-sectional views of stages in a method of fabricating a semiconductor device according to example embodiments.

[0135] Figures 9 to 27 is along Figure 4 A cross-sectional view taken along line AA'.

[0136] Reference Fig. 9 , a trench isolation process may be performed on the substrate 100 to form an isolation pattern 104 in the trench 102 at an upper portion of the substrate 100. In addition, a peripheral transistor 110 constituting a peripheral circuit may be formed on the substrate 100. Fig. 9 Only one peripheral transistor is shown in FIG. 1 , but a plurality of peripheral transistors may be formed on the substrate 100 .

[0137] The peripheral transistors 110 may be used as a peripheral circuit structure including a core circuit and a peripheral circuit. Each peripheral transistor 110 may be a planar transistor.

[0138] A first lower insulating interlayer 112 may be formed on the substrate 100 to cover the peripheral transistor 110. The first lower insulating interlayer 112 may include silicon oxide, but is not limited thereto.

[0139] Reference Fig.10 , the first lower insulating interlayer 112 may be etched to form a first contact hole 114 that passes through the first lower insulating interlayer 112 and exposes the surface of the substrate 100 .

[0140] In example embodiments, a metal silicide pattern 116 may be formed on the substrate 100 exposed by the bottom of each first contact hole 114 .

[0141] The first barrier metal layer 120 may be provided on the surfaces of the first contact hole 114 and the first lower insulating interlayer 112. For example, the first barrier metal layer 120 may be formed on the surfaces of the first contact hole 114 and the first lower insulating interlayer 112. That is, the first barrier metal layer 120 may be formed to conform to the surfaces of the first contact hole 114 and the first lower insulating interlayer 112. A first metal layer 122 may be formed on the first barrier metal layer 120 to fill the first contact hole 114.

[0142] In example embodiments, the first barrier metal layer 120 and the first metal layer 122 may be formed by a chemical vapor deposition process. The first barrier metal layer 120 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, carbon tungsten nitride, etc. The first metal layer 122 may include, but is not limited to, tungsten.

[0143] The metal layer formed by the chemical vapor deposition process may have a gap filling property better than the metal layer formed by the physical vapor deposition process. Therefore, in the example case where the first metal layer 122 is formed by the chemical vapor deposition process, the first metal layer 122 may be formed in the first contact hole 114 without a void.

[0144] In the example case where the metal layer is formed by a chemical vapor deposition process, the metal layer may have poor adhesion characteristics between the metal layer and the insulating layer. Therefore, the first barrier metal layer 120 may be interposed between the first metal layer 122 and the first lower insulating interlayer 112. The first barrier metal layer 120 may be an adhesion layer for the first metal layer 122.

[0145] Reference Fig.11, the first metal layer 122 and the first barrier metal layer 120 may be etched to form a first wiring 124 including a first barrier metal pattern 120a and a first metal pattern 122a. The first wiring 124 may be formed on the first lower insulating interlayer 112. For example, the first wiring 124 may be formed on the first lower insulating interlayer 112 and may fill the first contact hole 114. The first wiring 124 may include a first contact plug C1 filling the first contact hole 114, and a first conductive pattern L1 on the first contact plug C1 and the first lower insulating interlayer 112. The first conductive pattern L1 may be electrically connected to the first contact plug C1, and may extend in a direction parallel to the upper surface of the substrate 100.

[0146] The first wiring 124 may be a lowermost wiring directly connected to the substrate 100. In the first wiring 124, a first barrier metal pattern 120a may be provided on the sidewall and bottom of the first contact hole 114 and the upper surface of the first lower insulating interlayer 112. For example, the first barrier metal pattern 120a may be formed to conform to the sidewall and bottom of the first contact hole 114 and the upper surface of the first lower insulating interlayer 112. The first metal pattern 122a may be formed to fill the first contact hole 114 on the first barrier metal pattern 120a.

[0147] The first metal pattern 122a may contact the entire upper surface of the first barrier metal pattern 120a. However, the present disclosure is not limited thereto, and as such, the first metal pattern 122a may partially contact the upper surface of the first barrier metal pattern 120a. In addition, since the first contact plug C1 and the first conductive pattern L1 include the first metal pattern 122a having one body, the connection portion (e.g., interface) between the first contact plug C1 and the first conductive pattern L1 may not be distinguishable. For example, the first contact plug C1 and the first conductive pattern L1 may be provided as a single-piece (or single-piece) structure. According to an embodiment, there may be no clear interface between the first contact plug C1 and the first conductive pattern L1. The first wiring 124, which is the lowest wiring directly contacting the substrate 100, may have a first stacked structure S1.

[0148] Reference Fig.12 , a first etch stop layer 130 may be provided on surfaces of the first lower insulating interlayer 112 and the first wiring 124. The first etch stop layer 130 may be conformally formed on surfaces of the first lower insulating interlayer 112 and the first wiring 124. The first etch stop layer 130 may include, but is not limited to, silicon nitride.

[0149] A second lower insulating interlayer 132 may be formed on the first etch stop layer 130. The second lower insulating interlayer 132 may be planarized until an upper surface of the first etch stop layer 130 is exposed. The second lower insulating interlayer 132 may include, but is not limited to, silicon oxide.

[0150] Reference Fig.13 , a third lower insulating interlayer 134 may be formed on the second lower insulating interlayer 132 and the first etch stop layer 130 .

[0151] The third lower insulating interlayer 134 and the first etch stop layer 130 may be etched to form a second contact hole 136 that passes through the third lower insulating interlayer 134 and the first etch stop layer 130 and exposes an upper surface of the first metal pattern.

[0152] A second barrier metal layer 140 may be provided on the second contact hole 136 and the surface of the third lower insulating interlayer 134. The second barrier metal layer 140 may be conformally formed on the second contact hole 136 and the surface of the third lower insulating interlayer 134. A second metal layer 142 may be formed on the second barrier metal layer 140 to fill the second contact hole 136.

[0153] In example embodiments, the second barrier metal layer 140 and the second metal layer 142 may be formed by a chemical vapor deposition process. The second barrier metal layer 140 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, tungsten carbonitride, etc. The second metal layer 142 may include, but is not limited to, tungsten.

[0154] The third lower insulating interlayer 134 may include, but is not limited to, silicon nitride or silicon oxide. In example embodiments, the lower insulating interlayer provided over the lowermost wiring and including the contact hole may include silicon nitride.

[0155] Reference Fig.14 , the second metal layer 142 and the second barrier metal layer 140 are etched to form a second wiring 144 including a second barrier metal pattern 140a and a second metal pattern 142a. The second wiring 144 may be formed on the third lower insulating interlayer 134 and fill the second contact hole 136. The second wiring 144 may include a second contact plug C2 filling the second contact hole 136, and a second conductive pattern L2 provided on the second contact plug C2 and the third lower insulating interlayer 134. The second conductive pattern L2 may be electrically connected to the second contact plug C2, and may extend in a direction parallel to the upper surface of the substrate 100.

[0156] The second wiring 144 may have a first stack structure S1 .

[0157] A second etch stop layer 150 may be provided on surfaces of the third lower insulating interlayer 134 and the second wiring 144. The second etch stop layer 150 may be conformally formed on surfaces of the third lower insulating interlayer 134 and the second wiring 144. The second etch stop layer 150 may include, but is not limited to, silicon nitride.

[0158] A fourth lower insulating interlayer 152 may be formed on the second etch stop layer 150. The fourth lower insulating interlayer 152 may be planarized until an upper surface of the second etch stop layer 150 is exposed. The fourth lower insulating interlayer 152 may include, but is not limited to, silicon oxide.

[0159] Reference Fig.15 , a fifth lower insulating interlayer 154 may be formed on the fourth lower insulating interlayer 152 and the second etch stop layer 150 .

[0160] The fifth lower insulating interlayer 154 and the second etch stop layer 150 may be etched to form a third contact hole 156 passing through the fifth lower insulating interlayer 154 and the second etch stop layer 150 and exposing an upper surface of the second metal pattern 142 a .

[0161] The third barrier metal layer 160 may be conformally formed on the surfaces of the third contact hole 156 and the fifth lower insulating interlayer 154. The third barrier metal layer 160 may be conformally formed on the surfaces of the third contact hole 156 and the fifth lower insulating interlayer 154. A third metal layer 162 may be formed on the third barrier metal layer 160 to fill the third contact hole 156.

[0162] In example embodiments, the third barrier metal layer 160 and the third metal layer 162 may be formed by a chemical vapor deposition process. The third barrier metal layer 160 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, tungsten carbonitride, etc. The third metal layer 162 may include, but is not limited to, tungsten.

[0163] The fifth lower insulating interlayer 154 may include, but is not limited to, silicon nitride or silicon oxide. In example embodiments, the fifth lower insulating interlayer 154 may include silicon nitride.

[0164] Reference Fig.16 The third metal layer 162 and the third barrier metal layer 160 may be planarized until the upper surface of the fifth lower insulating interlayer 154 is exposed to form a third barrier metal pattern 160a and a third metal pattern 162a. The third barrier metal pattern 160a and the third metal pattern 162a may fill the third contact hole 156 and may function as a third contact plug C3.

[0165] The third contact plug C3 may include a metal material formed by a chemical vapor deposition process. For example, the third contact plug C3 may include tungsten formed by a chemical vapor deposition process.

[0166] Reference Fig.17 , a fourth metal layer 166 may be formed on the fifth lower insulating interlayer 154 and the third contact plug C3 .

[0167] In example embodiments, the fourth metal layer 166 may be formed by a physical vapor deposition process. Compared to a metal layer formed by a chemical vapor deposition process, a metal layer formed by a physical vapor deposition process may have poor gap filling characteristics and poor step coverage characteristics. Therefore, if a metal layer is formed by a physical vapor deposition process to fill a contact hole, the metal layer may include a void. However, since the upper surfaces of the fifth lower insulating interlayer 154 and the third contact plug C3 are substantially flat, the fourth metal layer 166 formed by a physical vapor deposition process may not have a void.

[0168] In the example case where the fourth metal layer 166 is formed by a physical vapor deposition process, the fourth metal layer 166 may have excellent adhesion between the fifth lower insulating interlayer 154 and the fourth metal layer 166, so that a barrier metal layer may not be formed. Therefore, the fourth metal layer 166 may directly contact the fifth lower insulating interlayer 154. For example, the fourth metal layer 166 may include tungsten formed by a physical vapor deposition process.

[0169] Reference Fig.18 The fourth metal layer 166 may be etched to form a fourth metal pattern 166a on the fifth lower insulating interlayer 154 and the third contact plug C3. The fourth metal pattern 166a may have a line shape extending in a direction parallel to the upper surface of the substrate 100.

[0170] The metal layer formed by the physical vapor deposition process may have a higher metal purity than the metal layer formed by the chemical vapor deposition process. Therefore, the metal layer formed by the physical vapor deposition process may have a lower resistance than the metal layer formed by the chemical vapor deposition process. In example embodiments, the fourth metal pattern 166a may have a lower resistance than the third metal pattern 162a.

[0171] In example embodiments, the fourth metal pattern 166a may include the same material as that of the third metal pattern 162a. In this case, since the fourth metal pattern 166a and the third metal pattern 162a are formed by different deposition processes, the materials of the third metal pattern 162a and the fourth metal pattern 166a may have different grain sizes. In example embodiments, the fourth metal pattern 166a may have a grain size smaller than that of the third metal pattern 162a.

[0172] In some example embodiments, the fourth metal pattern 166a may include a material different from that of the third metal pattern 162a, and a resistance of the material included in the fourth metal pattern 166a may be lower than a resistance of the material included in the third metal pattern 162a.

[0173] As described above, the third wiring 164 including the third contact plug C3 and the third conductive pattern L3 may be formed on the second wiring 144. The third contact plug C3 may include the third barrier metal pattern 160a and the third metal pattern 162a, and the third conductive pattern L3 may include the fourth metal pattern 166a.

[0174] In the third wiring 164, the third barrier metal pattern 160a may be formed only on the sidewall and the bottom of the third contact hole 156. The third barrier metal pattern 160a may not be formed on the upper surface of the fifth lower insulating interlayer 154. In addition, the third metal pattern 162a included in the third contact plug C3 and the fourth metal pattern 166a included in the third conductive pattern L3 may be formed by different deposition processes, so that the interface between the third metal pattern 162a and the fourth metal pattern 166a may be generated. The interface between the third metal pattern 162a and the fourth metal pattern 166a may be distinguished. For example, the third metal pattern 162a and the fourth metal pattern 166a may be independent and / or distinct from each other. For example, the third metal pattern 162a and the fourth metal pattern 166a may be formed as a two-piece structure.

[0175] The third wiring 164 may have a second stack structure S2. The conductive pattern included in the second stack structure S2 may be formed by a physical vapor deposition process. Therefore, the wiring having the second stack structure S2 may have a lower resistance than the wiring having the first stack structure S1.

[0176] Reference Fig.19 , a third etch stop layer 170 may be provided on the surfaces of the fifth lower insulating interlayer 154 and the third wiring 164. The third etch stop layer 170 may be conformally formed on the surfaces of the fifth lower insulating interlayer 154 and the third wiring 164. The third etch stop layer 170 may include, but is not limited to, silicon nitride.

[0177] A sixth lower insulating interlayer 172 may be formed on the third etch stop layer 170. The sixth lower insulating interlayer 172 may be planarized until an upper surface of the third etch stop layer 170 is exposed. The sixth lower insulating interlayer 172 may include, but is not limited to, silicon oxide.

[0178] A seventh lower insulating interlayer 174 may be formed on the sixth lower insulating interlayer 172 and the third etch stop layer 170 .

[0179] The seventh lower insulating interlayer 174 and the third etch stop layer 170 may be etched to form a fourth contact hole 176 passing through the seventh lower insulating interlayer 174 and the third etch stop layer 170 and exposing an upper surface of the fourth metal pattern 166 a .

[0180] A fourth barrier metal layer 180 may be provided on the surface of the fourth contact hole 176 and the seventh lower insulating interlayer 174. The fourth barrier metal layer 180 may be conformally formed on the surface of the fourth contact hole 176 and the seventh lower insulating interlayer 174. A fifth metal layer 182 may be formed on the fourth barrier metal layer 180 to fill the fourth contact hole 176.

[0181] In example embodiments, the fourth barrier metal layer 180 and the fifth metal layer 182 may be formed by a chemical vapor deposition process. The fourth barrier metal layer 180 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, carbon tungsten nitride, or the like. The fifth metal layer 182 may include, but is not limited to, tungsten.

[0182] The seventh lower insulating interlayer 174 may include, but is not limited to, silicon nitride or silicon oxide. In example embodiments, the seventh lower insulating interlayer 174 may include silicon nitride.

[0183] Reference Fig. 20 , the fifth metal layer 182 and the fourth barrier metal layer 180 may be etched to form a fourth wiring 184 including a fourth barrier metal pattern 180a and a fifth metal pattern 182a. The fourth wiring 184 may be formed on the seventh insulating interlayer 174 and fill the fourth contact hole 176. The fourth wiring 184 may include a fourth contact plug C4 filling the fourth contact hole 176 and a fourth conductive pattern L4 provided on the fourth contact plug C4 and the seventh lower insulating interlayer 174. The fourth conductive pattern L4 may be connected to the fourth contact plug C4. The fourth wiring 184 may have a first stacked structure S1.

[0184] The fourth wiring 184 may be an uppermost wiring and may serve as a bit line L4. The bit line L4 may extend in the first direction.

[0185] As described above, the lower wiring structure may include the third wiring 164 having the second stack structure S2 and the first wiring 124 , the second wiring 144 , and the fourth wiring 184 having the first stack structure S1 .

[0186] In example embodiments, a lower wiring structure of various structures including at least one of the first to fourth wirings 124, 144, 164, and 184 having a first stacking structure S1 and at least one of the first to fourth wirings 124, 144, 164, and 184 having a second stacking structure S2 may be manufactured. For example, the wiring having the second stacking structure may be fabricated by performing the same as reference. Figures 15 to 18 The wiring having the first stacking structure can be formed by performing the same process as described in reference Fig.13 and Fig.14 The same process as described is used to form.

[0187] A fourth etch stop layer 190 may be provided on surfaces of the seventh lower insulating interlayer 174 and the fourth wiring 184. The fourth etch stop layer 190 may be conformally formed on surfaces of the seventh lower insulating interlayer 174 and the fourth wiring 184. The fourth etch stop layer 190 may include, but is not limited to, silicon nitride.

[0188] An eighth lower insulating interlayer 192 may be formed on the fourth etch stop layer 190. The eighth lower insulating interlayer 192 may be planarized until an upper surface of the fourth etch stop layer 190 is exposed. The eighth lower insulating interlayer 192 may include, but is not limited to, silicon oxide.

[0189] As described above, a lower wiring structure including the wirings 124 , 144 , 164 , and 184 may be formed on the substrate 100 , and an uppermost wiring in the lower wiring structure may be the bit line L4 .

[0190] Reference Fig.21 , a first mold insulating layer and a second mold insulating layer may be sequentially formed on the fourth etch stop layer 190 and the eighth lower insulating interlayer 192 .

[0191] The second mold insulating layer, the first mold insulating layer, and the fourth etch stop layer 190 may be patterned to form a mold insulating structure 204. The mold insulating structure 204 may have a structure in which a fourth etch stop layer pattern 190a, a first mold insulating pattern 200, and a second mold insulating pattern 202 are stacked.

[0192] The first mold insulating pattern 200 may include, but is not limited to, silicon oxide. The second mold insulating pattern 202 may include, but is not limited to, silicon nitride.

[0193] The molded insulating structure 204 may have a line shape extending in the second direction. The molded insulating structures 204 may be spaced apart from each other in the first direction. A first trench 206 extending in the second direction may be formed between the molded insulating structures 204. The fourth conductive pattern L4 and the eighth lower insulating interlayer 192 may be exposed through the bottom of the first trench 206. Therefore, the bit line L4 may be exposed through the bottom of the first trench 206.

[0194] A channel layer 210 may be provided on the surface of the mold insulation structure 204 and the bottom of the first trench 206. The channel layer 210 may be conformally formed on the surface of the mold insulation structure 204 and the bottom of the first trench 206. The channel layer 210 may include an oxide semiconductor. The channel layer 210 including an oxide semiconductor may be used as a channel pattern for a vertical channel transistor through subsequent processes.

[0195] The channel layer 210 may cover the surface of the molded insulating structure 204, the upper surface of the fourth conductive pattern L4, and the upper surface of the eighth lower insulating interlayer 192. The channel layer 210 may not completely fill the first trench 206, and may be formed to have a uniform thickness along the surface profile of the first trench 206. The channel layer 210 may contact the fourth conductive pattern L4.

[0196] In example embodiments, the channel layer 210 may be amorphous. The channel layer 210 may include, but is not limited to, InxGayZnzO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, or a combination thereof. For example, the channel layer 210 may include InxGayZnzO.

[0197] In example embodiments, the channel layer 210 may be formed by an atomic layer deposition process.

[0198] Reference Fig. 22 , a first sacrificial layer may be formed on the channel layer 210. The first sacrificial layer may fill the first trench 206. An upper surface of the first sacrificial layer may be substantially flat. In example embodiments, the first sacrificial layer may include a spin-on hard mask. The spin-on hard mask may include, but is not limited to, amorphous carbon.

[0199] A first etching mask may be formed on the first sacrificial layer. The first sacrificial layer may be anisotropically etched using the first etching mask to form a first sacrificial layer pattern 212. Subsequently, the channel layer 210 may be anisotropically etched using the first sacrificial layer pattern 212 as an etching mask to form a preliminary channel pattern 210a. Therefore, the preliminary channel patterns 210a may be separated from each other in the second direction and may be spaced apart from each other in the second direction.

[0200] The first etch mask may overlap the upper surface of the bit line L4. Therefore, the first sacrificial layer pattern 212 may extend in the first direction to cover the upper surface of the bit line L4. A first opening may be formed between the first sacrificial layer pattern 212 and the mold insulation structure 204.

[0201] Reference Fig.23 , a second sacrificial layer may be formed on the eighth lower insulating interlayer 192 , the mold insulating structure 204 , the first sacrificial layer pattern 212 , and the preliminary channel pattern 210 a to fill the first opening.

[0202] The second sacrificial layer, the first sacrificial layer pattern 212, and the preliminary channel pattern 210a may be planarized until an upper surface of the mold insulation structure 204 is exposed. Thus, nodes of the preliminary channel pattern 210a may be separated to form a plurality of channel patterns 214. The planarization process may include an etch-back process.

[0203] Each channel pattern 214 may be provided on the sidewall of the mold insulation structure 204 and the upper surface of the bit line L4 between the mold insulation structure 204. For example, each channel pattern 214 may be conformally formed on the sidewall of the mold insulation structure 204 and the upper surface of the bit line L4 between the mold insulation structure 204. In a cross-sectional view, each channel pattern 214 may have a U-shape. The channel patterns 214 may be spaced apart in each of the first direction and the second direction. The bottom of each channel pattern 214 may contact the bit line L4.

[0204] The mold insulation structure 204 may be provided between the channel patterns 214 in the first direction, and the channel patterns 214 may be aligned in the first direction. The eighth lower insulating interlayer 192 may be exposed between the channel patterns 214 in the second direction.

[0205] Thereafter, the first sacrificial layer pattern 212 and the second sacrificial layer may be removed. Removing the first sacrificial layer pattern 212 and the second sacrificial layer may include an ashing process and a cleaning process. Thus, the upper surface of the channel pattern 214 may be exposed. In addition, the first trench 206 may be formed again between the mold insulation structures 204.

[0206] Reference Fig.24 , a gate insulating layer and a fifth conductive layer may be formed on the channel pattern 214 , the mold insulating structure 204 , and the eighth lower insulating interlayer 192 .

[0207] A gate insulating layer and a fifth conductive layer may be provided on the channel pattern 214, the mold insulating structure 204, and the eighth lower insulating interlayer 192. For example, the gate insulating layer and the fifth conductive layer may be conformally formed on surfaces of the channel pattern 214, the mold insulating structure 204, and the eighth lower insulating interlayer 192.

[0208] In example embodiments, the gate insulating layer may include a metal oxide having a higher dielectric constant than that of silicon nitride. For example, the gate insulating layer may include aluminum oxide. The fifth conductive layer may include a metal or a metal nitride, such as titanium nitride.

[0209] In example embodiments, the gate insulating layer and the fifth conductive layer may be formed by an atomic layer deposition process.

[0210] The fifth conductive layer and the gate insulating layer formed between the upper surface of the mold insulating structure 204 and the mold insulating structure 204 may be anisotropically etched. Thus, the fifth conductive layer and the gate insulating layer may be separated from each other to form a word line pattern 218 and a gate insulating layer pattern 216, respectively.

[0211] The gate insulating layer pattern 216 and the word line pattern 218 may be formed on the sidewall of the mold insulating structure 204 and may extend in the second direction. The channel pattern 214, the gate insulating layer pattern 216, and the word line pattern 218 may be sequentially stacked on the sidewall of the mold insulating structure 204. The word line pattern 218 may be used as a gate electrode of a vertical channel transistor. The upper surface of the word line pattern 218 may be lower than the upper surface of the mold insulating structure 204.

[0212] Reference Fig.25 , a filling insulation structure 226 may be formed to fill the inside of the first trench 206. The filling insulation structure 226 may include a liner insulation pattern 220 and first and second filling insulation patterns 222 and 224.

[0213] A liner insulating pattern 220 may be provided in the first trench 206 on the word line pattern 218, the gate insulating layer pattern 216, and the channel pattern 214. For example, the liner insulating pattern 220 may be conformally formed in the first trench 206 on surfaces of the word line pattern 218, the gate insulating layer pattern 216, and the channel pattern 214. A first filling insulating pattern 222 and a second filling insulating pattern 224 may be formed on the liner insulating pattern 220.

[0214] An upper surface of the filling insulation structure 226 may be substantially coplanar with an upper surface of the mold insulation structure 204 .

[0215] Reference Fig.26 , an upper portion of the channel pattern 214 may be partially etched to form a groove 228 .

[0216] A groove 228 may be formed between the gate insulating layer pattern 216 provided on both sidewalls of the channel pattern 214 and the mold insulating structure 204. The channel pattern 214 may be exposed through the bottom of the groove 228. An uppermost surface of the channel pattern 214 may be lower than an upper surface of the mold insulating structure 204.

[0217] A sixth conductive layer may be formed to fill the groove 228. The sixth conductive layer may be patterned to form landing pads 230 respectively contacting upper surfaces of the channel patterns 214. In a plan view, each landing pad 230 may have a circular, oval, rectangular, square, diamond, or hexagonal shape.

[0218] The upper insulating pattern 232 may be formed to fill the space between the landing pads 230. The upper insulating pattern 232 may include, but is not limited to, silicon nitride.

[0219] Reference Fig. 27 , a fifth etch stop layer 234 may be formed on the landing pad 230 and the upper insulating pattern 232 .

[0220] The capacitors 246 may be formed through the fifth etch stop layer 234 and may respectively contact upper surfaces of the landing pads 230. The capacitors 246 may include a lower electrode 240, a dielectric layer 242, and an upper electrode 244.

[0221] In example embodiments, a supporting layer pattern connecting the sidewalls of the lower electrode 240 may be further formed.

[0222] A planar electrode layer 248 may be formed on the upper electrode 244. The planar electrode layer 248 may include silicon germanium.

[0223] The capacitor 246 and the plate electrode layer 248 may be formed only on the memory cell region.

[0224] An upper insulating interlayer 250 may be formed on the plate electrode layer 248 and the upper insulating pattern 232. In example embodiments, an interconnection passing through the upper insulating interlayer may be further formed on a region other than the memory cell region. The interconnection may be connected to a lower wiring structure.

[0225] Fig.28 is an enlarged cross-sectional view illustrating a lower wiring structure in a semiconductor device according to example embodiments.

[0226] In addition to the lower wiring structure, the semiconductor device can be Figures 1 to 4 Therefore, it can be referred to as Fig.28 Only the lower wiring structure is described.

[0227] Reference Fig.28 , the lower wiring structure may include first to fourth wirings 124 , 144 , 164 , and 184 stacked in a vertical direction.

[0228] according to Fig.28 In the embodiment shown, at least one of the first to fourth wirings 124, 144, 164, and 184 included in the lower wiring structure may have a first stacking structure S1, and at least one of the first to fourth wirings 124, 144, 164, and 184 included in the lower wiring structure may have a third stacking structure S3 different from the first stacking structure S1. Here, the third stacking structure S3 may also be different from the second stacking structure S2.

[0229] For example, the contact plug included in the wiring having the third stacked structure S3 may include a lower barrier metal pattern on the sidewall and bottom of the contact hole and a lower metal pattern provided on the lower barrier metal pattern. The lower metal pattern may fill the contact hole. The conductive pattern included in the wiring of the third stacked structure may include an upper barrier metal pattern and an upper conductive pattern. The upper barrier metal pattern may be further provided on the bottom of the upper conductive pattern and may contact the bottom of the upper conductive pattern. For example, the upper barrier metal pattern may be sandwiched between the upper conductive pattern and the lower metal pattern in the vertical direction.

[0230] Each of the lower barrier metal pattern, the lower metal pattern, and the upper barrier metal pattern may include a metal formed by a chemical vapor deposition process. The upper metal pattern may include a metal formed by a physical vapor deposition process.

[0231] That is, the wirings having the third stacked structure S3 may be the same as the wirings of the second stacked structure S2 except that the conductive patterns on the contact plugs may further include an upper barrier metal pattern.

[0232] In the third stacked structure S3 , the material of the conductive pattern may have a lower resistance than that of the material of the contact plug.

[0233] In an example implementation, if Fig.28 As shown, the third wiring 164 may have a third stacked structure S3. The third wiring 164 includes a third contact plug C3 including a lower barrier metal pattern 160a and a lower metal pattern 162a and a third conductive pattern L3 including an upper barrier metal pattern 165 and an upper metal pattern 166a.

[0234] In example embodiments, the lower wiring structure included in the semiconductor device may have various structures in which at least one wiring has a third stacked structure. Figures 5 to 8 In the lower wiring structure included in the illustrated semiconductor device, the wiring having the second stacked structure may be replaced with the wiring having the third stacked structure.

[0235] The semiconductor device may have a lower wiring structure as shown in FIG. Figure 3 and Figure 4 The unit structure.

[0236] Fig.29 is an enlarged cross-sectional view illustrating a lower wiring structure in a semiconductor device according to example embodiments.

[0237] In addition to the lower wiring structure, the semiconductor device can be Figures 1 to 4 Therefore, it can be referred to as Fig.29 Only the lower wiring structure is described.

[0238] Reference Fig.29 , the lower wiring structure may include first to fourth wirings 124 , 144 , 164 , and 184 stacked in a vertical direction.

[0239] According to example embodiments, at least one of the first to fourth wirings 124, 144, 164, and 184 included in the lower wiring structure may have a first stacking structure S1, at least one of the first to fourth wirings 124, 144, 164, and 184 included in the lower wiring structure may have a second stacking structure S2, and at least one of the first to fourth wirings 124, 144, 164, and 184 included in the lower wiring structure may have a third stacking structure S3.

[0240] The material of the conductive pattern in the second stack structure S2 may have a lower resistance than the material of the contact plug in the second stack structure S2. The material of the conductive pattern in the third stack structure S3 may have a lower resistance than the material of the contact plug in the third stack structure S3.

[0241] In an example implementation, if Fig.29 As shown, the first wiring 124 and the fourth wiring 184 may have a first stacking structure S1, and the second wiring 144 may have a third stacking structure S3. The third wiring 164 may have a second stacking structure S2. The second wiring 144 may include a second contact plug C2 and a second conductive pattern L2, the second contact plug C2 includes a lower barrier metal pattern 140a and a lower metal pattern 142a, and the second conductive pattern L2 includes an upper barrier metal pattern 145 and an upper metal pattern 146a. The third wiring 164 may include a third contact plug C3 and a third conductive pattern L3, the third contact plug C3 includes a barrier metal pattern 160a and a lower metal pattern 162a, and the third conductive pattern L3 includes an upper metal pattern 166a.

[0242] In example embodiments, a lower wiring structure included in a semiconductor device may have various structures including wirings having first to third stacked structures.

[0243] The semiconductor device may have a lower wiring structure as shown in FIG. Figure 3 and Figure 4 The unit structure.

[0244] A semiconductor device in which a memory cell is provided on a lower wiring structure may include the lower wiring structure according to example embodiments. In addition, the semiconductor device according to the embodiments may be used as a memory included in electronic products such as mobile devices, memory cards, and computers.

[0245] The foregoing is an illustration of example embodiments of the inventive concept and should not be construed as limiting thereof. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without substantially departing from the scope of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as set forth in the claims.

[0246] CROSS-REFERENCE TO RELATED APPLICATIONS

[0247] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0079397 filed in the Korean Intellectual Property Office (KIPO) on June 21, 2023, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, comprising: a first wiring structure on a substrate, the first wiring structure comprising a plurality of wirings, each of the plurality of wirings comprising a contact plug and a conductive pattern stacked in a vertical direction perpendicular to a surface of the substrate; as well as a unit structure provided on an uppermost conductive pattern in the first wiring structure, the unit structure comprising a vertical channel transistor connected to the conductive pattern, The plurality of wirings of the first wiring structure include: a first wiring group including one or more first wirings having a first stacking structure among the plurality of wirings, the first stacking structure including a metal pattern and a barrier metal pattern constituting the contact plug and the conductive pattern, and the barrier metal pattern surrounding a lower surface of the metal pattern; as well as A second wiring group includes one or more second wirings having a second stacking structure different from the first stacking structure among the multiple wirings, the second stacking structure including a lower metal pattern constituting the contact plug and a lower barrier metal pattern surrounding the lower surface of the lower metal pattern, and an upper metal pattern constituting the conductive pattern, the upper metal pattern having a lower resistance than the lower metal pattern.

2. The semiconductor device according to claim 1, wherein The lower metal pattern includes a first metal having a first characteristic corresponding to a first deposition process, and the upper metal pattern includes a second metal having a second characteristic corresponding to a second deposition process different from the first deposition process.

3. The semiconductor device according to claim 1, wherein The lower metal pattern includes a first metal material formed by a chemical vapor deposition process, and the upper metal pattern includes a second metal material formed by a physical vapor deposition process.

4. The semiconductor device according to claim 1, wherein: The metal pattern includes a metal material formed by a chemical vapor deposition process.

5. The semiconductor device according to claim 1, wherein The lower metal pattern and the upper metal pattern include the same material.

6. The semiconductor device according to claim 5, wherein: The lower metal pattern and the upper metal pattern have different grain sizes.

7. The semiconductor device according to claim 1, wherein The lower metal pattern and the upper metal pattern include tungsten. 8 . The semiconductor device of claim 1 , further comprising an upper barrier metal pattern provided on a bottom of the upper metal pattern.

9. The semiconductor device according to claim 1, wherein: The vertical channel transistor comprises: a channel pattern contacting the uppermost conductive pattern of the first wiring structure and including a sidewall extending in the vertical direction; and The gate insulating layer pattern and the word line pattern are stacked laterally on the inner wall of the channel pattern.

10. The semiconductor device according to claim 9, wherein The channel pattern includes an oxide semiconductor. 11 . The semiconductor device according to claim 1 , further comprising a capacitor connected to the vertical channel transistor. 12 . The semiconductor device according to claim 1 , further comprising a peripheral circuit structure including a plurality of peripheral circuits provided on the substrate.

13. A semiconductor device comprising: a first wiring structure on a substrate, the first wiring structure comprising a plurality of wirings, each of the plurality of wirings comprising a contact plug and a conductive pattern stacked in a vertical direction perpendicular to a surface of the substrate; providing a channel pattern on the first wiring structure, the channel pattern including two or more sidewalls extending in the vertical direction and a lower surface connecting lower portions of two opposite sidewalls among the two or more sidewalls in the horizontal direction, the lower surface of the channel pattern contacting an uppermost conductive pattern in the first wiring structure; A gate insulating layer pattern and a word line pattern are stacked laterally on the inner wall of the channel pattern; as well as capacitor, connected to the upper surface of the channel pattern, Wherein, the plurality of wirings of the first wiring structure include: a first wiring group including one or more first wirings having a first stacking structure among the plurality of wirings, the first stacking structure including a metal pattern constituting the contact plug and the conductive pattern and a barrier metal pattern, the barrier metal pattern surrounding a lower surface of the metal pattern; and A second wiring group includes one or more second wirings among the multiple wirings having a second stacking structure different from the first stacking structure, the second stacking structure including a lower metal pattern constituting the contact plug and a lower barrier metal pattern surrounding the lower surface of the lower metal pattern, and an upper metal pattern constituting the conductive pattern, the upper metal pattern being formed by a physical vapor deposition process.

14. The semiconductor device according to claim 13, wherein: The lower metal pattern and the metal pattern include a metal material formed by a chemical vapor deposition process.

15. The semiconductor device according to claim 13, wherein: The lower metal pattern and the upper metal pattern include tungsten.

16. The semiconductor device according to claim 13, further comprising a first insulating interlayer provided on the first wiring structure, in, A portion of a bottom of the upper metal pattern contacts the first insulating interlayer. 17 . The semiconductor device according to claim 16 , further comprising an etch stop layer provided on surfaces of the conductive pattern of each of the plurality of wirings and the first insulating interlayer in which the contact plug is formed.

18. The semiconductor device according to claim 13, wherein: The channel pattern includes an oxide semiconductor.

19. A semiconductor device comprising: A peripheral circuit structure including a plurality of peripheral circuits provided on a substrate; a first wiring structure including a plurality of wirings connected to the plurality of peripheral circuit structures, each of the plurality of wirings including a contact plug and a conductive pattern stacked in a vertical direction perpendicular to a surface of the substrate, and an uppermost conductive pattern in the first wiring structure having a line shape extending in a first direction parallel to the surface of the substrate; providing a channel pattern on the first wiring structure, the channel pattern comprising two or more side walls extending in the vertical direction and a lower surface connecting lower portions of two opposite side walls among the two or more side walls in the horizontal direction, the channel pattern being regularly arranged in the first direction and in a second direction perpendicular to the first direction, the lower surface of the channel pattern contacting an uppermost conductive pattern in the first wiring structure; a word line pattern, formed laterally on an inner wall of the channel pattern, the word line pattern extending in the second direction; a gate insulating layer pattern between the channel pattern and the word line pattern, the gate insulating layer pattern extending in the second direction; as well as capacitor, connected to the upper surface of the channel pattern, Wherein, the plurality of wirings of the first wiring structure include: a first wiring group including one or more first wirings having a first stacking structure among the plurality of wirings, the first stacking structure including a metal pattern constituting the contact plug and the conductive pattern and a barrier metal pattern, the barrier metal pattern surrounding a lower surface of the metal pattern; and A second wiring group includes one or more second wirings among the multiple wirings having a second stacking structure different from the first stacking structure, the second stacking structure including a lower metal pattern formed by a chemical vapor deposition process constituting the contact plug and a lower barrier metal pattern surrounding the lower surface of the lower metal pattern, and an upper metal pattern formed by a physical vapor deposition process constituting the conductive pattern.

20. The semiconductor device according to claim 19, wherein The channel pattern includes an oxide semiconductor.

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