Memory, electronic equipment and preparation method of memory

Abstract

The embodiment of the invention provides a memory, electronic equipment and a preparation method of the memory, and relates to the technical field of storage. The memory comprises a substrate, a conductive layer, a first dielectric layer, a second dielectric layer, a first electrode wire and a second electrode wire. The conductive layer is arranged on one side of the substrate and is annularly arranged; the center line of the conductive layer intersects with the substrate. One of the first dielectric layer and the second dielectric layer is arranged on the inner side of the conductive layer, and the other one surrounds the outer side of the conductive layer; the first dielectric layer has ferroelectricity, and the second dielectric layer has switching characteristics. The first electrode wire is arranged on the side, away from the conductive layer, of the first dielectric layer, and the second electrode wire is arranged on the side, away from the conductive layer, of the second dielectric layer. According to the structural design of the memory, the storage density can be improved, and meanwhile crosstalk between devices in the read-write process can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory, an electronic device, and a method for preparing the memory. Background Art

[0002] Memory is a device used to store information. Usually, the information is digitized and then stored in electrical, magnetic or optical media. Ferroelectric Random Access Memory (FRAM) is a new type of memory. Compared with traditional dynamic random access memory (DRAM) or flash memory, it has the advantages of lower read and write voltage, low power consumption, small device size, high read and write speed, good cycle performance, radiation resistance and non-volatility, and is increasingly widely used.

[0003] With the rapid development of technologies such as the Internet of Things, big data, and artificial intelligence, the use of selectors instead of transistors to form 1S1C (1Selector1Capacitor) storage units has become widely popular. Improving the storage density and storage performance (such as anti-crosstalk capability) of 1S1C structured memory is of great significance to the further development of memory. Summary of the invention

[0004] The embodiments of the present application provide a memory, an electronic device, and a method for manufacturing the memory, with the aim of improving the storage density of the memory.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a memory is provided, comprising a substrate, a conductive layer, a first dielectric layer, a second dielectric layer, a first electrode line, and a second electrode line.

[0007] The conductive layer is arranged on one side of the substrate and is arranged in a ring shape; the center line of the conductive layer intersects with the substrate. One of the first dielectric layer and the second dielectric layer is arranged on the inner side of the conductive layer, and the other surrounds the outer side of the conductive layer; the first dielectric layer has ferroelectricity, and the second dielectric layer has switching characteristics. The first electrode line is arranged on the side of the first dielectric layer away from the conductive layer, and the second electrode line is arranged on the side of the second dielectric layer away from the conductive layer.

[0008] In the memory provided in the embodiment of the present application, by setting an annular conductive layer and stacking film layers such as a first dielectric layer and a second dielectric layer on the inner and outer sides of the conductive layer, compared with the related art, the memory in the present application can achieve a three-dimensional setting, that is, the design space occupied in the direction parallel to the substrate is reduced, thereby facilitating the improvement of the storage density of the memory.

[0009] In a possible implementation of the first aspect, the first electrode line is arranged on the inner side of the conductive layer; the first dielectric layer is arranged around the first electrode line and between the first electrode line and the conductive layer; the second dielectric layer is at least partially arranged around the conductive layer, and the second electrode line is at least partially arranged around the second dielectric layer.

[0010] That is, the relative positions of the ferroelectric capacitor and the selection tube can be flexibly set, so that the memory can be flexibly applied to a variety of different structures or application scenarios.

[0011] In a possible implementation of the first aspect, the second electrode line includes a first sub-line and a second sub-line that are electrically connected, the first sub-line and the second sub-line are parallel to each other and spaced apart, a portion of the second dielectric layer is disposed between the conductive layer and the first sub-line, and another portion of the second dielectric layer is disposed between the conductive layer and the second sub-line.

[0012] The second electrode line is thus in electrical contact with only part of the second dielectric layer, thereby reducing the overlapping area among the second electrode line, the second dielectric layer and the conductive layer, so as to achieve the purpose of making the effective area of ​​the ferroelectric capacitor larger than the effective area of ​​the selection tube.

[0013] In a possible implementation of the first aspect, the second dielectric layer includes a first dielectric pattern and a second dielectric pattern that are spaced apart, the first dielectric pattern is disposed between the conductive layer and the first sub-line, and the second dielectric pattern is disposed between the conductive layer and the second sub-line. This can further ensure that the purpose of reducing the effective area of ​​the selection tube can be achieved.

[0014] In a possible implementation of the first aspect, the second electrode line is arranged on the inner side of the conductive layer; the second dielectric layer is arranged at least partially around the second electrode line and between the second electrode line and the conductive layer; the first dielectric layer is arranged around the conductive layer, and the first electrode line is arranged around the first dielectric layer.

[0015] That is, the relative positions of the ferroelectric capacitor and the selection tube can be flexibly set, so that the memory can be flexibly applied to a variety of different structures or application scenarios.

[0016] In a possible implementation manner of the first aspect, a height of the first dielectric layer is greater than a height of the second dielectric layer; the height refers to a dimension in an extension direction of a center line of the conductive layer.

[0017] By setting the height of the first dielectric layer greater than the height of the second dielectric layer, the overlapping area of ​​the first dielectric layer, the first electrode line and the conductive layer can be made greater than the overlapping area of ​​the second dielectric layer, the second electrode line and the conductive layer, that is, the effective area of ​​the ferroelectric capacitor is greater than the effective area of ​​the selection tube.

[0018] In a possible implementation of the first aspect, the second dielectric layer is annular or fan-shaped. When the second dielectric layer is fan-shaped, the memory further includes an insulating layer, which is disposed between the second electrode line and the conductive layer, and the insulating layer and the second dielectric layer are connected to form a ring.

[0019] That is, the second dielectric layer may be cut off so as to reduce the effective area of ​​the selection tube.

[0020] In a possible implementation manner of the first aspect, an overlapping area among the conductive layer, the first dielectric layer, and the first electrode line is greater than an overlapping area among the conductive layer, the second dielectric layer, and the second electrode line.

[0021] That is, the effective area of ​​the ferroelectric capacitor is larger than the effective area of ​​the selection tube, which can also make the capacitance value of the ferroelectric capacitor larger than the equivalent capacitance value of the selection tube.

[0022] In addition, the effective area of ​​the ferroelectric capacitor is as large as possible, so that the ferroelectric capacitor can flip out as much charge as possible. The area of ​​the selection tube is as small as possible, so that the off-state resistance (resistance value in the closed state) of the selection tube can be increased. The closed state selection tube can effectively limit the flow of charge in the storage unit and reduce the shunt of the read current, so that more storage units can be connected in parallel on the same bit line (such as the second electrode line), thereby increasing the storage density of the memory.

[0023] In a possible implementation of the first aspect, a ratio of an overlapping area among the conductive layer, the second dielectric layer, and the second electrode line to an overlapping area among the conductive layer, the first dielectric layer, and the first electrode line is less than 1:3.

[0024] In a possible implementation manner of the first aspect, the memory includes a plurality of storage units, each of which includes a conductive layer, a first dielectric layer, a second dielectric layer, a first electrode line, and a second electrode line.

[0025] Among the multiple storage cells, at least some of the storage cells are arranged along a third direction; the third direction is parallel to the center line of the conductive layer. The first target electrode line extends along the third direction, and the multiple storage cells arranged along the third direction share the first target electrode line; the first target electrode line is an electrode line arranged inside the conductive layer between the first electrode line and the second electrode line.

[0026] A plurality of second target electrode lines corresponding to a plurality of storage units sharing a first target electrode line are arranged along a third direction; the second target electrode line is an electrode line surrounding the outside of the conductive layer among the first electrode line and the second electrode line.

[0027] The plurality of storage units arranged along the third direction also share the first dielectric layer and the second dielectric layer.

[0028] In the memory provided in the embodiment of the present application, a plurality of storage units may be stacked in a third direction, which is beneficial to improving the storage density of the memory.

[0029] In a possible implementation of the first aspect, at least some of the multiple storage cells are arranged along a first direction; the first direction intersects with a third direction. The second target electrode line extends along the first direction, and the multiple storage cells arranged along the first direction share the second target electrode line.

[0030] In the memory provided by the embodiment of the present application, multiple storage units can also be arranged in a first direction to further improve the storage density of the memory.

[0031] In a possible implementation manner of the first aspect, the memory further includes a contact column electrically connected to the second target electrode line; an extension direction of the contact column is parallel to a center line of the conductive layer.

[0032] By providing a contact column and setting the extension direction of the contact column to be parallel to the center line of the conductive layer, the first electrode line and the second electrode line can be externally connected in the same direction.

[0033] In a possible implementation of the first aspect, the memory includes a core area and a step area, the step area is arranged on at least one side of the core area; the storage unit is arranged in the core area, the step area has a plurality of step surfaces, each step surface exposes a portion of a second target electrode line, and the exposed portion of the second target electrode line is electrically contacted with the contact column.

[0034] By providing the step area, the second target electrode lines can be smoothly connected to each other, thereby avoiding interference between adjacent second target electrode lines.

[0035] In a possible implementation of the first aspect, the memory further includes an interconnection layer and a circuit control layer, wherein the interconnection layer is disposed on a side of the conductive layer away from the substrate, and the circuit control layer is disposed on a side of the conductive layer close to the substrate.

[0036] In a second aspect, an electronic device is provided, the electronic device comprising an electronic device and a memory provided by any one of the embodiments in the first aspect. The electronic device is electrically connected to the memory.

[0037] The technical effects brought about by the electronic device in the second aspect can refer to the technical effects brought about by the design method of the memory in the first aspect, and will not be repeated here.

[0038] In a third aspect, a method for preparing a memory is provided, the method comprising: forming a stacked and alternately arranged sacrificial layer and an insulating layer on a substrate. Forming a through hole penetrating the sacrificial layer and the insulating layer, and etching the portion of the inner wall of the through hole belonging to the sacrificial layer. Forming a conductive layer, a first target dielectric layer, and a first target electrode line on the inner wall of the through hole in sequence; the first target electrode line fills the through hole. Forming a groove penetrating the sacrificial layer and the insulating layer between two adjacent through holes, and etching at least a portion of the sacrificial layer from the inner wall of the groove until at least a portion of the conductive layer is exposed; the groove is strip-shaped. Forming a second target dielectric layer and an initial electrode line on the inner wall of the groove in sequence; one of the first target dielectric layer and the second target dielectric layer has ferroelectricity, and the other has switching characteristics; the initial electrode line fills the groove. Cutting the initial electrode line in a direction perpendicular to the substrate to form a second target electrode line.

[0039] The memory preparation method provided in the embodiment of the present application has a low preparation difficulty and can realize the synchronous preparation of multiple storage units in the memory, thereby improving the preparation efficiency of the memory.

[0040] In a possible implementation of the third aspect, when a portion of the sacrificial layer is etched from an inner wall of the trench until a portion of the conductive layer close to the trench is exposed:

[0041] The initial electrode line is cut along the length extension direction of the groove and perpendicular to the direction of the substrate to form a second target electrode line, including: cutting the initial electrode line along the length extension direction of the groove and perpendicular to the direction of the substrate to form two sub-lines; electrically connecting two sub-lines that are arranged on both sides of the same through hole and belong to the two initial electrode lines to form a second target electrode line.

[0042] By means of the preparation method, the second target electrode line (ie, the second electrode line) can be prepared as an electrode line including two sub-lines, thereby reducing the effective area of ​​the selection tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0044] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0045] Figure 3 An exploded diagram of the structure of the memory provided in the embodiment of the present application;

[0046] Figure 4Another structural schematic diagram of a memory provided in an embodiment of the present application;

[0047] Figure 5 Another structural schematic diagram of a memory provided in an embodiment of the present application;

[0048] Figure 6 For along Figure 5 A cross-sectional view of the section line AA' in FIG.

[0049] Figure 7 Another structural schematic diagram of a memory provided in an embodiment of the present application;

[0050] Figure 8 Another structural schematic diagram of a memory provided in an embodiment of the present application;

[0051] Fig. 9 Another structural schematic diagram of a memory provided in an embodiment of the present application;

[0052] Fig.10 For along Fig. 9 A cross-sectional view of the section line BB' in FIG.

[0053] Fig.11 For along Fig. 9 A cross-sectional view of the section line CC' in FIG.

[0054] Fig.12 An equivalent circuit diagram of the memory provided in the embodiment of the present application;

[0055] Fig.13 For along Fig. 9 Another cross-sectional view of the section line BB' in FIG.

[0056] Fig.14 Another structural schematic diagram of a memory provided in an embodiment of the present application;

[0057] Fig.15 A flow chart of the preparation of the memory provided in the embodiment of the present application;

[0058] Figure 16 to Figure 31 A structural diagram corresponding to the steps of preparing the memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0060] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0061] Unless the context requires otherwise, throughout the specification and claims, the term "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0062] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0063] When describing some embodiments, the expressions "coupled" or "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The terms "coupled", "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0064] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0065] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0066] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0067] In addition, the scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that, with the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0068] The embodiment of the present application provides an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, a radar, an aerospace equipment, an on-board device, a vehicle, and other different types of user devices or terminal devices; the electronic device may also be a network device such as a base station. The embodiment of the present application does not impose any special restrictions on the specific form of the electronic device.

[0069] Figure 1A schematic diagram of the structure of an electronic device exemplarily provided in an embodiment of the present application.

[0070] For example, Figure 1 As shown, the electronic device 1000 may include a bus 205 and a system on chip (SoC) 210 connected to the bus 205 .

[0071] The system on chip 210 may be used to process data, such as processing application data, processing image data, and caching temporary data.

[0072] Exemplarily, the system on chip 210 may include an application processor (AP) 211 for processing application programs, a graphics processing unit (GPU) 212 for processing image data, and an on-chip memory (On-chip Memory) 213 for caching high-speed data.

[0073] Exemplarily, the on-chip memory 213 may be a static random access memory (SRAM) or an embedded flash (eflash).

[0074] Exemplarily, the application processor 211 , the image processing unit 212 , and the on-chip memory 213 may be integrated into one die, or may be separately disposed in a plurality of dies.

[0075] For example, Figure 1 As shown, the electronic device 1000 may further include an off-chip memory 220 connected to the on-chip system 210 via the bus 205 .

[0076] Exemplarily, the off-chip memory 220 may be a dynamic random access memory (DRAM). The off-chip memory 220 may be used to store volatile data, such as temporary data generated by the on-chip system 210. The storage capacity of the off-chip memory 220 is usually larger than that of the on-chip memory 213, but the reading speed is usually slower than that of the on-chip memory 213.

[0077] For example, the on-chip system 210 and the off-chip memory 220 may be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, to obtain a faster data transmission rate between chips.

[0078] For example, Figure 1 As shown, the electronic device 1000 may further include a communication chip 230 and a power management chip 240 connected to the system on chip 210 via the bus 205 .

[0079] The communication chip 230 can be used for processing the protocol stack, or amplifying and filtering analog radio frequency signals, or realizing the above functions at the same time. The power management chip 240 can be used to supply power to other chips.

[0080] Understandably, Figure 1 The structure of the electronic device 1000 shown in the figure does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include, for example, Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0081] The present application also provides a memory 100, which can be applied to the electronic device 1000. For example, the memory 100 can be Figure 1 Alternatively, the memory 100 may be an on-chip memory 213 as shown. Figure 1 The off-chip memory 220 is shown. The embodiment of the present application does not limit the specific application scenario of the memory 100.

[0082] Figure 2 and Figure 4 A schematic diagram of the structure of the memory 100 provided in an embodiment of the present application. Figure 3 It is a structural explosion diagram of the memory 100 provided in the embodiment of the present application.

[0083] like Figure 2 , Figure 3 and Figure 4 As shown, the memory 100 includes a substrate 10 , a conductive layer 20 , a first dielectric layer 30 , a second dielectric layer 40 , a first electrode line 50 , and a second electrode line 60 .

[0084] Among them, illustratively, the material of the substrate 10 may include single crystal silicon (Si), single crystal germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), III-V compound semiconductor materials, II-VI compound semiconductor materials or at least one of other semiconductor materials known in the art, or may also be made of non-conductive materials such as glass, plastic or sapphire wafers.

[0085] See also Figure 2 , Figure 3 and Figure 4The conductive layer 20 is disposed on one side of the substrate 10, and the conductive layer 20 is disposed in a ring shape.

[0086] See also Figure 2 , Figure 3 and Figure 4 , the center line Li of the conductive layer 20 intersects with the substrate 10 , for example, the center line Li of the conductive layer 20 can be arranged perpendicular to the substrate 10 .

[0087] Exemplarily, the conductive layer 20 may be arranged in a circular ring shape or a square ring shape. Figure 2 The conductive layer 20 is only taken as a circular ring as an example for schematic description, and the embodiment of the present application does not limit the specific ring shape of the conductive layer 20.

[0088] Exemplarily, the material of the conductive layer 20 may be a semiconductor material or a metal material. For example, the material of the conductive layer 20 may be polysilicon (Poly-Si), titanium nitride (TiN), tungsten (W) or molybdenum (Mo).

[0089] It can be understood that the annular conductive layer 20 has an inner side and an outer side. The side close to the center line Li of the conductive layer 20 is the inner side, and the side away from the center line Li of the conductive layer 20 is the outer side.

[0090] In this embodiment, one of the first dielectric layer 30 and the second dielectric layer 40 is disposed on the inner side of the conductive layer 20 , and the other surrounds the outer side of the conductive layer 20 .

[0091] For example, see Figure 2 and Figure 3 , the first dielectric layer 30 is disposed on the inner side of the conductive layer 20 , and the second dielectric layer 40 is disposed on the outer side of the conductive layer 20 .

[0092] Or, for example, see Figure 4 , the second dielectric layer 40 is disposed on the inner side of the conductive layer 20 , and the first dielectric layer 30 is disposed on the outer side of the conductive layer 20 .

[0093] The first dielectric layer 30 has ferroelectricity, that is, the first dielectric layer 30 has spontaneous polarization within a certain temperature range, and the direction of the spontaneous polarization can be reversed due to the reversal of the direction of the external electric field.

[0094] For example, the material of the first dielectric layer 30 may be a ferroelectric material based on a hafnium oxide (HfO) material system. For example, the material of the first dielectric layer 30 may be zirconium (Zr)-doped hafnium oxide (HfO2), silicon (Si)-doped HfO2, aluminum (Al)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, gadolinium (Gd)-doped HfO2, strontium (Sr)-doped HfO2, etc.

[0095] Alternatively, the material of the first dielectric layer 30 may also be a ferroelectric material of the hafnium zirconium oxide (HZO) material system. For example, the material of the first dielectric layer 30 may be lanthanum (La)-doped HZO, yttrium (Y)-doped HZO, strontium (Sr)-doped HZO, gadolinium (Gd)-doped HZO, gadolinium-lanthanum (Gd / La) co-doped HZO, etc. The doping element may also be one or more of nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium, gallium, calcium, and carbon.

[0096] Alternatively, the material of the first dielectric layer 30 may also be a ferroelectric material from a material system such as hafnium silicon oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium lanthanum oxide, hafnium zirconium cerium oxide, hafnium zirconium yttrium oxide, or hafnium zirconium gadolinium oxide.

[0097] Exemplarily, the first dielectric layer 30 may be a single-layer structure or a multi-layer structure. In the case where the first dielectric layer 30 is a multi-layer structure, the materials of different layers may be the same or different.

[0098] The second dielectric layer 40 has a switching characteristic, that is, the resistance of the second dielectric layer 40 can change with the applied voltage, so that the current flowing through the second dielectric layer 40 changes nonlinearly and reversibly, thereby realizing the switching function.

[0099] For example, as the applied voltage changes, the resistance of the second dielectric layer 40 changes, and the second dielectric layer 40 reversibly enters a high resistance state or a low resistance state. For example, when the second dielectric layer 40 is greater than a threshold resistance, the second dielectric layer 40 enters a high resistance state, and vice versa. The threshold resistance may be, for example, 1E9 ohm.

[0100] Exemplarily, the material of the second dielectric layer 40 may include a phase change material. The phase change material has a low resistance property in a crystalline state and a high resistance property in an amorphous state. Therefore, the switching function of the second dielectric layer 40 can be realized by a set operation of switching the state of the phase change material from a high resistance amorphous state to a low resistance crystalline state and a reset operation of switching the state of the phase change material from a low resistance crystalline state to a high resistance amorphous state.

[0101] Exemplarily, the material of the second dielectric layer 40 may include silicon (Si) or silicon compounds, germanium (Ge) or germanium compounds, or any combination thereof, such as amorphous silicon (a-Si).

[0102] Alternatively, illustratively, the material of the second dielectric layer 40 may include a metal oxide. For example, the material of the second dielectric layer 40 includes at least one of tantalum oxide (Ta2O5), niobium oxide (Nb2O5), titanium dioxide (TiO2), hafnium dioxide (HfO2), or indium gallium zinc oxide (IGZO).

[0103] Alternatively, illustratively, the material of the second dielectric layer 40 may also include a PNP junction, an NPN junction, a back-to-back Schottky junction, or an Ovonic Threshold Switching (OST), etc.

[0104] It can be understood that the embodiment of the present application does not limit the specific material of the second dielectric layer 40 , and any material that can achieve the selected function is within the protection scope of the present application.

[0105] For example, the second dielectric layer 40 may be in a fan-shaped ring shape (see Figure 2 , Figure 3 , Figure 7 and Figure 8 ), or the second dielectric layer 40 may be annular (see Figure 4 and Figure 5 ).

[0106] In this embodiment, refer to Figure 2 , Figure 3 and Figure 4 The first electrode line 50 is disposed on a side of the first dielectric layer 30 away from the conductive layer 20 , and the second electrode line 60 is disposed on a side of the second dielectric layer 40 away from the conductive layer 20 .

[0107] That is, the first dielectric layer 30 is disposed between the conductive layer 20 and the first electrode line 50, and the second dielectric layer 40 is disposed between the conductive layer 20 and the second electrode line 60, so that the first electrode line 50, the first dielectric layer 30 and the conductive layer 20 form a ferroelectric capacitor FC (FeCap), and the second electrode line 60, the second dielectric layer 40 and the conductive layer 20 form a selector S (Selector).

[0108] For example, when the second electrode line 60 is disposed outside the conductive layer 20, the second electrode line 60 may be in the form of an integrally disposed strip (see Figure 5 and Figure 8 ), or the second electrode line 60 may include two sub-lines spaced apart (see Figure 2 and Figure 3 ).

[0109] See also Figure 2 , Figure 3 and Figure 4 It can be seen that the ferroelectric capacitor FC and the selection tube S share one electrode (ie, the conductive layer 20 ), which is equivalent to the ferroelectric capacitor FC and the selection tube S being connected in series.

[0110] Since the second dielectric layer 40 has a switching characteristic, the selection tube S has a switching function. When a voltage is applied to the first electrode line 50 and the second electrode line 60 to form an electric field, the selection tube S can be turned on, so that the conductive layer 20 is filled with electric charges. After the selection tube S is turned on, the resistance of the selection tube S decreases (low resistance state), and most of the voltage in the electric field is loaded on the ferroelectric capacitor FC, so that the first dielectric layer 30 in the ferroelectric capacitor FC can be polarized. Reversal occurs.

[0111] By controlling the voltage applied to the first electrode line 50 and / or the second electrode line 60, the polarization direction of the first dielectric layer 30 in the ferroelectric capacitor FC is controlled, and different polarization directions correspond to different information states (eg, "1" or "0").

[0112] For example, the first electrode line 50 can be used as a word line (WL), and the second electrode line 60 can be used as a bit line. By transmitting different electrical signals to the first electrode line 50 and the second electrode line 60, information writing and information reading of the memory 100 can be realized.

[0113] Writing information means that by applying voltage differences of different polarities to the first electrode line 50 and the second electrode line 60 in the memory 100, the polarization direction of the ferroelectric capacitor FC in the memory 100 is changed to achieve writing of information (eg, "1" or "0").

[0114] Reading information means applying voltage to the first electrode line 50 and the second electrode line 60 in the memory 100 and reading the corresponding current on the bit line BL (eg, the second electrode line 60) of the memory 100, thereby reading information according to the magnitude of the current.

[0115] In the 1S1C memory provided by the related art, the film layers of the selection tube and the capacitor are stacked along a preset direction (for example, a direction perpendicular to the substrate), so that the design space occupied by the memory is relatively large, which is not conducive to improving the storage density of the memory.

[0116] In the memory 100 provided in the embodiment of the present application, by setting a ring-shaped conductive layer 20, and stacking film layers such as a first dielectric layer 30 and a second dielectric layer 40 on the inner and outer sides of the conductive layer 20, compared with the related art, the memory 100 in the present application can achieve a three-dimensional setting, that is, the design space occupied in the direction parallel to the substrate 10 is reduced, thereby facilitating the improvement of the storage density of the memory 100.

[0117] In the memory 100 provided in the embodiment of the present application, the positions of the ferroelectric capacitor FC and the selection tube S can be flexibly set.

[0118] For example, see Figure 2 and Figure 3 The first electrode line 50 is disposed inside the conductive layer 20, the first dielectric layer 30 is disposed around the first electrode line 50 and disposed between the first electrode line 50 and the conductive layer 20. The second dielectric layer 40 is at least partially disposed around the conductive layer 20, and the second electrode line 60 is at least partially disposed around the second dielectric layer 40.

[0119] That is, the ferroelectric capacitor FC is arranged inside, and the selection tube S is arranged around the ferroelectric capacitor FC.

[0120] Or, for example, see Figure 4 The second electrode line 60 is disposed inside the conductive layer 20, and the second dielectric layer 40 is disposed at least partially around the second electrode line 60 and between the second electrode line 60 and the conductive layer 20. The first dielectric layer 30 is disposed around the conductive layer 20, and at least part of the first electrode line 50 is disposed around the first dielectric layer 30.

[0121] That is, the selection tube S is arranged on the inner side, and the ferroelectric capacitor FC is arranged around the selection tube S.

[0122] It is understandable that the aforementioned “the second dielectric layer 40 is at least partially disposed around the conductive layer 20” may include a situation where the second dielectric layer 40 is partially disposed around the conductive layer 20, for example, the second dielectric layer 40 is in a fan-shaped ring shape (see Figure 2 , Figure 3 , Figure 7 and Figure 8 ), the conductive layer 20 is disposed inside the second dielectric layer 40, and the inner surface of the second dielectric layer 40 surrounds and adheres to the outer surface of the conductive layer 20, that is, the outer surface of the conductive layer 20 is not entirely wrapped by the second dielectric layer 40. Alternatively, the second dielectric layer 40 may be disposed completely around the conductive layer 20, for example, the second dielectric layer 40 is annular (see Figure 4 and Figure 5), the conductive layer 20 is disposed inside the second dielectric layer 40, and the inner surface of the second dielectric layer 40 surrounds and adheres to the outer surface of the conductive layer 20. The aforementioned “the second dielectric layer 40 is at least partially disposed around the second electrode line 60” is similar.

[0123] By flexibly setting the relative positions of the ferroelectric capacitor FC and the selection tube S, the memory 100 can be flexibly adapted to a variety of different structures or application scenarios.

[0124] In some embodiments, the capacitance value of the ferroelectric capacitor FC is greater than the equivalent capacitance value of the selection transistor S.

[0125] It can be understood that the calculation formula for the capacitance value is Wherein, C is the capacitance value, ε is the dielectric constant of the dielectric layer between the two capacitor plates, S is the effective area of ​​the device (i.e., the overlapping area of ​​the two capacitor plates and the dielectric layer), and d is the distance between the two capacitor plates.

[0126] It can be seen that the capacitance of the ferroelectric capacitor FC depends on the dielectric constant of the first dielectric layer 30 , the overlapping area between the first electrode line 50 , the conductive layer 20 and the first dielectric layer 30 , and the distance between the first electrode line 50 and the conductive layer 20 .

[0127] The aforementioned “equivalent capacitance value of the selection tube S” means that although the selection tube S does not act as a capacitor, it can be equivalent to a capacitor, and the charge capacity that can be generated by its two electrodes (the second electrode line 60 and the conductive layer 20) can be reflected by the equivalent capacitance value. Therefore, the calculation method of its equivalent capacitance value can refer to the calculation method of the capacitance value of a traditional capacitor (such as a ferroelectric capacitor FC), that is, the capacitance value of the selection tube S depends on the dielectric constant of the second dielectric layer 40, the overlapping area among the second electrode line 60, the conductive layer 20 and the second dielectric layer 40, and the distance between the second electrode line 60 and the conductive layer 20.

[0128] The memory 100 may include a plurality of storage units G (see Fig. 9 ), each memory cell G includes the above-mentioned conductive layer 20, the first dielectric layer 30, the second dielectric layer 40, the first electrode line 50 and the second electrode line 60, wherein at least some of the memory cells G share a word line or a bit line (i.e., share the first electrode line 50 or the second electrode line 60).

[0129] During the process of writing information, after applying an operating voltage (read-write voltage) to the first electrode line 50 and the second electrode line 60, the selection tube S in the selected storage cell G is turned on, and there is a crosstalk voltage of half the operating voltage at both ends of the storage cell G (unselected storage cell G) that shares the same first electrode line 50 or second electrode line 60 with the selected storage cell G. In order to prevent the unselected storage cell G from being turned on unexpectedly under the action of the crosstalk voltage, the on-state threshold voltage of the selection tube S (the voltage that can turn on the selection tube S) needs to be greater than the crosstalk voltage, but needs to be less than the operating voltage (to ensure that it can be turned on when selected).

[0130] In the reading and writing (reading and writing) state of information, at the moment the operating voltage is applied, the selection tube S and the ferroelectric capacitor FC will divide the operating voltage. In the relevant technology, the effective area, dielectric constant, etc. of the selection tube and the ferroelectric capacitor are roughly the same, that is, the capacitance value of the selection tube and the equivalent capacitance value of the ferroelectric capacitor are roughly equal, and the impedance of the two is equivalent, resulting in the voltage division of the selection tube being equal to or even less than half of the operating voltage. This requires that the on-state threshold voltage of the selection tube be less than half of the operating voltage to achieve the turning on of the selection tube.

[0131] It can be seen that in the related art, if the on-state threshold voltage of the selection tube is greater than half of the operating voltage, the selection tube will not be able to be turned on (the voltage division is too small), and if the on-state threshold voltage of the selection tube is less than half of the operating voltage, the unselected storage unit G will remain in the on state under the action of the crosstalk voltage (half of the operating voltage). That is, it is difficult for the memory to take into account both the read and write performance and the anti-crosstalk performance, resulting in serious crosstalk problems.

[0132] The embodiment of the present application sets the capacitance value of the ferroelectric capacitor FC to be greater than the equivalent capacitance value of the selection tube S, so that during the reading and writing process, the impedance of the selection tube S is larger and the voltage division is also larger (greater than half of the operating voltage), so that the on-state threshold voltage of the selection tube S can be set within a range that can take into account both the reading and writing performance and the anti-crosstalk performance, that is, the on-state threshold voltage of the selection tube S can be greater than half of the operating voltage and less than the operating voltage, so that the storage unit G can be smoothly turned on when it is selected, and will not be turned on unexpectedly under the action of the crosstalk voltage when it is not selected.

[0133] The embodiments of the present application provide a variety of implementation methods to achieve the purpose of making the capacitance value of the ferroelectric capacitor FC greater than the equivalent capacitance value of the selection tube S, as described in detail below.

[0134] In some embodiments, the thickness of the first dielectric layer 30 is smaller than the thickness of the second dielectric layer 40 .

[0135] That is, the distance between the first electrode line 50 and the conductive layer 20 is smaller than the distance between the second electrode line 60 and the conductive layer 20 , so that the capacitance value of the ferroelectric capacitor FC is greater than the equivalent capacitance value of the selection transistor S.

[0136] In some embodiments, the dielectric constant of the first dielectric layer 30 is greater than the dielectric constant of the second dielectric layer 40 , which can also make the capacitance value of the ferroelectric capacitor FC greater than the equivalent capacitance value of the selection transistor S.

[0137] In some embodiments, the overlapping area among the conductive layer 20 , the first dielectric layer 30 , and the first electrode line 50 is greater than the overlapping area among the conductive layer 20 , the second dielectric layer 40 , and the second electrode line 60 .

[0138] That is, the effective area of ​​the ferroelectric capacitor FC is larger than the effective area of ​​the selection tube S, and the capacitance value of the ferroelectric capacitor FC can also be larger than the equivalent capacitance value of the selection tube S.

[0139] In addition, the effective area of ​​the ferroelectric capacitor FC is as large as possible, so that the ferroelectric capacitor FC can flip out as much charge as possible. The area of ​​the selection tube S is as small as possible, so that the off-state resistance (resistance value in the closed state) of the selection tube S can be increased. The selection tube S in the closed state can effectively limit the flow of charge in the storage unit G and reduce the shunt of the read current, so that more storage units G can be connected in parallel on the same bit line (such as the second electrode line 60), thereby increasing the storage density of the memory 100.

[0140] Exemplarily, the ratio of the overlapping area among the conductive layer 20 , the second dielectric layer 40 and the second electrode line 60 to the overlapping area among the conductive layer 20 , the first dielectric layer 30 and the first electrode line 50 is less than 1:3.

[0141] For example, the ratio may be 1:3, 1:4.5, 1:6.75 or 1:7, etc.

[0142] That is, the effective area of ​​the ferroelectric capacitor FC is more than 3 times the effective area of ​​the selection tube S, for example, 3 times, 5.6 times or 7 times, thereby ensuring that at the moment of loading the voltage, most of the operating voltage is loaded on the selection tube S (for example, three quarters or seven eighths of the operating voltage, etc.), which is much larger than one half of the operating voltage. On the one hand, the window of the on-state threshold voltage of the selection tube S can be increased, and on the other hand, the instantaneous opening of the selection tube S can be achieved, thereby improving the read and write speed of the memory 100.

[0143] In addition, it can also be ensured that, after the selection tube S is turned on, most of the operating voltage is loaded on the ferroelectric capacitor FC, which helps the ferroelectric capacitor FC to quickly achieve polarization reversal and further improve the reading and writing speed of the memory 100.

[0144] like Figure 5 , Figure 7 and Figure 8 Some other structural schematic diagrams of the memory 100 provided in the embodiments of the present application, Figure 6 For along Figure 5 Cross-sectional view along section line AA'.

[0145] The embodiments of the present application provide a variety of design methods to achieve the purpose of selecting the effective area of ​​the tube S to be smaller than the effective area of ​​the ferroelectric capacitor FC. The specific design methods are described below.

[0146] In some embodiments, Figure 4 As shown, the first dielectric layer 30 and the first electrode line 50 are arranged on the outside of the conductive layer 20, and the second dielectric layer 40 and the second electrode line 60 are arranged on the inside of the conductive layer 20. Since the outer area of ​​the annular conductive layer 20 is necessarily larger than the inner area, the area of ​​the second dielectric layer 40 and the second electrode line 60 arranged on the inner side is smaller, and the area of ​​the first dielectric layer 30 and the first electrode line 50 arranged on the outer side is larger, that is, the purpose of achieving the effective area of ​​the ferroelectric capacitor FC on the outer side being larger than the effective area of ​​the selection tube S on the inner side is achieved.

[0147] Exemplarily, in this embodiment, the difference between the effective area of ​​the outer ferroelectric capacitor FC and the effective area of ​​the inner selection tube S can also be controlled by controlling the thickness of the conductive layer 20. For example, the outer ring diameter of the conductive layer 20 can be set to be twice the inner ring diameter, so that the effective area of ​​the outer ferroelectric capacitor FC is larger than the effective area of ​​the inner selection tube S.

[0148] In other embodiments, Figure 2 and Figure 3 As shown, the effective area of ​​the ferroelectric capacitor FC can be made larger than the effective area of ​​the selection tube S by dividing the second electrode line 60 into two sub-lines to reduce the area of ​​the second electrode line 60 used to contact the second dielectric layer 40.

[0149] See also Figure 2 and Figure 3 The second electrode line 60 includes a first sub-line 61 and a second sub-line 62. The first sub-line 61 and the second sub-line 62 are parallel to each other and spaced apart. A portion of the second dielectric layer 40 is disposed between the conductive layer 20 and the first sub-line 61, and another portion of the second dielectric layer 40 is disposed between the conductive layer 20 and the second sub-line 62.

[0150] That is, the second electrode line 60 only has a facing area with a portion of the outer surface of the conductive layer 20 , thereby reducing the overlapping area among the second electrode line 60 , the second dielectric layer 40 and the conductive layer 20 .

[0151] The first sub-line 61 and the second sub-line 62 are electrically connected, for example, see Figure 2 and Figure 3 The first sub-wire 61 and the second sub-wire 62 are electrically connected via the connection structure N. Alternatively, the first sub-wire 61 and the second sub-wire 62 may also be electrically connected via an interconnection layer 80 (see Fig.13 ) or conductive patterns in other film layers to achieve electrical connection.

[0152] That is, the first sub-line 61 and the second sub-line 62 transmit the same signal at the same time, and both serve as electrodes of the selection tube S.

[0153] Exemplarily, the first sub-line 61 and the second sub-line 62 may be provided with insulating material, and the connection structure N may penetrate the insulating material so that the first sub-line 61 and the second sub-line 62 can be electrically connected at a preset position to avoid unexpected electrical connection or crosstalk.

[0154] For example, see Figure 2 and Figure 3 When the second electrode line 60 is arranged outside the conductive layer 20 and the second electrode line 60 includes a first sub-line 61 and a second sub-line 62, the second dielectric layer 40 includes a first dielectric pattern 41 and a second dielectric pattern 42 arranged at intervals, the first dielectric pattern 41 is arranged between the conductive layer 20 and the first sub-line 61, and the second dielectric pattern 42 is arranged between the conductive layer 20 and the second sub-line 62.

[0155] For example, see Figure 2 , the first dielectric pattern 41 and the second dielectric pattern 42 are disconnected from each other, and the cross-section surfaces (surfaces at the disconnection positions) of the first dielectric pattern 41 and the second dielectric pattern 42 are flush with the surfaces opposite to the first sub-line 61 and the second sub-line 62. This structure can reduce the difficulty of manufacturing the memory 100, and can ensure that the effective area of ​​the selection tube S is reduced.

[0156] Alternatively, illustratively, the cross-section of the first dielectric pattern 41 is recessed relative to the surface of the first sub-line 61 opposite to the second sub-line 62 , that is, the area of ​​the first dielectric pattern 41 is further reduced, thereby further reducing the effective area of ​​the selection tube S. The second dielectric pattern 42 is similar.

[0157] It can be understood that an insulating material is filled between the first dielectric pattern 41 and the second dielectric pattern 42 to achieve disconnection between the two.

[0158] In other embodiments, Figure 5 and Figure 6 As shown, the height H1 of the first dielectric layer 30 is greater than the height H2 of the second dielectric layer 40 .

[0159] Here, “height” refers to the dimensions of the first dielectric layer 30 and the second dielectric layer 40 in the extension direction of the center line Li of the conductive layer 20 .

[0160] By setting the height H1 of the first dielectric layer 30 to be greater than the height H2 of the second dielectric layer 40, the overlapping area of ​​the first dielectric layer 30, the first electrode line 50 and the conductive layer 20 can be greater than the overlapping area of ​​the second dielectric layer 40, the second electrode line 60 and the conductive layer 20, that is, the effective area of ​​the ferroelectric capacitor FC is greater than the effective area of ​​the selection tube S.

[0161] Figure 5 It is only exemplarily shown that in the case where the first dielectric layer 30 is located on the inner side of the conductive layer 20 and the second dielectric layer 40 is located on the outer side of the conductive layer 20, the height H1 of the first dielectric layer 30 is greater than the height H2 of the second dielectric layer 40. It can be understood that in the case where the first dielectric layer 30 is located on the outer side of the conductive layer 20 and the second dielectric layer 40 is located on the inner side of the conductive layer 20, the present design mode (the height H1 of the first dielectric layer 30 is greater than the height H2 of the second dielectric layer 40) is still applicable.

[0162] In other embodiments, Figure 7 and Figure 8 As shown, the second dielectric layer 40 is in a fan-shaped ring shape. Figure 7 and Figure 8 , the second dielectric layer 40 is in contact with only a portion of the side surface of the conductive layer 20 .

[0163] Here, "sector ring" refers to a part of a ring, for example, it can be a figure obtained by cutting off a part of a circular ring, of course, it can also be a figure obtained by cutting off a part of a square ring or a ring of other shapes.

[0164] “The second dielectric layer 40 contacts only a portion of the side surface of the conductive layer 20” means that the second dielectric layer 40 does not contact the entire area of ​​the side surface of the conductive layer 20. For example, Figure 8 In the case where the second dielectric layer 40 is disposed outside the conductive layer 20, the second dielectric layer 40 is partially disposed around the conductive layer 20, or for example, see Figure 7 In the case where the second dielectric layer 40 is disposed on the inner side of the conductive layer 20 , the second dielectric layer 40 is in contact with only a portion of the inner surface of the conductive layer 20 .

[0165] That is, the second dielectric layer 40 is cut off along a direction perpendicular to the substrate 10, thereby reducing the area of ​​the second dielectric layer 40, so that the overlapping area among the second dielectric layer 40, the second electrode line 60 and the conductive layer 20 is reduced, so as to achieve the purpose of making the effective area of ​​the ferroelectric capacitor FC larger than the effective area of ​​the selection tube S.

[0166] Among them, see Figure 7 and Figure 8 The memory 100 further includes an insulating layer 70 (a first insulating layer 71 or a second insulating layer 72 ), which is disposed between the second electrode line 60 and the conductive layer 20 . The insulating layer 70 is connected to the second dielectric layer 40 and together forms a ring.

[0167] For example, see Figure 7 In the case where the second dielectric layer 40 is disposed inside the conductive layer 20 and the second dielectric layer 40 is cut off, the memory 100 further includes a first insulating layer 71. The first insulating layer 71 has electrical insulating properties.

[0168] See also Figure 7 The first insulating layer 71 is disposed between the second electrode line 60 and the conductive layer 20 . The first insulating layer 71 is connected to the second dielectric layer 40 and together form a ring around the second electrode line 60 .

[0169] That is, after the second dielectric layer 40 is cut off to reduce the effective area of ​​the selection tube S, the first insulating layer 71 is filled at the cut-off position of the second dielectric layer 40 to prevent the conductive layer 20 from directly electrically contacting the second electrode line 60 at that position.

[0170] Similarly, see Figure 8 In the case where the second dielectric layer 40 is disposed outside the conductive layer 20, the second dielectric layer 40 is cut off, and the second electrode line 60 surrounds the entire second dielectric layer 40, the memory 100 further includes a second insulating layer 72. The second insulating layer 72 has electrical insulation properties.

[0171] See also Figure 8 The second insulating layer 72 is disposed between the second electrode line 60 and the conductive layer 20 . The second insulating layer 72 is connected to the second dielectric layer 40 and together they form a ring surrounding the conductive layer 20 .

[0172] That is, after the second dielectric layer 40 is cut off to reduce the effective area of ​​the selection tube S, the second insulating layer 72 is filled at the cut-off position of the second dielectric layer 40 to prevent the conductive layer 20 from directly electrically contacting the second electrode line 60 at that position.

[0173] For example, Figure 5 and Figure 8 As shown, the second electrode line 60 may also be in a complete long strip shape, and the first electrode line 50 , the first dielectric layer 30 , the conductive layer 20 and the second dielectric layer 40 may be arranged through the second electrode line 60 .

[0174] It is understandable that the aforementioned various embodiments can be combined at will to flexibly control the difference between the capacitance value of the ferroelectric capacitor FC and the equivalent capacitance value of the selection tube S. For example, when the dielectric constant of the first dielectric layer 30 is greater than the dielectric constant of the second dielectric layer 40, the effective area of ​​the ferroelectric capacitor FC can be set to be greater than the effective area of ​​the selection tube S. For example, referring to Figure 2 In the case where the second dielectric layer 40 is disposed outside the conductive layer 20, the second dielectric layer 40 can be cut off (i.e., the second dielectric layer 40 is in a fan-shaped shape), and the second electrode line 60 is configured to include a first sub-line 61 and a second sub-line 62, thereby reducing the effective area of ​​the selection tube S through various design methods. Other combination methods are similar and will not be described in detail here.

[0175] Fig. 9 Another structural diagram of the memory 100 provided in an embodiment of the present application is shown in FIG. Fig.10 For along Fig. 9 The cross-sectional view of the section line BB' in Fig.11 For along Fig. 9 Cross-sectional view along section line CC'.

[0176] In some embodiments, Fig. 9 , Fig.10 and Fig.11 As shown, the memory 100 includes a plurality of memory cells G, each of which includes a conductive layer 20 , a first dielectric layer 30 , a second dielectric layer 40 , a first electrode line 50 and a second electrode line 60 .

[0177] See also Fig. 9 and Fig.10 Among the multiple storage cells G, at least some of the storage cells G are arranged along a third direction Z.

[0178] The third direction Z is parallel to the center line Li of the conductive layer 20. Fig. 9 , the center line Li of the conductive layer 20 and the third direction Z are both perpendicular to the substrate 10 .

[0179] In the memory 100 provided in the embodiment of the present application, a plurality of memory cells G may be stacked in a third direction Z, which is beneficial to improving the storage density of the memory 100 .

[0180] See also Fig. 9 and Fig.10 The first target electrode line L1 extends along the third direction Z, and a plurality of memory cells G arranged along the third direction Z share the first target electrode line L1.

[0181] The first target electrode line L1 is the electrode line of the first electrode line 50 and the second electrode line 60, which is arranged inside the conductive layer 20. For example, when the first electrode line 50 and the first dielectric layer 30 are arranged inside the conductive layer 20, and the second electrode line 60 and the second dielectric layer 40 are arranged outside the conductive layer 20, the first target electrode line L1 is the first electrode line 50; conversely, when the second electrode line 60 and the second dielectric layer 40 are arranged inside the conductive layer 20, and the first electrode line 50 and the first dielectric layer 30 are arranged outside the conductive layer 20, the first target electrode line L1 is the second electrode line 60.

[0182] By sharing the first target electrode line L1 , electrical signals may be transmitted to a plurality of memory cells G arranged along the third direction Z at the same time.

[0183] See also Fig. 9 and Fig.10 The plurality of second target electrode lines L2 corresponding to the plurality of storage units G sharing one first target electrode line L1 are arranged along the third direction X.

[0184] The second target electrode line L2 is the electrode line of the first electrode line 50 and the second electrode line 60, which is arranged outside the conductive layer 20. For example, when the first electrode line 50 and the first dielectric layer 30 are arranged inside the conductive layer 20, and the second electrode line 60 and the second dielectric layer 40 are arranged outside the conductive layer 20, the second target electrode line L2 is the second electrode line 60; conversely, when the second electrode line 60 and the second dielectric layer 40 are arranged inside the conductive layer 20, and the first electrode line 50 and the first dielectric layer 30 are arranged outside the conductive layer 20, the second target electrode line L2 is the first electrode line 50.

[0185] See also Fig.10 The plurality of memory cells G arranged along the third direction Z can also share the first dielectric layer 30 and the second dielectric layer 40. This facilitates the synchronous preparation of the plurality of memory cells G arranged along the third direction Z, and reduces the difficulty of preparing the memory 100.

[0186] For example, see Fig.10 The memory 100 further includes an insulating layer 70. The insulating layer 70 is used to wrap the conductive structure of the memory 100 to prevent the conductive structure of the memory 100 from having unexpected electrical connections. Fig.10 , a portion of the insulating layer 70 may be disposed between two second target electrode lines L2 adjacently disposed along the third direction Z.

[0187] In some embodiments, Fig. 9 and Fig.11As shown, in the case where the memory 100 includes a plurality of memory cells G, at least some of the memory cells G are arranged along the first direction X.

[0188] The first direction X intersects with the third direction Z. For example, see Fig. 9 and Fig.11 , the first direction X and the third direction Z are perpendicular to each other.

[0189] In the memory 100 provided in the embodiment of the present application, a plurality of storage units G may be arranged in an array in the first direction X to further improve the storage density of the memory 100 .

[0190] See also Fig. 9 and Fig.11 The second target electrode line L2 extends along the first direction X, and a plurality of memory cells G arranged along the first direction X share the second target electrode line L2.

[0191] By sharing the second target electrode line L2 , electrical signals can be transmitted to a plurality of memory cells G arranged along the first direction X at the same time.

[0192] In some embodiments, Fig. 9 As shown, in the case where the memory 100 includes a plurality of memory cells G, at least some of the memory cells G are arranged along the second direction Y.

[0193] The second direction Y intersects the first direction X and the third direction Z. For example, the first direction X, the second direction Y and the third direction Z are arranged perpendicular to each other.

[0194] For example, see Fig. 9 , a plurality of memory cells G are arranged in a row along a first direction X, and a plurality of rows of memory cells G are arranged along a second direction Y.

[0195] In the memory 100 provided in the embodiment of the present application, a plurality of storage units G may be arranged in an arrangement in the second direction Y to further improve the storage density of the memory 100 .

[0196] Fig.12 An equivalent circuit diagram of the memory 100 provided in an embodiment of the present application.

[0197] See also Fig.12In the process of information reading and writing, by transmitting an electrical signal to the first target electrode line L1, a plurality of storage cells G stacked along the third direction Z can be selected; by transmitting an electrical signal to the second target electrode line L2, a plurality of storage cells G stacked along the first direction X can be selected; and by transmitting an electrical signal to the first target electrode line L1 and the second target electrode line L2 at the same time, a specific storage cell G can be selected, thereby facilitating data reading or data writing to the specific storage cell G.

[0198] Fig.13 For along Fig. 9 Another cross-sectional view of the section line BB' in FIG. Fig.14 Another structural schematic diagram of the memory 100 provided in an embodiment of the present application.

[0199] In some embodiments, Fig.13 As shown, the memory 100 further includes an interconnection layer 80 . The interconnection layer 80 is disposed on a side of the conductive layer 20 away from the substrate 10 .

[0200] The interconnection layer 80 is used to connect various conductive structures in the memory 100 to form a complete circuit or system, or the interconnection layer 80 is also used to form a contact point connected to a power source outside the memory 100.

[0201] For example, the interconnection layer 80 may include a first contact and a second contact, the first contact is electrically connected to the first electrode line 50, the second contact is electrically connected to the second electrode line 60, and the first contact is used to receive an external first power signal, and the second contact is used to receive an external second power signal, so as to transmit the first power signal to the first electrode line 50 and the second power signal to the second electrode line 60. The voltages of the first power signal and the second power signal are different.

[0202] In some embodiments, Fig.13 As shown, the memory 100 further includes a circuit control layer 90, which is disposed on a side of the conductive layer close to the substrate.

[0203] Exemplarily, the circuit control layer 90 includes a decoder, a decoder, a signal amplifier, an address circuit, and the like.

[0204] In some embodiments, Fig.14 As shown, the memory 100 further includes a contact column 11 .

[0205] See also Fig.14The contact column 11 is electrically connected to the electrode line (i.e., the second target electrode line L2) disposed outside the conductive layer 20 among the first electrode line 50 and the second electrode line 60. For example, when the first electrode line 50 and the first dielectric layer 30 are disposed inside the conductive layer 20, and the second electrode line 60 and the second dielectric layer 40 are disposed outside the conductive layer 20, the contact column 11 is electrically connected to the second electrode line 60. Conversely, when the second electrode line 60 and the second dielectric layer 40 are disposed inside the conductive layer 20, and the first electrode line 50 and the first dielectric layer 30 are disposed outside the conductive layer 20, the contact column 11 is electrically connected to the first electrode line 50.

[0206] See also Fig.14 The extension direction of the contact pillar 11 is parallel to the center line Li of the conductive layer 20 .

[0207] By setting the contact column 11 and setting the extension direction of the contact column 11 to be parallel to the center line Li of the conductive layer 20, the first electrode line 50 and the second electrode line 60 can be externally connected in the same direction. For example, the first target electrode line L1 can be directly connected to the interconnection layer 80, and the second target electrode line L2 can be connected to the interconnection layer 80 through the contact column 11.

[0208] For example, see Fig.13 In the case where the memory 100 includes a plurality of memory cells G, and at least a portion of the memory cells G are arranged along the third direction Z, a plurality of second target electrode lines L2 are arranged along the third direction Z.

[0209] Among them, see Fig.14 The memory 100 includes a core region Q1 and a step region Q2, wherein the step region Q2 is disposed on at least one side of the core region Q1. The memory cell G is disposed in the core region Q1, and the step region Q2 has a plurality of step surfaces U, each of which exposes a portion of a second target electrode line L2, and the exposed portion of the second target electrode line L2 is in electrical contact with the contact pillar 11.

[0210] That is, the core area Q1 of the memory 100 is used to set the memory cell G, and the step area Q2 is used to realize the external connection of the second target electrode line L2. By setting the step area Q2, the second target electrode line L2 can be smoothly externalized to avoid interference between adjacent second target electrode lines L2.

[0211] The embodiment of the present application also provides a method for preparing the memory 100 .

[0212] Fig.15 The method for preparing the memory 100 provided in the embodiment of the present application is as follows: Fig.16 , Fig.17 , Figure 19 to Figure 23 , Fig. 27 , Fig.28 and Fig.30 is a cross-sectional view corresponding to the memory 100 during the preparation process, Fig.18 and Fig.24 is a top view corresponding to the memory 100 during the preparation process, Fig.25 For along Fig.23 The cross-sectional view of the section line D-D' in Fig.26 For along Fig.23 The cross-sectional view of the section line E-E' in Fig.29 For along Fig.28 The cross-sectional view of the section line F-F' in Fig.31 For along Fig.30 Cross-sectional view along section line G-G'.

[0213] In some embodiments, Fig.15 As shown, the preparation method includes the following steps S1 to S6:

[0214] S1: Fig.16 As shown, a sacrificial layer A1 and an insulating layer 70 are stacked and alternately arranged on a substrate 10 .

[0215] Exemplarily, both the sacrificial layer A1 and the insulating layer 70 have electrical insulating properties.

[0216] For example, the material of the sacrificial layer A1 may include silicon oxide (SiO 2 ).

[0217] For example, the material of the insulating layer 70 may include silicon nitride (Si 3 N 4 ).

[0218] For example, the insulating layer 70 includes but is not limited to low dielectric constant materials such as phosphorus-doped SiO 2 .

[0219] It can be understood that the location of the sacrificial layer A1 is used to form the memory cell G, so refer to Fig.16 The top and bottom layers of the stacked structure are both insulating layers 70 , so that the memory cell G subsequently formed at the location of the sacrificial layer A1 can be covered by the insulating layer 70 , thereby preventing the conductive structure in the memory cell G from having unexpected electrical connection.

[0220] S2: Fig.17 and Fig.18 As shown, a through hole Ho penetrating the sacrificial layer A1 and the insulating layer 70 is formed, and a portion of the inner wall of the through hole Ho belonging to the sacrificial layer A1 is etched.

[0221] See also Fig.17 , step S2 comprises:

[0222] S21 : forming a through hole Ho penetrating the sacrificial layer A1 and the insulating layer 70 .

[0223] For example, see Fig.17, the through hole Ho extends to the substrate 10 .

[0224] Illustratively, the through hole Ho may be formed using a photolithography mask and a dry etching process.

[0225] For example, see Fig.18 The through hole Ho may be a circular through hole, or the through hole may be a square through hole, etc. The embodiment of the present application does not limit the specific shape of the through hole.

[0226] S22: Etching the portion of the inner wall of the through hole Ho that belongs to the sacrificial layer A1.

[0227] For example, see Fig.17 In step S22, the sacrificial layer A1 is not completely etched away, but only the portion of the sacrificial layer A1 surrounding the through hole Ho is etched away.

[0228] For example, a wet etching process may be used to remove the portion of the inner wall of the through hole Ho that belongs to the sacrificial layer A1 .

[0229] S3: Figure 19 to Figure 22 As shown, a conductive layer 20, a first target dielectric layer 30' and a first target electrode line L1 are sequentially formed on the inner wall of the through hole Ho; the first target electrode line L1 fills the through hole Ho.

[0230] The first target dielectric layer 30' is the dielectric layer located inside the conductive layer 20 in the first dielectric layer 30 and the second dielectric layer 40 in the aforementioned embodiment. For example, when the first dielectric layer 30 is located inside the conductive layer 20, the first target dielectric layer 30' is the first dielectric layer 30, otherwise, it is the second dielectric layer 40.

[0231] Similarly, the first target electrode line L1 is the electrode line located inside the conductive layer 20 among the first electrode line 50 and the second electrode line 60 in the aforementioned embodiment. For example, when the first electrode line 50 is located inside the conductive layer 20, the first target electrode line L1 is the first electrode line 50, otherwise, it is the second electrode line 60.

[0232] It is understandable that, when the first dielectric layer 30 is disposed inside the conductive layer 20, the first electrode line 50 must be disposed inside the conductive layer 20. The second dielectric layer 40 and the second electrode line 60 are similar.

[0233] For example, see Figure 19 to Figure 22 , the step S3 comprises:

[0234] S31: forming a conductive layer 20 on the inner wall of the through hole Ho.

[0235] For example, the conductive layer 20 may be prepared by atomic layer deposition technology.

[0236] S32 : removing a portion of the conductive layer 20 located on the surface of the insulating layer 70 perpendicular to the surface of the substrate 10 .

[0237] Exemplarily, the partial removal of the conductive layer 20 may be achieved by using isotropic dry etching.

[0238] By way of example, only the portion of the conductive layer 20 located on the sacrificial layer A1 may be retained.

[0239] Or, for example, see Fig. 20 The portion of the conductive layer 20 located on the sacrificial layer A1 and the portion of the insulating layer 70 parallel to the surface of the substrate 10 can be retained to increase the area of ​​the conductive layer 20 and facilitate increasing the effective area of ​​the ferroelectric capacitor FC or the selection tube S in the memory 100.

[0240] S33: Depositing a first target dielectric layer 30' (see Fig.21 ).

[0241] For example, a thin film deposition technique, such as an atomic layer deposition technique, may be used to prepare the first target dielectric layer 30 ′.

[0242] It can be understood that the first target dielectric layer 30' can be the first dielectric layer 30 or the second dielectric layer 40. That is, the first target dielectric layer 30' can have ferroelectricity or switching characteristics.

[0243] S34: forming a first target electrode line L1.

[0244] See also Fig. 22 , the first target electrode line L1 fills the through hole Ho.

[0245] Exemplarily, after the first target electrode line L1 is filled, the end of the first target electrode line L1 (the end in a direction perpendicular to the substrate 10) may be chemically mechanically polished to achieve planarization. During the polishing process, the uppermost insulating layer 70 may be used as a stop layer.

[0246] Through step S3, a stacked structure of the first target electrode line L1, the first target dielectric layer 30' and the conductive layer 20 can be formed, thereby forming a ferroelectric capacitor FC or a selection tube S. For example, when the first target electrode line L is the first electrode line 50 and the first target dielectric layer 30' is the first dielectric layer 30, a ferroelectric capacitor FC is formed in step S3, otherwise a selection tube S is formed.

[0247] S4: Fig.23 and Fig.24As shown, a trench K penetrating the sacrificial layer A1 and the insulating layer 70 is formed between two adjacent through holes Ho, and at least a portion of the sacrificial layer A1 is etched from the inner wall of the trench K until at least a portion of the conductive layer 20 is exposed.

[0248] For example, see Fig.23 , step S4 comprises:

[0249] S41: forming a groove K by etching.

[0250] Exemplarily, the preparation of the trench K may be achieved by photolithography and dry etching.

[0251] For example, see Fig.24 The groove K is in the shape of a long strip, so that the structures corresponding to the two adjacent rows of through holes Ho are separated.

[0252] S42 : etching at least a portion of the sacrificial layer A1 from the inner wall of the trench K until at least a portion of the conductive layer 20 is exposed.

[0253] See also Fig.25 and Fig.26 It can be understood that the aforementioned “etching at least a portion of the sacrificial layer A1 from the inner wall of the trench K” means that the sacrificial layer A1 is etched from the portion of the inner wall of the trench K belonging to the sacrificial layer A1, and the sacrificial layer A1 can be completely etched away, or only a portion can be etched away, leaving the sacrificial layer A1 between two adjacent through holes arranged along the extension direction perpendicular to the trench K (such as Fig.26 shown).

[0254] Understandably, see Fig.23 The aforementioned “until at least a portion of the conductive layer 20 is exposed” means that when etching the sacrificial layer A1 in the inner wall of the groove K, the conductive layer 20 is used as an etching stop layer, so that after removing the sacrificial layer A1, the conductive layer 20 can be exposed on the inner wall of the groove K, thereby facilitating the subsequent structure prepared in the groove K to contact the conductive layer 20.

[0255] For example, when the entire sacrificial layer A1 is etched away, the entire outer surface of the conductive layer 20 may be exposed, or, for example, see Fig.26 When a portion of the sacrificial layer A1 is etched away, only the surface of the conductive layer 20 close to the trench K may be exposed.

[0256] S5: Fig. 27 and Fig.28 As shown, a second target dielectric layer 40' and an initial electrode line L' are sequentially formed on the inner wall of the trench K.

[0257] Step S5 includes:

[0258] S51: See Fig. 27, forming a second target dielectric layer 40'.

[0259] The second target dielectric layer 40' is the dielectric layer located outside the conductive layer 20 in the first dielectric layer 30 and the second dielectric layer 40 in the above-mentioned embodiment. For example, when the first dielectric layer 30 is located outside the conductive layer 20, the second target dielectric layer 40' is the first dielectric layer 30, otherwise, it is the second dielectric layer 40.

[0260] It is understandable that one of the first target dielectric layer 30 ′ and the second target dielectric layer 40 ′ has ferroelectricity, and the other has switching characteristics, that is, one is the first dielectric layer 30 , and the other is the second dielectric layer 40 .

[0261] Exemplarily, when all the sacrificial layers A1 are etched away to expose the entire outer surface of the conductive layer 20 , the second target dielectric layer 40 ′ is disposed around the conductive layer 20 and contacts all positions of the outer surface of the conductive layer 20 .

[0262] Or, for example, see Fig.29 In the case where a portion of the sacrificial layer A1 is etched away to expose a portion of the outer surface of the conductive layer 20 , the second target dielectric layer 40 ′ only covers a portion of the conductive layer 20 .

[0263] S52: See Fig.28 , forming an initial electrode line L'.

[0264] See also Fig.28 , the initial electrode line L' fills the groove K.

[0265] It is understandable that the preparation process of the second target dielectric layer 40' may refer to the preparation process of the first target dielectric layer 30', and the preparation process of the initial electrode line L' may refer to the preparation process of the first target electrode line L1, which will not be repeated here.

[0266] Exemplarily, when the entire sacrificial layer A1 is etched away to expose the entire outer surface of the conductive layer 20 , after the initial electrode line L′ is filled, the two initial electrode lines L′ in two adjacent trenches K are integrally arranged.

[0267] Or, for example, see Fig.29 When a portion of the sacrificial layer A1 is etched away to expose a portion of the outer surface of the conductive layer 20 , two initial electrode lines L′ in two adjacent trenches K are separated by the remaining sacrificial layer A1 .

[0268] S6: Fig.30 As shown, the initial electrode line L' is cut along the length extension direction of the groove K and in a direction perpendicular to the substrate 10 to form a second target electrode line L2.

[0269] The second target electrode line L2 is the electrode line located outside the conductive layer 20 among the first electrode line 50 and the second electrode line 60 in the above-mentioned embodiment. For example, when the first electrode line 50 is located outside the conductive layer 20, the second target electrode line L2 is the first electrode line 50, otherwise, it is the second electrode line 60.

[0270] Exemplarily, in the case where a portion of the sacrificial layer A1 is etched from the inner wall of the trench K until a portion of the conductive layer 20 close to the trench K is exposed, step S6 includes:

[0271] The initial electrode line L' is cut along the length extension direction of the groove K and perpendicular to the direction of the substrate 10 to form two sub-lines L" (see Fig.31 ).

[0272] Two sub-lines L" which are disposed on both sides of the same through hole Ho and belong to two initial electrode lines L' are electrically connected to form a second target electrode line L2.

[0273] Understandably, see Fig.31 The two sub-lines L" disposed on both sides of the same through hole Ho and belonging to the two initial electrode lines L' are the first sub-line 61 and the second sub-line 62 in the aforementioned embodiment.

[0274] That is, by etching part of the sacrificial layer A1 and retaining part of the sacrificial layer A1, the second electrode line 60 can be prepared to include the first sub-line 61 and the second sub-line 62. On the one hand, the effective area of ​​the selection tube S can be reduced, and on the other hand, the difficulty of preparing the memory 100 can be reduced.

[0275] Similarly, for example, when all the sacrificial layers A1 are etched away, a complete strip-shaped second electrode line 60 (eg Figure 5 shown).

[0276] It is understandable that, according to the different structures of the memory 100 in the aforementioned embodiments, the method for preparing the memory 100 provided in this embodiment may be partially deformed accordingly.

[0277] For example, when the second dielectric layer 40 is located outside the conductive layer 20 (ie, the second dielectric layer 40 is the second target dielectric layer 40') and the second dielectric layer 40 is fan-shaped (ie, the second dielectric layer 40 is truncated), step S51 also includes a process of truncating the second target dielectric layer 40'.

[0278] Based on the method for preparing the memory 100 provided in the embodiment of the present application, the method for preparing the memory 100 may be partially deformed according to the structure of the memory 100 in the aforementioned embodiment, and the specific deformation steps will not be described in detail here.

[0279] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present disclosure should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: substrate; A conductive layer is disposed on one side of the substrate and is arranged in a ring shape; a center line of the conductive layer intersects with the substrate; a first dielectric layer and a second dielectric layer, wherein one of the first dielectric layer and the second dielectric layer is arranged on the inner side of the conductive layer, and the other surrounds the outer side of the conductive layer; the first dielectric layer has ferroelectricity, and the second dielectric layer has switching characteristics; A first electrode line and a second electrode line, wherein the first electrode line is arranged on a side of the first dielectric layer away from the conductive layer, and the second electrode line is arranged on a side of the second dielectric layer away from the conductive layer.

2. The memory according to claim 1, characterized in that: The first electrode line is arranged on the inner side of the conductive layer; the first dielectric layer is arranged around the first electrode line and between the first electrode line and the conductive layer; the second dielectric layer is at least partially arranged around the conductive layer, and the second electrode line is at least partially arranged around the second dielectric layer.

3. The memory according to claim 2, characterized in that: The second electrode line includes a first sub-line and a second sub-line that are electrically connected, the first sub-line and the second sub-line are parallel to each other and spaced apart, a portion of the second dielectric layer is disposed between the conductive layer and the first sub-line, and another portion of the second dielectric layer is disposed between the conductive layer and the second sub-line.

4. The memory according to claim 3, characterized in that: The second dielectric layer includes a first dielectric pattern and a second dielectric pattern which are arranged at intervals. The first dielectric pattern is arranged between the conductive layer and the first sub-line, and the second dielectric pattern is arranged between the conductive layer and the second sub-line.

5. The memory according to claim 1, characterized in that: The second electrode line is arranged inside the conductive layer; the second dielectric layer is arranged at least partially around the second electrode line and between the second electrode line and the conductive layer; the first dielectric layer is arranged around the conductive layer, and the first electrode line is arranged around the first dielectric layer.

6. The memory according to any one of claims 1 to 5, characterized in that: The height of the first dielectric layer is greater than the height of the second dielectric layer; the height refers to the dimension in the extension direction of the center line of the conductive layer.

7. The memory according to any one of claims 1 to 6, characterized in that: The second dielectric layer is in the shape of a ring or a sector ring; In the case where the second dielectric layer is in a fan-shaped ring shape, the memory further includes: The insulating layer is disposed between the second electrode line and the conductive layer, and the insulating layer is connected to the second dielectric layer and together forms a ring shape.

8. The memory according to any one of claims 1 to 7, characterized in that: An overlapping area among the conductive layer, the first dielectric layer and the first electrode line is greater than an overlapping area among the conductive layer, the second dielectric layer and the second electrode line.

9. The memory according to any one of claims 1 to 8, characterized in that: The ratio of the overlapping area among the conductive layer, the second dielectric layer and the second electrode line to the overlapping area among the conductive layer, the first dielectric layer and the first electrode line is less than 1:

3.

10. The memory according to any one of claims 1 to 9, characterized in that: include: A plurality of storage units, each storage unit comprising the conductive layer, the first dielectric layer, the second dielectric layer, the first electrode line and the second electrode line; Among the plurality of storage units, at least some of the storage units are arranged along a third direction; the third direction is parallel to a center line of the conductive layer; A first target electrode line extends along the third direction, and a plurality of memory cells arranged along the third direction share the first target electrode line; the first target electrode line is an electrode line disposed inside the conductive layer between the first electrode line and the second electrode line; A plurality of second target electrode lines corresponding to a plurality of storage units sharing one first target electrode line are arranged along the third direction; the second target electrode line is an electrode line of the first electrode line and the second electrode line surrounding the outer side of the conductive layer; The plurality of storage units arranged along the third direction also share the first dielectric layer and the second dielectric layer.

11. The memory according to claim 10, characterized in that: Among the plurality of storage units, at least some of the storage units are arranged along a first direction; the first direction intersects with the third direction; The second target electrode line extends along the first direction, and a plurality of memory cells arranged along the first direction share the second target electrode line.

12. The memory according to claim 10 or 11, characterized in that: Also includes: A contact post is electrically connected to the second target electrode line; an extension direction of the contact post is parallel to a center line of the conductive layer.

13. The memory according to claim 12, characterized in that: The memory includes a core area and a step area, wherein the step area is arranged on at least one side of the core area; the storage unit is arranged in the core area, the step area has a plurality of step surfaces, each step surface exposes a portion of a second target electrode line, and the exposed portion of the second target electrode line is electrically contacted with the contact column.

14. The memory according to any one of claims 1 to 13, characterized in that: Also includes: An interconnection layer, disposed on a side of the conductive layer away from the substrate; The circuit control layer is arranged on a side of the conductive layer close to the substrate.

15. An electronic device, characterized in that: include: The memory as claimed in any one of claims 1 to 14; An electronic device is electrically connected to the memory.

16. A method for preparing a memory, characterized in that: include: forming a stacked and alternately arranged sacrificial layer and an insulating layer on a substrate; forming a through hole penetrating the sacrificial layer and the insulating layer, and etching a portion of an inner wall of the through hole belonging to the sacrificial layer; forming a conductive layer, a first target dielectric layer and a first target electrode line on the inner wall of the through hole in sequence; the first target electrode line fills the through hole; forming a groove penetrating the sacrificial layer and the insulating layer between two adjacent through holes, and etching at least a portion of the sacrificial layer from an inner wall of the groove until at least a portion of the conductive layer is exposed; The groove is in strip shape; forming a second target dielectric layer and an initial electrode line in sequence on the inner wall of the trench; One of the first target dielectric layer and the second target dielectric layer has ferroelectricity, and the other has switching characteristics; the initial electrode line fills the groove; The initial electrode line is cut along the length extension direction of the groove and in a direction perpendicular to the substrate to form a second target electrode line.

17. The preparation method according to claim 16, characterized in that: In the case where a portion of the sacrificial layer is etched from an inner wall of the trench until a portion of the conductive layer close to the trench is exposed: The method of cutting the initial electrode line along the length extension direction of the groove and in a direction perpendicular to the substrate to form a second target electrode line includes: Cutting the initial electrode line along the length extension direction of the groove and in a direction perpendicular to the substrate to form two sub-lines; Two sub-lines which are arranged on both sides of the same through hole and belong to two initial electrode lines are electrically connected to form the second target electrode line.

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