A circuit and method for testing the avalanche energy of power devices

Abstract

This invention discloses an avalanche energy testing circuit and method for power devices. This testing circuit, while enabling avalanche energy testing using existing non-clamped inductive switch testing circuits, suppresses current and voltage oscillations caused by charging and discharging between the inductor and the parasitic capacitance of the device under test (DUT) after avalanche energy loss. This avoids inaccurate avalanche energy testing due to losses caused by current and voltage oscillations in the DUT, and avoids false turn-on due to gate-source oscillations caused by drain-source oscillations in the DUT. A constant current source circuit allows for testing the cooling curve and heat dissipation time of the DUT using a temperature-sensitive electrical parameter method after avalanche energy loss. This power device avalanche energy testing circuit and method, based on accurate measurement of single-pulse avalanche energy, calculates the optimal duty cycle required for repetitive pulse avalanche energy testing, improving the accuracy of repetitive pulse avalanche energy testing.

Description

Technical Field

[0001] This invention relates to the field of avalanche energy testing technology, specifically to an avalanche energy testing circuit and method for power devices. Background Technology

[0002] Wide-bandgap semiconductor devices (such as SiC MOSFETs) are widely used in new energy power generation, electric vehicles, aerospace, communication power supplies, and smart grids due to their excellent electrical characteristics, including high switching speed, low conduction loss, and resistance to high temperatures and voltages. As voltage-controlled switching devices, SiC MOSFETs are widely used in inductive, capacitive, and resistive load systems. In inductive load power electronic systems, a sudden device turn-off can cause an overvoltage due to rapid current changes, leading to avalanche state. However, in capacitive or resistive load power electronic systems, no overvoltage occurs across the load after a sudden device turn-off. Testing the maximum avalanche energy and the number of repetitive avalanche cycles that a power device can withstand is crucial for selecting the appropriate rated voltage power device for inductive load systems at different voltage levels. After avalanche begins, the junction temperature rises to 500K–700K. To accurately measure the number of repetitive pulse avalanche cycles, the device should be allowed to return to room temperature after each pulse cycle before the next test, eliminating the influence of temperature on the repetitive pulse avalanche energy test. However, after the avalanche ends, the avalanche voltage and current of the device will oscillate for hundreds of microseconds due to the influence of inductance and parasitic capacitance. It is impossible to measure the device cooling curve by the temperature-sensitive electrical parameter method, which in turn makes it impossible to accurately set the time interval between each cycle: if the interval is too short, the device will not dissipate heat sufficiently, and heat accumulation will occur during the repetitive pulse avalanche energy test, which will damage the device; if the interval is too long, the repetitive pulse avalanche energy test can be performed hundreds of thousands of times, which will extend the repetitive pulse avalanche energy test time several times, and it will be impossible to accurately measure the number of avalanches the device has withstood in the repetitive pulse avalanche test, resulting in extremely low efficiency.

[0003] In academia and industry, unclamped inductive switch (UIS) test circuits are commonly used for avalanche energy testing. UIS test circuits are used to simulate power devices operating under extreme conditions, particularly voltage spikes generated when a highly inductive load is suddenly disconnected. This test method is simple and low-cost; its simplest circuit consists only of a voltage source, inductor, driver circuit, and the device under test (DUT). However, the avalanche process of a power device lasts only a few microseconds, making it difficult to observe the avalanche process and subsequent junction temperature changes using thermal imaging. Furthermore, because the withstand voltage drops significantly after opening the package, it is impossible to test the avalanche process and subsequent junction temperature changes using fiber optic probes. Additionally, the presence of large inductance and parasitic capacitance in the test circuit means that even after the avalanche ends, the power device still experiences current and voltage oscillations for hundreds of microseconds, making the measurement of junction temperature changes after avalanche using temperature-sensitive electrical parameters inaccurate. Therefore, it is difficult to determine whether the DUT has returned to normal temperature after avalanche, making it impossible to accurately set the time interval between each pulse cycle in a repetitive pulse avalanche test. Summary of the Invention

[0004] This invention addresses the shortcomings of existing technologies by proposing a circuit and method for testing the avalanche energy of power devices. The test circuit designed in this invention can suppress current and voltage oscillations caused by the charging and discharging of the inductor and the parasitic capacitance of the device under test (DUT). This avoids inaccurate avalanche energy testing due to losses caused by current and voltage oscillations in the DUT, and prevents false turn-on of the device due to gate-source oscillations caused by drain-source oscillations. It also enables monitoring of temperature changes after avalanche events using temperature-sensitive electrical parameter testing methods. Furthermore, it accurately determines the time interval between each pulse cycle in the repetitive pulse avalanche energy test, i.e., the repetitive pulse duty cycle, significantly reducing test time and improving test efficiency while ensuring test accuracy.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: an avalanche energy testing circuit for power devices, characterized in that the circuit includes a current oscillation suppression circuit and a constant current source circuit, wherein the current oscillation suppression circuit includes a DC power supply (VDD), a normally open switch (Q1), an inductor (L), a normally closed switch (Q2), a diode (D1), a device under test (DUT1), and a first pulse signal generator (V G ), gate resistor (R) GThe positive output terminal of the DC power supply (VDD) is connected to the collector of the normally open switch, and the emitter of the normally open switch is connected to one end of the inductor (L); the other end of the inductor (L) is connected to the drain of the device under test (DUT), and the source of the DUT is connected to the negative input terminal of the DC power supply (VDD); the cathode of the diode (D1) is connected to the junction of the emitter of the normally open switch (Q1) and the inductor (L), the anode of the diode (D1) is connected to the emitter of the normally closed switch (Q2), and the collector of the normally closed switch (Q2) is connected to the junction between the inductor (L) and the drain of the DUT; the first pulse signal generator (V G The negative terminal of the gate resistor (R) is connected to the negative input terminal of the DC power supply (VDD), and its positive terminal is connected to the gate resistor (R). G One end of the gate resistor (R) is connected to the gate resistor (R). G The other end of the connector is connected to the gate of the device under test (DUT1);

[0006] The constant current source circuit includes a second pulse signal generator, a current source chip (U1), a Zener diode (D2), and a high-precision resistor (R2). The negative output terminal of the second pulse signal generator is connected to the drain of the device under test (DUT1), and the positive output terminal is connected to the IN terminal of the current source chip (U1). The SET terminal of the current source chip (U1) is connected to the cathode of the Zener diode (D2), and the anode of the Zener diode (D2) is connected to the source of the device under test (DUT1). The OUT terminal of the current source chip (U1) is connected to one end of the high-precision resistor (R2), and the other end of the high-precision resistor (R2) is connected to the connection point between the Zener diode (D2) and the source of the device under test (DUT1).

[0007] Furthermore, this invention designs a method for testing the avalanche energy of power devices, characterized in that the method is based on the avalanche energy testing circuit of power devices as described above, and the method includes the following steps:

[0008] Step 1: Set the conduction time t1 of the device under test (DUT1), and set the pulse width and duty cycle of the pulse drive signal of the first pulse signal generator during the first single-pulse avalanche energy test;

[0009] Step 2: Turn on the current oscillation suppression circuit and turn off the constant current source circuit; the first pulse signal generator (V G When the pulse drive signal is issued, the device under test (DUT1) is turned on; the current flowing through the device under test (DUT1) gradually increases to the set value at a constant rate and charges the inductor (L);

[0010] Step 3: First pulse signal generator (V) GAfter the pulse drive signal is emitted for a period of time t1, the pulse drive signal stops, the device under test (DUT1) is turned off, and the DUT1 enters an avalanche state. The avalanche duration is t. av ;

[0011] Step 4: After the avalanche of the device under test (DUT1) ends, the normally closed switch (Q2) is turned on and the normally open switch (Q1) is turned off;

[0012] Step 5: 10 μs after the avalanche of the device under test (DUT1) ends, turn on the second pulse signal generator to output a pulse drive signal, causing the constant current source circuit to output a constant current of 10 mA, and measure the parasitic diode voltage drop inside the DUT1; using the parasitic diode voltage drop inside the DUT1 as a temperature-sensitive parameter, monitor the time t for the junction temperature of the DUT1 to recover to room temperature after the avalanche ends using the temperature-sensitive electrical parameter method. i ;

[0013] Step 6: The process from Step 2 to Step 5 constitutes one single-pulse avalanche energy test. The duration of one single-pulse avalanche energy test is T. S :

[0014] T S =t1+t av +t i +10

[0015] In the formula, t1 is the conduction time of the device under test (DUT1), t av t represents the avalanche duration of the device under test (DUT1). i The time it takes for the junction temperature of the device under test (DUT1) to return to room temperature after the avalanche energy test is completed;

[0016] After time T S Afterwards, the device under test (DUT1) has returned to room temperature, at which point T is used. S The pulse period is used as the pulse period for repetitive pulse avalanche energy testing; t1 / T S As the optimal duty cycle D for the repetitive pulse, the first pulse signal generator (V) G A pulse drive signal is emitted with the optimal duty cycle D. The test condition for the repetitive pulse avalanche energy test is 80% of the maximum avalanche energy value of the device under test (DUT1). The process of single pulse avalanche energy test is repeated continuously until the device under test (DUT1) is damaged. The number of repetitive pulse avalanche tests that the device under test (DUT1) withstands when it is damaged is the service life of the device under test (DUT1) under the current test conditions.

[0017] Compared with existing technologies, the beneficial effects of the present invention are as follows: The avalanche energy testing circuit for power devices designed in this invention can suppress current and voltage oscillations caused by charging and discharging between the inductor and the parasitic capacitance of the device under test (DUT) after the avalanche event, while achieving avalanche energy testing using existing non-clamped inductive switch testing circuits. This avoids inaccurate avalanche energy testing due to losses caused by current and voltage oscillations in the DUT, and avoids false turn-on of the device due to gate-source oscillations caused by drain-source oscillations in the DUT. Furthermore, the constant current source circuit enables the testing of the cooling curve and heat dissipation time of the DUT using a temperature-sensitive electrical parameter method after the avalanche event. The avalanche energy testing circuit and method for power devices designed in this invention can calculate the optimal duty cycle required for repetitive pulse avalanche energy testing based on accurate measurement of single-pulse avalanche energy, thereby improving the accuracy of the number of avalanche withstand cycles during repetitive pulse avalanche energy testing. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a conventional non-clamped inductive switch test circuit.

[0019] Figure 2 To pass as Figure 1 The diagram shows the signal curves during a single-pulse avalanche energy test using a non-clamped inductive switch test circuit; in the diagram, V G V represents the first pulse signal generator G A schematic diagram of the triggered pulse signal curve, I DS This is a schematic diagram representing the current signal curve through the device under test (DUT1), V DS A schematic diagram of the drain-source voltage signal curve representing the device under test (DUT1).

[0020] Figure 3 This is a schematic diagram of the current oscillation suppression circuit of one embodiment of the avalanche energy testing circuit for a power device according to the present invention.

[0021] Figure 4 To pass as Figure 3 The diagram shows the signal curve during a single-pulse avalanche energy test using the current oscillation suppression circuit shown; in the diagram, V G I DS V DS The curve shown is Figure 2 The symbols in the diagram are consistent. Q1 represents the schematic diagram of the drive signal curve when the normally open switch is activated, and Q2 represents the schematic diagram of the drive signal curve when the normally closed switch is activated.

[0022] Figure 5 This is a schematic diagram of one embodiment of an avalanche energy testing circuit for a power device according to the present invention.

[0023] Figure 6 To pass as Figure 5 The diagram shows the signal curves of the power device's avalanche energy test circuit during a single-pulse avalanche energy test; where V G I DS V DS The curves shown in Q1 and Q2 are... Figure 4 The consistency represented by I SD A schematic diagram representing the current signal curve emitted by the constant current source circuit, V SD The diagram shows the diode voltage drop signal curve representing the device under test (DUT1), and the cooling curve represents the junction temperature change curve of DUT1 after the avalanche, as measured by the thermistor method. Detailed Implementation

[0024] To make the present invention more easily understood, the technical solution of the present invention will be further described below in conjunction with specific embodiments and accompanying drawings, and is not intended to limit the scope of protection of this application.

[0025] Figure 1 This is a standard non-clamping inductive switch test circuit diagram. The non-clamping inductive switch circuit includes a DC power supply VDD, a bus inductance L, a device under test (DUT1), and a first pulse signal generator V. G Gate resistance R G The positive output terminal of the DC power supply VDD is connected to one end of the inductor L, and the other end of the inductor L is connected to the drain of the device under test (DUT1); the source of the DUT1 is connected to the negative output terminal of the DC power supply VDD and grounded; the first pulse signal generator V... G The negative terminal is connected to ground, and the positive terminal is connected to the gate resistor R. G One end is connected, and the gate resistor R G The other end is connected to the gate of the device under test (DUT1).

[0026] When the device under test (DUT1) is turned on, due to the extremely small on-state voltage drop, the DC power supply VDD voltage can be approximated as being entirely borne by the inductor L. Therefore, the inductor voltage can be calculated using the following formula:

[0027]

[0028] Obtain the required avalanche current I ds :

[0029]

[0030] t1 is the pulse period T×D of the pulse drive signal (D is the duty cycle of the pulse drive signal). t1 can be designed and adjusted by the test personnel according to the test requirements. L0 is the inductance value of inductor L.

[0031] Before testing, after adjusting the appropriate t1 according to the test requirements, the single-pulse avalanche energy test can be performed. First, the pulse drive signal emits a drive signal with an appropriate pulse width and duty cycle, and the device under test (DUT1) is turned on. Due to the presence of inductor L, the current I... ds The inductor L is charged with a constant di / dt. At this time, the voltage of the device under test (DUT1) is the on-state voltage drop V. ds The DC power supply VDD voltage is supplied by inductor L. After the drive signal ends and the device under test is turned off, since inductor L still stores a large amount of energy, when inductor L releases energy, it acts as a power source, generating an I at an approximately constant di / dt rate. av Because the device under test (DUT1) is turned off, its resistance is extremely high, causing the energy in the inductor L to dissipate very quickly. This results in a very large di / dt value, causing DUT1 to experience an extremely high voltage, namely the avalanche voltage V. BR(DS) The device under test (DUT) enters an avalanche state; once the energy of the inductor L is fully released, the avalanche of DUT1 ends, and the voltage of DUT1 becomes the DC power supply voltage VDD.

[0032] To measure the maximum avalanche energy value of the device under test (DUT1), during the avalanche energy test, the conduction time t1 of DUT1 is increased at fixed intervals (usually in increments of 10µs) until the device fails. The energy of the single-pulse avalanche before device failure is then taken as the maximum avalanche energy value of the DUT.

[0033] by Figure 1 The avalanche energy calculation formula for a conventional non-clamped inductive switch test circuit is as follows:

[0034]

[0035] exist Figure 1 The avalanche voltage in a circuit can be expressed as:

[0036]

[0037] By combining the two equations, we can obtain:

[0038]

[0039] Figure 2 This is a schematic diagram of the single-pulse avalanche energy test using the method described above. The avalanche energy of the device under test can be calculated from the voltage and current values ​​shown in the diagram.

[0040] However, the test curves reveal the shortcomings of the above method: during the avalanche, the inductor L continuously discharges to the device under test (DUT); after the avalanche ends, the DUT is turned off, and due to the parasitic capacitance C at the drain-source terminals of the DUT... ds During the avalanche process of the device under test, the parasitic capacitance C ds It also stores some energy; when the energy in inductor L is completely released, due to the parasitic capacitance C ds Some energy remains, parasitic capacitance C ds Discharge begins into inductor L, at the inductor L and parasitic capacitance C ds During the mutual charging and discharging process, even after the avalanche of the device under test ends, the device will still be subjected to long-term current and voltage oscillations, which will damage the device's lifespan.

[0041] like Figure 2 As shown, due to the prolonged current and voltage oscillations after an avalanche, the thermistor method cannot be used to monitor the junction temperature of the device. Consequently, it is impossible to verify whether the device has returned to room temperature after the avalanche. This makes it difficult to properly set the interval between two adjacent pulse cycles when performing repetitive pulse avalanche energy tests. Consequently, during repetitive pulse avalanche energy tests, the junction temperature of the device under test may not drop to room temperature after each pulse due to an unreasonable pulse interval design. In multiple repetitive pulse avalanche energy tests, heat accumulation is likely to occur, resulting in inaccurate measurements of repetitive pulse avalanche energy and the number of avalanches the device can withstand, and significantly shortening the device's lifespan.

[0042] This invention provides an avalanche energy testing circuit for power devices (see...) Figure 5 The circuit includes a current oscillation suppression circuit and a constant current source circuit, wherein the current oscillation suppression circuit (such as...) Figure 3 (As shown) includes a DC power supply VDD, a normally open switch Q1, an inductor L, a normally closed switch Q2, a diode D1, a device under test DUT1, and a first pulse signal generator V. G Gate resistance R G The positive output terminal of the DC power supply VDD is connected to the collector of a normally open switch, and the emitter of the normally open switch is connected to one end of an inductor L; the other end of inductor L is connected to the drain of the device under test (DUT), and the source of the DUT is connected to the negative input terminal of the DC power supply VDD; the cathode of diode D1 is connected to the junction of the emitter of normally open switch Q1 and inductor L, the anode of diode D1 is connected to the emitter of normally closed switch Q2, and the collector of normally closed switch Q2 is connected to the junction between inductor L and the drain of the DUT. The first pulse signal generator V... G The negative terminal is connected to the negative input terminal of the DC power supply VDD, and its positive terminal is connected to the gate resistor R. G One end is connected, and the gate resistor R G The other end is connected to the gate of the device under test (DUT1).

[0043] The constant current source circuit includes a second pulse signal generator, a current source chip U1, a Zener diode D2, and a high-precision resistor R2. The negative output terminal of the second pulse signal generator is connected to the drain of the device under test (DUT1), and the positive output terminal is connected to the IN terminal of the current source chip. The SET terminal of the current source chip is connected to the cathode of the Zener diode D2, and the anode of the Zener diode D2 is connected to the source of the device under test (DUT1). The OUT terminal of the current source chip is connected to one end of the high-precision resistor R2, and the other end of the high-precision resistor R2 is connected to the junction between the Zener diode D2 and the source of the device under test (DUT1).

[0044] This avalanche energy testing circuit, while ensuring the original functions of the non-clamped inductive switch testing circuit, can suppress the current oscillation caused by the mutual charging and discharging of inductor L and parasitic capacitance after the avalanche ends, thus enabling the measurement of the device junction temperature after the avalanche ends using the temperature-sensitive electrical parameter method.

[0045] Furthermore, the present invention provides a method for testing the avalanche energy of power devices. This method is based on the avalanche energy testing circuit for power devices described above, and includes the following steps:

[0046] Step 1: Set the conduction time t1 of the device under test and set the first pulse signal generator V. G The pulse width (i.e., the duration of the high level, which is equal to the conduction time of the device under test) and duty cycle of the pulse drive signal Vg during the first single-pulse avalanche energy test.

[0047] The on-time t1 of the device under test is set as follows:

[0048]

[0049] Among them, I p I represents the current value passing through the device under test. p The value range is between the rated continuous drain current value in the device datasheet of the device under test and the maximum avalanche current value in its single-pulse avalanche energy test; V DD V is the output voltage of the DC power supply VDD. DDThe value can be set to 50V according to the common test conditions of SiCMOSFET manufacturers on the market; L0 is the inductance value of inductor L. The method for determining the maximum avalanche current in the single-pulse avalanche energy test is as follows: First, calculate the device's on-time during the first single-pulse avalanche energy test, i.e., the pulse width of the pulse signal, using the rated continuous drain current value in the device datasheet of the device under test; for the second single-pulse avalanche energy test, increase the on-time of the device under test by 10μs; and so on, gradually increasing the on-time of the device under test in 10μs increments until failure, obtaining the maximum avalanche current value. The single-pulse avalanche energy before the device under test fails is taken as the maximum avalanche energy value of the device under test.

[0050] Step 2: Turn on the current oscillation suppression circuit and turn off the constant current source circuit; the first pulse signal generator V G When the pulse drive signal is emitted, the device under test (DUT) is turned on; the current I flowing through the DUT... ds The inductor L is charged by gradually increasing the value at a constant rate to the set value.

[0051] Step 3: First pulse signal generator V G After the pulse drive signal is emitted for a period of time t1, the pulse drive signal Vg stops, the device under test (DUT) is turned off, and the DUT enters an avalanche state. The avalanche duration is t. av ;

[0052] Step 4: After the avalanche test of the device under test ends, normally closed switch Q2 is turned on and normally open switch Q1 is turned off, so that the oscillating current can continue between inductor L, diode D1 and normally closed switch Q2; at the same time, it prevents the oscillating current from causing unnecessary oscillation when it flows between the freewheeling circuits, so as to suppress the current and voltage oscillation after the avalanche energy test ends.

[0053] By using the above-mentioned oscillation suppression circuit test method, the current and voltage oscillations after the single-pulse avalanche energy test are well suppressed, and the cooling time of the device under test after the avalanche ends can be measured by the temperature-sensitive electrical parameter method.

[0054] To accurately suppress current and voltage oscillations, it is necessary to precisely control the turn-off time of normally open switch Q1 and the turn-on time of normally closed switch Q2. Figure 1 Transient analysis of the conventional non-clamped inductive switch test circuit shown is performed under the conduction state. Figure 1 The transient analysis equations for the circuit in the on-state are as follows:

[0055]

[0056] In this formula, V DD V0 is the output voltage of the DC power supply VDD, and L0 is the inductance value of inductor L. BR(DS) R is the avalanche voltage.L Let i be the parasitic resistance value of inductor L. (t) The current flowing through the device under test (DUT) is given by the initial values ​​t=0 and i when the DUT enters the avalanche state. (t) =I L =I ds Solving the state equations for the boundary conditions yields:

[0057]

[0058] By solving the above equation, the duration of the avalanche is obtained as follows:

[0059]

[0060] The on-time t1 and avalanche duration t of the device under test are used. av The opening time of normally closed switch Q2 and the closing time of normally open switch Q1 can then be calculated as t = t1 + t av By controlling the signal delay through software, normally open switch Q1 and normally closed switch Q2 will transition in state after time t, i.e., after the avalanche event of the device under test (DUT) has ended. The test circuit diagram is shown below. Figure 4 As shown in the figure, after the normally open switch Q1 is turned off and the normally closed switch Q2 is turned on, the voltage and current oscillations after the avalanche energy test can be well suppressed. The dotted line in the figure represents the suppressed portion. The current oscillation suppression circuit achieves the purpose of suppressing the voltage and current oscillations after the avalanche energy test, enabling the subsequent monitoring of the time it takes for the junction temperature of the device under test to recover to room temperature using the temperature-sensitive electrical parameter method.

[0061] In repetitive pulse avalanche energy testing, if the time interval between adjacent pulses is too short, insufficient heat dissipation will occur, leading to heat accumulation and reducing the lifespan of the power device. If the time interval is too long, it will significantly extend the testing time. Since repetitive pulse avalanche energy testing may require hundreds of thousands of cycles, an excessively long interval will often increase the testing time several times over, resulting in extremely low efficiency. To set a suitable time interval between adjacent pulses during repetitive pulse avalanche energy testing, i.e., the duty cycle of the pulse drive signal, it is necessary to use the temperature-sensitive electrical parameter method to monitor the time it takes for the junction temperature of the device under test to recover to room temperature after the avalanche energy test.

[0062] Step 5: 10μs after the avalanche event ends on the device under test, turn on the second pulse signal generator and output the pulse drive signal V. i This causes the constant current source circuit to output a constant current I of 10mA. sdThe parasitic diode voltage drop Vsd inside the device under test (DUT1) was measured. Using Vsd as a temperature-sensitive parameter, the time t for the junction temperature to recover to room temperature after an avalanche event was monitored using the temperature-sensitive electrical parameter method. i .

[0063] The curve showing the junction temperature recovering to room temperature after avalanche energy testing of power devices using a constant current source circuit and the temperature-sensitive electrical parameter method is shown below. Figure 6 As shown, the time it takes for the junction temperature of the device under test to recover to room temperature is monitored by monitoring the change in the voltage drop of the parasitic diode inside the device under test.

[0064] Due to the inherent characteristics of the pulse drive signal of the second pulse signal generator, i.e., the current source chip itself, there is a delay in the pulse current triggering. In order to completely eliminate the influence of current and voltage oscillation, the triggering of the second pulse signal generator is set to 10μs after the state transition of switches Q1 and Q2.

[0065] Step 6: The process from Step 2 to Step 5 constitutes one single-pulse avalanche energy test. The duration of one single-pulse avalanche energy test is T. S :

[0066] T S =t1+t av +t i +10

[0067] In the formula, t1 is the conduction time of the device under test, t av t represents the avalanche duration of the device under test. i The time it takes for the junction temperature of the device under test to return to room temperature after the avalanche energy test is completed;

[0068] After time T S Afterwards, the device under test has returned to room temperature, at which point T can be used. S The pulse period is used as the pulse period for repetitive pulse avalanche energy testing; t1 / T S By using the optimal duty cycle D for the repetitive pulse, the influence of temperature during the repetitive pulse avalanche energy test can be effectively eliminated, resulting in more accurate test results. First pulse signal generator V G A pulse drive signal is emitted with an optimal duty cycle D. The test condition for repetitive pulse avalanche energy testing is set to 80% of the maximum avalanche energy value of the device under test (DUT). This process is repeated continuously until the DUT fails. The number of repetitive pulse avalanche tests the DUT withstands before failure is the lifespan of the DUT under the current test conditions.

[0069] The optimal duty cycle D of the drive signal during repetitive pulse avalanche energy testing is:

[0070]

[0071] The optimal duty cycle for repetitive pulse avalanche energy testing can be set using the method described above. If time cost is not a concern, when setting the duty cycle d for repetitive pulse avalanche energy testing, ensure that d is less than the optimal duty cycle D to avoid heat accumulation in the device under test during the test.

[0072] In this invention, "avalanche energy testing of power devices" refers to obtaining the number of repeated avalanches, i.e., the lifespan of the power device, using an avalanche energy testing method. For power devices, the maximum avalanche energy value is of reference value and can be obtained using a common single-pulse avalanche energy testing method, a process that is existing in the field.

[0073] Any aspects not covered in this invention are applicable to existing technologies.

Claims

1. An avalanche energy test circuit for a power device, characterized by, The circuit comprises a current oscillation suppression circuit and a constant current source circuit, wherein the current oscillation suppression circuit comprises a direct current power supply (VDD), a normally open switch (Q1), an inductor (L), a normally closed switch (Q2), a diode (D1), a device under test (DUT1), a first pulse signal generator (V G ), and a gate resistor (R G ); a positive output terminal of the direct current power supply (VDD) is connected with a collector of the normally open switch, an emitter of the normally open switch is connected with one end of the inductor (L); the other end of the inductor (L) is connected with a drain of the device under test, a source of the device under test is connected with a negative input terminal of the direct current power supply (VDD); a cathode of the diode (D1) is connected with a connection point of the emitter of the normally open switch (Q1) and the inductor (L), an anode of the diode (D1) is connected with an emitter of the normally closed switch (Q2), a collector of the normally closed switch (Q2) is connected with a connection point between the inductor (L) and the drain of the device under test; a negative electrode of the first pulse signal generator (V G ) is connected with the negative input terminal of the direct current power supply (VDD), a positive electrode thereof is connected with one end of the gate resistor (R G ), the other end of the gate resistor (R G ) is connected with a gate of the device under test (DUT1). The constant current source circuit comprises a second pulse signal generator, a current source chip (U1), a stabilizing diode (D2) and a high-precision resistor (R2); the negative output end of the second pulse signal generator is connected with the drain of a device under test (DUT1), and the positive output end is connected with the IN end of the current source chip (U1); the SET end of the current source chip (U1) is connected with the cathode of the stabilizing diode (D2), and the anode of the stabilizing diode (D2) is connected with the source of the device under test (DUT1); the OUT end of the current source chip (U1) is connected with one end of the high-precision resistor (R2), and the other end of the high-precision resistor (R2) is connected with the connection point between the stabilizing diode (D2) and the source of the device under test (DUT1).

2. A method of avalanche energy testing of a power device, characterized by, The method is based on the avalanche energy test circuit of the power device as claimed in claim 1, and comprises the following steps: Step 1: setting the value of the on-time t1 of the device under test (DUT1) and setting the pulse width and duty cycle of the pulse driving signal of the first pulse signal generator in the first single-pulse avalanche energy test; Step 2: Turn on the current oscillation suppression circuit, turn off the constant current source circuit; the pulse driving signal of the first pulse signal generator (V G ) is sent out, and the device under test (DUT1) is turned on; the current flowing through the device under test (DUT1) gradually increases to the set value at a constant rate and charges the inductor (L); Step 3: The pulse driving signal of the first pulse signal generator (V G ) stops after the time of the pulse driving signal reaching t1, the device under test (DUT1) is turned off, the device under test (DUT1) enters an avalanche state, and the avalanche duration t av ; Step 4: after the avalanche of the device under test (DUT1) ends, the normally closed switch (Q2) is opened, and the normally open switch (Q1) is disconnected; Step 5: After the avalanche of the device under test (DUT1) ends for 10 μs, the second pulse signal generator is turned on to output a pulse driving signal, so that the constant current source circuit outputs a constant current of 10 mA, and the internal parasitic diode voltage drop of the device under test (DUT1) is tested; the internal parasitic diode voltage drop of the device under test (DUT1) is taken as a temperature-sensitive parameter, and the time t for the junction temperature of the device under test (DUT1) to recover to room temperature after the avalanche is monitored by the temperature-sensitive electrical parameter method i ; Step 6: The process of Step 2 to Step 5 is a one-time single-pulse avalanche energy test process, and the one-time single-pulse avalanche energy test duration is T S : T S = t1+ t av + t i + 10 Wherein t1 is the on time of the device under test (DUT1), t av is the avalanche duration of the device under test (DUT1), t i is the time for the junction temperature to recover to room temperature after the avalanche energy test of the device under test (DUT1) is completed. Time elapsed T S After the DUT1 has returned to normal temperature, the T S As the pulse period of the repetitive pulse avalanche energy test; t1 / T S As the optimal duty cycle D of the repetitive pulse, the first pulse signal generator (V G ) sends out the pulse driving signal with the optimal duty cycle D, and takes 80% of the maximum avalanche energy value of the DUT1 as the test condition when the repetitive pulse avalanche energy test is performed, and repeatedly performs the process of the single pulse avalanche energy test until the DUT1 is damaged. The number of repeated pulse avalanche tests that the device under test can withstand when damaged is the service life of the device under test under the current test condition.

3. The method of claim 2, wherein the step of applying a voltage to the power device comprises applying a voltage to the power device such that the voltage is greater than the breakdown voltage of the power device. The setting of the on-time t1 of the device under test (DUT1) is as follows: wherein, I p is a current value passing through the device under test, I p is in a range between a rated continuous drain current value and a maximum avalanche current value of a single pulse avalanche energy test in a device manual of the device under test; V DD is an output voltage of a direct current power supply VDD, V DD a value can be set as 50V according to a common test condition of a common SiC MOSFET manufacturer; L0 is an inductance value of the inductance L; wherein, a determination method of the maximum avalanche current of the single pulse avalanche energy test is: firstly, a device on time of a first single pulse avalanche energy test is calculated according to the rated continuous drain current value in the device manual of the device under test, that is, a pulse width of the pulse signal; a device on time of a second single pulse avalanche energy test is 10us longer than that of the first single pulse avalanche energy test; the device on time is increased by 10us as a gradient until the device is damaged, and the maximum avalanche current value is obtained; a single pulse avalanche energy before the device under test is damaged is taken as the maximum avalanche energy value of the device under test.

4. The method of claim 2, wherein the step of applying a voltage to the power device comprises applying a voltage to the power device such that the voltage is greater than the breakdown voltage of the power device. Duration of avalanche t av The solution method is: the on-state transient analysis of the conventional non-clamp inductive switch test circuit, the equations are as follows: In the formula, V DD is the output voltage of the direct current power supply (VDD), L0 is the inductance value of the inductor (L), V BR(DS) is the avalanche voltage, R L is the parasitic resistance value of the inductor (L), i (t) is the current value flowing through the device under test (DUT1); the initial value t=0 and i (t) =I L =I ds is the boundary condition solution state equation: By solving the above formula, the avalanche duration is obtained as follows: By solving the above formula, the avalanche duration is obtained as follows:

Images