Power cycle test system suitable for power semiconductor device
By using analog signal selection circuit and voltage signal acquisition circuit in the power cycle test system, the junction temperature of semiconductor devices is calculated in real time, and the problems of inaccurate monitoring and narrow application range in the prior art are solved, and the high quality of various devices is achieved Accuracy and reliability test.
Patent Information
- Application Number
- CN202411356582.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2019-03-05
- Publication Date
- 2024-12-27
AI Technical Summary
The existing power cycle testing system cannot accurately monitor the junction temperature of semiconductor devices, and its application range is limited, so it cannot effectively evaluate the reliability of devices such as GaN HEMT.
A power cycle testing system for power semiconductor devices is designed, using analog signal selection circuit and voltage signal acquisition circuit, and periodically transmits the current sensing resistor and the voltage across the device under test to the controller, combining the pre-obtained junction temperature and resistance value. Corresponding relationship curve model, calculate the junction temperature of the device in real time, avoid reverse low current testing, reduce device control difficulty and improve test accuracy.
Accurate and real-time junction temperature monitoring of devices such as IGBT, MOSFET and GaN HEMT is achieved, which improves the accuracy and reliability of testing, expands the scope of application, and avoids junction temperature fluctuations and equipment control complexity.
Smart Images
Figure CN119199449A_ABST
Abstract
Description
[0001] This application is a divisional application of the invention patent application with application date of March 5, 2019, application number 2019101624378, and invention name “Power semiconductor device power cycle test system”. Technical Field
[0002] The invention relates to a semiconductor device testing device, and in particular to a power cycle testing system for power semiconductor devices with high accuracy, good reliability and wide application range. Background Art
[0003] Power semiconductor devices (IGBT, MOSFET, GaN HEMT, etc.) are important devices for power electronics and power conversion and have been widely used in new energy power generation, server power supplies, electric vehicles and other fields. As the core power device of the switching power supply, the reliability of power semiconductor devices directly affects the stability of the system, and the main reason for the reduction of the reliability of power semiconductor devices is the damage during the switching process. Therefore, how to effectively evaluate the intermittent life of power semiconductor devices is crucial.
[0004] At present, a power cycle test system has been used to conduct reliability tests on samples of devices (hundreds of devices) in production to evaluate the intermittent life of the batch of power semiconductor devices. The main purpose is to test the number of complete power cycle cycles including heating and cooling that the device under test can achieve within a set time. The maximum junction temperature reached during heating is T jmax and cooling to achieve the minimum junction temperature T jmin , the difference between the two needs to reach a certain standard (such as 100°C), that is, the junction temperature of the device under test needs to be monitored in real time.
[0005] However, the existing power cycle test system usually uses the detection of parasitic diode voltage drop to determine the junction temperature of the device under test, and for this purpose, a reverse small current test needs to be added. This method not only increases the difficulty of system equipment control, but also prolongs the temperature measurement interval, and cannot accurately feedback the real-time junction temperature of the device under test; at the same time, the heating will be interrupted, resulting in large fluctuations in the junction temperature of the device under test during the test, affecting the test accuracy. In addition, the existing power cycle test system is only suitable for devices such as IGBT or MOSFET, and cannot be used to test GaN HEMT, so the scope of application is relatively narrow.
[0006] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above content has been disclosed before the filing date of this patent application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention
[0007] The present invention aims to solve the above technical problems existing in the prior art and to provide a power semiconductor device power cycle test system with high accuracy, good reliability and wide application range.
[0008] The technical solution of the present invention is: a power semiconductor device power cycle test system, characterized in that: a control circuit and a voltage-stabilized power supply, a refrigeration device and a device under test drive circuit controlled by the control circuit are provided; the output of the voltage-stabilized power supply is respectively connected to multiple detection branches; the detection branch is provided with a current-sensing resistor connected to the voltage-stabilized power supply, a low-resistance switching device controlled to be disconnected by the control circuit is connected in series with the detection resistor, a voltage-dividing resistor is connected in parallel with the low-resistance switching device, both ends of the current-sensing resistor are connected to an analog signal selection circuit, the output of the analog signal selection circuit is connected to a voltage signal acquisition circuit; the output of the voltage signal acquisition circuit is connected to the control circuit; during testing, the device under test drive circuit is connected to the gate of the device under test, the low-resistance switching device is connected in series with the device under test, and the analog signal selection circuit is also connected between the source and drain of the device under test.
[0009] The present invention can periodically transmit the voltage across the current sensing resistor and the voltage across the device under test to the controller through the analog signal selection circuit and the voltage signal acquisition circuit provided. The controller calculates the resistance of the device under test in real time by calculating the two voltage values, and calculates the junction temperature of the device under test based on the pre-obtained curve model of the corresponding relationship between junction temperature and resistance. The junction temperature of the device under test can be accurately captured in real time without the need for reverse small current testing, which reduces the difficulty of equipment control, avoids the phenomenon of large fluctuations in junction temperature due to passive interruption of heating, and improves test accuracy and reliability. The present invention is not only applicable to devices such as IGBT or MOSFET, but can also be used to test GaN HEMT, expanding the scope of application. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0011] Figure 1 4 is a circuit principle block diagram of an embodiment of the present invention.
[0012] Figure 2 4 is a circuit diagram of each test branch in an embodiment of the present invention.
[0013] Figure 3 It is a timing diagram of two test branches according to an embodiment of the present invention. DETAILED DESCRIPTION
[0014] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0015] The power semiconductor device power cycle test system of the present invention is as follows Figure 1 , Figure 2 As shown: the box is equipped with a control circuit (single chip microcomputer, etc.) and multiple voltage-stabilized power supplies, refrigeration devices and the device under test drive circuit controlled by the control circuit. The refrigeration device can use a fan or a cooling water circulation system, etc.; the output V 0 They are connected to multiple detection branches respectively. According to actual needs, each voltage-stabilized power supply can be connected to 1 to 40 test branches; the detection branch is equipped with a current-sensing resistor R connected to the voltage-stabilized power supply. view , and the current sensing resistor R view The output voltage (V gate ) controls the low-resistance switch device FET to be turned on and off, and a voltage divider resistor R is connected in parallel with the low-resistance switch device FET 0 , resistor R 0 The resistance value can be set to 10-1000Ω, which is much higher than the on-resistance of FET. view The two ends X1 and Y1 are connected to the analog signal selection circuit (CD4052B logic chip), and the output of the analog signal selection circuit is connected to the voltage signal acquisition circuit (voltmeter, etc.); the output of the voltage signal acquisition circuit is connected to the control circuit; during the test, the device under test drive circuit is connected to the gate of the device under test DUT, and the output voltage V 1 The gate of the device under test DUT is controlled to keep the device under test DUT in the on state all the time. The low-resistance switch device FET is connected in series with the device under test DUT, and the analog signal selection circuit is also connected between the drain and source (X2, Y2) of the device under test DUT.
[0016] Working process:
[0017] The control circuit controls each regulated power supply to provide V for each test branch. 0 (1~100V) intermittent power supply. For example, the power supply is on for 1~999 seconds and off for 1~999 seconds. The complete power supply and off process is one cycle. Each test can be set to 1~99999 cycles. During the continuous power supply of the regulated power supply, the device under test DUT works in two states. One is when the low-resistance switch device FET is on. Due to the resistance R 0The resistance is much larger than the on-resistance R of the FET FETon , which is equivalent to the current sensing resistor R in the circuit view The on-resistance R of the FET FETon And the on-resistance R DUTon In series, the current flowing through the device under test DUT is the largest, which is I DUT =V 0 / (R view +R FETon +R DUT )) to achieve rapid temperature rise of the device under test DUT; the other is when the low-resistance switching device FET is turned off, due to the resistance R 0 The resistance is much smaller than the off resistance of FET, which is equivalent to the current sensing resistor R in the circuit. view With the voltage divider resistor R 0 And the on-resistance R DUTon In series, the current flowing through the device under test DUT is small, which is I DUT =V 0 / (R view +R 0 +R DUT )) to achieve slow cooling of the device under test.
[0018] At the same time, the analog signal selection circuit realizes that the measured terminals X1, Y1 and X2, Y2 are periodically connected to the voltage signal acquisition circuit, so as to quickly obtain the measured voltage value V X1Y1 、V X2Y2 The control circuit controls the voltage signal V X1Y1 、V X2Y2 The real-time on-resistance R of the device under test DUT is obtained by calculation and analysis. DUT Resistance, i.e. R DUT =V X2Y2 / (V X1Y1 / R view ). The junction temperature T of the device under test is calculated by using the pre-obtained junction temperature and resistance corresponding curve model. j , so as to realize the junction temperature T of the device under test DUT j Real-time crawling.
[0019] The control circuit measures the junction temperature T j For analysis, when the junction temperature T j reaches the preset maximum junction temperature T jmax When the junction temperature Tj is lower than the set value T jsetThe low-resistance switch device FET is turned on again and continues to heat the device under test. The low-resistance switch device FET is repeatedly controlled to turn on and off until the set power supply time is reached. At this time, the power supply is turned off, and the controller controls the refrigeration device to quickly cool the device under test DUT to the lowest junction temperature T jmin , and in T jmin Maintain stability until the set regulated power supply off time is reached.
[0020] The power semiconductor device power cycle test system of the present invention will repeat the above operation to complete a complete power cycle including heating and cooling until the set number of cycles is completed. The timing diagram of the two test branches of the embodiment of the present invention is shown in FIG. Figure 3 shown. Figure 3 DUT1 and DUT2 are two devices under test, V gate1 V gate2 They are the voltages that control the FET of the low-resistance switch device in the test branch to turn off. If the set number of cycles is not reached, it is considered unqualified. After all the cycle tests are completed, the basic parameters of the products will be tested after they are taken out. If the parameters are unqualified, they are still considered unqualified.
[0021] The above embodiments prepared by the method of the present invention are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be included in the protection scope of the present invention.
Claims
1. A power cycle test system suitable for power semiconductor devices, characterized in that: It includes a control circuit, a voltage-stabilized power supply, a refrigeration device and a device under test driving circuit; the output of the voltage-stabilized power supply is respectively connected to a plurality of detection branches; the detection branch has a current-sensing resistor connected to the voltage-stabilized power supply, and the current-sensing resistor is connected in series with a low-resistance switch device; the device under test is connected in series with the low-resistance switch device; The control circuit is used to control each voltage-stabilized power supply to provide intermittent power supply for each detection branch; during the process of continuous power supply by the voltage-stabilized power supply, the device under test has two states, the first state is when the low-resistance switching device is in the on state, at which time the current flowing through the device under test is the largest, which is used to achieve temperature increase of the device under test; the second state is when the low-resistance switching device is in the off state, at which time the current flowing through the device under test is small, which is used to achieve temperature reduction of the device under test.
2. The power cycle test system according to claim 1, characterized in that: The voltage-stabilized power supply, the refrigeration device and the device-under-test drive circuit are all connected to and controlled by the control circuit.
3. The power cycle test system according to claim 1, characterized in that: The two ends of the current-sensing resistor are connected to the analog signal selection circuit, and the output of the analog signal selection circuit is connected to the voltage signal acquisition circuit; the output of the voltage signal acquisition circuit is connected to the control circuit; the device under test is connected between the device under test driving circuit and the analog signal selection circuit.
4. The power cycle test system according to claim 3, characterized in that: During testing, the device under test driving circuit is connected to the gate of the device under test, and the analog signal selection circuit is connected between the source and drain of the device under test.
5. The power cycle test system according to claim 1, characterized in that: The low-resistance switch device is switched on and off by the output voltage of the control circuit; and a voltage-dividing resistor is connected in parallel to the low-resistance switch device.
6. The power cycle test system according to claim 5, characterized in that: The resistance value of the voltage-dividing resistor is greater than the on-resistance of the low-resistance switch device; the resistance value of the voltage-dividing resistor is less than the off-resistance of the low-resistance switch device.
7. The power cycle test system according to claim 6, characterized in that: In the first state, the current I flowing through the device under test DUT For I DUT =V0 / (R view +R FETon +R DUT ), where V0 is the output voltage of the regulated power supply, R view is the resistance of the current sensing resistor, R FETon is the on-resistance of the low-resistance switch device, R DUT is the on-resistance of the device under test.
8. The power cycle test system according to claim 6, characterized in that: In the second state, the current I flowing through the device under test DUT For I DUT =V0 / (R view +R0+R DUT ), where V0 is the output voltage of the regulated power supply, R view is the resistance value of the current sensing resistor, R0 is the resistance value of the voltage divider resistor, R DUT is the on-resistance of the device under test.
9. The power cycle test system according to claim 1, characterized in that: A complete power supply and shutdown process in the intermittent power supply is a cycle, and each test can be set to 1 to 99999 cycles.
10. The power cycle test system according to any one of claims 1 to 9, characterized in that: Each of the voltage-stabilized power supplies is connected to 1 to 40 test branches.