Test circuit and induction amplifier performance test method

Abstract

The invention provides a test circuit which is applied to the technical field of memories. The test circuit comprises a memory bank control circuit, a test mode setting module and a memory block control circuit, the memory bank control circuit is used for generating and outputting an equalization control signal according to a control instruction, and the control instruction comprises a column control enable signal and an equalization enable signal; the test mode setting module is used for receiving a test mode setting instruction and a column control enable signal, and generating and outputting a column control test signal; the memory bank control circuit is in communication connection with the memory bank control circuit and the test mode setting module, and is used for generating a pre-charge control signal according to the column control test signal and the balance control signal; and controlling the potential of the local data line or the local complementary data line to be pre-charged from the bit line balanced voltage to the starting time of the power supply voltage in the working stage of the induction amplifier so as to control the influence of noise generated when the local data line or the local complementary data line is pre-charged to the power supply voltage on the induction amplifier.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit testing, and in particular to a test circuit for testing the performance of a sense amplifier and a sense amplifier performance test method implemented by using the test circuit. Background Art

[0002] The sensor amplifier is an important component in DRAM, and its performance directly affects the performance of the memory. Therefore, it is an important requirement in the memory manufacturing field to perform performance testing on the sensor amplifier to optimize the design parameters of the sensor amplifier.

[0003] Since the layout of the sense amplifier part is relatively tight, the noise caused by the coupling effect between signals particularly affects the performance of the sense amplifier. Therefore, when performing performance testing on the sense amplifier, testing the sense amplifier's resistance to signal noise is an important test item.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a test circuit and a method for testing the performance of a sense amplifier, which are used to perform a performance test on the sense amplifier to assist in optimizing the design parameters of the sense amplifier.

[0006] According to a first aspect of the present disclosure, a test circuit is provided, comprising: a memory body control circuit, configured to receive a control instruction, and generate and output an equalization control signal according to the control instruction; wherein the control instruction comprises a column control enable signal and an equalization enable signal; a test mode setting module, configured to receive a test mode setting instruction and a column control enable signal, and generate and output a column control test signal according to the test mode setting instruction and the column control enable signal; a memory block control circuit, communicatively connected to the memory body control circuit and the test mode setting module, configured to generate a precharge control signal according to the column control test signal and the equalization control signal, and in a working phase of a sense amplifier, controlling whether a potential of a local data line or a local complementary data line is precharged from a bit line equalization voltage to a power supply voltage according to the precharge control signal, and controlling a start time when the potential of the local data line or the local complementary data line is precharged from the bit line equalization voltage to the power supply voltage, so as to test the influence of noise generated when the local data line or the local complementary data line is precharged to the power supply voltage on the sense amplifier; wherein the local data line and the local complementary data line are connected to corresponding sense amplifiers.

[0007] In an exemplary embodiment of the present disclosure, the column control enable signal indicates that the sense amplifier operates in a read / write mode or a refresh mode; the first state of the equalization enable signal indicates that the memory control circuit generates an equalization control signal after the offset elimination phase of the sense amplifier ends, and the second state of the equalization enable signal indicates that the memory control circuit does not generate an equalization control signal after the offset elimination phase of the sense amplifier ends; the test mode setting instruction includes a noise-free test instruction, a noise test instruction, and an adaptive test instruction; the memory control circuit generates a first equalization control signal when the equalization enable signal is in a first state; the memory block control circuit generates a first precharge control signal according to the first equalization control signal to control the potential of the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage after the offset elimination phase of the sense amplifier ends; the memory control circuit generates a second equalization control signal when the equalization enable signal is in a second state; the memory block control circuit generates a second equalization control signal; The control circuit generates a second pre-charge control signal according to the second equalization control signal, so as to control the potential of the local data line and the local complementary data line to be pre-charged from the bit line equalization voltage to the power supply voltage after the sense amplifier is activated and before the offset elimination phase begins; the test mode setting module generates a column control test signal for prohibiting the column operation state when the test mode setting instruction is a noise-free test instruction, so as to set the storage block control circuit to generate and output a third pre-charge control signal, so as to control the potential of the local data line and the local complementary data line to remain unchanged during the working phase of the sense amplifier; the test mode setting module generates a column control test signal for allowing the column operation state when the test mode setting instruction is a noisy test instruction, so as to set the storage block control circuit to generate and output the first pre-charge control signal or the second pre-charge control signal according to the equalization control signal; the test mode setting module generates a column control test signal with the same state as the column control enable signal when the test mode setting instruction is an adaptive test instruction.

[0008] In an exemplary embodiment of the present disclosure, a test mode setting instruction is represented by a first identifier and a second identifier, and a test mode setting module includes: a first inverter, whose input terminal receives a column control enable signal; an AND gate, whose first input terminal is used to receive the first identifier, and whose second input terminal is connected to the output terminal of the first inverter; and an NOR gate, whose first input terminal is used to receive the second identifier, whose second input terminal is connected to the output terminal of the AND gate, and whose output terminal is used to output a column control test signal.

[0009] In an exemplary embodiment of the present disclosure, a storage body control circuit is connected to multiple storage block control circuits; the storage body control circuit is also used to receive a row enable control signal and a row address signal, generate a row control signal according to the row enable control signal, and send the row control signal to the corresponding storage block control circuit according to the row address signal; the storage block control circuit is used to receive a row control signal and a row address signal, and control the corresponding row control circuit to perform a row operation according to the row control signal and the row address signal.

[0010] In an exemplary embodiment of the present disclosure, a storage block control circuit includes a column operation control circuit, the column operation control circuit determines the state of an output precharge control signal according to a column control test signal, and the column operation control circuit includes: a first enable signal inverter, an input end of the first enable signal inverter receives the column control test signal, and an output end of the first enable signal inverter outputs a first enable signal; a second enable signal inverter, an input end of the second enable signal inverter is connected to an output end of the first enable signal inverter, and is used to invert the first enable signal to output a second enable signal; the column operation signal The control path has an input end, an output end, a first control end and a second control end. The input end of the column operation signal control path receives the pre-charge control signal, and the output end of the column operation control path is used to output the pre-charge control signal. The first control end and the second control end of the column operation control path respectively receive the first enable signal and the second enable signal. When the first enable signal and the second enable signal are both in a valid state, the column operation control path outputs the first pre-charge control signal or the second pre-charge control signal. When the first enable signal and the second enable signal are both in an invalid state, the column operation control path outputs a third pre-charge control signal.

[0011] In an exemplary embodiment of the present disclosure, a column operation signal control path includes: a pull-up transistor, which is a P-type transistor, whose gate serves as the first control end of the column operation control path to receive a first enable signal, and whose source is connected to a power supply voltage; a pull-down transistor, which is an N-type transistor, whose gate serves as the second control end of the column operation control path to receive a second enable signal, and whose source is grounded; a first P-type inverter, a first N-type inverter, a second P-type inverter, and a second N-type inverter connected in series, wherein the power supply ends of the first P-type inverter and the second P-type inverter are connected to the drain of the pull-up transistor, the ground ends of the first N-type inverter and the second N-type inverter are connected to the drain of the pull-down transistor, the input end of the first P-type inverter is the input end of the column operation control path, and the output end of the second N-type inverter is the output end of the column operation control path.

[0012] In an exemplary embodiment of the present disclosure, the sense amplifier in the sense amplifier test circuit corresponds to a set of design parameters through the test circuit of any of the above embodiments, and the design parameters include one or more signal characteristic parameters and one or more circuit characteristic parameters, and the method includes: determining a target operating mode, the target operating mode includes a first read-write mode and a second read-write mode; in the target operating mode, before the sense amplifier completes the sensing amplification action, the potential of the local data line and the local complementary data line is controlled to remain unchanged, and a sensing margin test is performed to obtain a first sensing margin; in the target operating mode, the potential of the local data line and the local complementary data line is controlled to be precharged from a bit line equalization voltage to a power supply voltage during the working phase of the sense amplifier, and a sensing margin test is performed to obtain a second sensing margin; according to the second sensing margin and the first sensing margin, a sensing margin impact evaluation value corresponding to the target operating mode of the sense amplifier under the current design parameters is determined; a plurality of sensing margin impact evaluation values ​​corresponding to a plurality of operating modes under the current design parameters are obtained, and the current design parameters are evaluated or optimized according to the plurality of sensing margin impact evaluation values.

[0013] In an exemplary embodiment of the present disclosure, performing a sensing margin test includes: writing test data to a target storage unit connected to a sensing amplifier according to a test charge; controlling the sensing amplifier to perform sensing amplification and then reading a target bit line to obtain a data reading result, the target bit line connecting the sensing amplifier and the target storage unit; when the data reading result corresponds to a correct reading result of the test data, reducing the value of the test charge, rewriting the test data, and looping the previous step; when the data reading result does not correspond to a correct reading result of the test data, determining a sensing margin value of the sensing amplifier in a current test environment according to the test charge, the current test environment including a target operating mode and a level change of a local data line connected to the sensing amplifier during a working phase of the sensing amplifier.

[0014] In an exemplary embodiment of the present disclosure, in a first read-write mode, the sense amplifier operates in a read-write mode, and the storage body control circuit generates a first equalization control signal, and in the working phase of the sense amplifier, controlling the potential of the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage includes: inputting an adaptive test instruction or a noisy test instruction to a test mode setting module, so that the test mode setting module generates a column control test signal that allows a column operation state, so that the storage block control circuit outputs the first precharge control signal, and after the offset elimination phase ends, controlling the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage.

[0015] In an exemplary embodiment of the present disclosure, in the second read-write mode, the sense amplifier operates in the read-write mode, and the storage body control circuit generates a second equalization control signal, and in the working stage of the sense amplifier, the potential of the local data line and the local complementary data line is controlled to be precharged from the bit line equalization voltage to the power supply voltage, including: inputting an adaptive test instruction or a noisy test instruction to the test mode setting module, so that the test mode setting module outputs a column control test signal that allows the column operation state, so that the storage block control circuit outputs the second precharge control signal, and the potential of the local data line and the local complementary data line is controlled to change from the bit line equalization voltage to the power supply voltage after the sense amplifier is activated and before the offset elimination stage begins.

[0016] In an exemplary embodiment of the present disclosure, in the first read-write mode or the second read-write mode, controlling the potential of the local data line and the local complementary data line to remain unchanged during the working phase of the sense amplifier includes: inputting a noise-free test instruction to a test mode setting module in response to an activation instruction to the sense amplifier, so that the test mode setting module outputs a column control test signal that prohibits the column operation state, so that the storage block control circuit outputs a third pre-charge control signal, and controls the potential of the local data line and the local complementary data line to remain unchanged before a first time point when the sense amplifier completes the sensing amplification action; at the first time point when the sense amplifier completes the sensing amplification action, inputting an adaptive noise instruction to the test mode setting module, so that the test mode setting module outputs a column control test signal that allows the column operation state, so that the storage block control circuit controls the local data line and the local complementary data line to be pre-charged from the bit line equalization voltage to the power supply voltage after the first time point.

[0017] In an exemplary embodiment of the present disclosure, the target operating mode also includes a first refresh mode. In the first refresh mode, the storage body control circuit generates and outputs a first equalization control signal. Controlling the potential of the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage during the working phase of the sense amplifier includes: inputting a noisy test instruction to the test mode setting module, so that the test mode setting module outputs a column control test signal that allows the column operation state, so that the storage block control circuit outputs the first precharge control signal, and controlling the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage after the equalization control signal ends.

[0018] In an exemplary embodiment of the present disclosure, the target operating mode also includes a second refresh mode, in which the sense amplifier operates in a refresh mode, and the storage body control circuit generates a second equalization control signal, and in the working phase of the sense amplifier, the potential of the local data line and the local complementary data line is controlled to be precharged from the bit line equalization voltage to the power supply voltage, including: inputting a noisy test instruction to the test mode setting module, so that the test mode setting module outputs a column control test signal that allows the column operation state, so that the storage block control circuit generates a second precharge control signal, and the potential of the local data line and the local complementary data line is controlled to change from the bit line equalization voltage to the power supply voltage after the sense amplifier is activated and before the offset elimination phase begins.

[0019] In an exemplary embodiment of the present disclosure, in the first refresh mode or the second refresh mode, controlling the potential of the local data line and the local complementary data line to remain unchanged during the working phase of the sense amplifier includes: inputting a noise-free test instruction or an adaptive test instruction to a test mode setting module, so that the test mode setting module outputs a column control test signal that prohibits the column operation state, so that the storage block control circuit outputs a third pre-charge control signal, and controlling the potential of the local data line and the local complementary data line to remain unchanged during the working phase of the sense amplifier.

[0020] In an exemplary embodiment of the present disclosure, determining the inductive margin impact evaluation value corresponding to the target operating mode of the sensing amplifier under the current design parameters based on the second inductive margin and the first inductive margin includes: determining the difference between the first inductive margin and the second inductive margin as the inductive margin impact evaluation value corresponding to the target operating mode.

[0021] In an exemplary embodiment of the present disclosure, evaluating or optimizing current design parameters according to multiple inductive margin impact evaluation values ​​includes: obtaining multiple inductive margin impact evaluation values ​​corresponding to each group of design parameters in multiple groups of design parameters; and determining the design parameters of the inductive amplifier according to the multiple inductive margin impact evaluation values ​​corresponding to the multiple groups of design parameters.

[0022] The embodiments of the present disclosure set up a test circuit and use the test circuit to perform a sensing margin test in the presence of noise and a sensing margin test in the absence of noise on the sensing amplification process of the sensing amplifier in various working modes. The test circuit can test the degree of influence of noise generated during the control process of the sensing margin of the sensing amplifier under current design parameters, thereby evaluating or improving the design parameters of the sensing amplifier.

[0023] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0025] Figure 1 is a schematic structural diagram of a test circuit in an exemplary embodiment of the present disclosure.

[0026] Figure 2A This is the connection diagram of the sense amplifier.

[0027] Figure 2B is the circuit diagram of the sense amplifier.

[0028] Figure 2C It is a schematic diagram of the control relationship between the local data line and the local complementary data line and the equalization control signal and the pre-charge control signal.

[0029] Figure 3A and Figure 3B There are two normal working modes Figure 2A to Figure 2C Control timing diagram of the circuit shown.

[0030] Figure 4 is a schematic diagram of a column operation control circuit in one implementation of the present disclosure.

[0031] Figure 5 It is a schematic diagram of a test mode setting module in one embodiment of the present disclosure.

[0032] Figure 6 It is a schematic diagram of the relationship between various signals and circuits in the embodiment of the present disclosure.

[0033] Figure 7 4 is a flow chart of a method for testing performance of a sensing amplifier in an embodiment of the present disclosure.

[0034] Figure 8 is a flow chart of a sensing margin test in one embodiment of the present disclosure.

[0035] Fig. 9A and Fig. 9B This is a control timing comparison diagram of a noisy test and a noise-free test in a first read-write mode in an embodiment of the present disclosure.

[0036] Fig. 10A and Fig. 10B This is a control timing comparison diagram of a noisy test and a noise-free test in a second read-write mode in an embodiment of the present disclosure.

[0037] Fig.11A and Fig. 11B3 is a control timing comparison diagram of a noisy test and a noise-free test in the first refresh mode in an embodiment of the present disclosure.

[0038] Fig. 11C and Fig.11D 3 is a control timing comparison diagram of a noisy test and a noise-free test in the second refresh mode in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0040] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0041] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0042] Figure 1 is a schematic structural diagram of a test circuit in an exemplary embodiment of the present disclosure.

[0043] refer to Figure 1 , the test circuit 100 may include:

[0044] The memory control circuit 1 is used to receive a control instruction, and generate and output an equalization control signal EQ according to the control instruction; wherein the control instruction includes a column control enable signal Scmos_Col and an equalization enable signal NCEQ;

[0045] A test mode setting module 2, used for receiving a test mode setting instruction TM and a column control enable signal Scmos_Col, and generating and outputting a column control test signal Scmos_Col_Xdec according to the test mode setting instruction TM and the column control enable signal Scmos_Col;

[0046] The memory block control circuit 3 is communicatively connected with the memory body control circuit 1 and the test mode setting module 2, and is used to generate a precharge control signal EQIO according to the column control test signal Scmos_Col_Xdec and the equalization control signal EQ, and in the working phase of the sense amplifier in the memory array 4, controls whether the potential of the local data line LIO or the local complementary data line LIO# is precharged from the bit line equalization voltage VBLP to the power supply voltage VCC according to the precharge control signal EQIO, and controls the start time of precharging the potential of the local data line LIO or the local complementary data line LIO# from the bit line equalization voltage VBLP to the power supply voltage, so as to test the influence of the noise generated when the local data line LIO or the local complementary data line LIO# is precharged to the power supply voltage VCC on the sense amplifier;

[0047] The local data line LIO or the local complementary data line LIO# is connected to the corresponding sense amplifier 4 .

[0048] The bank control circuit 1 is also called a bank logic circuit (Bank Logic), and is used to output control logic, such as an equalization control signal EQ, to multiple storage block control circuits 3 (Array SAControl, sense amplifier array control) in a bank.

[0049] The storage block control circuit 3 performs column control on the sense amplifier in the storage array (referred to as a storage block in the disclosed embodiment) according to the equalization control signal EQ output by the storage body control circuit 1 and the column control test signal Scmos_Col_Xdec output by the test mode setting module 2. The column control includes controlling whether the potential of the local data line LIO or the local complementary data line LIO# is precharged from the bit line equalization voltage VBLP to the power supply voltage VCC through the precharge control signal EQIO, and controlling the start time of the potential of the local data line LIO or the local complementary data line LIO# being precharged from the bit line equalization voltage VBLP to the power supply voltage. The column control test signal Scmos_Col_Xdec is used to determine whether the potential of the local data line LIO or the local complementary data line LIO# is precharged from the bit line equalization voltage VBLP to the power supply voltage.

[0050] The line equalization voltage VBLP is precharged to the power supply voltage VCC, and the equalization control signal EQ is used to determine the start time when the potential of the local data line LIO or the local complementary data line LIO# is precharged from the bit line equalization voltage VBLP to the power supply voltage.

[0051] In addition, the storage body control circuit 1 also receives a row enable control signal and a row address signal, generates a row control signal according to the row enable control signal, and sends the row control signal to the corresponding storage block control circuit 3 according to the row address signal; the storage block control circuit 3 receives the row control signal and the row address signal, and controls the corresponding row control circuit to perform row operations according to the row control signal and the row address signal.

[0052] The following describes the principles of application of the embodiments of the present disclosure.

[0053] Figure 2A This is a connection diagram of the storage array.

[0054] Figure 2B is the circuit diagram of the sense amplifier.

[0055] Figure 2C It is a schematic diagram of the control relationship between the local data line and the local complementary data line and the equalization control signal and the pre-charge control signal.

[0056] refer to Figure 2A The memory array 4 includes a sense amplifier 41 and a memory cell 42 . The sense amplifier 41 and the memory cell 42 are connected via a bit line BLA. Meanwhile, the bit line BLA is connected to a local data line LIO via a read / write control unit 5 .

[0057] The storage cell 42 includes a storage transistor Mcell and a storage capacitor C. The drain and source of the storage transistor Mcell are connected to the bit line BLA and the upper plate of the storage capacitor C respectively, and the gate is connected to the word line WL; the lower plate of the storage capacitor C is grounded. The storage cell 42 is controlled by the word line WL, and charge sharing is realized between the bit line BLA and the storage capacitor C, and charge / data storage is realized through the storage capacitor C.

[0058] The read / write control unit 5 is used to transmit data between the local data line LIO and the bit line BLA. The read / write control unit 5 mainly includes a read / write control transistor MRW. The source of the read / write control transistor MRW is connected to the bit line BLA, the drain is connected to the local data line LIO, and the gate is controlled by the column selection signal CSL.

[0059] In the data writing operation, the column selection signal CSL controls the read / write control transistor MRW to turn on, and the local data line LIO transmits data to the bit line BLA. The sense amplifier 41 senses and amplifies the charge transmitted from the local data line LIO to the bit line BLA, and pulls the potential of the bit line BLA and the complementary bit line BLB to the power supply voltage and the zero potential respectively (the specific potential of the bit line BLA depends on the data transmitted on the bit line BLA), that is, the easily identifiable data 1 and data 0. After the sense amplification action is completed, the word line WL controls the storage transistor Mcell to turn on, so that the charge exchange occurs between the bit line BLA and the storage capacitor C. After the word line WL controls the storage transistor Mcell to turn off, the storage capacitor C realizes data storage.

[0060] In the data reading operation, the word line WL controls the storage transistor Mcell to turn on, so that charge exchange occurs between the bit line BLA and the storage capacitor C. The sensing amplifier 41 senses and amplifies the potential difference between the bit line BLA with charge change and the complementary bit line BLB with no charge change, so as to set the bit line BLA and the complementary bit line BLB to easily readable data 0 / 1 respectively. After the sensing and amplification action is completed, the column selection signal CSL controls the read-write control transistor MRW to turn on, and transfers the data on the bit line BLA to the local data line LIO, so as to realize the reading of the data stored in the storage capacitor C.

[0061] The bit line BLA and the complementary bit line BLB are in a relative relationship and are connected to different memory cells respectively.

[0062] refer to Figure 2B The sensing amplifier 41 includes a first P-type transistor MP1, a second P-type transistor MP2, a first N-type transistor MN1, and a second N-type transistor MN2 for sensing amplification, a first switch tube MC1, a second switch tube MC2, a third switch tube MC3, and a fourth switch tube MC4 for noise elimination / offset elimination, and a fifth switch tube MC5 and a sixth switch tube MC6 for controlling node potential balance.

[0063] The sources of the first P-type transistor MP1 and the second P-type transistor MP2 are connected to the first voltage PCS, the sources of the first N-type transistor MN1 and the second N-type transistor MN2 are connected to the second voltage NCS, the drains of the first P-type transistor MP1 and the first N-type transistor MN1 are connected to the first node N1, and the drains of the second P-type transistor MP2 and the second N-type transistor MN2 are connected to the second node N2.

[0064] The first end and the second end of the first switch transistor MC1 are respectively connected to the first node N1 and the complementary bit line BLB, the first end and the second end of the second switch transistor MC2 are respectively connected to the second node N2 and the bit line B1A, the first end and the second end of the third switch transistor MC3 are respectively connected to the first node N1 and the bit line BLA, and the first end and the second end of the fourth switch transistor MC4 are respectively connected to the second node N2 and the complementary bit line BLB. The first switch transistor MC1 and the second switch transistor MC2 are controlled by the isolation control signal ISO, and the third switch transistor MC3 and the fourth switch transistor MC4 are controlled by the offset cancellation signal NC.

[0065] The first end and the second end of the fifth switch tube MC5 are connected to the bit line equalization voltage VBLP and the first node N1 respectively, the first end and the second end of the sixth switch tube MC6 are connected to the bit line equalization voltage VBLP and the second node N2 respectively, and the fifth switch tube MC5 and the sixth switch tube MC6 are both controlled by the equalization control signal EQ to achieve potential balance between the first node N1 and the second node N2.

[0066] refer to Figure 2C The local data line LIO and the complementary local data line LIO# (connected to another bit line) can be connected by Figure 2C The precharge circuit shown implements precharge before read and write operations.

[0067] Combination Figure 2B The circuit of the sensing amplifier 41 shown in the figure needs to keep the voltage levels between the first node N1 and the second node N2 equal (that is, the levels of the bit line BLA and the complementary bit line BLB are equal) before the sensing amplifier 41 amplifies the voltage difference between the first node N1 and the second node N2, and when data is transmitted to the first node N1 or the second node N2, it is necessary to keep the potential of the node that does not receive the data transmission unchanged, so that when the voltage of the first node N1 or the second node N2 changes due to the data transmission process, the voltage difference between the bit line BLA and the complementary bit line BLB can be amplified by comparing the voltage difference between the node where the voltage changes and the node where the potential remains unchanged.

[0068] Before activating the sense amplifier, the bit line BLA and the complementary bit line BLB must be controlled to be equal to the bit line equalization voltage VBLP. At the same time, in order to avoid signal confusion during data transmission, the equalization control signal EQ must also be used to control the bit line voltage. Figure 2C The circuit portion 22 shown sets both the local data line LIO and the complementary local data line LIO# equal to the bit line equalization voltage VBLP.

[0069] Before the column select signal CSL is used to control the read / write control transistor MRW to turn on and connect the bit line BLA to the local data line LIO, the precharge control signal EQIO is required to control the Figure 2CThe circuit portion 21 shown raises the potential of the local data line LIO and the complementary local data line LIO# from the bit line equalization voltage VBLP to the power supply voltage VCC, thereby realizing data transmission.

[0070] When the potential of the local data line LIO and the complementary local data line LIO# is increased from the bit line equalization voltage VBLP to the power supply voltage VCC, noise will be generated. This noise can be called IO noise. Since the layout of the sense amplifier part is very compact, the crosstalk (coupling) between signals will be very serious. The existence of IO noise will affect the sense margin (SM) of the storage array 4.

[0071] Under different design parameters (including circuit design parameters and signal design parameters), the sense amplifier 41 is affected by the above noise to different degrees. Therefore, when optimizing the design parameters of the sense amplifier 41, the resistance of the sense amplifier 41 to the above noise needs to be considered.

[0072] The disclosed embodiment implements the noise resistance of the sense amplifier 41 in various working modes through the test circuit 100, and can evaluate the advantages and disadvantages of the current design parameters of the sense amplifier, and then improve the design parameters of the sense amplifier by subsequently testing the noise resistance of the sense amplifier under multiple sets of design parameters. This part of the principle and embodiment will be explained in detail later.

[0073] Figure 3A and Figure 3B There are two normal working modes Figure 2A to Figure 2C Control timing diagram of the circuit shown.

[0074] refer to Figure 3A In one embodiment, when the idle phase (IDLE) ends, the equalization signal EQ changes from a high level to a low level, and the balancing transistor MEQ is turned off, ending the restriction on the potential equalization of the internal nodes of the sense amplifier, allowing a voltage difference to appear in the internal nodes of the sense amplifier, and allowing the potential of the internal nodes of the sense amplifier to be not equal to the bit line equalization voltage VBLP.

[0075] At this time, the offset cancel (OC) phase or the noise cancel (NC) phase is entered. The offset cancel signal NC is at a high level, the first node N1 is connected to the bit line BLA, and the second node N2 is connected to the complementary bit line BLB. Due to the voltage difference between the first node N1 and the second node N2, a voltage difference occurs between the bit line BLA and the complementary bit line BLB.

[0076] After the offset elimination phase is over, the word line WL changes from a low level to a high level, the word line WL controls the storage transistor Mcell to turn on, and charge exchange occurs between the storage capacitor C and the bit line BLA, which is called the charge sharing (CS) phase. Figure 3A In the illustrated embodiment, some time after the end of the offset cancellation stage, the equalization signal EQ changes from a low level to a high level and then changes back to a low level after a period of time. In this stage, the isolation control signal ISO and the offset cancellation signal NC are both low levels, the internal nodes of the sense amplifier are not connected to the bit line BLA or the complementary bit line BLB, and the potentials of the internal nodes of the sense amplifier are reset to the bit line equalization voltage VBLP. This operation is called NCEQ (Noise Cancel Equal, equalization after offset cancellation) operation.

[0077] After the NCEQ operation is completed, the isolation control signal ISO is converted from a low level to a high level, allowing the bit line BLA to be connected to the second node N2 of the sense amplifier, and the complementary bit line BLB to be connected to the first node N1 of the sense amplifier, and the voltage difference between the bit line BLA and the complementary bit line BLB is converted to the sense amplifier that has eliminated the internal node offset, so that the sense amplifier enters the sense amplification (Sense) stage, senses and amplifies the voltage difference on the internal node, and allows the voltage after the sense amplification action is completed to be transmitted to the bit line BLA and the complementary bit line BLB, so that the local data line LIO or the complementary local data line LIO# can read the data on the bit line BLA or the complementary bit line BLB by turning on the column selection signal CSL.

[0078] Before reading data, the state of the precharge control signal EQIO needs to be changed to control Figure 2C The precharge circuit 21 in the circuit is turned on to charge the local data line LIO and the complementary local data line LIO# from the bit line equalization voltage VBLP to the power supply voltage VCC.

[0079] exist Figure 3A In the illustrated embodiment, this process occurs after the NCEQ operation is completed. Since the layout of the sense amplifier part is very compact, the crosstalk (coupling) between signals will be very serious, and the noise on the local data line LIO and the complementary local data line LIO# can affect the charge sharing stage and the sense amplification stage of the sense amplifier.

[0080] This working mode with NCEQ operation and allowing data reading and writing after the sense amplification action is completed can be called a first read-write mode.

[0081] refer to Figure 3BIn another embodiment, the equalization control signal EQ only appears before the offset cancellation phase, that is, there is no NCEQ operation in the charge sharing phase. Correspondingly, in this working mode, the precharge control signal EQIO changes after the equalization control signal EQ, and controls the local data line LIO and the complementary local data line LIO# to be charged from the bit line equalization voltage VBLP to the power supply voltage VCC after the sense amplifier is activated and before the offset cancellation phase begins. The noise caused by charging on the local data line LIO and the complementary local data line LIO# can affect the offset cancellation phase, the charge sharing phase, and the sense amplification phase.

[0082] This operation mode without NCEQ operation and allowing data reading and writing after the sense amplification action is completed can be called the second read-write mode.

[0083] In addition to the above read and write modes, the sense amplifier can also work in refresh mode. In refresh mode, the sense amplifier follows the above Figure 3A or Figure 3B The method shown performs offset elimination, charge sharing, and inductive amplification, but after the inductive amplification action is completed, the bit line BLA or the complementary bit line BLB does not perform data transmission with the local data line LIO and the complementary local data line LIO#, that is, no read or write operation is performed. Instead, after the inductive amplification action is completed, that is, after the word line BLA reaches the zero voltage corresponding to data 0 or the power supply voltage VCC corresponding to data 1, the storage capacitor C is restored to data through the open state of the word line WL to offset the charge change of the storage capacitor C over time and maintain the correct data storage state.

[0084] In refresh mode, the refresh action is performed according to the set refresh cycle. Since the sense amplifier does not transmit data with the local data line LIO and the complementary local data line LIO# in refresh mode, the noise generated by the LIO change does not affect any stage of the sense amplifier operation, that is, the sense amplifier is not affected by the noise on the local data line LIO at this time.

[0085] Although the sense amplifier does not transmit data to the local data line LIO and the complementary local data line LIO# in the refresh mode, the bit line equalization signal EQ and the pre-charge control signal EQIO still exist during the refresh process. The output of the pre-charge control signal EQIO is shielded only by setting the column control enable signal Scmos_Col and the corresponding column operation control circuit in the memory, thereby shielding the control of the local data line LIO and the complementary local data line LIO# by the pre-charge control signal EQIO, and shielding the column operation control in the refresh mode.

[0086] In the storage block control circuit 3, a column operation control circuit is provided. The original intention of the design of the column operation control circuit is to receive the column control enable signal Scmos_Col, so as to allow the sense amplifier to perform column operation or shield the column operation according to the state of the column control enable signal Scmos_Col, for example, whether to allow the pre-charge control signal EQIO to be output to control the potential change of the local data line LIO and the complementary local data line LIO#. In the read-write mode (including the first read-write mode and the second read-write mode), the column control enable signal Scmos_Col from the controller is in a valid state, so that the column operation control circuit 400 allows the pre-charge control signal EQIO to be output to control the local data line LIO and the complementary local data line LIO# to be charged to the power supply voltage VCC. In the refresh mode, the column control enable signal Scmos_Col is in an invalid state, so that the storage block control circuit 3 shields the pre-charge control signal EQIO, so that the local data line LIO and the complementary local data line LIO# remain unchanged in the working phase of the sense amplifier. Therefore, the column control enable signal Scmos_Col can indicate whether the sense amplifier is working in the read-write state or the refresh state.

[0087] Figure 4 is a schematic diagram of a column operation control circuit in one implementation of the present disclosure.

[0088] refer to Figure 4 In the embodiment of the present disclosure, the column operation control circuit in the storage block control circuit 3 is configured to receive the column control test signal Scmos_Col_Xdec.

[0089] exist Figure 4 In the embodiment, the column operation control circuit 400 first includes a first enable signal inverter 41 and a second enable signal inverter 42 for generating an enable signal, the input end of the first enable signal inverter 41 receives the column control test signal Scmos_Col_Xdec, and the output end of the first enable signal inverter 41 outputs the first enable signal EnN (the first enable signal EnN is inverted with the column control test signal Scmos_Col_Xdec); the input end of the second enable signal inverter 42 is connected to the output end of the first enable signal inverter 41, and is used to invert the first enable signal EnN to output the second enable signal En (the second enable signal En is in phase with the column control test signal Scmos_Col_Xdec).

[0090] In addition, the column operation control circuit 400 also includes a column operation signal control path 43. One end of the column operation signal control path 43 is used to receive the column operation signal (Column Logic) from the memory body control circuit 1, and the other end is used to output the column operation signal. Whether the column operation signal control path 43 allows the column operation signal received at the input end to be output from its output end is controlled by the first enable signal EnN and the second enable signal En, that is, whether the column operation signal control path 43 works or not is controlled by the column control test signal Scmos_Col_Xdec. Among them, the column operation signal includes but is not limited to the pre-charge control signal EQIO and the column selection signal CSL.

[0091] like Figure 4 As shown, the column operation signal control path 43 is composed of four inverters connected in series, and the four inverters include a first P-type inverter 401, a first N-type inverter 402, a second P-type inverter 403, and a second N-type inverter 404, wherein the power supply terminals of the first P-type inverter 401 and the second P-type inverter 403 are connected to the power supply voltage VCC through a P-type pull-up transistor P0, and the gate of the pull-up transistor P0 receives the first enable signal EnN; the power supply terminals of the first N-type inverter 402 and the second N-type inverter 404 are grounded through an N-type pull-down transistor N0, and the gate of the pull-down transistor N0 receives the second enable signal En.

[0092] When the column control test signal Scmos_Col_Xdec is at a high level, the first enable signal EnN is at a low level, the second enable signal En is at a high level, the pull-up transistor P0 and the pull-down transistor N0 are both turned on, the first P-type inverter 401, the first N-type inverter 402, the second P-type inverter 403, and the second N-type inverter 404 are all working, and the column operation signal of the first P-type inverter 401 is output through the output end of the second N-type inverter 404 to control the sense amplifier to perform column operation.

[0093] When the column control test signal Scmos_Col_Xdec is at a low level, the first enable signal EnN is at a high level, the second enable signal En is at a low level, the pull-up transistor P0 and the pull-down transistor N0 are both turned off, the first P-type inverter 401, the first N-type inverter 402, the second P-type inverter 403, and the second N-type inverter 404 all stop working, the column operation signal of the first P-type inverter 401 will not be transmitted to the output end of the second N-type inverter 404, and the sense amplifier does not perform column operation.

[0094] Therefore, by adjusting the state of the column control test signal Scmos_Col_Xdec, it is possible to set whether to allow the memory block control circuit 3 to perform the column operation or not. Correspondingly, when the memory block control circuit 3 is allowed to perform the column operation, IO noise caused by charging to the power supply voltage VCC will appear on the bit line LIO and the complementary bit line LIO#, which will have a noise impact on the working phase of the sense amplifier; when the memory block control circuit 3 is not allowed to perform the column operation, the voltage on the bit line LIO and the complementary bit line LIO# remains unchanged, no IO noise is generated, and the working phase of the sense amplifier is not affected.

[0095] From the above analysis, it can be seen that both the column control enable signal Scmos_Col and the column control test signal Scmos_Col_Xdec have two conditions: allowing column operation (equal to 1) and not allowing column operation (equal to 0).

[0096] The disclosed embodiment uses a test mode setting instruction TM and a test mode setting module (control logic) to control the state of a column control test signal Scmos_Col_Xdec, and can implement tests with IO noise (column operation allowed) and without IO noise (column operation not allowed) in each operating mode.

[0097] Figure 5 It is a schematic diagram of a test mode setting module in one embodiment of the present disclosure.

[0098] refer to Figure 5 In one embodiment, the test mode setting instruction TM is represented by a first identifier A and a second identifier B, and the test mode setting module 2 includes:

[0099] A first inverter 51, an input terminal of which receives a column control enable signal Scmos_Col;

[0100] An AND gate 52, a first input terminal for receiving a first identifier A, and a second input terminal connected to an output terminal of the first inverter 51;

[0101] The NOR gate 53 has a first input terminal for receiving the second identifier B, a second input terminal connected to the output terminal of the AND gate 52, and an output terminal for outputting the column control test signal Scmos_Col_Xdec.

[0102] The output end of the NAND gate 53 may also output the column control test signal Scmos_Col_Xdec through an even number of inverters connected in series, so as to clamp the signal level of the column control test signal Scmos_Col_Xdec.

[0103] like Figure 5As shown, when the first identifier A=0 and the second identifier B=0, that is, when the test mode setting instruction TM is 00, the output terminal of the NOR gate 53 outputs 1. At this time, no matter what state the column control enable signal Scmos_Col is in, the column control test signal Scmos_Col_Xdec is equal to 1, and the column operation logic transmitted from the memory body control circuit 1 can produce a column operation control effect on the memory block control circuit 3. Therefore, the test mode setting instruction 00 corresponds to a noisy test mode.

[0104] When the first identifier A=0 and the second identifier B=1, that is, the test mode setting instruction TM is 10, or when the first identifier A=1 and the second identifier B=1, the test mode setting instruction TM is 11, the output of the NOR gate 53 outputs 0. At this time, no matter what signal the column control enable signal Scmos_Col is, the column control test signal Scmos_Col_Xdec is equal to 0, and the column operation logic transmitted from the memory body control circuit 1 will not produce a column operation control effect on the memory block control circuit 3. Therefore, the test mode setting instruction is 10 or 11 corresponding to the noise-free test mode.

[0105] When the first identifier A=1 and the second identifier B=0, that is, when the test mode setting instruction TM is 01, the state of the column control test signal Scmos_Col_Xdec changes with the state of the column control enable signal Scmos_Col. If the column control enable signal Scmos_Col is equal to 1, the column control test signal Scmos_Col_Xdec is also equal to 1; if the column control enable signal Scmos_Col is equal to 0, the column control test signal Scmos_Col_Xdec is also equal to 0. At this time, whether the column operation logic transmitted from the storage body control circuit 1 will produce a column operation control effect on the storage block control circuit 3 is directly controlled by the column control enable signal Scmos_Col, which is equivalent to the column control enable signal Scmos_Col being transparently transmitted to the storage body control circuit 3 through the test mode setting module 2. Therefore, the test mode setting instruction is 01 corresponding to the adaptive test mode.

[0106] In combination with all the above figures, it is assumed that the effective state of the column control enable signal Scmos_Col is 1. When the column control enable signal Scmos_Col is 1, the controller allows the column operation to produce a column operation control effect on the storage block control circuit 3, that is, reading and writing are allowed, and the controller sets the sense amplifier to operate in a read-write mode (including the first read-write mode and the second read-write mode mentioned above); when the column control enable signal Scmos_Col is 0, the column operation cannot produce a column operation control effect on the storage block control circuit 3, that is, reading and writing are not allowed, and the controller sets the sense amplifier to operate in a refresh mode.

[0107] The equalization enable signal NCEQ is used to indicate whether the memory control circuit 1 generates the equalization control signal EQ after the offset elimination phase of the sense amplifier ends. That is, the equalization enable signal NCEQ can adjust the timing of the equalization control signal EQ to form Figure 3A or Figure 3B When the sense amplifier operates in the read / write mode, the equalization enable signal NCEQ can set the sense amplifier to operate in the first read / write mode (with NCEQ operation) or the second read / write mode (without NCEQ operation).

[0108] The test mode setting instruction TM includes a noise-free test instruction, a noise-containing test instruction and an adaptive test instruction, as shown in the above embodiment.

[0109] Figure 6 It is a schematic diagram of the relationship between various signals and circuits in the embodiment of the present disclosure.

[0110] refer to Figure 6 The equalization control signal in the embodiment of the present disclosure includes a first equalization control signal and a second equalization control signal; the pre-charge control signal includes a first pre-charge control signal, a second pre-charge control signal, and a third pre-charge control signal. The relationship between these signals is described below.

[0111] When the equalization enable signal NCEQ indicates that an equalization control signal is generated after the offset elimination phase ends (ie, there is an NCEQ operation), the memory bank control circuit 1 generates a first equalization control signal EQ (eg, Figure 3A As shown in FIG. 1 ), the memory block control circuit 3 is configured to control the local data line LIO and the local complementary data line LIO# to be charged from the bit line equalization voltage VBLP to the power supply voltage VCC after the offset elimination phase of the sense amplifier is completed. Specifically, the memory block control circuit 3 generates a first precharge control signal EQIO (as shown in FIG. Figure 3A shown).

[0112] It should be noted that whether the pre-charge control signal EQIO can be output and function is controlled by the test mode setting instruction TM.

[0113] When the equalization enable signal NCEQ indicates that the equalization control signal is not generated after the offset elimination phase ends (ie, no NCEQ operation), the memory bank control circuit 1 generates the second equalization control signal EQ (eg, Figure 3B As shown in FIG. 1 ), the memory block control circuit 3 is set to control the local data line LIO and the local complementary data line LIO# to be charged from the bit line equalization voltage VBLP to the power supply voltage VCC after the sense amplifier is activated and before the offset elimination phase begins, that is, the memory block control circuit 3 can generate the second pre-charge control signal EQIO (as shown in FIG. 1 ). Figure 3B shown).

[0114] When the test mode setting instruction TM is a noise-free test instruction, the test mode setting module 2 generates a column control test signal Scmos_Col_Xdec (in Figure 5 equal to 0) to set the storage block control circuit 3 to output the third pre-charge control signal EQIO (low level) to control the local data line LIO and the local complementary data line LIO# not to change their potentials, that is, the pre-charge control signal EQIO generated by the storage block control circuit 3 cannot reach the local data line LIO.

[0115] When the test mode setting instruction TM is a noise test instruction, the test mode setting module 2 generates a column control test signal Scmos_Col_Xdec (in Figure 5 equals 1) to set the storage block control circuit 3 to control the local data line LIO and the local complementary data line LIO# to be charged from the bit line equalization voltage VBLP to the power supply voltage VCC according to the equalization control signal EQ, that is, the pre-charge control signal EQIO generated by the storage block control circuit 3 can reach the local data line LIO.

[0116] When the test mode setting instruction TM is an adaptive test instruction, the test mode setting module 2 generates a column control test signal Scmos_Col_Xdec having the same state as the column control enable signal Scmos_Col.

[0117] Based on the improved circuit, the IO noise impact performance test of the sense amplifier in various working modes can be implemented.

[0118] Figure 7 4 is a flow chart of a method for testing performance of a sensing amplifier in an embodiment of the present disclosure. Figure 7 The method shown can be Figure 1 The test circuit 100 in the illustrated embodiment performs.

[0119] refer to Figure 7 During the test, the sense amplifier must correspond to a set of design parameters, which include one or more signal characteristic parameters and one or more circuit characteristic parameters. Under the set of design parameters (referred to as current test parameters), the sense amplifier performance test method 700 includes:

[0120] Step S1, determining a target working mode, where the target working mode includes a first read-write mode and a second read-write mode;

[0121] Step S2, in the target working mode, before the sense amplifier completes the sense amplification action, the potential of the local data line and the local complementary data line is controlled to remain unchanged, and a sense margin test is performed to obtain a first sense margin;

[0122] Step S3, in the target working mode, in the working phase of the sense amplifier, the potential of the local data line and the local complementary data line is controlled to be precharged from the bit line equalization voltage to the power supply voltage, and a sensing margin test is performed to obtain a second sensing margin;

[0123] Step S4, determining a sensing margin impact evaluation value corresponding to a target operating mode of the sensing amplifier under current design parameters according to the second sensing margin and the first sensing margin;

[0124] Step S5, obtaining a plurality of sensing margin impact evaluation values ​​corresponding to a plurality of working modes under the current design parameters, and evaluating or optimizing the current design parameters according to the plurality of sensing margin impact evaluation values.

[0125] Figure 7 In the illustrated embodiment, by performing a noise-free test (step S2) and a noise test (step S3) on each operating mode, a first sensing margin not affected by noise and a second sensing margin affected by noise are obtained, and the degree of influence of noise on the sensing margin in each operating mode can be calculated to obtain the degree of influence of noise corresponding to the current design parameters, that is, the anti-noise performance of the sense amplifier under the current design parameters is measured. Furthermore, the design parameters of the sense amplifier can be optimized by comparing the anti-noise performance of the sense amplifier under multiple sets of design parameters.

[0126] When the target operating mode is the first read-write mode or the second read-write mode, the process of performing the sensing margin test is the same.

[0127] Figure 8 is a flow chart of a sensing margin test in one embodiment of the present disclosure.

[0128] refer to Figure 8 , in both noisy and noiseless tests in read and write mode, the induction margin test includes:

[0129] Step S81, writing test data into the target memory cell connected to the sense amplifier according to the test charge;

[0130] Step S82, controlling the sense amplifier to perform sense amplification and then read the target bit line to obtain a data reading result, wherein the target bit line connects the sense amplifier and the target storage unit;

[0131] Step S83, when the data reading result corresponds to the correct reading result of the test data, the value of the test charge is reduced, the test data is rewritten, and the process proceeds to step S82;

[0132] Step S84, when the data reading result does not correspond to the correct reading result of the test data, determining the sensing margin value of the sense amplifier in the current test environment according to the test charge, the current test environment including the target working mode and the level change of the local data line connected to the sense amplifier in the working stage of the sense amplifier.

[0133] exist Figure 8 In the illustrated embodiment, no matter what kind of noise environment (referred to as test condition) is used for testing, the sense margin (SM) under the current test condition is tested by writing and reading.

[0134] The sensing margin refers to how much the charge change of the target bit line (i.e., the potential difference between the target bit line and the corresponding complementary bit line) can be detected by the sense amplifier when charge sharing is performed between the target bit line and the target memory cell during the charge sharing phase of the sense amplifier, so that the sense amplifier can perform normal sensing amplification on the potential difference (the voltage difference has been transmitted to the internal nodes of the sense amplifier, i.e., the first node N1 and the second node N2).

[0135] This is related to the inductive amplification principle of the sense amplifier. When a voltage difference occurs between the bit line BLA and the complementary bit line BLB, the voltage difference reaches the first node N1 and the second node N2 through the turned-on first switch tube MC1 and the second switch tube MC2, so that a voltage difference occurs between the first node N1 and the second node N2, and the gate voltages of the first P-type transistor MP1 and the second P-type transistor MP2 in the sense amplifier are different, and the gate voltages of the first N-type transistor MN1 and the second N-type transistor MN2 are different.

[0136] When the voltage of the first node N1 is greater than the voltage of the second node N2, the conduction degree of the first P-type transistor MP1 is greater than the conduction degree of the second P-type transistor MP2, the conduction degree of the second N-type transistor MN2 is greater than the conduction degree of the first N-type transistor MN1, and the voltage rise rate of the first node N1 is greater than the voltage rise rate of the second node N2, which in turn causes the second P-type transistor MP2 to be turned off, the second N-type transistor MN2 to be turned on, and the potential of the second node N2 is equal to NCS (i.e., 0 potential). Correspondingly, the first P-type transistor MP1 is fully turned on, the first N-type transistor MN1 is fully turned off, and the potential of the first node N1 is equal to PCS (i.e., power supply voltage VCC). This process is the induction amplification process of the voltage difference between the bit line BLA and the complementary bit line BLB, and the voltage difference between the bit line BLA and the complementary bit line BLB is amplified to VCC.

[0137] In the charge sharing process, noise and the initial voltage state of the target bit line can affect the charge change of the target bit line, and then affect the voltage difference between the bit line BLA and the complementary bit line BLB. According to the above analysis, if the voltage difference between the bit line BLA and the complementary bit line BLB is not large enough, and the transistor conduction speed is not much different, the induction amplification failure will occur in the subsequent working stage, resulting in data reading failure.

[0138] After the charge sharing process is completed, the minimum voltage difference between the bit line and the complementary bit line corresponding to the normal sensing amplification of the sense amplifier is the sensing margin of the sense amplifier under the current conditions. The smaller the sensing margin, the smaller the voltage difference that the sense amplifier can detect, and the better the performance of the sense amplifier. The larger the sensing margin, the higher the requirement of the sense amplifier for the voltage difference, and the worse the performance of the sense amplifier.

[0139] exist Figure 8 In the illustrated embodiment, by adjusting the amount of charge stored in the storage capacitor C in step S81 or step S83, and performing a sensing amplification operation in step S82, and reading the target bit line after the sensing amplification operation, it is possible to test to what extent the amount of charge is too small for the sensing amplifier to detect the amount of charge (the voltage difference between the bit line and the complementary bit line), and determine the minimum amount of charge that the sensing amplifier can detect (approximately equal to the amount of the test charge) as the sensing margin of the sensing amplifier under the current conditions.

[0140] It should be emphasized that the amount of test charge for the storage capacitor in step S81 and step S83 is not written into the storage capacitor by conventional write instructions, but is controlled by conventional test control means.

[0141] In step S83, the correct reading result of the test data means that if the test data is 0, the correct reading result is the level of the target bit line after normal sensing and amplification, that is, 0V; if the test data is 1, the correct reading result is the level of the target bit line after normal sensing and amplification, that is, the power supply voltage VCC. When the test data is 0, the amount of test charge can be gradually increased to test the sensing margin. When the test data is 1, the same data 1 can also be represented by different charge amounts. Therefore, the value of the test charge can be adjusted in step S81 and step S83, and the written test data can still be guaranteed to be the same.

[0142] By adjusting the test parameters or the design parameters of the sense amplifier, the sense margin of the sense amplifier under each condition can be tested accordingly, and the sense margin can be used as a reference value for evaluating the performance of the sense amplifier.

[0143] Next, various embodiments of implementing the test method 700 using the test circuit 100 are introduced.

[0144] Fig. 9A and Fig. 9B This is a control timing comparison diagram of a noisy test and a noise-free test in a first read-write mode in an embodiment of the present disclosure.

[0145] refer to Fig. 9A , in the first read-write mode, the column control enable signal Scmos_Col is equal to 1, the equalization enable signal NCEQ indicates that the equalization control signal EQ is generated after the offset elimination stage, the sense amplifier operates in the read-write mode, and the storage body control circuit 1 outputs the first equalization control signal EQ, then the noisy test is performed in step S3, including: inputting an adaptive test instruction or a noisy test instruction to the test mode setting module 2, so that the test mode setting module 2 generates a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=1) that allows the column operation state, so that the storage block control circuit 3 generates and outputs the first pre-charge control signal EQIO, and controls the local data line LIO to be pre-charged from the bit line equalization voltage VBLP to the power supply voltage VCC after the offset elimination stage (the equalization control signal EQ ends).

[0146] At this time, the column control test signal Scmos_Col_Xdec and the column control enable signal Scmos_Col are in the same state, and both are converted from low level to high level when the idle phase ends (i.e., when the activation signal Active is received), allowing the storage block control circuit 3 to output a column operation signal, controlling the voltage of the local data line LIO to change, so that the voltage of the local data line LIO changes to the noise generated by the power supply voltage VCC, affecting the charge sharing phase and the induction amplification phase. Under this test condition, the following is performed: Figure 8 The sensing margin detection shown in the figure can obtain the sensing margin (second sensing margin) of the sensing amplifier when the IO noise affects the charge sharing stage and the sensing amplification stage in the first read-write mode. Fig. 9A As shown, after the sense amplification operation is completed, a valid pulse appears in the column selection signal CSL, and the bit line BLA is read.

[0147] It should be noted that the storage block control circuit 3 generates the pre-charge control signal EQIO based on the equalization control signal EQ output by the storage body control circuit 1, but determines whether to output or when to output the pre-charge control signal EQIO based on the column control test signal Scmos_Col_Xdec output by the test mode setting module 2. Therefore, in the timing diagram, the pre-charge control signal EQIO is divided into the pre-charge control signal EQIO generated by the storage block control circuit 3 and the pre-charge control signal EQIO output by the storage block control circuit 3. Fig. 9A , Fig. 10A , Fig.11A , Fig. 11CIn the noise test, the storage block control circuit 3 is allowed to output the pre-charge control signal EQIO generated by it, and the two pre-charge control signals EQIO overlap; Fig. 9B , Fig. 10B , Fig. 11B , Fig.11D In the process, the output of the pre-charge control signal EQIO will be controlled. At this time, the two pre-charge control signals EQIO are represented by solid lines and dotted lines in the timing diagram.

[0148] refer to Fig. 9B In the first read-write mode, step S2 performs a noiseless test including: responding to an activation instruction (Active) to the sense amplifier, inputting a noiseless test instruction to the test mode setting module 2, so that the test mode setting module 2 outputs a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=0) that prohibits the column operation state, so that the storage block control circuit 3 outputs a third pre-charge control signal EQIO (EQIO=0) (in fact, the storage block control circuit 3 generates the first pre-charge control signal EQIO, but cannot output it), and after the sense amplifier completes the sense amplification, Before the first time point T1 of the operation, the potential of the local data line LIO and the local complementary data line LIO# are controlled to remain unchanged; at the first time point T1 when the sense amplifier completes the sense amplification action, an adaptive noise instruction is input to the test mode setting module 2, so that the test mode setting module 2 outputs a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=1) that allows the column operation state, so that the storage block control circuit 3 controls the local data line LIO and the local complementary data line LIO# to be precharged from the bit line equalization voltage VBLP to the power supply voltage VCC after the first time point T1.

[0149] When performing a noise-free test, before the sensing amplification action is completed, the column control test signal Scmos_Col_Xdec is not affected by the column control enable signal Scmos_Col, and is always 0, controlling the potential of the local data line LIO to remain unchanged. After the sensing amplification action is completed, the column control test signal Scmos_Col_Xdec is converted from a low level to a high level, allowing the storage block control circuit 3 to respond to the column operation signal to control the level of the local data line LIO to change to the power supply voltage VCC, preparing for subsequent data reading and sensing margin testing. In the above process, the noise after the local data line LIO voltage changes to the power supply voltage VCC does not affect the sensing amplification process of the sense amplifier.

[0150] Under this test condition, Figure 8The sensing margin detection shown can obtain the sensing margin (first sensing margin) of the sensing amplifier in the first read / write mode when the IO noise does not affect the sensing amplification process. The first sensing margin is obviously smaller than the second sensing margin.

[0151] Next, in step S4 , the difference between the second sensing margin and the first sensing margin in the first read / write mode can be determined as an evaluation value of the sensing margin affected by noise in the first read / write mode, ie, a sensing margin impact evaluation value corresponding to the first read / write mode.

[0152] Fig. 10A and Fig. 10B This is a control timing comparison diagram of a noisy test and a noise-free test in a second read-write mode in an embodiment of the present disclosure.

[0153] refer to Fig. 10A , in the second read-write mode, the column control enable signal Scmos_Col is equal to 1, the equalization enable signal NCEQ indicates that the equalization control signal EQ is generated after the non-offset elimination stage, the sense amplifier operates in the read-write mode, and the storage body control circuit 1 outputs the second equalization control signal EQ, then the noisy test is performed in step S3, including: inputting an adaptive test instruction or a noisy test instruction to the test mode setting module 2, so that the test mode setting module 2 generates a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=1) that allows the column operation state, so that the storage block control circuit 3 generates and outputs the second pre-charge control signal EQIO, and controls the local data line LIO to be pre-charged from the bit line equalization voltage VBLP to the power supply voltage VCC after the idle stage ends and before the offset elimination stage.

[0154] At this time, the column control test signal Scmos_Col_Xdec and the column control enable signal Scmos_Col are in the same state, and both are converted from low level to high level when the idle phase ends (i.e., when the activation signal Active is received), allowing the storage block control circuit 3 to output a column operation signal, controlling the voltage change of the local data line LIO, so that the voltage of the local data line LIO changes to the noise generated by the power supply voltage VCC, affecting the offset elimination phase, the charge sharing phase and the induction amplification phase. Under this test condition, the following is performed: Figure 8 The sensing margin detection shown in FIG. 1 can obtain the sensing margin (second sensing margin) of the sensing amplifier when the IO noise affects the offset elimination stage, the charge sharing stage and the sensing amplification stage in the second read / write mode. Fig. 10A As shown, after the sense amplification operation is completed, a valid pulse appears in the column selection signal CSL, and the bit line BLA is read.

[0155] refer to Fig. 10BIn the second read-write mode, step S2 performs a noiseless test including: responding to an activation instruction (Active) to the sense amplifier, inputting a noiseless test instruction to the test mode setting module 2, so that the test mode setting module 2 outputs a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=0) that prohibits the column operation state, so that the storage block control circuit 3 outputs a third pre-charge control signal EQIO (EQIO=0) (in fact, the storage block control circuit 3 generates the second pre-charge control signal EQIO, but it cannot be output), and after the sense amplifier completes the sense amplification, Before the first time point T1 of the operation, the potential of the local data line LIO and the local complementary data line LIO# are controlled to remain unchanged; at the first time point T1 when the sense amplifier completes the sense amplification action, an adaptive noise instruction is input to the test mode setting module 2, so that the test mode setting module 2 outputs a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=1) that allows the column operation state, so that the storage block control circuit 3 controls the local data line LIO and the local complementary data line LIO# to be precharged from the bit line equalization voltage VBLP to the power supply voltage VCC after the first time point T1.

[0156] When performing a noise-free test, before the sensing amplification action is completed, the column control test signal Scmos_Col_Xdec is not affected by the column control enable signal Scmos_Col, and is always 0, controlling the potential of the local data line LIO to remain unchanged. After the sensing amplification action is completed, the column control test signal Scmos_Col_Xdec is converted from a low level to a high level, allowing the storage block control circuit 3 to respond to the column operation signal to control the level of the local data line LIO to change to the power supply voltage VCC, preparing for subsequent data reading and sensing margin testing. In the above process, the noise after the local data line LIO voltage changes to the power supply voltage VCC does not affect the sensing amplification process of the sense amplifier.

[0157] Under this test condition, Figure 8 The sensing margin detection shown can obtain the sensing margin (first sensing margin) of the sensing amplifier in the second read / write mode when the IO noise does not affect the sensing amplification process. The first sensing margin is obviously smaller than the second sensing margin.

[0158] Next, in step S4 , the difference between the second sensing margin and the first sensing margin in the second read / write mode can be determined as an evaluation value of the sensing margin affected by noise in the second read / write mode, ie, a sensing margin impact evaluation value corresponding to the second read / write mode.

[0159] In addition to testing the conventional read and write working modes, the refresh mode can also be tested for further research. Although no column operation is performed in the refresh mode and the column control enable signal Scmos_Col is equal to 0, the column control test signal Scmos_Col_Xdec can be forcibly set to 1 through the test mode setting module 2 and the test mode setting instruction TM, allowing the column operation signal to reach the storage block control circuit 3, so that the sense amplifier in the refresh mode is affected by the column operation.

[0160] Corresponding to the read-write mode, when the refresh mode is affected by the column operation, the impact with and without NCEQ operation can also be tested. In the embodiment of the present disclosure, the refresh mode with NCEQ operation is called the first refresh mode, and the refresh mode without NCEQ operation is called the second refresh mode.

[0161] Fig.11A and Fig. 11B 3 is a control timing comparison diagram of a noisy test and a noise-free test in the first refresh mode in an embodiment of the present disclosure.

[0162] When the sense amplifier operates in refresh mode, the column control enable signal Scmos_Col is equal to 0, but controlled by the test mode setting module 2 and the test mode setting instruction TM, the column control test signal Scmos_Col_Xdec will have different states to shield or pass the column operation signal.

[0163] refer to Fig.11A , in the first refresh mode, the column control enable signal Scmos_Col is equal to 0, the equalization enable signal NCEQ indicates that the offset elimination phase of the sense amplifier is ended and then the equalization control signal EQ is generated, the sense amplifier operates in the refresh mode, the storage body control circuit 1 generates the first equalization control signal EQ, and the step S3 performs a noisy test including: inputting a noisy test instruction to the test mode setting module 2, so that the test mode setting module 2 generates a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=1) that allows the column operation state, so that the storage block control circuit 3 generates and outputs the first pre-charge control signal EQIO, and controls the local data line LIO to be pre-charged from the bit line equalization voltage VBLP to the power supply voltage VCC after the offset elimination phase (the equalization control signal EQ ends).

[0164] At this time, the column control test signal Scmos_Col_Xdec is not affected by the column control enable signal Scmos_Col. When the idle phase ends (i.e., the activation signal Active is received), it is converted from a low level to a high level, allowing the storage block control circuit 3 to output a column operation signal, controlling the voltage change of the local data line LIO, causing the voltage of the local data line LIO to change to the noise generated by the power supply voltage VCC, affecting the charge sharing phase and the induction amplification phase.

[0165] After completing a refresh under this test condition, the sense amplifier stores the data of the bit line BLA back to the storage capacitor C. At this time, it enters the next activation cycle and performs normal data reading. The data stored in the storage capacitor C can be read. Since this reading does not control the storage charge, the reading state is not affected by the boundary value of the sensing margin, and the reading result must be equal to the data stored in the storage capacitor C.

[0166] If the read result is equal to the data that should be stored in the storage capacitor C (for example, 1), the test charge is reduced and multiple tests are performed until the read data is not equal to the data that should be stored in the storage capacitor C, indicating that the storage charge used in this test exceeds the sensing boundary under the current situation. The value of the storage charge used in the last test can be used as the sensing boundary under the current test environment, that is, the sensing margin (second sensing margin) of the sense amplifier when the IO noise affects the charge sharing stage and the sensing amplification stage in the first refresh mode.

[0167] refer to Fig. 11B The normal refresh working mode is a noise-free test. Therefore, the sensing margin test can be performed in the normal refresh working mode to obtain the first sensing margin of the noise-free test.

[0168] In the first refresh mode, step S2 performs a noiseless test including: inputting an adaptive test instruction or a noiseless instruction to the test mode setting module 2, so that the test mode setting module 2 outputs a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=0) that prohibits the column operation state, so that the storage block control circuit 3 outputs a third pre-charge control signal EQIO (EQIO=0) (in fact, the storage block control circuit 3 generates the first pre-charge control signal EQIO, but cannot output it), and controls the potential of the local signal line LIO to remain unchanged during the working phase of the sense amplifier. At this time, the column control test signal Scmos_Col_Xdec and the column control enable signal Scmos_Col are in the same state, and both are always maintained at a low level.

[0169] After completing a refresh under this test condition, the sense amplifier stores the data of the bit line BLA back to the storage capacitor C. At this time, it enters the next activation cycle and performs normal data reading. The data stored in the storage capacitor C can be read. Since this reading does not control the storage charge, the reading state is not affected by the boundary value of the sensing margin, and the reading result must be equal to the data stored in the storage capacitor C.

[0170] If the read result is equal to the data that should be stored in the storage capacitor C (for example, 1), the test charge is reduced and multiple tests are performed until the read data is not equal to the data that should be stored in the storage capacitor C, indicating that the storage charge used in this test exceeds the sensing boundary under the current situation. The value of the storage charge used in the previous test can be used as the sensing boundary under the current test environment, that is, the sensing margin (first sensing margin) of the sense amplifier when the IO noise does not affect the operation of the sense amplifier in the first refresh mode.

[0171] Next, the process proceeds to step S4 , where the difference between the second sensing margin and the first sensing margin in the first refresh mode is determined as an evaluation value of the sensing margin being affected by noise in the first refresh mode, ie, a sensing margin impact evaluation value corresponding to the first refresh mode.

[0172] Fig. 11C and Fig.11D 3 is a control timing comparison diagram of a noisy test and a noise-free test in the first refresh mode in an embodiment of the present disclosure.

[0173] refer to Fig. 11C , the target operation mode further includes a second refresh mode, the column control enable signal Scmos_Col is equal to 0, the equalization enable signal NCEQ indicates that the equalization control signal EQ is generated after the non-offset elimination phase, the sense amplifier operates in the read-write mode, and the memory control circuit 1 outputs the second equalization control signal EQ, then the noisy test in step S3 includes:

[0174] A noisy test instruction is input to the test mode setting module 2, and the test mode setting module 2 generates a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=1) that allows the column operation state, so that the storage block control circuit 3 generates and outputs the second pre-charge control signal EQIO, which controls the local data line LIO to be pre-charged from the bit line equalization voltage VBLP to the power supply voltage VCC after the idle phase ends and before the offset elimination phase.

[0175] At this time, the column control test signal Scmos_Col_Xdec is not affected by the column control enable signal Scmos_Col. When the idle phase ends (i.e., the activation signal Active is received), it is converted from a low level to a high level, allowing the storage block control circuit 3 to output a column operation signal, controlling the voltage change of the local data line LIO, so that the voltage of the local data line LIO changes to the noise generated by the power supply voltage VCC, affecting the offset elimination phase, the charge sharing phase and the inductive amplification phase.

[0176] After completing a refresh under this test condition, the sense amplifier stores the data of the bit line BLA back to the storage capacitor C. At this time, it enters the next activation cycle and performs normal data reading. The data stored in the storage capacitor C can be read. Since this reading does not control the storage charge, the reading state is not affected by the boundary value of the sensing margin, and the reading result must be equal to the data stored in the storage capacitor C.

[0177] If the read result is equal to the data that should be stored in the storage capacitor C (for example, 1), the test charge is reduced and multiple tests are performed until the read data is not equal to the data that should be stored in the storage capacitor C, indicating that the storage charge used in this test exceeds the sensing boundary under the current situation. The value of the storage charge used in the last test can be used as the sensing boundary under the current test environment, that is, the sensing margin (second sensing margin) of the sense amplifier when the IO noise affects the offset elimination stage, charge sharing stage and sensing amplification stage of the sense amplifier in the second refresh mode.

[0178] refer to Fig.11D The normal refresh working mode is a noise-free test. Therefore, the sensing margin test can be performed in the normal refresh working mode to obtain the first sensing margin of the noise-free test.

[0179] In the second refresh mode, step S2 performs a noiseless test including: inputting an adaptive test instruction or a noiseless instruction to the test mode setting module 2, so that the test mode setting module 2 outputs a column control test signal Scmos_Col_Xdec (Scmos_Col_Xdec=0) that prohibits the column operation state, so that the storage block control circuit 3 outputs a third pre-charge control signal EQIO (EQIO=0) (in fact, the storage block control circuit 3 generates the second pre-charge control signal EQIO, but cannot output it), and controls the potential of the local signal line LIO to remain unchanged during the working phase of the sense amplifier. At this time, the column control test signal Scmos_Col_Xdec and the column control enable signal Scmos_Col are in the same state, and both are always maintained at a low level.

[0180] After completing a refresh under this test condition, the sense amplifier stores the data of the bit line BLA back to the storage capacitor C. At this time, it enters the next activation cycle and performs normal data reading. The data stored in the storage capacitor C can be read. Since this reading does not control the storage charge, the reading state is not affected by the boundary value of the sensing margin, and the reading result must be equal to the data stored in the storage capacitor C.

[0181] If the read result is equal to the data that should be stored in the storage capacitor C (for example, 1), the test charge is reduced and multiple tests are performed until the read data is not equal to the data that should be stored in the storage capacitor C, indicating that the storage charge used in this test exceeds the sensing boundary under the current situation. The value of the storage charge used in the previous test can be used as the sensing boundary under the current test environment, that is, the sensing margin (first sensing margin) of the sense amplifier when the IO noise does not affect the operation of the sense amplifier in the second refresh mode.

[0182] Next, the process proceeds to step S4 , where the difference between the second sensing margin and the first sensing margin in the second refresh mode is determined as an evaluation value of the sensing margin being affected by noise in the first refresh mode, ie, a sensing margin impact evaluation value corresponding to the first refresh mode.

[0183] After obtaining the induction margin impact evaluation values ​​of the above four working modes, the current design parameters can be evaluated or optimized according to the multiple induction margin impact evaluation values.

[0184] In one embodiment, step S5 may include: obtaining a plurality of sensing margin impact evaluation values ​​corresponding to each set of design parameters in a plurality of sets of design parameters, and determining design parameters of the sensing amplifier according to the plurality of sensing margin impact evaluation values ​​corresponding to the plurality of sets of design parameters.

[0185] For example, among the multiple sensing margin impact evaluation values ​​corresponding to the multiple sets of design parameters, a set of design parameters with the smallest average value of the sensing margin impact evaluation values ​​(i.e., the sensing margin is least affected by IO noise in various working modes) can be selected as a set of optimal design parameters for the sense amplifier. Alternatively, when any sensing margin impact evaluation value is less than a preset threshold value of its corresponding working mode, a set of design parameters corresponding to the sensing margin impact evaluation value is listed as candidate design parameters, and finally multiple sets of candidate design parameters are determined, and the design parameters are optimized based on the extraction of common features of the multiple sets of candidate design parameters.

[0186] There may be multiple methods for optimizing the design parameters of the sensing amplifier according to multiple sensing margin impact evaluation values ​​corresponding to multiple sets of design parameters, and there may also be multiple ways of using the above test results, which are not particularly limited in the present disclosure.

[0187] It should be noted that, although several modules or units for performing functions are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0188] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A test circuit, characterized in that: include: A memory control circuit, used for receiving a control instruction, and generating and outputting a balance control signal according to the control instruction; wherein the control instruction includes a column control enable signal and a balance enable signal; A test mode setting module, used for receiving a test mode setting instruction and the column control enable signal, and generating and outputting a column control test signal according to the test mode setting instruction and the column control enable signal; a storage block control circuit, which is in communication connection with the storage body control circuit and the test mode setting module, and is used to generate a precharge control signal according to the column control test signal and the equalization control signal, and in the working stage of the sense amplifier, control whether the potential of the local data line or the local complementary data line is precharged from the bit line equalization voltage to the power supply voltage according to the precharge control signal, and control the start time of precharging the potential of the local data line or the local complementary data line from the bit line equalization voltage to the power supply voltage, so as to test the influence of noise generated when the local data line or the local complementary data line is precharged to the power supply voltage on the sense amplifier; Wherein, the local data line and the local complementary data line are connected to corresponding sense amplifiers.

2. The test circuit according to claim 1, characterized in that: The column control enable signal indicates that the sense amplifier operates in a read / write mode or a refresh mode; the first state of the equalization enable signal indicates that the memory control circuit generates an equalization control signal after the offset elimination phase of the sense amplifier ends, and the second state of the equalization enable signal indicates that the memory control circuit does not generate an equalization control signal after the offset elimination phase of the sense amplifier ends; the test mode setting instruction includes a noise-free test instruction, a noise-containing test instruction, and an adaptive test instruction; the equalization control signal includes a first equalization control signal and a second equalization control signal, and the precharge control signal includes a first precharge control signal, a second precharge control signal, and a third precharge control signal; The memory bank control circuit generates a first equalization control signal when the equalization enable signal is in a first state; The memory block control circuit generates a first precharge control signal according to the first equalization control signal, so as to control the potential of the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage after the offset elimination phase of the sense amplifier ends; The memory bank control circuit generates a second equalization control signal when the equalization enable signal is in a second state; The memory block control circuit generates a second precharge control signal according to the second equalization control signal, so as to control the potential of the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage after the sense amplifier is activated and before the offset elimination phase begins; The test mode setting module generates the column control test signal for disabling the column operation state when the test mode setting instruction is a noise-free test instruction, so as to set the storage block control circuit to output a third precharge control signal, and control the potential of the local data line and the local complementary data line to remain unchanged; The test mode setting module generates the column control test signal that allows the column operation state when the test mode setting instruction is a noisy test instruction, so as to set the storage block control circuit to generate and output the first pre-charge control signal or the second pre-charge control signal according to the equalization control signal; The test mode setting module generates the column control test signal having the same state as the column control enable signal when the test mode setting instruction is an adaptive test instruction.

3. The test circuit according to claim 1 or 2, characterized in that: The test mode setting instruction is represented by a first identifier and a second identifier, and the test mode setting module includes: A first inverter, an input terminal of which receives the column control enable signal; An AND gate, a first input terminal for receiving the first identifier, and a second input terminal connected to an output terminal of the first inverter; A NOR gate, having a first input terminal for receiving the second identifier, a second input terminal connected to the output terminal of the AND gate, and an output terminal for outputting the column control test signal.

4. The test circuit according to claim 1, characterized in that: The memory bank control circuit is connected to a plurality of the memory block control circuits; The memory body control circuit is also used to receive a row enable control signal and a row address signal, generate a row control signal according to the row enable control signal, and send the row control signal to the corresponding memory block control circuit according to the row address signal; The storage block control circuit is used to receive the row control signal and the row address signal, and control the corresponding row control circuit to perform a row operation according to the row control signal and the row address signal.

5. The test circuit according to claim 1, characterized in that: The storage block control circuit includes a column operation control circuit, and the column operation control circuit determines the state of the output precharge control signal according to the column control test signal, and the column operation control circuit includes: A first enable signal inverter, wherein an input terminal of the first enable signal inverter receives the column control test signal, and an output terminal of the first enable signal inverter outputs a first enable signal; A second enable signal inverter, wherein an input end of the second enable signal inverter is connected to an output end of the first enable signal inverter, and is used to invert the first enable signal to output a second enable signal; A column operation signal control path has an input end, an output end, a first control end, and a second control end. The input end of the column operation signal control path receives the pre-charge control signal, and the output end of the column operation control path is used to output the pre-charge control signal. The first control end and the second control end of the column operation control path respectively receive the first enable signal and the second enable signal. When the first enable signal and the second enable signal are both in a valid state, the column operation control path outputs the first pre-charge control signal or the second pre-charge control signal. When the first enable signal and the second enable signal are both in an invalid state, the column operation control path outputs a third pre-charge control signal.

6. The test circuit according to claim 5, characterized in that: The column operation signal control path includes: The pull-up transistor is a P-type transistor, the gate of which serves as the first control terminal of the column operation control path to receive the first enable signal, and the source of which is connected to the power supply voltage; The pull-down transistor is an N-type transistor, the gate of which serves as the second control terminal of the column operation control path to receive the second enable signal, and the source of which is grounded; A first P-type inverter, a first N-type inverter, a second P-type inverter, and a second N-type inverter are connected in series, the power supply ends of the first P-type inverter and the second P-type inverter are connected to the drain of the pull-up transistor, the ground ends of the first N-type inverter and the second N-type inverter are connected to the drain of the pull-down transistor, the input end of the first P-type inverter is the input end of the column operation control path, and the output end of the second N-type inverter is the output end of the column operation control path.

7. A method for testing the performance of a sensing amplifier, characterized in that: The test circuit according to any one of claims 1 to 6 is implemented, wherein the sense amplifier in the sense amplifier test circuit corresponds to a set of design parameters, wherein the design parameters include one or more signal characteristic parameters and one or more circuit characteristic parameters, and are characterized in that: Determining a target operating mode, wherein the target operating mode includes a first read-write mode and a second read-write mode; In the target working mode, before the sense amplifier completes the sense amplification action, the potentials of the local data line and the local complementary data line are controlled to remain unchanged, and a sense margin test is performed to obtain a first sense margin; In the target working mode, in the working phase of the sense amplifier, the potentials of the local data line and the local complementary data line are controlled to be precharged from the bit line equalization voltage to the power supply voltage, and a sensing margin test is performed to obtain a second sensing margin; determining, according to the second sensing margin and the first sensing margin, a sensing margin impact evaluation value corresponding to the target operating mode of the sensing amplifier under current design parameters; Acquire a plurality of the sensing margin impact evaluation values ​​corresponding to a plurality of working modes under the current design parameters, and evaluate or optimize the current design parameters according to the plurality of sensing margin impact evaluation values.

8. The method according to claim 7, characterized in that The induction margin test comprises: Writing test data into the target memory cell connected to the sense amplifier according to the test charge; Controlling the sense amplifier to perform sense amplification and then read a target bit line to obtain a data reading result, wherein the target bit line connects the sense amplifier and the target storage unit; When the data reading result corresponds to the correct reading result of the test data, reducing the value of the test charge, rewriting the test data, and looping the previous step; When the data reading result does not correspond to a correct reading result of the test data, a sensing margin value of the sensing amplifier in a current test environment is determined according to the test charge, wherein the current test environment includes the target operating mode and a level change of a local data line connected to the sensing amplifier during a working phase of the sensing amplifier.

9. The method according to claim 7, characterized in that In the first read / write mode, the sense amplifier operates in the read / write mode, and the memory control circuit generates a first equalization control signal, and in the working phase of the sense amplifier, the potential of the local data line and the local complementary data line is controlled to be precharged from the bit line equalization voltage to the power supply voltage, including: An adaptive test instruction or a noisy test instruction is input to the test mode setting module, so that the test mode setting module generates the column control test signal that allows the column operation state, so that the storage block control circuit outputs a first pre-charge control signal, and controls the local data line and the local complementary data line to be pre-charged from the bit line equalization voltage to the power supply voltage after the offset elimination phase ends.

10. The method according to claim 7, characterized in that In the second read-write mode, the sense amplifier operates in the read-write mode, and the memory control circuit generates a second equalization control signal, and in the working phase of the sense amplifier, the potential of the local data line and the local complementary data line is controlled to be precharged from the bit line equalization voltage to the power supply voltage, including: An adaptive test instruction or a noisy test instruction is input to the test mode setting module, so that the test mode setting module outputs the column control test signal that allows the column operation state, so that the storage block control circuit outputs a second pre-charge control signal, and controls the potential of the local data line and the local complementary data line to change from the bit line equalization voltage to the power supply voltage after the sense amplifier is activated and before the offset elimination phase begins.

11. The method according to claim 9 or 10, characterized in that In the first read-write mode or the second read-write mode, controlling the potential of the local data line and the local complementary data line to remain unchanged during the working phase of the sense amplifier includes: In response to the activation instruction of the sense amplifier, inputting a noiseless test instruction to the test mode setting module, so that the test mode setting module outputs the column control test signal for prohibiting the column operation state, so that the storage block control circuit outputs a third precharge control signal, and controls the potential of the local data line and the local complementary data line to remain unchanged before the first time point when the sense amplifier completes the sense amplification action; At a first time point when the sense amplifier completes the sense amplification action, an adaptive noise instruction is input to the test mode setting module, so that the test mode setting module outputs the column control test signal that allows the column operation state, so that the storage block control circuit controls the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage after the first time point.

12. The method according to claim 7, characterized in that The target operation mode further includes a first refresh mode. In the first refresh mode, the memory bank control circuit generates and outputs a first equalization control signal. Controlling the potential of the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage during the operation phase of the sense amplifier includes: A noisy test instruction is input to the test mode setting module, so that the test mode setting module outputs the column control test signal that allows the column operation state, so that the storage block control circuit outputs a first pre-charge control signal, and after the equalization control signal ends, the local data line and the local complementary data line are controlled to be pre-charged from the bit line equalization voltage to the power supply voltage.

13. The method according to claim 7, characterized in that The target operation mode further includes a second refresh mode, in which the sense amplifier operates in a refresh mode, and the memory bank control circuit generates a second equalization control signal, and in the operation phase of the sense amplifier, controlling the potential of the local data line and the local complementary data line to be precharged from the bit line equalization voltage to the power supply voltage includes: A noisy test instruction is input to the test mode setting module, so that the test mode setting module outputs the column control test signal that allows the column operation state, so that the storage block control circuit generates a second pre-charge control signal, and controls the potential of the local data line and the local complementary data line to change from the bit line equalization voltage to the power supply voltage after the sense amplifier is activated and before the offset elimination phase begins.

14. The method according to claim 12 or 13, characterized in that In the first refresh mode or the second refresh mode, controlling the potentials of the local data line and the local complementary data line to remain unchanged during the working phase of the sense amplifier includes: A noise-free test instruction or an adaptive test instruction is input to the test mode setting module, so that the test mode setting module outputs the column control test signal that prohibits the column operation state, so that the storage block control circuit outputs a third pre-charge control signal, and controls the potential of the local data line and the local complementary data line to remain unchanged during the working phase of the sense amplifier.

15. The method according to claim 7, characterized in that Determining, according to the second sensing margin and the first sensing margin, a sensing margin impact evaluation value corresponding to the target operating mode under current design parameters of the sensing amplifier includes: A difference between the second sensing margin and the first sensing margin is determined as a sensing margin impact evaluation value corresponding to the target operating mode.

16. The method according to claim 7, characterized in that The evaluating or optimizing the current design parameters according to the multiple induction margin impact evaluation values ​​includes: Obtaining a plurality of the induction margin impact assessment values ​​corresponding to each group of the design parameters in a plurality of groups of design parameters; The design parameters of the sense amplifier are determined according to the multiple sensing margin impact evaluation values ​​corresponding to the multiple groups of design parameters.

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