System and method suitable for broadband radar receiver to realize pulse acquisition

Abstract

The invention relates to a system suitable for a broadband radar receiver to achieve pulse acquisition, and the system comprises a register read-write module, a pulse detection module, a pulse acquisition module, a DDR4 data storage and positioning module and an upper computer, the output end of the register read-write module is connected with the pulse detection module and the pulse acquisition module; the output end of the pulse detection module is connected with the pulse acquisition module, the output end of the pulse acquisition module is connected with the DDR4 data storage and positioning module, and the DDR4 data storage and positioning module is connected with the upper computer. By adopting the system and the method suitable for the broadband radar receiver to realize pulse acquisition, the integrity of radar pulse signals is ensured, and subsequent signal processing and analysis are facilitated. And a plurality of flexible and settable pulse acquisition parameters ensure the reliability and integrity of the acquired pulse signals. Modularization of the functional unit is realized, the system can be flexibly transplanted to a scene requiring long-time pulse acquisition, and the modular design requirement of the system is met.

Description

Technical Field

[0001] The present invention relates to the field of radar pulse signals, in particular to the field of broadband radar signal acquisition and analysis, and specifically refers to a system and method suitable for broadband radar receivers to realize pulse acquisition. Background Art

[0002] Pulse signals are a common and useful signal in wireless communications. They are widely used in applications such as radar and laser ranging. Therefore, it is of practical significance to study the effective information acquisition and storage of pulse signals.

[0003] Radar pulse signals are composed of two main parameters: pulse period and pulse width. Figure 1 As shown in the radar pulse signal acquisition and storage time axis diagram, Tduration is the pulse acquisition window duration, and it must be greater than the actual signal pulse width; Tperiod is the pulse period, which is a parameter of the actual signal, and Tpulse is the pulse acquisition process duration. The green window in the time axis diagram is the effective pulse acquisition window duration, and the rest of the pulse period is not collected. The number of pulses collected determines the total pulse acquisition process duration. The effective parameters require that the pulse period is much longer than the pulse acquisition window duration, and the pulse period is greater than 5us, otherwise it will cause pulse acquisition errors.

[0004] Wideband radar pulse signals have a certain duty cycle and period, and their pulse width is much shorter than the pulse period. Continuous acquisition and storage of radar pulse signals for a certain period of time is required to collect important parameters of radar pulse signals and save storage space. The key consideration is that the pulse acquisition window duration is shorter than the pulse period, and the pulse period information is retained through timestamps. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a system and method for implementing pulse acquisition in a broadband radar receiver which has good integrity, high reliability and a wide range of applications.

[0006] In order to achieve the above object, the system and method for implementing pulse acquisition in a broadband radar receiver of the present invention are as follows:

[0007] The system is suitable for realizing pulse acquisition by a broadband radar receiver, and its main characteristics are that the system includes a register read-write module, a pulse detection module, a pulse acquisition module, a DDR4 data storage and positioning module and a host computer, the output end of the register read-write module is connected to the pulse detection module and the pulse acquisition module, the output end of the pulse detection module is connected to the pulse acquisition module, the output end of the pulse acquisition module is connected to the DDR4 data storage and positioning module, and the DDR4 data storage and positioning module is connected to the host computer;

[0008] The register read-write module is used to set pulse detection parameters and acquisition parameters. The pulse detection module is used to calculate the power of the signal collected by the AD chip and detect whether the pulse exists according to the sign bit. The pulse acquisition module is used to delay the data for a period of time according to the pulse acquisition window advance time parameter. The DDR4 data storage and positioning module is used to use DDR4 as a cache space for read and write operations, and send the frame header address information of the first pulse collected after the pulse acquisition is enabled to the host computer. The host computer is used to query the pulse acquisition first frame address and pulse acquisition data volume register after receiving the data processing request interrupt, and obtain the frame header, data volume information and timestamp information of each pulse acquisition data through the first frame address and data volume information, and obtain the specific information of each pulse signal.

[0009] Preferably, the pulse detection module calculates the power of the signal collected by the AD chip, subtracts the collected signal power value from the pulse trigger power threshold, and if it does not exceed the pulse trigger power threshold, the highest sign bit is 0; if it exceeds the pulse trigger power threshold, the highest sign bit becomes 1;

[0010] The sign bit is used as the basis for detecting the existence of a pulse. If a pulse is detected, the pulse acquisition signal becomes a high-level output. If a pulse is detected not to exist, counting starts according to the pulse acquisition window holding time. After the counting result is equal to the pulse acquisition window holding time, the pulse acquisition signal becomes a low-level output.

[0011] Preferably, after detecting that the pulse acquisition enable signal is at a high level and the pulse acquisition signal is at a high level, the pulse acquisition module starts transmitting the first pulse data; transmits the frame header identification information of the pulse, and records the data of the first pulse signal currently transmitted for the first pulse, ensures the data particle integrity, and outputs the frame end information; enters the waiting state for the second pulse trigger, and performs pulse acquisition in a loop until the last pulse acquisition is completed; fills the data particle integrity, and sends a data processing request interrupt signal to the host computer.

[0012] Preferably, the pulse acquisition module performs pulse acquisition cyclically, specifically comprising the following steps:

[0013] (1-1) The data signal is actually stored in DDR4 under the control of the trigger state machine. The write condition is when the pulse power is detected, that is, when the trig_pulse signal is high;

[0014] (1-2) When it is detected that the parameter configuration completion signal cfg_en, the pulse acquisition enable signal trig_en and the pulse acquisition signal trig_pulse are all high, jump to the TRIG state and continue with step (1-3);

[0015] (1-3) In the TRIG state, the pulse frame header identification information is transmitted, the current pulse collection quantity is recorded, and the data of the pulse signal is started to be transmitted;

[0016] (1-4) During the execution of (1-3), if the trig_pulse signal is detected to be low, data transmission is stopped, the state jumps to the GRANULARITY_i state, and step (1-5) is continued;

[0017] (1-5) In the GRANULARITY_i state, continue to transmit the data of the current frame of the pulse signal;

[0018] (1-6) When the data end signal dat_vld_last of the current frame is detected to be high, it jumps to the EOF state and continues with step (1-7);

[0019] (1-7) In the EOF state, the data volume, timestamp and frame end identifier of this pulse are output;

[0020] (1-8) After detecting the frame end transmission completion signal eof_vld, if the current pulse collection number pul_cnt is less than the set pulse collection number pulse_number, enter the SLEEP state and continue with step (1-9); if the current pulse collection number pul_cnt is equal to the set pulse collection number pulse_number, or the forced interrupt pulse collection signal pul_intr is detected to be high, jump to the GRANULARITY_ii state and continue with step (1-10);

[0021] (1-9) In the SLEEP state, stop storing data into DDR4. If the pulse acquisition signal trig_pulse is detected to be at a high level, jump to the TRIG state and continue with step (1-3) to start the next pulse data acquisition;

[0022] (1-10) In the GRANULARITY_ii state, transmit all-0 data of the DDR4 data block size to meet the DDR4 storage conditions and ensure that all valid data is completely stored in the DDR4 until the last pulse triggers the end of the frame;

[0023] (1-11) If the pulse acquisition completion signal pul_acq_down is detected to be valid, jump to the STOP state and continue with step (1-12);

[0024] (1-12) In the STOP state, a data processing request interrupt is sent to the host computer, and data storage in DDR4 is stopped. The pulse characteristic information remains unchanged. After the host computer processes the data, it exits the trigger acquisition mode and causes the state machine to jump to the FREE state.

[0025] The method for pulse acquisition based on the above system is applicable to a wideband radar receiver, and its main feature is that the method comprises the following steps:

[0026] According to the power comparison result of the data source as the pulse acquisition signal, the pulse signal data is collected through the pulse module and stored in the DDR4 space in the data frame format. After completing a pulse acquisition, wait for the next pulse acquisition signal, and perform pulse acquisition in a cycle until the acquisition requirements are met. Stop the acquisition, send a signal processing request interrupt to the host computer, and keep the key parameters valid.

[0027] The system and method for implementing pulse acquisition in a broadband radar receiver of the present invention are used to fully utilize the large capacity provided by the hardware DDR4 RAM, and to ensure continuous data acquisition for a long time by only collecting part of the effective signal of the radar pulse. The periodic parameters of the radar pulse are retained through the timestamp information, which ensures the integrity of the radar pulse signal and facilitates the subsequent signal processing and analysis. A variety of flexible and configurable pulse acquisition parameters ensure the reliability and integrity of the collected pulse signal. The modularization of the functional unit is realized, and it can be flexibly transplanted to the scene requiring long-term pulse acquisition, meeting the modular design requirements of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The present invention is a schematic diagram of the radar pulse signal acquisition and storage time axis of the system and method for implementing pulse acquisition in a wideband radar receiver.

[0029] Figure 2 The present invention is a schematic diagram of the pulse acquisition data processing flow of the system and method for implementing pulse acquisition in a wideband radar receiver.

[0030] Figure 3 The present invention is a schematic diagram of a pulse acquisition module state machine of a system and method for implementing pulse acquisition in a wideband radar receiver.

[0031] Figure 4 The present invention is a schematic diagram of a pulse data storage format of a system and method for implementing pulse acquisition in a wideband radar receiver.

[0032] Figure 5 The present invention is a schematic diagram of a pulse frame header address detection state machine of a system and method for implementing pulse acquisition in a broadband radar receiver. DETAILED DESCRIPTION

[0033] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0034] The system of the present invention, which is applicable to a wideband radar receiver for implementing pulse acquisition, comprises:

[0035] A register read-write module, a pulse detection module, a pulse acquisition module, a DDR4 data storage and positioning module and a host computer, wherein the output end of the register read-write module is connected to the pulse detection module and the pulse acquisition module, the output end of the pulse detection module is connected to the pulse acquisition module, the output end of the pulse acquisition module is connected to the DDR4 data storage and positioning module, and the DDR4 data storage and positioning module is connected to the host computer;

[0036] The register read-write module is used to set pulse detection parameters and acquisition parameters. The pulse detection module is used to calculate the power of the signal collected by the AD chip and detect whether the pulse exists according to the sign bit. The pulse acquisition module is used to delay the data for a period of time according to the pulse acquisition window advance time parameter. The DDR4 data storage and positioning module is used to use DDR4 as a cache space for read and write operations, and send the frame header address information of the first pulse collected after the pulse acquisition is enabled to the host computer. The host computer is used to query the pulse acquisition first frame address and pulse acquisition data volume register after receiving the data processing request interrupt, and obtain the frame header, data volume information and timestamp information of each pulse acquisition data through the first frame address and data volume information, and obtain the specific information of each pulse signal.

[0037] As a preferred embodiment of the present invention, the pulse detection module calculates the power of the signal collected by the AD chip, and subtracts the collected signal power value from the pulse trigger power threshold. If it does not exceed the pulse trigger power threshold, the highest bit sign bit is 0; if it exceeds the pulse trigger power threshold, the highest bit sign bit becomes 1;

[0038] The sign bit is used as the basis for detecting the existence of a pulse. If a pulse is detected, the pulse acquisition signal becomes a high-level output. If a pulse is detected not to exist, counting starts according to the pulse acquisition window holding time. After the counting result is equal to the pulse acquisition window holding time, the pulse acquisition signal becomes a low-level output.

[0039] As a preferred embodiment of the present invention, the pulse acquisition module starts the transmission of the first pulse data after detecting that the pulse acquisition enable signal is at a high level and the pulse acquisition signal is at a high level; transmits the frame header identification information of the pulse, and records the data of the first pulse signal currently transmitted for the first pulse, ensures the data particle integrity, and outputs the frame end information; enters the waiting state for the second pulse trigger, and performs pulse acquisition in a loop until the last pulse acquisition is completed; fills the data particle integrity, and sends a data processing request interrupt signal to the host computer.

[0040] As a preferred embodiment of the present invention, the pulse acquisition module performs pulse acquisition cyclically, specifically comprising the following steps:

[0041] (1-1) The data signal is actually stored in DDR4 under the control of the trigger state machine. The write condition is when the pulse power is detected, that is, when the trig_pulse signal is high;

[0042] (1-2) When it is detected that the parameter configuration completion signal cfg_en, the pulse acquisition enable signal trig_en and the pulse acquisition signal trig_pulse are all high, jump to the TRIG state and continue with step (1-3);

[0043] (1-3) In the TRIG state, the pulse frame header identification information is transmitted, the current pulse collection quantity is recorded, and the data of the pulse signal is started to be transmitted;

[0044] (1-4) During the execution of (1-3), if the trig_pulse signal is detected to be low, data transmission is stopped, the state jumps to the GRANULARITY_i state, and step (1-5) is continued;

[0045] (1-5) In the GRANULARITY_i state, continue to transmit the data of the current frame of the pulse signal;

[0046] (1-6) When the data end signal dat_vld_last of the current frame is detected to be high, it jumps to the EOF state and continues with step (1-7);

[0047] (1-7) In the EOF state, the data volume, timestamp and frame end identifier of this pulse are output;

[0048] (1-8) After detecting the frame end transmission completion signal eof_vld, if the current pulse collection number pul_cnt is less than the set pulse collection number pulse_number, enter the SLEEP state and continue with step (1-9); if the current pulse collection number pul_cnt is equal to the set pulse collection number pulse_number, or the forced interrupt pulse collection signal pul_intr is detected to be high, jump to the GRANULARITY_ii state and continue with step (1-10);

[0049] (1-9) In the SLEEP state, stop storing data into DDR4. If the pulse acquisition signal trig_pulse is detected to be at a high level, jump to the TRIG state and continue with step (1-3) to start the next pulse data acquisition;

[0050] (1-10) In the GRANULARITY_ii state, transmit all-0 data of the DDR4 data block size to meet the DDR4 storage conditions and ensure that all valid data is completely stored in the DDR4 until the last pulse triggers the end of the frame;

[0051] (1-11) If the pulse acquisition completion signal pul_acq_down is detected to be valid, jump to the STOP state and continue with step (1-12);

[0052] (1-12) In the STOP state, a data processing request interrupt is sent to the host computer, and data storage in DDR4 is stopped. The pulse characteristic information remains unchanged. After the host computer processes the data, it exits the trigger acquisition mode and causes the state machine to jump to the FREE state.

[0053] The method for pulse acquisition by a broadband radar receiver based on the above system of the present invention comprises the following steps:

[0054] According to the power comparison result of the data source as the pulse acquisition signal, the pulse signal data is collected through the pulse module and stored in the DDR4 space in the data frame format. After completing a pulse acquisition, wait for the next pulse acquisition signal, and perform pulse acquisition in a cycle until the acquisition requirements are met. Stop the acquisition, send a signal processing request interrupt to the host computer, and keep the key parameters valid.

[0055] In a specific embodiment of the present invention, a method is proposed to capture and store pulse signals within the radar signal pulse period based on the signal power detection result, and timestamp information is added at the end of the pulse to realize the storage of radar pulse signal pulse width and pulse period parameters, thereby saving DDR4 storage space, extending the acquisition time, satisfying the adjustable number of pulse acquisitions, and adjustable pulse effective acquisition window width, thereby ensuring signal integrity.

[0056] The functional structure of the program is as follows Figure 2 As shown in the pulse acquisition data processing flow chart, it mainly consists of five parts, namely, pulse triggering and acquisition parameter register reading and writing module; pulse detection module; pulse acquisition module; DDR4 data storage and positioning module; host computer data analysis.

[0057] Further description according to different functional units:

[0058] 1. Register read and write module: used to set pulse detection and acquisition parameters. Detection related: pulse trigger power threshold; acquisition related: pulse acquisition enable, pulse acquisition quantity, pulse acquisition window advance time, pulse acquisition window hold time; host computer related: pulse acquisition first frame address, pulse acquisition data volume, pulse acquisition data processing request interrupt;

[0059] 2. Pulse detection module: Calculate the power of the signal collected by the AD chip, subtract the collected signal power value from the pulse trigger power threshold. If it does not exceed the pulse trigger power threshold, the calculation result is positive, and the highest sign bit is 0. If it exceeds the pulse trigger power threshold, the calculation result is negative, and the highest sign bit becomes 1. The sign bit is used as the basis for detecting the existence of the pulse. After the pulse is detected, the pulse acquisition signal becomes a high-level output. If the pulse is not detected, the counting starts according to the pulse acquisition window holding time, until the counting result is equal to the pulse acquisition window holding time, and then the pulse acquisition signal becomes a low-level output.

[0060] 3. Pulse acquisition module: The processed signal data itself can be in stream mode or frame mode. According to the pulse acquisition window advance time parameter, the FIFO is used to delay the data for a period of time to ensure the integrity of the pulse signal acquisition. After detecting that the pulse acquisition enable signal is high and the pulse acquisition signal is high, the transmission of the first pulse data begins. First, the frame header identification information of the pulse is transmitted, and the current first pulse is recorded. Then the data of the first pulse signal is transmitted to ensure the integrity of the data particles, and finally the frame end information is output; then the state of waiting for the second pulse trigger is entered, and pulse acquisition is performed in a loop until the last pulse acquisition is completed, the data particle integrity is filled, and the DDR4 storage conditions are met. After ensuring that all valid data can be completely stored in DDR4, a data processing request interrupt signal is sent to the host computer.

[0061] 4. DDR4 data cache module: DDR4 is used as cache space for read and write operations. The DDR4 AXI4 interface uses data blocks as operation units for burst access. The data block size has two parameters, one is the data bit width, and the other is the data length. The data needs to be read out and rounded into data blocks before it can be written into DDR4. The frame header address information of the first pulse collected after pulse collection is enabled is sent to the host computer, such as Figure 5 As shown, it is convenient for the host computer to find and analyze the pulse acquisition data stored in DDR4;

[0062] 5. After the host computer receives the data processing request interrupt, it queries the pulse acquisition first frame address and pulse acquisition data volume register, and uses the first frame address and data volume information to deduce the frame tail of the last pulse acquisition data frame. The frame tail contains the data volume information of the last pulse acquisition, and the frame tail of the previous frame is deduced. This process is repeated in this way to obtain the frame header, data volume information and timestamp information of each pulse acquisition data, and organize them into a list. Based on the information in the list, the host computer can obtain the specific information of each pulse signal from DDR4, including waveform, power, and pulse period.

[0063] The pulse acquisition method suitable for a broadband radar receiver proposed in the present invention uses the data source power comparison result as the pulse acquisition signal, mainly acquires pulse signal data through a pulse module, and stores it in a data frame format (with timestamp information) to the DDR4 space. After completing one pulse acquisition, it waits for the next pulse acquisition signal, and performs pulse acquisition in a cycle until the acquisition requirements are met, stops acquisition, sends a signal processing request interrupt to the host computer, and keeps key parameters valid.

[0064] The pulse acquisition module state machine block diagram is as follows Figure 3 This block diagram further explains the pulse acquisition implementation in detail and identifies key states and jump information.

[0065] Pulse data storage format is as follows Figure 4 shown.

[0066] The pulse acquisition module state machine is described below:

[0067] (1) In the FREE state, the data signal is stored in DDR4 in real time;

[0068] (2) When cfg_en (parameter configuration completed), trig_en (pulse acquisition enable), and trig_pulse (pulse acquisition signal) are detected to be high, it jumps to the TRIG state;

[0069] (3) In the TRIG state, the pulse frame header identification information is first transmitted, and the current pulse collection number is recorded, and then the pulse signal data is transmitted;

[0070] (4) When trig_pulse (pulse acquisition signal) is detected to be at a low level, it jumps to the GRANULARITY_i state;

[0071] (5) In the GRANULARITY_i state, continue to transmit the data of the current frame of the pulse signal;

[0072] (6) When dat_vld_last (data end signal of the current frame) is detected to be high, it jumps to the EOF state;

[0073] (7) In the EOF state, output the data volume, timestamp and end-of-frame identifier of this pulse;

[0074] (8) When the eof_vld (frame end transmission completion) signal is detected, if the current pul_cnt (pulse collection number) is less than the set pulse_number (pulse collection number), then enter the SLEEP state and continue with step (9); if the current pul_cnt is equal to the set pulse_number, or pul_intr (forced interrupt pulse collection) is detected to be high, jump to the GRANULARITY_ii state and continue with step (10);

[0075] (9) In the SLEEP state, stop storing data into DDR4. If trig_pulse (pulse acquisition signal) is detected to be high, jump to the TRIG state, continue with step (3), and start the next pulse data acquisition;

[0076] (10) In the GRANULARITY_ii state, transmit all-0 data of the DDR4 data block size to meet the DDR4 storage conditions and ensure that all valid data can be completely stored in the DDR4 until the end of the last pulse trigger frame;

[0077] (11) When pul_acq_down (pulse acquisition completed) is detected to be valid, it jumps to the STOP state;

[0078] (12) In the STOP state, a data processing request interrupt is sent to the host computer, and data storage in DDR4 is stopped, and the pulse characteristic information remains unchanged. After the host computer processes the data, it sends ~trig_en (exit trigger acquisition mode) to make the state machine jump to the FREE state.

[0079] pul_intr (forced interruption of pulse collection) includes: exiting pulse collection mode, pausing pulse collection, and DDR4 disk overflow. In these cases, pulse collection will be completed in advance and related information will be stored in the register for easy query by the host computer.

[0080] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.

[0081] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0082] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0083] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0084] The system and method for implementing pulse acquisition in a broadband radar receiver of the present invention are used to fully utilize the large capacity provided by the hardware DDR4 RAM, and to ensure continuous data acquisition for a long time by only collecting part of the effective signal of the radar pulse. The periodic parameters of the radar pulse are retained through the timestamp information, which ensures the integrity of the radar pulse signal and facilitates the subsequent signal processing and analysis. A variety of flexible and configurable pulse acquisition parameters ensure the reliability and integrity of the collected pulse signal. The modularization of the functional unit is realized, and it can be flexibly transplanted to the scene requiring long-term pulse acquisition, meeting the modular design requirements of the system.

[0085] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system for implementing pulse acquisition in a broadband radar receiver, characterized in that: The system includes a register read-write module, a pulse detection module, a pulse acquisition module, a DDR4 data storage and positioning module and a host computer, wherein the output end of the register read-write module is connected to the pulse detection module and the pulse acquisition module, the output end of the pulse detection module is connected to the pulse acquisition module, the output end of the pulse acquisition module is connected to the DDR4 data storage and positioning module, and the DDR4 data storage and positioning module is connected to the host computer; The register read-write module is used to set pulse detection parameters and acquisition parameters. The pulse detection module is used to calculate the power of the signal collected by the AD chip and detect whether the pulse exists according to the sign bit. The pulse acquisition module is used to delay the data for a period of time according to the pulse acquisition window advance time parameter. The DDR4 data storage and positioning module is used to use DDR4 as a cache space for read and write operations, and send the frame header address information of the first pulse collected after the pulse acquisition is enabled to the host computer. The host computer is used to query the pulse acquisition first frame address and pulse acquisition data volume register after receiving the data processing request interrupt, and obtain the frame header, data volume information and timestamp information of each pulse acquisition data through the first frame address and data volume information, and obtain the specific information of each pulse signal.

2. The system for implementing pulse acquisition in a broadband radar receiver according to claim 1, characterized in that: The pulse detection module calculates the power of the signal collected by the AD chip, and subtracts the collected signal power value from the pulse trigger power threshold. If it does not exceed the pulse trigger power threshold, the highest bit sign is 0; if it exceeds the pulse trigger power threshold, the highest bit sign becomes 1; The sign bit is used as the basis for detecting the existence of a pulse. If a pulse is detected, the pulse acquisition signal becomes a high-level output. If a pulse is detected not to exist, counting starts according to the pulse acquisition window holding time. After the counting result is equal to the pulse acquisition window holding time, the pulse acquisition signal becomes a low-level output.

3. The system for implementing pulse acquisition in a broadband radar receiver according to claim 1, characterized in that: The pulse acquisition module starts the transmission of the first pulse data after detecting that the pulse acquisition enable signal is at a high level and the pulse acquisition signal is at a high level; transmits the frame header identification information of the pulse, and records the data of the first pulse signal currently transmitted for the first pulse, ensures the integrity of the data particles, and outputs the frame end information; Enter the state of waiting for the second pulse trigger, and perform pulse acquisition in a loop until the last pulse acquisition is completed; fill in the data particle completeness and send a data processing request interrupt signal to the host computer.

4. The system for implementing pulse acquisition in a broadband radar receiver according to claim 1, characterized in that: The pulse acquisition module performs pulse acquisition cyclically, specifically comprising the following steps: (1-1) The data signal is actually stored in DDR4 under the control of the trigger state machine. The write condition is when the pulse power is detected, that is, when the trig_pulse signal is high; (1-2) When it is detected that the parameter configuration completion signal cfg_en, the pulse acquisition enable signal trig_en and the pulse acquisition signal trig_pulse are all high, jump to the TRIG state and continue with step (1-3); (1-3) In the TRIG state, the pulse frame header identification information is transmitted, the current pulse collection quantity is recorded, and the data of the pulse signal is started to be transmitted; (1-4) During the execution of (1-3), if the trig_pulse signal is detected to be low, data transmission is stopped, the state jumps to the GRANULARITY_i state, and step (1-5) is continued; (1-5) In the GRANULARITY_i state, continue to transmit the data of the current frame of the pulse signal; (1-6) When the data end signal dat_vld_last of the current frame is detected to be high, it jumps to the EOF state and continues with step (1-7); (1-7) In the EOF state, the data volume, timestamp and frame end identifier of this pulse are output; (1-8) After detecting the frame end transmission completion signal eof_vld, if the current pulse collection number pul_cnt is less than the set pulse collection number pulse_number, enter the SLEEP state and continue with step (1-9); if the current pulse collection number pul_cnt is equal to the set pulse collection number pulse_number, or the forced interrupt pulse collection signal pul_intr is detected to be high, jump to the GRANULARITY_ii state and continue with step (1-10); (1-9) In the SLEEP state, stop storing data into DDR4. If the pulse acquisition signal trig_pulse is detected to be at a high level, jump to the TRIG state and continue with step (1-3) to start the next pulse data acquisition; (1-10) In the GRANULARITY_ii state, transmit all-0 data of the DDR4 data block size to meet the DDR4 storage conditions and ensure that all valid data is completely stored in the DDR4 until the last pulse triggers the end of the frame; (1-11) If the pulse acquisition completion signal pul_acq_down is detected to be valid, jump to the STOP state and continue with step (1-12); (1-12) In the STOP state, a data processing request interrupt is sent to the host computer, and data storage in DDR4 is stopped. The pulse characteristic information remains unchanged. After the host computer processes the data, it exits the trigger acquisition mode and causes the state machine to jump to the FREE state.

5. A method for pulse acquisition by a wideband radar receiver based on the system of claim 1, characterized in that: The method comprises the following steps: According to the power comparison result of the data source as the pulse acquisition signal, the pulse signal data is collected through the pulse module and stored in the DDR4 space in the data frame format. After completing a pulse acquisition, wait for the next pulse acquisition signal, and perform pulse acquisition in a cycle until the acquisition requirements are met. Stop the acquisition, send a signal processing request interrupt to the host computer, and keep the key parameters valid.

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