Reference voltage generating circuit

Abstract

The reference voltage generation circuit comprises a current bias circuit used for generating bias current, a voltage division circuit and a temperature compensation circuit, the voltage division circuit comprises a bipolar transistor used for generating negative temperature coefficient voltage, at least two first NMOS (N-channel Metal Oxide Semiconductor) tubes serving as voltage division devices, a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube, the first NMOS transistor is in cascade connection between the emitting electrode of the bipolar transistor and the ground; the grid electrode of the first PMOS tube is connected with the emitting electrode, and the source electrode is connected with a power supply through a first resistor; the second PMOS tube is connected between the drain electrode of the first NMOS tube and the power supply, the grid electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube, and the second PMOS tube is a native device. The negative temperature coefficient characteristic of the first voltage is compensated through the positive temperature coefficient characteristic voltage of the temperature compensation circuit, so that the zero temperature coefficient reference voltage can be output. The circuit can ensure that the voltage dividing device does not exceed the withstand voltage and is in a normal working area, so that the accuracy and stability of the reference voltage are ensured.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit design, and in particular to a reference voltage generating circuit. Background Art

[0002] In analog and mixed-signal integrated circuit design, a voltage reference source is a key component that provides a stable voltage reference point for the circuit, which is essential for the correct operation of the circuit.

[0003] The reference voltage source is usually realized by a voltage divider circuit, and the metal-oxide-semiconductor field effect transistor (MOSFET) is usually used as a voltage divider device in the voltage divider circuit due to its advantages in performance, integration, power consumption, etc.

[0004] However, when the power supply voltage is high, the voltage divider device may be subjected to a voltage exceeding or approaching its withstand voltage limit, which may cause device damage or degradation of operating performance, and affect the accuracy and stability of the reference voltage. Summary of the invention

[0005] An object of one or more embodiments of the present disclosure is to provide a reference voltage generating circuit.

[0006] The reference voltage generating circuit comprises a current bias circuit, a voltage dividing circuit and a temperature compensation circuit;

[0007] The current bias circuit is used to generate a bias current;

[0008] The voltage divider circuit comprises:

[0009] A bipolar transistor, wherein the bias current is input into the bipolar transistor and generates a negative temperature coefficient voltage;

[0010] At least two first NMOS tubes are cascade-connected between the emitter of the bipolar transistor and the ground, wherein the gate of the first first NMOS tube in the cascade is connected to the emitter, and the drain of the last first NMOS tube outputs a first voltage;

[0011] a first PMOS transistor, wherein a gate of the first PMOS transistor is connected to an emitter of the bipolar transistor, and a source of the first PMOS transistor is connected to a power source via a first resistor;

[0012] a second PMOS tube connected between the drain of the first NMOS tube and a power supply, a gate of the second PMOS tube connected to the source of the first PMOS tube, wherein the second PMOS tube is a native device;

[0013] The temperature compensation circuit is used to perform temperature compensation on the first voltage and output a zero temperature coefficient reference voltage.

[0014] In some embodiments, the voltage divider circuit also includes a third PMOS tube and a fourth PMOS tube, wherein the third PMOS tube is used to mirror the bias current, the source of the fourth PMOS tube is connected to the drain of the third PMOS tube, the drain is connected to the emitter of the bipolar transistor, and the input voltage of the gate is the bias voltage provided by the current bias circuit.

[0015] In some embodiments, the voltage divider circuit further includes a second NMOS transistor connected in a diode manner, and the drain of the first PMOS transistor is grounded via the second NMOS transistor.

[0016] In some embodiments, the current bias circuit includes a first current mirror, a second current mirror and a second resistor, the first current mirror includes a fifth PMOS tube and a sixth PMOS tube whose gates are connected to each other and whose sources are connected to a power supply, and the gate of the sixth PMOS tube is connected to the drain; the second current mirror is cascade-connected to the first current mirror, the second current mirror includes a third NMOS tube and a fourth NMOS tube whose gates are connected to each other, the gate of the third NMOS tube is connected to the drain, and the fourth NMOS tube is grounded via a second resistor.

[0017] In some embodiments, the current bias circuit further includes a fifth NMOS tube and a seventh PMOS tube;

[0018] The fifth NMOS tube is used to mirror the current output by the second current mirror. The source of the fifth NMOS tube is grounded, and the drain is connected to the power supply via the seventh PMOS tube connected in a diode manner. The gate of the seventh PMOS tube outputs a bias voltage.

[0019] In some embodiments, the reference voltage generating circuit further includes an eighth PMOS tube, a ninth PMOS tube, and a tenth PMOS tube for replicating the current of the sixth PMOS tube, and a sixth NMOS tube, a seventh NMOS tube, and an eighth NMOS tube for replicating the current of the third NMOS tube;

[0020] Wherein, the source of the ninth PMOS tube is connected to the power supply, the drain is connected to the drain of the sixth NMOS tube, the gate is connected to the drain of the fifth PMOS tube, the gate of the tenth PMOS tube is connected to the drain of the ninth PMOS tube, the source is connected to the gate of the ninth PMOS tube, and the drain is connected to the drain of the third NMOS tube;

[0021] The source of the seventh NMOS tube is grounded, the drain is connected to the drain of the eighth PMOS tube, the gate is connected to the drain of the fourth NMOS tube, the gate of the eighth NMOS tube is connected to the drain of the seventh NMOS tube, the source is connected to the gate of the seventh NMOS tube, and the drain is connected to the drain of the sixth PMOS tube.

[0022] In some embodiments, the temperature compensation circuit includes multiple threshold difference voltage sub-circuits, wherein each threshold difference voltage sub-circuit has a positive temperature coefficient, and the number of the threshold difference voltage sub-circuit is determined based on the numerical relationship between the negative temperature coefficient of the bipolar transistor and the positive temperature coefficient of each of the threshold difference voltage sub-circuits.

[0023] In some embodiments, the reference voltage generating circuit further includes a startup circuit, and the startup circuit includes an eleventh NMOS tube, a twelfth NMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube and an inverter;

[0024] Wherein, the gates of the eleventh NMOS tube and the twelfth NMOS tube are connected to each other, the sources are grounded, and the gate and drain of the twelfth NMOS tube are connected;

[0025] The fourteenth PMOS tube is connected between the power supply and the eleventh NMOS tube in a diode manner, and the fifteenth PMOS tube is connected between the power supply and the twelfth NMOS tube;

[0026] The gate of the fourteenth PMOS tube is connected to the gates of the sixteenth PMOS tube and the seventeenth PMOS tube via the inverter, the sources of the sixteenth PMOS tube and the seventeenth PMOS tube are connected to a power supply, and the drains are respectively used to provide a first initial current and a second initial current.

[0027] In some embodiments, the number of the first NMOS tubes is two or three.

[0028] The reference voltage generating circuit provided by the present disclosure includes a current bias circuit, a voltage divider circuit and a temperature compensation circuit, wherein the current bias circuit is used to generate a bias current; the voltage divider circuit includes: a bipolar transistor generating a negative temperature coefficient voltage, at least two first NMOS tubes as voltage divider devices, a first PMOS tube and a second PMOS tube, wherein the at least two first NMOS tubes are cascaded and connected between the emitter and the ground of the bipolar transistor, wherein the gate of the first first NMOS tube of the cascade is connected to the emitter, and the drain of the last one outputs a first voltage; the gate of the first PMOS tube is connected to the emitter of the bipolar transistor, and the source is connected to the power supply through a first resistor; the second PMOS tube is connected between the drain of the first first NMOS tube and the power supply, and the gate of the second PMOS tube is connected to the source of the first PMOS tube, wherein the second PMOS tube is a native device. The negative temperature coefficient characteristic of the first voltage is compensated by the positive temperature coefficient characteristic voltage of the temperature compensation circuit, so that a zero temperature coefficient reference voltage can be output. Since the first PMOS tube and the first resistor form a source follower, the gate voltage of the second PMOS tube is clamped at the sum of the negative temperature coefficient voltage and the gate-source voltage of the first PMOS tube. Since the threshold voltage of the native device is close to 0V, the drain voltage of the first voltage divider device is also clamped at this voltage. Therefore, it can be ensured that the voltage divider device does not exceed the withstand voltage and is in the normal working area, thereby ensuring the accuracy and stability of the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in one or more embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0030] Figure 1 A schematic diagram of the structure of a reference voltage generating circuit provided by at least one embodiment of the present disclosure;

[0031] Figure 2 A schematic diagram of a voltage divider circuit provided by at least one embodiment of the present disclosure;

[0032] Figure 3 A schematic diagram of the structure of a current bias circuit provided by at least one embodiment of the present disclosure;

[0033] Figure 4 A schematic diagram of the structure of a threshold difference voltage subcircuit provided by at least one embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of a start-up circuit provided by at least one embodiment of the present disclosure;

[0035] Figure 6 A schematic structural diagram of another reference voltage generating circuit provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this disclosure.

[0037] At least one embodiment of the present disclosure provides a reference voltage generating circuit for providing accurate and stable parameter voltage. The circuit can withstand high power supply voltage and can therefore be applied to systems with a large power supply voltage range and a long standby time. It can also be used in products that need to be compatible with multiple power supply voltage standards.

[0038] like Figure 1 As shown, the reference voltage generating circuit includes a current bias circuit 11 , a voltage divider circuit 12 , and a temperature compensation circuit 13 .

[0039] The current bias circuit 11 is used to generate a bias current I B In the embodiment of the present disclosure, a current mirror structure can be used to provide a stable bias current I B .

[0040] The voltage divider circuit 12 may include a bipolar transistor B1, at least two first NMOS transistors N1i (i is a positive integer not greater than N, and N is the number of first NMOS transistors), a first PMOS transistor P1, and a second PMOS transistor P2. Figure 1 The case where three first NMOS tubes are included is shown as an example.

[0041] The bipolar transistor B1 is used to generate a bias current I B Generates a negative temperature coefficient voltage V be .like Figure 1 As shown, the bipolar transistor B1 can be set to ground the base and collector, and the bias current I BInput from the emitter generates a forward bias voltage relative to the base. This voltage depends on the type of bipolar transistor and is approximately 0.6 to 0.7 V when the transistor is a silicon tube.

[0042] At least two first NMOS transistors are cascaded as voltage dividers between the emitter of B1 and ground GND, wherein the gate of the first cascaded first NMOS transistor N11 is connected to the emitter of B1, and the drain of the last first NMOS transistor N1N outputs the first voltage Vo'.

[0043] The first NMOS transistors as voltage dividers are usually low-voltage MOS transistors, and the channel length L and width W of each first NMOS transistor are the same. Therefore, at least two first NMOS transistors are connected to V be The voltage is divided, and the voltage is almost not affected by the changes in process parameters, power supply voltage and bias current I B impact.

[0044] The number of voltage dividers included in the reference voltage generation circuit can be determined according to the magnitude of the negative temperature coefficient voltage and the output reference voltage, and usually includes two or three voltage dividers, that is, the negative temperature coefficient voltage is divided into two or three voltages. However, due to the influence of the lining effect, the voltage division may not completely meet the requirements of dividing into two or three equal parts.

[0045] In the case of two voltage divider devices, the gate of the first NMOS transistor N11 is connected to the emitter of B1, the gate is connected to the drain of the second NMOS transistor N12, the drain and gate of N12 are connected, and the source is grounded. The source of N11 (the drain or gate of N12) outputs the first voltage Vo'.

[0046] In the case of including three voltage divider devices, the gate of the first NMOS transistor N11 is connected to the emitter of B1, and the gate is connected to the drain of the second NMOS transistor N12; the drain and gate of N12 are connected, and the source is connected to the drain of the third NMOS transistor N13; the drain and gate of N13 are connected, and the source is grounded. The source of N12 (the drain or gate of N13) outputs the first voltage Vo'.

[0047] The gate of the first PMOS transistor P1 is connected to the emitter of B1, and the source is connected to the power supply VCC through the first resistor R1. The second PMOS transistor P2 is connected between the drain of N1 and the power supply VCC, that is, the source of P2 is connected to the drain of N1, the drain is connected to VCC, and the gate of P2 is connected to the source of P1, wherein P2 is a native device. A native device refers to a MOS transistor with a threshold voltage close to zero.

[0048] In some embodiments, the voltage divider circuit 12 further includes a second NMOS transistor N2, which is an NMOS transistor connected in a diode manner. R1, P1, and N2 form a bias circuit to provide a bias voltage for the gate of P2. N2 can also be replaced by a diode.

[0049] The gate voltage of P1 is connected to the emitter of B1, so the gate voltage is V be , P1 and R1 form a source follower, and the gate voltage of P2 is V be +VGS P1 Since the threshold voltage of the native device P2 is close to 0V, the drain voltage of the voltage divider device N11 is approximately V be +VGS P1 It can be seen that by superimposing the native device on the voltage divider device, the drain voltage of the voltage divider device is limited, which can ensure that each voltage divider device does not exceed the withstand voltage and is in the normal working area.

[0050] Since the bipolar transistor B1 generates a negative temperature coefficient voltage V be , so for V be The first voltage Vo' obtained by voltage division also has a negative temperature coefficient, so the reference voltage generating circuit also includes a temperature compensation circuit 13. The voltage generated by the temperature compensation circuit has a positive temperature coefficient to offset the negative temperature coefficient of the first voltage Vo', thereby obtaining a zero temperature coefficient reference voltage Vo that is independent of temperature changes.

[0051] The reference voltage generating circuit provided by the present disclosure includes a current bias circuit, a voltage divider circuit and a temperature compensation circuit, wherein the current bias circuit is used to generate a bias current; the voltage divider circuit includes: a bipolar transistor that generates a negative temperature coefficient, at least two first NMOS tubes, a first PMOS tube and a second PMOS tube as voltage divider devices, wherein the at least two first NMOS tubes are cascaded and connected between the emitter of B1 and the ground, wherein the gate of the first first NMOS tube in the cascade is connected to the emitter of B1, and the drain of the last one outputs a first voltage; the gate of the first PMOS tube is connected to the emitter of B1, and the source is connected to the power supply through a first resistor; the second PMOS tube is connected between the drain of the first first NMOS tube and the power supply, and the gate of the second PMOS tube is connected to the source of the first PMOS tube, wherein the second PMOS tube is a native device; the temperature compensation circuit performs temperature compensation on the first voltage and outputs a reference voltage with a zero temperature coefficient. Since the first PMOS tube and the first resistor form a source follower, the gate voltage of the second PMOS tube is clamped at the sum of the negative temperature coefficient voltage and the gate-source voltage of the first PMOS tube. Since the threshold voltage of the native device is close to 0V, the drain voltage of the first voltage divider device is also clamped at this voltage. Therefore, it can be ensured that the voltage divider device does not exceed the withstand voltage and is in the normal working area, thereby ensuring the accuracy and stability of the reference voltage.

[0052] like Figure 2 As shown, in some embodiments, the voltage divider circuit 12 further includes a third PMOS transistor P3 and a fourth PMOS transistor P4. The third PMOS transistor P3 is used to mirror the bias current I B , that is, the bias current I B The gate of the third PMOS tube is used to receive the bias current I B , the source is connected to the power supply VCC; the source of the fourth PMOS tube P4 is connected to the drain of the third PMOS tube P3, the drain is connected to the emitter of B1, and the input voltage of the gate is the bias voltage provided by the current bias circuit 12.

[0053] The third PMOS transistor P3 and the fourth PMOS transistor P4 form a common-source and common-gate current mirror, which can ensure that the bipolar transistor B1 can generate a stable voltage and make the entire circuit more robust to changes in temperature and power supply voltage.

[0054] See also Figure 3 In some embodiments, the current bias circuit 11 includes a first current mirror 110, a second current mirror 120 and a second resistor R2, and these three parts constitute the core part of the bias circuit that is independent of the power supply voltage.

[0055] The first current mirror 110 includes a fifth PMOS transistor P5 and a sixth PMOS transistor P6, whose gates are connected to each other and whose sources are connected to a power supply. The channel length L and width W of these two transistors are the same. The gate and drain of the sixth PMOS transistor P6 are connected to form a short-circuited PMOS transistor, which serves as a reference branch of the first current mirror 110. Since the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6, the drain current will be equal to the current of the reference branch, which is a mirror branch of the first current mirror.

[0056] The second current mirror 120 includes a third NMOS transistor N3 and a fourth NMOS transistor N4 whose gates are connected to each other. The channel length L and width W of the two transistors are the same. The second current mirror 120 is cascade-connected to the first current mirror 110, that is, the drain of the third NMOS transistor N3 receives the current of the mirror branch, and the drain of the fourth NMOS transistor N4 receives the current of the reference branch. The gate and drain of the third NMOS transistor N3 are connected to form the reference branch of the second current mirror 120, and the fourth NMOS transistor N4 is grounded via the second resistor R2.

[0057] The current bias circuit provides a stable reference current through the reference branches of the first current mirror 110 and the second current mirror 120. The reference current is copied to the output transistor through the characteristics of the current mirror and forms a bias current I through the resistor. B Output. Among them, the third NMOS tube N3 and the fourth NMOS tube N4 work in the subthreshold region, and the bias circuit formula generated at the source and drain ends of the fourth NMOS tube N4 is as follows:

[0058] I B =(VGS N3 -VGS N4 ) / R2 (1)

[0059] Among them, VGS N3 is the gate-source voltage of the third NMOS tube N3, VGS N4 is the gate-source voltage of the fourth NMOS tube N4.

[0060] Due to the design of the current mirror, the current bias circuit can provide a stable bias current and is insensitive to variations in process, temperature, and supply voltage. Figure 3 The current bias circuit 11 further includes a fifth NMOS transistor N5 and a seventh PMOS transistor P7. The fifth NMOS transistor N5 is used to mirror the current output by the second current mirror 120. The source of the fifth NMOS transistor N5 is grounded, and the drain is connected to the power supply via the seventh PMOS transistor P7 connected in a diode manner. The gate of the seventh PMOS transistor P7 outputs a bias voltage.

[0061] In some embodiments, the current bias circuit 11 further includes a negative feedback loop.

[0062] Still see Figure 3 The first current mirror 110 further includes an eighth PMOS transistor P8 for replicating the current of the sixth PMOS transistor P6, and the second current mirror 120 further includes a sixth NMOS transistor P6 for replicating the current of the third NMOS transistor N3.

[0063] The current bias circuit further includes a ninth PMOS tube P9 and a tenth PMOS tube P10, and a seventh NMOS tube N7 and an eighth NMOS tube N8.

[0064] The source of the ninth PMOS tube P9 is connected to the power supply VCC, the drain is connected to the drain of the sixth NMOS tube N6, the gate is connected to the drain of the fifth PMOS tube P5, the gate of the tenth PMOS tube P10 is connected to the drain of the ninth PMOS tube P9, the source is connected to the gate of the ninth PMOS tube P9, and the drain is connected to the drain of the third NMOS tube N3. The ninth PMOS tube P9 and the tenth PMOS tube P10 form a negative feedback loop 130, which clamps the drain-source voltage of the fifth PMOS tube P5 to VGS. P9 In this example, the channel length L and width W of the ninth PMOS transistor P9 are set to be the same as those of the sixth PMOS transistor P6, so VGS P9 Approximately equal to VGS P6 , the drain-source voltages of the fifth PMOS tube P5 and the sixth PMOS tube P6 are similar, making the mirror current more accurate.

[0065] The source of the seventh NMOS tube N7 is grounded, the drain is connected to the drain of the eighth PMOS tube P8, the gate is connected to the drain of the fourth NMOS tube N4, the gate of the eighth NMOS tube N8 is connected to the drain of the seventh NMOS tube N7, the source is connected to the gate of the seventh NMOS tube N7, and the drain is connected to the drain of the sixth PMOS tube P6. The seventh NMOS tube N7 and the eighth NMOS tube N8 form a negative feedback loop 140 to clamp the drain-source voltage of the fourth NMOS tube N4 to VGS. N7 In this example, the channel length L and width W of the seventh NMOS transistor N7 are set to be the same as those of the fourth NMOS transistor N4, and VGS N7 Approximately equal to VGS N4 The drain-source terminals of the third NMOS tube N3 and the fourth NMOS tube N4 are close to each other, making the mirror current more accurate.

[0066] The current bias current proposed in the embodiment of the present disclosure can generate a stable and accurate bias circuit through the setting of a current mirror and a negative feedback loop.

[0067] In some embodiments, the temperature compensation circuit 13 may include multiple threshold difference (△VGS) voltage sub-circuits, wherein each threshold difference voltage sub-circuit has a positive temperature coefficient, and the number of the threshold difference voltage sub-circuits is determined based on the numerical relationship between the negative temperature coefficient of the bipolar transistor and the positive temperature coefficient of each of the threshold difference voltage sub-circuits.

[0068] In one example, the circuit structure of the threshold difference voltage subcircuit is as follows: Figure 4 The threshold difference voltage subcircuit includes an eleventh PMOS tube P11, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a ninth NMOS tube N9, and a tenth NMOS tube N10. The gates of the ninth NMOS tube N9 and the tenth NMOS tube N10 are connected to each other, the source is grounded, and the gate and drain of the ninth NMOS tube N9 are connected; the gate input bias voltage V B , the bias voltage V B For example, it can be provided by the current bias circuit 11. The gate input voltage V 1i The drain is connected to the drain of the ninth NMOS tube N9, and the source is connected to the drain of the eleventh PMOS tube P11; the gate and drain of the thirteenth PMOS tube P13 are connected to output the voltage V 1o , and this end is connected to the drain of the tenth NMOS tube, and the source is connected to the drain of the eleventh PMOS tube P11.

[0069] In this circuit, the ninth NMOS tube N9 and the tenth NMOS tube N10 form a current mirror structure, and the channel length L and width W of the two are the same, and the fi ngers or multipliers may be the same or different; the channel length L and width W of the twelfth PMOS tube P12 and the thirteenth PMOS tube P13 are the same, but the fi ngers or multipliers of the thirteenth PMOS tube P3 are usually set to be several times that of the twelfth PMOS tube P12.

[0070] The voltage output by the thirteenth PMOS tube P3 can be calculated by the following formula:

[0071] V o1 =V oi +(VGS P13 -VGS P12 ) (2)

[0072] Among them, V oi is the input voltage of the threshold difference voltage subcircuit, VGS P13 is the gate-source voltage of the thirteenth PMOS tube P13, VGS P12 is the gate-source voltage of the twelfth PMOS tube P12.

[0073] The n threshold difference voltage subcircuits are cascaded, and the final output voltage is:

[0074] V o =V i +n*(VGS P13 -VGS P12 ) (3)

[0075] Among them, V i is the input voltage of the first threshold difference voltage sub-circuit (ie, temperature compensation circuit) of the cascade, and n is the number of the threshold difference voltage sub-circuits of the cascade.

[0076] In the embodiment of the present disclosure, when V be In the case of three-voltage division, the output voltage of the voltage divider circuit, that is, the input voltage of the temperature compensation circuit is:

[0077] V i =V be / 3 (4)

[0078] Among them, V be is the gate voltage of bipolar transistor B1.

[0079] The output voltage is:

[0080] V o =V be / 3+n*(VGS P13 -VGS P12 ) (5)

[0081] Since V be The twelfth PMOS tube P12 and the thirteenth PMOS tube P13 work in the subthreshold region, VGS P13 -VGS P12 It has a positive temperature coefficient. Taking a suitable value of n can make the negative temperature coefficient offset the positive temperature coefficient, so that a reference voltage V that is independent of temperature changes can be obtained. o .

[0082] Those skilled in the art should understand that the temperature compensation circuit may also use other circuits that can be realized with V be The circuit structure having a positive temperature system in which the negative temperature coefficient is offset is not limited to the structure shown above.

[0083] In some embodiments, the reference voltage generating circuit also includes a startup circuit for providing an initial current or voltage condition for the current bias circuit to help the components in the current bias circuit quickly reach a stable state, while the current bias circuit provides a stable bias condition, so that the reference voltage generating circuit can maintain stable performance after startup.

[0084] like Figure 5 As shown, in one example, the startup circuit includes an eleventh NMOS tube N11, a twelfth NMOS tube N12, a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a seventeenth PMOS tube P17 and an inverter I NV.

[0085] The gates of the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12 are connected to each other, the sources are grounded, and the gate and drain of the twelfth NMOS transistor N12 are connected, that is, the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12 form a current mirror structure.

[0086] The fourteenth PMOS transistor P14 is connected between the power supply VCC and the eleventh NMOS transistor N11 in a diode manner, the fifteenth PMOS transistor P15 is connected between the power supply VCC and the twelfth NMOS transistor N12, and the gate of the fifteenth PMOS transistor P15 can be connected to the gate of the fifth PMOS transistor P5 in the current bias circuit.

[0087] The gate of the fourteenth PMOS transistor P14 is connected to the gates of the sixteenth PMOS transistor P16 and the seventeenth PMOS transistor P17 via the inverter I NV. The sources of the sixteenth PMOS transistor P16 and the seventeenth PMOS transistor P17 are connected to the power supply VCC. The drains provide the first initial current and the second initial current respectively.

[0088] When the bias current does not establish a stable working state, the gate voltages of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are at a high level close to the power supply voltage, that is, the gate voltage of the fifteenth PMOS transistor P15 is also at a high level close to the power supply voltage. The fifteenth PMOS transistor P15 is in a cut-off state, and no current flows through it, that is, no current flows through the twelfth NMOS transistor N12, the gate voltage of the twelfth NMOS transistor N12 is close to the ground level, and the twelfth NMOS transistor N12 and the eleventh NMOS transistor N11 are both in a cut-off state. If no current flows through the eleventh NMOS tube N11 and the fourteenth PMOS tube P14, the gate of the fourteenth PMOS tube P14 is at a high level close to the power supply voltage, and after passing through the inverter I NV, the inverter output is at a low level, that is, the gate voltages of the sixteenth PMOS tube P16 and the seventeenth PMOS tube P17 are at a low level, the sixteenth PMOS tube P16 and the seventeenth PMOS tube P17 are in a conducting state, and a pull-up current is generated, and the gates of the third NMOS tube N3 and the eighth NMOS tube N8 of the bias circuit are pulled high respectively, then the sixth PMOS tube P6, the eighth NMOS tube N8, and the fourth NMOS tube N4 form a current path, and the current bias circuit leaves the steady state of zero current and enters the steady state after the activation current.

[0089] When the current bias circuit is started, the fifth PMOS tube P5 and the sixth PMOS tube P6 enter the saturation region, and the gate establishes a normal working voltage, that is, the gate voltage of the fifteenth PMOS tube P15 is established, and the fifteenth PMOS tube P15 is in a conducting state, generating a pull-up current flowing through the twelfth NMOS tube N12, mirrored to the eleventh NMOS tube N11 to generate a pull-down current. The gate of the fourteenth PMOS tube P14 is pulled down to a low level, and a high level is output through the inverter, and the sixteenth PMOS tube P16 and the seventeenth PMOS tube P17 are in a cut-off state, and the pull-up current is turned off, which no longer affects the normal working current bias circuit.

[0090] Figure 6 A schematic diagram of another reference voltage generating circuit provided by at least one embodiment of the present disclosure. Figure 6 As shown, the reference voltage generating circuit includes a start-up circuit 14, a current bias circuit 11, a voltage divider circuit 12 and a temperature compensation circuit 14. The specific structures of the above circuits can be referred to the above embodiments, and will not be described again.

[0091] like Figure 6 The reference voltage generation circuit shown supports ultra-low power supply operation and can withstand high power supply voltage. Therefore, it can be applied to systems with a large power supply voltage range and a long standby time, and can also be applied to products that support different types of power supply voltages.

[0092] In this specification, the same and similar parts between the various embodiments refer to each other, and each embodiment focuses on the differences from other embodiments.

[0093] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0094] Although this specification includes many specific implementation details, these should not be interpreted as limiting the scope of any invention or the scope of protection claimed, but are mainly used to describe the features of the specific embodiments of specific inventions. Certain features described in multiple embodiments in this specification may also be implemented in combination in a single embodiment. On the other hand, the various features described in a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may work in certain combinations as described above and even initially claim protection, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may point to a sub-combination or a variation of a sub-combination.

[0095] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that these operations be performed in the particular order shown or performed sequentially, or requiring that all illustrated operations be performed to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various circuit modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and circuits can generally be integrated together in a single hardware product, or packaged into multiple hardware products.

[0096] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the particular order or sequential order shown to achieve the desired results. In some implementations, multitasking and parallel processing may be advantageous.

[0097] The above description is merely a preferred embodiment of one or more embodiments of the present specification and is not intended to limit one or more embodiments of the present specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present specification shall be included in the scope of protection of one or more embodiments of the present specification.

Claims

1. A reference voltage generating circuit, characterized in that: The circuit includes a current bias circuit, a voltage divider circuit and a temperature compensation circuit; The current bias circuit is used to generate a bias current; The voltage divider circuit comprises: A bipolar transistor, wherein the bias current is input into the bipolar transistor and generates a negative temperature coefficient voltage; At least two first NMOS tubes are cascade-connected between the emitter of the bipolar transistor and the ground, wherein the gate of the first first NMOS tube in the cascade is connected to the emitter, and the drain of the last first NMOS tube outputs a first voltage; a first PMOS transistor, wherein a gate of the first PMOS transistor is connected to an emitter of the bipolar transistor, and a source of the first PMOS transistor is connected to a power source via a first resistor; a second PMOS tube connected between the drain of the first NMOS tube and a power supply, a gate of the second PMOS tube connected to the source of the first PMOS tube, wherein the second PMOS tube is a native device; The temperature compensation circuit is used to perform temperature compensation on the first voltage and output a zero temperature coefficient reference voltage.

2. The circuit according to claim 1, characterized in that The voltage divider circuit also includes a third PMOS tube and a fourth PMOS tube, wherein the third PMOS tube is used to mirror the bias current, the source of the fourth PMOS tube is connected to the drain of the third PMOS tube, the drain is connected to the emitter of the bipolar transistor, and the input voltage of the gate is the bias voltage provided by the current bias circuit.

3. The circuit according to claim 1, characterized in that The voltage divider circuit further includes a second NMOS tube connected in a diode manner, and the drain of the first PMOS tube is grounded via the second NMOS tube.

4. The circuit according to claim 1, characterized in that The current bias circuit includes a first current mirror, a second current mirror and a second resistor. The first current mirror includes a fifth PMOS tube and a sixth PMOS tube whose gates are connected to each other and whose sources are connected to a power supply, and the gate of the sixth PMOS tube is connected to the drain. The second current mirror is cascade-connected to the first current mirror. The second current mirror includes a third NMOS tube and a fourth NMOS tube whose gates are connected to each other, the gate of the third NMOS tube is connected to the drain, and the fourth NMOS tube is grounded via a second resistor.

5. The circuit according to claim 4, characterized in that The current bias circuit also includes a fifth NMOS tube and a seventh PMOS tube; The fifth NMOS tube is used to mirror the current output by the second current mirror. The source of the fifth NMOS tube is grounded, and the drain is connected to the power supply via the seventh PMOS tube connected in a diode manner. The gate of the seventh PMOS tube outputs a bias voltage.

6. The circuit according to claim 5, characterized in that It also includes an eighth PMOS tube, a ninth PMOS tube, and a tenth PMOS tube for replicating the current of the sixth PMOS tube, and a sixth NMOS tube, a seventh NMOS tube, and an eighth NMOS tube for replicating the current of the third NMOS tube; Wherein, the source of the ninth PMOS tube is connected to the power supply, the drain is connected to the drain of the sixth NMOS tube, the gate is connected to the drain of the fifth PMOS tube, the gate of the tenth PMOS tube is connected to the drain of the ninth PMOS tube, the source is connected to the gate of the ninth PMOS tube, and the drain is connected to the drain of the third NMOS tube; The source of the seventh NMOS tube is grounded, the drain is connected to the drain of the eighth PMOS tube, the gate is connected to the drain of the fourth NMOS tube, the gate of the eighth NMOS tube is connected to the drain of the seventh NMOS tube, the source is connected to the gate of the seventh NMOS tube, and the drain is connected to the drain of the sixth PMOS tube.

7. The circuit according to claim 1, characterized in that The temperature compensation circuit includes a plurality of threshold difference voltage subcircuits, wherein each threshold difference voltage subcircuit has a positive temperature coefficient, and the number of the threshold difference voltage subcircuits is determined according to the numerical relationship between the negative temperature coefficient of the bipolar transistor and the positive temperature coefficient of each of the threshold difference voltage subcircuits.

8. The circuit according to claim 1, characterized in that It also includes a startup circuit, which includes an eleventh NMOS tube, a twelfth NMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube and an inverter; Wherein, the gates of the eleventh NMOS tube and the twelfth NMOS tube are connected to each other, the sources are grounded, and the gate and drain of the twelfth NMOS tube are connected; The fourteenth PMOS tube is connected between the power supply and the eleventh NMOS tube in a diode manner, and the fifteenth PMOS tube is connected between the power supply and the twelfth NMOS tube; The gate of the fourteenth PMOS tube is connected to the gates of the sixteenth PMOS tube and the seventeenth PMOS tube via the inverter, the sources of the sixteenth PMOS tube and the seventeenth PMOS tube are connected to a power supply, and the drains are respectively used to provide a first initial current and a second initial current.

9. The circuit according to claim 1, characterized in that The number of the first NMOS tubes is two or three.

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