Clock frequency division processing device

Abstract

The invention relates to the technical field of clock frequency division, in particular to a clock frequency division processing device. The device comprises a decimal frequency division module and an integer frequency division module, the input of the decimal frequency division module comprises an original clock and a decimal frequency division coefficient, and the output of the decimal frequency division module is a clock subjected to decimal frequency division processing; the input of the integer frequency division module comprises a clock subjected to fractional frequency division processing and an integer frequency division coefficient, and the output of the integer frequency division module is a target clock; the fractional frequency division coefficient and the integer frequency division coefficient are obtained according to the frequency of the original clock and the frequency of the target clock, the integer frequency division coefficient r1 is obtained according to the frequency of the original clock and the frequency of the target clock, r1 = round down (f0 / f1), f0 is the frequency of the original clock, and f1 is the frequency of the target clock; and obtaining a fractional frequency division coefficient r2 according to the frequency of the original clock, the frequency of the target clock and the integer frequency division coefficient, wherein r2 = f1 / f0 * r1. According to the invention, clock frequency division is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of clock frequency division, and in particular to a clock frequency division processing device. Background Art

[0002] Different images have different resolutions. The resolution of an image refers to the number of pixels in the image, usually expressed in pixels of width and height, such as 1920×1080. If you use a lower clock frequency to try to display a higher resolution image, you will not be able to complete the transmission of a frame within the specified time, resulting in incomplete image display or tearing. On the contrary, if you use a clock frequency that is too high to display a lower resolution image, although it will not affect the display of the image, it may cause unnecessary power consumption. In order to ensure the correct and timely transmission and display of image data, images of different resolutions should match different clock frequencies. How to achieve clock division is an urgent problem to be solved. Summary of the invention

[0003] The object of the present invention is to provide a clock frequency division processing device to realize clock frequency division.

[0004] According to the present invention, a clock frequency division processing device is provided, the clock frequency division processing device comprises a fractional frequency division module and an integer frequency division module, the input of the fractional frequency division module comprises an original clock and a fractional frequency division coefficient, the fractional frequency division module is used to perform fractional frequency division processing on the original clock according to the fractional frequency division coefficient, and the output of the fractional frequency division module is a clock after the fractional frequency division processing; the input of the integer frequency division module comprises a clock after the fractional frequency division processing and an integer frequency division coefficient, the integer frequency division module is used to perform integer frequency division processing on the clock after the fractional frequency division processing, and the output of the integer frequency division module is a target clock; the process of obtaining the fractional frequency division coefficient and the integer frequency division coefficient comprises: S100, obtaining the frequency of the original clock.

[0005] S200, obtaining the frequency of a target clock.

[0006] S300, obtaining an integer frequency division coefficient r1 according to the frequency of the original clock and the frequency of the target clock, r1=rounddown(f0 / f1), rounddown( ) is rounding down, f0 is the frequency of the original clock, and f1 is the frequency of the target clock.

[0007] S400, obtaining a fractional frequency division coefficient r2 according to the frequency of the original clock, the frequency of the target clock and the integer frequency division coefficient, where r2=f1 / f0×r1.

[0008] Compared with the prior art, the present invention has at least the following beneficial effects: The present invention provides a clock frequency division processing device, which includes a fractional frequency division module and an integer frequency division module, wherein the fractional frequency division module is used to implement fractional frequency division processing of the original clock according to the fractional frequency division coefficient, and the integer frequency division module is used to implement integer frequency division processing of the clock after the fractional frequency division processing according to the integer frequency division coefficient, and the clock obtained after the integer frequency division processing is the target clock, which is also the desired clock. The fractional frequency division coefficient and the integer frequency division coefficient of the present invention are obtained according to the frequency of the original clock and the frequency of the target clock, and the target clock can be obtained based on the fractional frequency division coefficient and the integer frequency division coefficient of the present invention; the clock frequency division device of the present invention has higher efficiency in obtaining the target clock and higher accuracy of the obtained target clock, and can be used to meet the display requirements of images with different resolutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 A flowchart of a process for obtaining fractional frequency division coefficients and integer frequency division coefficients provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0012] According to this embodiment, a clock division processing device is provided, which includes a fractional division module and an integer division module. The input of the fractional division module includes an original clock and a fractional division coefficient. The fractional division module is used to perform fractional division processing on the original clock according to the fractional division coefficient, and the output of the fractional division module is a clock after the fractional division processing; the input of the integer division module includes the clock after the fractional division processing and the integer division coefficient. The integer division module is used to perform integer division processing on the clock after the fractional division processing, and the output of the integer division module is a target clock.

[0013] like Figure 1 As shown, the process of obtaining the fractional frequency division coefficient and the integer frequency division coefficient includes: S100, obtaining the frequency of the original clock.

[0014] As a specific implementation, the original clock is a basic clock of the system.

[0015] S200, obtaining the frequency of a target clock.

[0016] As an optional specific implementation, the frequency of the target clock is obtained according to the resolution of the target image or the sampling rate of the audio coding in the usage mode. Those skilled in the art know that any method of obtaining the corresponding clock frequency according to the resolution of the image or the sampling rate of the audio coding in the prior art falls within the protection scope of the present invention.

[0017] As an optional specific implementation, the frequency of the target clock is a frequency given by a user in a test mode.

[0018] In this embodiment, the original clock is to be divided, the original clock is known, and the frequency of the original clock and the frequency of the target clock are known. This embodiment can divide the original clock according to the frequency of the original clock and the frequency of the target clock to obtain the target clock.

[0019] S300, obtaining an integer frequency division coefficient r1 according to the frequency of the original clock and the frequency of the target clock, r1=rounddown(f0 / f1), rounddown( ) is rounding down, f0 is the frequency of the original clock, and f1 is the frequency of the target clock.

[0020] S400, obtaining a fractional frequency division coefficient r2 according to the frequency of the original clock, the frequency of the target clock and the integer frequency division coefficient, where r2=f1 / f0×r1.

[0021] As a preferred specific implementation, the decimal frequency division coefficient is in decimal form. When the decimal frequency division coefficient in binary form is stored and subsequently calculated, the number of bits of binary storage is set to qua, and qua satisfies: when the decimal frequency division coefficient stored in binary form with qua bits is converted into decimal form, the difference between the decimal result obtained after conversion and r2 is less than or equal to the preset difference threshold.

[0022] As a specific implementation, the fractional frequency division module includes a first switch, a counting module, a judgment module and a second switch, the first switch is used to control the fractional frequency division module to be turned on or off, the input of the first switch includes an original clock and a control signal, and the control signal is used to control the first switch to be turned on or off; the output of the first switch is the input of the counting module, and the input of the counting module also includes a fractional frequency division coefficient, and the counting module is used to obtain a first counting value according to the original clock and the fractional frequency division coefficient when the first switch is in an on state; the input of the judgment module is the first counting value, and the judgment module is used to judge whether the first counting value is greater than or equal to 1. If the first counting value is greater than or equal to 1, the output value of the judgment module is 1; if the first counting value is less than 1, the output value of the judgment module is 0; the input of the second switch includes the output of the first switch and the output of the judgment module. If the output value of the judgment module is 1, the output of the second switch is the output of the first switch; if the output value of the judgment module is 0, the output of the second switch is a low level.

[0023] As a specific implementation, if the system enters the low power consumption mode, the control signal is a signal that turns the first switch off; if the system is in the normal mode, the control signal is a signal that turns the first switch on.

[0024] As a specific implementation, the fractional frequency division module further includes a fractional frequency division coefficient selection module, the input of which includes a mode selection signal, a fractional frequency division coefficient of a test mode, and a fractional frequency division coefficient of a use mode, and the fractional frequency division coefficient selection module is used to select the fractional frequency division coefficient of the test mode or the fractional frequency division coefficient of the use mode as the fractional frequency division coefficient output to the counting module according to the mode selection signal. Thus, the clock frequency division processing device of this embodiment supports frequency division in two modes.

[0025] As a specific implementation mode, in the use mode, if the fractional frequency division coefficient in decimal form is the maximum value when it is binary (that is, each binary bit is 1), the original clock is directly used as the output of the second switch, that is, as the clock after the fractional frequency division processing; if the fractional frequency division coefficient in decimal form is not the maximum value when it is binary, the counting module and the judgment module are used to obtain the clock after the fractional frequency division processing. In this way, the integer frequency division module can be verified separately and quickly.

[0026] As a specific implementation, the acquiring the first count value according to the original clock and the fractional frequency division coefficient when the first switch is in the open state includes: S1, obtain the first count value c corresponding to the i-th cycle of the original clock i ;ci =i×r2-∑ i-1 j=1 c j , c j is the output value of the judgment module corresponding to the jth cycle of the original clock, the value range of j is 1 to i-1, i≥2; c1=0.

[0027] In this embodiment, the integer frequency division module is used to perform integer frequency division processing on the clock after the fractional frequency division processing; as a preferred specific implementation method, the integer frequency division module is used to implement the following steps: S10, if r1=1, then enter S11; if r1≠1, then enter S12.

[0028] S11, determining the clock after the fractional frequency division process as the target clock.

[0029] S12, if r1 is an even number, enter S13; if r1 is an odd number, enter S14.

[0030] S13, performing a first process on the clock processed by the fractional frequency division according to the rising edge of the clock processed by the fractional frequency division to obtain a target clock.

[0031] In this embodiment, the first process includes: starting from when the cumulative number of rising edges of the clock after the fractional frequency division process is 1, a level flip is performed every time the cumulative number of rising edges of the clock after the fractional frequency division process increases by r1 / 2.

[0032] Thus, the target clock maintains a high level after the first rising edge of the clock after fractional frequency division processing until the r1 / 2+1th rising edge of the clock after fractional frequency division processing arrives; and maintains a low level after the r1 / 2+1th rising edge of the clock after fractional frequency division processing until the r1+1th rising edge of the clock after fractional frequency division processing arrives; and maintains a high level after the r1+1th rising edge of the clock after fractional frequency division processing until the r1 / 2+r1+1th rising edge of the clock after fractional frequency division processing arrives; and so on.

[0033] S14, performing a second process on the clock after the fractional frequency division process according to the rising edge and the falling edge of the clock after the fractional frequency division process to obtain a target clock.

[0034] In this embodiment, the second process includes: S141, performing a third processing on the clock after the fractional frequency division processing according to the cumulative number of rising edges of the clock after the fractional frequency division processing to obtain a first sub-clock; the third processing includes: starting from the cumulative number of rising edges of the clock after the fractional frequency division processing being 1, performing a level flip when the cumulative number of rising edges of the clock after the fractional frequency division processing increases by (r1-1) / 2, performing a level flip when the cumulative number of rising edges of the clock after the fractional frequency division processing increases by (r1+1) / 2, performing a level flip when the cumulative number of rising edges of the clock after the fractional frequency division processing increases by (r1-1) / 2, performing a level flip when the cumulative number of rising edges of the clock after the fractional frequency division processing increases by (r1+1) / 2, performing a level flip when the cumulative number of rising edges of the clock after the fractional frequency division processing increases by (r1-1) / 2, performing a level flip when the cumulative number of rising edges of the clock after the fractional frequency division processing increases by (r1+1) / 2, and performing the level flip in a cycle.

[0035] Thus, the first sub-clock maintains a high level after the first rising edge of the clock after the fractional frequency division processing until the (r1-1) / 2+1th rising edge of the clock after the fractional frequency division processing arrives; and maintains a low level after the (r1-1) / 2+1th rising edge of the clock after the fractional frequency division processing until the r1+1th rising edge of the clock after the fractional frequency division processing arrives; and maintains a high level after the r1+1th rising edge of the clock after the fractional frequency division processing until the (r1-1) / 2+r1+1th rising edge of the clock after the fractional frequency division processing arrives; and maintains a low level after the (r1-1) / 2+r1+1th rising edge of the clock after the fractional frequency division processing until the 2×r1+1th rising edge of the clock after the fractional frequency division processing arrives; and so on.

[0036] S142, obtaining a second sub-clock according to the falling edge of the clock after fractional division processing and the first sub-clock; the second sub-clock satisfies the following conditions: if the first moment of the first sub-clock is a low level, the second moment of the second sub-clock is a low level; if the first moment of the first sub-clock is a high level, the second moment of the second sub-clock is a high level; the first moment is a moment that is separated from the second moment by a target time length and is earlier than the first moment, and the target time length is the time interval between the first falling edge and the first rising edge after the first rising edge of the clock after fractional division processing.

[0037] In this embodiment, the second sub-clock starts to maintain a high level from the first falling edge after the first rising edge of the clock after the fractional division processing, and the level at a certain moment thereafter (i.e., the second moment) is consistent with the level of the first sub-clock at the first moment, that is, when the level of the first sub-clock at the first moment is high, the level of the second sub-clock at the second moment is also high; when the level of the first sub-clock at the first moment is low, the level of the second sub-clock at the second moment is also low.

[0038] S143, superimposing the first sub-clock and the second sub-clock; the superimposing includes: if the first sub-clock and the second sub-clock are both low levels at the target moment, outputting the level at the target moment as a low level; otherwise, outputting the level at the target moment as a high level.

[0039] In this embodiment, the first sub-clock and the second sub-clock are superimposed to obtain a target clock; the level of the target clock at a certain moment (i.e., the target moment) is related to the level of the first sub-clock at the target moment and the level of the second sub-clock at the target moment. If the level of the first sub-clock at the target moment and the level of the second sub-clock at the target moment are both low levels, the level of the target clock at the target moment is a low level; otherwise, the level of the target clock at the target moment is a high level.

[0040] The present embodiment provides a clock frequency division processing device, which includes a fractional frequency division module and an integer frequency division module, wherein the fractional frequency division module is used to implement fractional frequency division processing of the original clock according to the fractional frequency division coefficient, and the integer frequency division module is used to implement integer frequency division processing of the clock after fractional frequency division processing according to the integer frequency division coefficient, and the clock obtained after the integer frequency division processing is the target clock, which is also the desired clock. The fractional frequency division coefficient and the integer frequency division coefficient of the present embodiment are obtained according to the frequency of the original clock and the frequency of the target clock, and the target clock can be obtained based on the fractional frequency division coefficient and the integer frequency division coefficient of the present embodiment; the clock frequency division device of the present embodiment has a higher efficiency in obtaining the target clock and a higher accuracy of the obtained target clock, which can be used to meet the display requirements of images with different resolutions.

[0041] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A clock frequency division processing device, characterized in that: The clock frequency division processing device includes a fractional frequency division module and an integer frequency division module, the input of the fractional frequency division module includes an original clock and a fractional frequency division coefficient, the fractional frequency division module is used to perform fractional frequency division processing on the original clock according to the fractional frequency division coefficient, and the output of the fractional frequency division module is a clock after the fractional frequency division processing; the input of the integer frequency division module includes a clock after the fractional frequency division processing and an integer frequency division coefficient, the integer frequency division module is used to perform integer frequency division processing on the clock after the fractional frequency division processing, and the output of the integer frequency division module is a target clock; The process of obtaining the fractional frequency division coefficient and the integer frequency division coefficient includes: S100, obtaining the frequency of the original clock; S200, obtaining the frequency of the target clock; S300, obtaining an integer frequency division coefficient r1 according to the frequency of the original clock and the frequency of the target clock, r1=rounddown(f0 / f1), rounddown( ) is rounded down, f0 is the frequency of the original clock, and f1 is the frequency of the target clock; S400, obtaining a fractional frequency division coefficient r2 according to the frequency of the original clock, the frequency of the target clock and the integer frequency division coefficient, where r2=f1 / f0×r1.

2. The clock frequency division processing device according to claim 1, characterized in that: The fractional frequency division module includes a first switch, a counting module, a judging module, and a second switch. The first switch is used to control the opening or closing of the fractional frequency division module. The input of the first switch includes an original clock and a control signal. The control signal is used to control the opening or closing of the first switch. The output of the first switch is the input of the counting module. The input of the counting module also includes a fractional frequency division coefficient. The counting module is used to obtain a first counting value according to the original clock and the fractional frequency division coefficient when the first switch is in an open state. The input of the judging module is the first counting value. The judging module is used to judge whether the first counting value is greater than or equal to 1. If the first counting value is greater than or equal to 1, the output value of the judging module is 1; if the first counting value is less than 1, the output value of the judging module is 0. The input of the second switch includes the output of the first switch and the output of the judging module. If the output value of the judging module is 1, the output of the second switch is the output of the first switch. If the output value of the judgment module is 0, the output of the second switch is a low level.

3. The clock frequency division processing device according to claim 2, characterized in that: The step of obtaining a first count value according to the original clock and the fractional frequency division coefficient when the first switch is in the on state comprises: S1, obtain the first count value c corresponding to the i-th cycle of the original clock i ;c i =i×r2-∑ i-1 j=1 c j , c j is the output value of the judgment module corresponding to the jth cycle of the original clock, the value range of j is 1 to i-1, i≥2; c1=0.

4. The clock frequency division processing device according to claim 1, characterized in that: The integer frequency division module is used to implement the following steps: S10, if r1=1, then enter S11; if r1≠1, then enter S12; S11, determining the clock after the fractional frequency division process as the target clock; S12, if r1 is an even number, then go to S13; if r1 is an odd number, then go to S14; S13, performing a first process on the clock after the fractional frequency division process according to the rising edge of the clock after the fractional frequency division process to obtain a target clock; S14, performing a second process on the clock after the fractional frequency division process according to the rising edge and the falling edge of the clock after the fractional frequency division process to obtain a target clock.

5. The clock frequency division processing device according to claim 4, characterized in that: The first processing includes: starting from the cumulative number of rising edges of the clock after the fractional frequency division processing being 1, a level flip is performed every time the cumulative number of rising edges of the clock after the fractional frequency division processing increases by r1 / 2.

6. The clock frequency division processing device according to claim 4, characterized in that: The second process comprises: S141, performing a third process on the clock processed by the fractional frequency division according to the cumulative number of rising edges of the clock processed by the fractional frequency division to obtain a first sub-clock; the third process comprises: starting from when the cumulative number of rising edges of the clock processed by the fractional frequency division is 1, performing a level flip when the cumulative number of rising edges of the clock processed by the fractional frequency division increases by (r1-1) / 2, performing a level flip when the cumulative number of rising edges of the clock processed by the fractional frequency division increases by (r1+1) / 2, performing a level flip when the cumulative number of rising edges of the clock processed by the fractional frequency division increases by (r1-1) / 2, performing a level flip when the cumulative number of rising edges of the clock processed by the fractional frequency division increases by (r1+1) / 2, performing a level flip when the cumulative number of rising edges of the clock processed by the fractional frequency division increases by (r1-1) / 2, performing a level flip when the cumulative number of rising edges of the clock processed by the fractional frequency division increases by (r1+1) / 2, and performing the level flip in a cycle; S142, obtaining a second sub-clock according to the falling edge of the clock processed by fractional frequency division and the first sub-clock; the second sub-clock satisfies the following conditions: if the first moment of the first sub-clock is a low level, the second moment of the second sub-clock is a low level; if the first moment of the first sub-clock is a high level, the second moment of the second sub-clock is a high level; the first moment is a moment that is separated from the second moment by a target time length and is earlier than the first moment, and the target time length is the time interval between the first falling edge and the first rising edge after the first rising edge of the clock processed by fractional frequency division; S143, superimposing the first sub-clock and the second sub-clock; the superimposing includes: if the first sub-clock and the second sub-clock are both low levels at the target moment, outputting the level at the target moment as a low level; otherwise, outputting the level at the target moment as a high level.

7. The clock frequency division processing device according to claim 2, characterized in that: The fractional frequency division module also includes a fractional frequency division coefficient selection module, the input of which includes a mode selection signal, a fractional frequency division coefficient of a test mode, and a fractional frequency division coefficient of a usage mode. The fractional frequency division coefficient selection module is used to select the fractional frequency division coefficient of the test mode or the fractional frequency division coefficient of the usage mode as the fractional frequency division coefficient output to the counting module according to the mode selection signal.

8. The clock frequency division processing device according to claim 1, characterized in that: The frequency of the target clock is obtained according to the resolution of the target image or the sampling rate of the audio encoding.

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