Electronic equipment and heat dissipation system

Abstract

The invention provides electronic equipment and a heat dissipation system, the electronic equipment comprises a plurality of machine frames, each machine frame comprises a first processor, a first mainboard and a connector, the first mainboard in any machine frame is connected with the first processor and the connector in the same machine frame, and the first processor is connected with the first mainboard in any machine frame. The connector in the first machine frame is connected with the connector in the at least one second machine frame, so that through the design of no backboard in the electronic equipment, the heat dissipation capability of the electronic equipment is improved, and the high-speed link problem can be solved without an additional chip. And meanwhile, the flexibility, the convenience and the economical efficiency of machine frame superposition expansion in the electronic equipment can be improved.

Description

[0001] This application is a divisional application. The application number of the original application is 202310365954.1, and the original application date is March 30, 2023. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of server technology, and in particular to an electronic device and a heat dissipation system. Background Art

[0003] In the prior art, an electronic device includes multiple central processing units (CPUs), and the multiple CPUs are connected via a backplane, and the multiple CPUs are located in the same frame of the electronic device. In addition, the electronic device may also include multiple types of processors (represented by xPU) such as a graphics processing unit (GPU) and a neural network processor (NPU), and the CPU and the xPU are also connected via a backplane, and the CPU and the xPU are also located in the same frame of the electronic device.

[0004] For example, suppose an electronic device contains 4 CPUs and 8 xPUs. The 4 CPUs and 8 xPUs are located in the same chassis of the electronic device, and the 4 CPUs serve as one computing node and the 8 xPUs serve as another computing node. Although the 4 CPUs and 8 xPUs can be connected through the backplane in the chassis, the design of the backplane will affect the heat dissipation of the electronic device. At the same time, due to the excessive loss of signal integrity (SI), the electronic device needs to add a retimer chip to solve the high-speed link problem. Summary of the invention

[0005] In view of this, the present application provides an electronic device and a heat dissipation system, which can improve the heat dissipation capacity of the electronic device and solve the high-speed link problem without the need for additional chips.

[0006] In a first aspect, the present application provides an electronic device, comprising: a plurality of frames; wherein each frame comprises: a first processor, a first mainboard and a connector; the first mainboard in any frame is respectively connected to the first processor and the connector in the same frame. The connector in the first frame is respectively connected to the connector in the at least one second frame, the first frame is any one of the plurality of frames, and the at least one second frame is another frame in the plurality of frames except the first frame.

[0007] Compared with the prior art, this application improves the heat dissipation capacity of electronic devices through a backplane-free design, and can solve the high-speed link problem without the need for additional chips. At the same time, this solution can also improve the flexibility, convenience and economy of the stacking and expansion of frames in electronic devices, and simplify the device configuration of the frames in electronic devices, making it easier to maintain electronic devices.

[0008] In a possible design, the number of first processors in each frame is the same; or, the number of first processors in each frame is determined according to the first target ratio.

[0009] The present application can be evenly distributed to each frame according to the number of first processors contained in the electronic device, so that the weight of the entire electronic device is balanced; or it can be distributed to each frame according to a first target ratio of the number of first processors contained in the electronic device, to obtain frames with multiple different configurations, thereby improving the space utilization of the frames.

[0010] In a possible design, each frame further includes a pull-up power supply, and the connector in each frame includes a first pin and a second pin; the first pin of the connector in any frame is respectively connected to the first mainboard and the pull-up power supply in the same frame, and the second pin of the connector in any frame is grounded. The second pin of the connector in the first frame is also connected to the first pin of the connector in the at least one second frame.

[0011] The present application sets the connection mode of the first pin and the second pin of the connector in each frame, and then determines the master and slave frames in multiple frames according to the state of the first pin and the state of the second pin of the connector in each frame.

[0012] In one possible design, each frame also includes a baseboard management controller, and the baseboard management controller in any frame is connected to the first mainboard located in the same frame, and the baseboard management controller in the first frame is also connected to the baseboard management controller in the at least one second frame.

[0013] The present application sets a baseboard management controller in a first frame to connect to a baseboard management controller in at least one second frame, so that management information in each frame can be obtained only through the first frame, and the operation is simple.

[0014] In a possible design, each frame also includes: a second processor, a second mainboard; the second mainboard in any frame is respectively connected to the first mainboard, the second processor, and the connector located in the same frame.

[0015] The present application can obtain a variety of different types of electronic devices by having each frame also include a second processor and a second mainboard, and then realize different processing functions through different types of electronic devices.

[0016] In a possible design, the number of second processors in each frame is the same; or, the number of second processors in each frame is determined according to the second target ratio.

[0017] The present application can be evenly distributed to each frame according to the number of second processors contained in the electronic device, so that the weight of the entire electronic device is balanced, or it can be distributed to each frame according to the second target ratio of the number of second processors contained in the electronic device, so as to obtain frames with multiple different configurations, that is, by reasonably allocating the second processors of each frame, the space utilization rate of the frame is improved. At the same time, the design can also improve the flexibility, convenience and economy of the superposition and expansion of frames in electronic devices.

[0018] In a possible design, the connection between the second mainboard in any frame and the first mainboard in the same frame is a cable connection, and the connectors of each frame are connected by cables.

[0019] The present application avoids the backplane connection design in the prior art by connecting the second mainboard in any frame to the first mainboard in the same frame with cables, thereby solving the high-speed link problem without the need for a retimer chip. By setting the connectors of each frame as cable connections, the flexibility of stacking and expanding the frames in the server is achieved. The number of frames in the electronic device can also be determined according to actual needs, thereby improving the space utilization of the frames.

[0020] In one possible design, each frame also includes a pull-up power supply, and the connector in each frame includes a first pin and a second pin; the first pin of the connector in any frame is respectively connected to the first main board, the second main board, and the pull-up power supply located in the same frame, and the second pin of the connector in any frame is grounded; the second pin of the connector in the first frame is also connected to the first pin of the connector in at least one second frame.

[0021] The present application sets the connection mode of the first pin and the second pin of the connector in each frame, and then determines the master and slave frames in multiple frames according to the state of the first pin and the state of the second pin of the connector in each frame.

[0022] In one possible design, each frame also includes a baseboard management controller. The baseboard management controller in any frame is connected to the first main board and the second main board located in the same frame. The baseboard management controller in the first frame is also connected to the baseboard management controller in at least one second frame.

[0023] The present application sets a baseboard management controller in a first frame to connect to a baseboard management controller in at least one second frame, so that management information in each frame can be obtained only through the first frame, and the operation is simple.

[0024] In one possible design, the first processor is a central processing unit, and the second processor is any one of an image processor, a neural network processor, a tensor processor, and a deep learning processor. By setting the first processor and the second processor to different processor types, a variety of electronic device frames can be obtained.

[0025] In one possible design, when the electronic device includes two frames, the first frame and the second frame also include a clock signal buffer and a clock chip, respectively; the clock signal buffer in each frame includes a third interface and a fourth interface, and the clock chip in each frame includes a fifth interface and a sixth interface; and the third interface of the clock signal buffer in any frame is connected to the fifth interface of the clock chip in the same frame, the fourth interface of the clock signal buffer in the first frame is connected to the sixth interface of the clock chip in the second frame, and the fourth interface of the clock signal buffer in the second frame is connected to the sixth interface of the clock chip in the first frame.

[0026] The present application sets a connection mode between the clock chip of the master and slave frames and the clock signal buffer so that the clock chip of the master and slave frames can automatically switch the clock signal, thereby achieving the same clock source of the master and slave frames.

[0027] In a second aspect, the present application provides a heat dissipation system, comprising the first aspect and an electronic device of any design of the first aspect, and each frame in the electronic device also includes a radiator, and the first processor in any frame is connected to the radiator located in the same frame.

[0028] This application improves the heat dissipation capacity of electronic devices in the heat dissipation system through a backplane-free design, and can solve the high-speed link problem without the need for a retimer chip. The design can also determine the number of frames in the electronic device according to actual needs, thereby improving the space utilization of the frames in the heat dissipation system. At the same time, the design can also improve the flexibility, convenience and economy of the stacking and expansion of frames in electronic devices.

[0029] In a third aspect, the present application provides a cooling system, comprising the first aspect and an electronic device of any design of the first aspect, and each frame in the electronic device also includes a radiator, a cold plate, a heat exchanger and a pump, the first processor in any frame is connected to the radiator located in the same frame, and the second processor in any frame is connected to the cold plate located in the same frame; the heat exchanger in any frame is connected to the pump and cold plate located in the same frame.

[0030] This application improves the heat dissipation capacity of electronic equipment in the heat dissipation system through a backplane-free design, and can solve the high-speed link problem without a retimer chip. The design can also determine the number of frames in the electronic equipment according to actual needs, thereby improving the space utilization of the frames in the heat dissipation system. At the same time, the design can also improve the flexibility, convenience and economy of the stacking and expansion of frames in electronic equipment. In addition, through the design of the components in the frame of this application, the occupied area of ​​the heat exchanger in the heat dissipation system can be increased, thereby improving the heat dissipation capacity of the electronic equipment in the heat dissipation system. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the frame structure of a server in the prior art;

[0032] Figure 2 A schematic diagram of the structure of multiple frames of an electronic device provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of the interaction process between the first frame 204 and the BMC 207 in the second frame 301 provided in an embodiment of the present application;

[0034] Figure 4 A schematic diagram of the master and slave frame clocks being of the same source provided in an embodiment of the present application;

[0035] Figure 5 A schematic diagram of the structure of multiple frames of an electronic device provided in an embodiment of the present application;

[0036] Figure 6 A schematic diagram of the structure of a heat dissipation system provided in an embodiment of the present application;

[0037] Figure 7 A schematic diagram of the structure of a heat dissipation system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to enable ordinary persons in the art to better understand the technical solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0040] Take the electronic device as a server as an example. In the prior art, a server includes multiple CPUs, which are connected via a backplane and are located in the same frame of the server. In addition, the server may also include multiple processors (represented by xPU) such as GPU and NPU, where the CPU and xPU are also connected via a backplane and are located in the same frame of the server. Figure 1 As shown, the server includes 4 CPUs, 8 xPUs and multiple power supply units (PSUs), where the height of 4 CPUs is represented by 2U, the height of 8 xPUs is represented by 5U, and the height of multiple PSUs is represented by 1U. The 4 CPUs and 8 xPUs are connected via a backplane. Figure 1 The server also includes multiple fans.

[0041] Continue to follow Figure 1 For example, assuming that the server contains 4 CPUs and 8 xPUs, then the 4 CPUs and 8 xPUs are all located in the same frame of the server, and the 4 CPUs serve as one computing node, and the 8 xPUs serve as another computing node. Although the 4 CPUs and 8 xPUs can be connected through the backplane in the frame, the design of the backplane will affect the heat dissipation of the server. At the same time, due to the excessive loss of SI, the server needs to add a retimer chip to solve the high-speed link problem. In addition, if there are a large number of xPUs in the server and the CPU and xPU are in the same frame of the server, the weight distribution of the server will be uneven, and the drawer plug-in design is required to separate the computing node where the CPU is located and the computing node where the xPU is located for maintenance. In addition, for application scenarios that require 2 CPUs and 4 xPUs, the space and resource utilization of the frame of the server with configuration information of 4 CPUs and 8 xPUs is low.

[0042] In view of this, an embodiment of the present application provides an electronic device and a heat dissipation system. The present application improves the heat dissipation capacity of the electronic device through a backplane-free design, and solves the high-speed link problem without the need for a retimer chip. At the same time, the solution can also improve the flexibility, convenience and economy of the stacking and expansion of frames in electronic devices.

[0043] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0044] like Figure 2 As shown, the electronic device includes: multiple frames, wherein each frame includes: a first processor 201, a first mainboard 202 and a connector 203. The first mainboard 202 in any frame is respectively connected to the first processor 201 and the connector 203 located in the same frame. The connector 203 in the first frame 204 is respectively connected to the connector 203 in at least one second frame. The first frame 204 is any frame in the multiple frames, and the at least one second frame is other frames in the multiple frames except the first frame 204. The number of the first processors 201 in each frame can be determined based on the number of first processors included in the electronic device. Figure 2 Each frame also includes a plurality of fans 205. The connectors 203 of each frame can be connected by cables. Optionally, the number of fans 205 in each frame can be determined according to actual conditions.

[0045] Alternatively, the number of first processors 201 in each frame is the same; or, the number of first processors 201 in each frame is determined according to the first target ratio. It should be noted that the present application does not limit the specific value of the first target ratio.

[0046] Assuming that the electronic device includes 4 CPUs and 8 xPUs, and the electronic device includes two frames, namely the first frame and the second frame, then the first frame and the second frame may include 2 CPUs and 4 xPUs respectively; or, the first frame includes 3 CPUs and 6 xPUs, and the second frame includes 1 CPU and 2 xPUs. When the demand is 2 CPUs and 4 xPUs, the calculation can be performed by the 2 CPUs and 4 xPUs in the first frame, or by the 2 CPUs and 4 xPUs in the second frame, thereby avoiding the simultaneous calculation of the 4 CPUs and 8 xPUs contained in the electronic device, thereby improving the frame space utilization of the electronic device. At the same time, when there is a larger-scale computing demand, the cables of the connectors 203 in multiple frames of the electronic device can be connected, so that the electronic device can be superimposed with different numbers of frames to achieve expansion of processing power.

[0047] In a possible embodiment, Figure 2As shown, each frame also includes a pull-up power supply 206, and the connector 203 in each frame includes a first pin 203-1 and a second pin 203-2. The first pin 203-1 of the connector 203 in any frame is respectively connected to the first mainboard 202 and the pull-up power supply 206 located in the same frame, and the second pin 203-2 of the connector 203 in any frame is grounded. The second pin 203-2 of the connector 203 in the first frame 204 is also connected to the first pin 203-1 of the connector 203 in at least one second frame.

[0048] Since the first pin 203-1 of the connector 203 in each frame is connected to the pull-up power supply 206, the first pin 203-1 of the connector 203 in each frame is in a high level state. Since the second pin 203-2 of the connector 203 in each frame is grounded, the second pin 203-2 of the connector 203 in each frame is in a low level state. Since the second pin 203-2 of the connector 203 in the first frame 204 is respectively connected to the first pin 203-1 of the connector 203 in at least one second frame, the first pin 203-1 of the connector 203 in at least one second frame is adjusted from a high level state to a low level state.

[0049] In a possible embodiment, each chassis further includes a baseboard management controller (BMC) 207. The baseboard management controller 207 in any chassis is connected to the first mainboard 202 in the same chassis. The baseboard management controller 207 in the first chassis 204 is also connected to the baseboard management controller 207 in at least one second chassis. Figure 2 not shown).

[0050] The first mainboard 202 in each frame may include a complex programmable logic device (CPLD), and the CPLD in the first mainboard 202 in any frame is connected to the first processor 201, BMC 207, and connector 203 in the same frame. The CPLD in the first mainboard 202 in any frame can determine the master and slave frames of multiple frames through the state of the first pin 203-1 and the state of the second pin 203-2 of the connector 203 in the same frame, for example Figure 2The first frame 204 is the master frame, and the other frames are all slave frames. The baseboard management controller 207 in the first frame 204 is also connected to the baseboard management controller 207 in at least one second frame, and the information of each frame in at least one second frame can be obtained through the first frame 204, and then the user can perform management operations of the electronic device through the standard command interface IPMI in the first frame 204. Here, the BMC 207 in any frame can automatically complete the software configuration according to the CPLD of the first mainboard 202 in the same frame. It should be known that the configuration of specific software is not limited here.

[0051] For example, Figure 3 As shown, the interaction process of BMC207 in the frame is described by taking the electronic device including the first frame 204 and the second frame 301 as an example. BMC207 in the first frame 204 can interact with the first mainboard 202 through protocols such as peripheral component interconnect express (PCIE) protocol, link protocol converter (LPC), serial peripheral interface (SPI), intelligent platform management bus (IPMB), integrated circuit (I2C) bus, joint test action group (JTAG), etc. Similarly, BMC207 in the second frame 301 can also interact with the first mainboard 202 through protocols such as PCIE, LPC, SPI, IPMB, I2C, and JTAG. Furthermore, the first chassis 204 can also obtain management information in the second chassis 301, such as firmware upgrade, command operation, etc., from MAC0 of BMC207 in the second chassis 301 through MAC0 in BMC207. Here, the user can access the GE_MAC1 interface of BMC207 in the first chassis 204.

[0052] Here, the first processor 201 in each frame can be a CPU. When it is determined that the first frame 204 is a host frame and the other frames are slave frames, the first processor 201 in the first frame 204 can be defined as CPU0, and the first processors 201 in other frames can be defined as CPU1, ..., CPUX, where X is a positive integer greater than or equal to 1. The host frame, i.e., CPU0 in the first frame 204, can start the basic input output system (BIOS) in the frame, and then store data in the memory flash 208. At this time, CPU1, ..., CPUX in the slave frame automatically prohibits starting the BIOS in the corresponding frame.

[0053] like Figure 4 As shown, for the case where the electronic device includes a first frame 204 and a second frame 301, the first frame 204 and the second frame 301 also include a clock signal buffer 209 and a clock chip 2010. The clock signal buffer 209 in each frame includes a third interface 209-1 and a fourth interface 209-2, and the clock chip 2010 in each frame includes a fifth interface 2010-1 and a sixth interface 2010-2. The third interface 209-1 of the clock signal buffer 209 in any frame is connected to the fifth interface 2010-1 of the clock chip 2010 in the same frame, the fourth interface 209-2 of the clock signal buffer 209 in the first frame 204 is connected to the sixth interface 2010-2 of the clock chip 2010 in the second frame 301, and the fourth interface 209-2 of the clock signal buffer 209 in the second frame 301 is connected to the sixth interface 2010-2 of the clock chip 2010 in the first frame 204.

[0054] Each frame also includes a first crystal oscillator 2011 and a second crystal oscillator 2012. The clock chip 2010 in any frame operates normally through the working clock signal sent by the second crystal oscillator 2012 in the same frame. When the first frame 204 performs calculations independently, the first crystal oscillator 2011 in the first frame 204 sends a tracking clock signal IN0 to the clock chip 2010 through the clock signal buffer 209, and the CPLD in the first mainboard 202 sends a signal IN_SEL to the clock chip 2010, and the tracking clock signal IN0 and the signal IN_SEL are processed by the MUX in the clock chip 2010. Here, the present application does not limit the specific processing method of the signal. Similarly, when the second machine frame 301 performs calculations independently, the first crystal oscillator 2011 in the second machine frame 301 sends the tracking clock signal IN0 to the clock chip 2010 through the clock signal buffer 209, and the CPLD in the first mainboard 202 sends the signal IN_SEL to the clock chip 2010, and the tracking clock signal IN0 and the signal IN_SEL are processed by MUX in the clock chip 2010.

[0055] When the first frame 204 is used as the master frame and the second frame 301 is used as the slave frame for calculation, based on the above description that the first frame 204 independently calculates and the second frame 301 independently calculates, the clock signal buffer 209 in the first frame 204 also sends the tracking clock signal IN1 to the clock chip 2010 in the second frame 301, and the tracking clock signal IN0, the tracking clock signal IN1 and the signal IN_SEL are processed by the MUX in the clock chip 2010 of the second frame 301. Similarly, the clock signal buffer 209 in the second frame 301 also sends the tracking clock signal IN1 to the clock chip 2010 in the first frame 204, and the tracking clock signal IN0, the tracking clock signal IN1 and the signal IN_SEL are processed by the MUX in the clock chip 2010 of the first frame 204.

[0056] Here, the first processor 201 and BMC207 in any frame can be set on the first motherboard 202 in the same frame. This is just an example, and the present application does not limit the specific connection method of the first processor 201, BMC207 and the first motherboard 202 in any frame.

[0057] By setting the connection mode between the clock chip of the master and slave frames and the clock signal buffer, the clock chip of the master and slave frames can automatically switch the clock signal, thereby realizing the same clock source of the master and slave frames.

[0058] In a possible embodiment, in the above Figure 2 The electronic equipment shown is based on Figure 5As shown, each frame in the electronic device may further include: a second processor 501 and a second mainboard 502. The second mainboard 502 in any frame is respectively connected to the first mainboard 202, the second processor 501, and the connector 203 in the same frame. The number of second processors 501 in each frame may be determined based on the number of second processors included in the electronic device. The connection between the second mainboard 502 in any frame and the first mainboard 202 in the same frame is a cable connection, and the connectors 203 in each frame are connected by cables.

[0059] Optionally, the number of the second processors 501 in each frame is the same; or, the number of the second processors 501 in each frame is determined according to the second target ratio.

[0060] In a possible embodiment, each frame further includes a pull-up power supply 206, and the connector 203 in each frame includes a first pin 203-1 and a second pin 203-2. The first pin 203-1 of the connector 203 in any frame is respectively connected to the first mainboard 202, the second mainboard 502, and the pull-up power supply 206 located in the same frame, and the second pin 203-2 of the connector 203 in any frame is grounded. The second pin 203-2 of the connector 203 in the first frame 204 is also connected to the first pin 203-1 of the connector 203 in at least one second frame.

[0061] In a possible embodiment, each frame also includes a baseboard management controller 207. The baseboard management controller 207 in any frame is connected to the first main board 202 and the second main board 502 located in the same frame. The baseboard management controller 207 in the first frame 204 is also connected to the baseboard management controller 207 in at least one second frame.

[0062] Here, the second processor 501 can be any one of a graphics processor GPU, a neural network processor NPU, a tensor processor (Tensor Processing Unit, TPU), and a deep learning processing unit (DPU).

[0063] The specific implementation method of this embodiment can be referred to Figure 2 The corresponding description will not be repeated here.

[0064] An embodiment of the present application may also provide a heat dissipation system, comprising an electronic device in any of the above schemes, and each frame in the electronic device further comprises a heat sink. The first processor in any frame is connected to a heat sink located in the same frame; or, the first processor and the second processor in any frame are connected to a heat sink located in the same frame. Here, the number of heat sinks in any frame may be the same as the number of first processors in the same frame; or, the number of heat sinks in any frame may be the same as the total number of first processors and second processors in the same frame.

[0065] like Figure 6 As shown, it is assumed that the electronic device in the heat dissipation system includes two frames, and both frames include 1 CPU, 2 xPUs, multiple PSUs, connectors, a first mainboard, a second mainboard, a radiator, and an IO interface. The CPU and xPU in any frame are connected to the radiator located in the same frame, and the number of radiators is the same as the total number of 1 CPU and 2 xPUs. The CPU in each frame is also connected to the first mainboard, and the 2 xPUs are connected to the second mainboard. The first mainboard and the second mainboard are connected by a cable, and the first mainboard and the second mainboard are also connected to the connector. The two frames are connected by their respective connectors. The heat dissipation system is purely air-cooled by a fan.

[0066] Here, the electronic device may be a server, and each frame may further include a plurality of fans, and the number of fans may be determined according to actual conditions.

[0067] As the power consumption of the second processor xPU becomes higher and higher, if the pure air-cooling heat dissipation system cannot meet the heat dissipation problem of electronic equipment, an air-liquid hybrid heat dissipation system based on liquid assisted air cooling (LAAC) can be used under the conditions of an air-cooled computer room to further improve the heat dissipation capacity of electronic equipment.

[0068] An embodiment of the present application may also provide a heat dissipation system, including an electronic device in any of the above schemes, and each frame in the electronic device also includes a radiator, a cold plate, a heat exchanger (heat exchanger, HEX) and a pump. The first processor in any frame is connected to the radiator located in the same frame, and the second processor in any frame is connected to the cold plate located in the same frame, and the heat exchanger in any frame is connected to the pump and cold plate located in the same frame. Here, the number of radiators in any frame can be the same as the number of first processors in the same frame, and the number of cold plates in any frame can be the same as the number of second processors in the same frame.

[0069] like Figure 7As shown, it is assumed that the electronic device in the cooling system includes two frames, and both frames contain 1 CPU, 2 xPUs, multiple PSUs, connectors, a first mainboard, a second mainboard, a radiator, a cold plate, a heat exchanger, a pump and an IO interface. The CPU in each frame is connected to a radiator, and the number of radiators is the same as the number of 1 CPU. The xPU in each frame is connected to a cold plate, and the number of cold plates is the same as the number of 2 xPUs. The CPU in each frame is also connected to the first mainboard, and the 2 xPUs are connected to the second mainboard. The first mainboard and the second mainboard are connected by a cable, and the first mainboard and the second mainboard are also connected to a connector. The two frames are connected by their respective connectors. The cooling system is cooled by multiple fans and HEX. It should be known that Figure 7 The direction shown in the figure is the direction of heat dissipation after the HEX, pump and cold plate are connected through pipes, which is only an example.

[0070] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An electronic device, characterized in that: include: Multiple chassis; Each of the multiple frames includes a connector; the connector of the first frame in the multiple frames is connected to the connector in at least one second frame in the multiple frames, wherein each frame also includes: a first processor and a first motherboard; the first motherboard in any frame is respectively connected to the first processor and the pins of the connector located in the same frame.

2. The electronic device according to claim 1, wherein: The number of the first processors in each frame is the same; or, the number of the first processors in each frame is determined according to the first target ratio.

3. The electronic device according to claim 1 or 2, characterized in that: Each frame also includes a pull-up power supply, and the connector in each frame includes a first pin and a second pin; the first pin of the connector in any frame is respectively connected to the first mainboard and the pull-up power supply located in the same frame, and the second pin of the connector in any frame is grounded; the second pin of the connector in the first frame is also connected to the first pin of the connector in the at least one second frame.

4. The electronic device according to any one of claims 1 to 3, characterized in that: Each frame also includes a baseboard management controller. The baseboard management controller in any frame is connected to the first mainboard located in the same frame. The baseboard management controller in the first frame is also connected to the baseboard management controller in the at least one second frame.

5. The electronic device according to any one of claims 1 to 4, characterized in that: The first processor is a central processing unit.

6. The electronic device according to claim 1 or 2, characterized in that: Each frame also includes: a second processor and a second mainboard; the second mainboard in any frame is respectively connected to the first mainboard, the second processor and the connector in the same frame.

7. The electronic device according to claim 6, characterized in that: The number of the second processors in each frame is the same; or, the number of the second processors in each frame is determined according to the second target ratio.

8. The electronic device according to claim 6 or 7, characterized in that: The connection between the second mainboard in any frame and the first mainboard in the same frame is a cable connection, and the connectors of each frame are connected by cables.

9. The electronic device according to any one of claims 6 to 8, characterized in that: Each frame also includes a pull-up power supply, and the connector in each frame includes a first pin and a second pin; the first pin of the connector in any frame is respectively connected to the first main board, the second main board, and the pull-up power supply located in the same frame, and the second pin of the connector in any frame is grounded; the second pin of the connector in the first frame is also connected to the first pin of the connector in the at least one second frame.

10. The electronic device according to any one of claims 6 to 9, characterized in that: Each frame also includes a baseboard management controller. The baseboard management controller in any frame is connected to the first mainboard and the second mainboard in the same frame. The baseboard management controller in the first frame is also connected to the baseboard management controller in the at least one second frame.

11. The electronic device according to any one of claims 6 to 10, characterized in that: The second processor is any one of an image processor, a neural network processor, a tensor processor, and a deep learning processor.

12. The electronic device according to any one of claims 1 to 11, characterized in that: When the electronic device includes two frames, the first frame and the second frame also include a clock signal buffer and a clock chip respectively; the clock signal buffer in each frame includes a third interface and a fourth interface, and the clock chip in each frame includes a fifth interface and a sixth interface; and the third interface of the clock signal buffer in any frame is connected to the fifth interface of the clock chip in the same frame, the fourth interface of the clock signal buffer in the first frame is connected to the sixth interface of the clock chip in the second frame, and the fourth interface of the clock signal buffer in the second frame is connected to the sixth interface of the clock chip in the first frame.

13. A heat dissipation system, characterized in that: The electronic device comprises the electronic device as claimed in any one of claims 1 to 12, wherein each frame in the electronic device further comprises a heat sink, and the first processor in any frame is connected to the heat sink located in the same frame.

14. A heat dissipation system, characterized in that: The electronic device comprises an electronic device as described in any one of claims 1 to 12, and each frame in the electronic device further comprises a radiator, a cold plate, a heat exchanger and a pump, the first processor in any frame is connected to the radiator located in the same frame, and the second processor in any frame is connected to the cold plate located in the same frame; the heat exchanger in any frame is connected to the pump and the cold plate located in the same frame.

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