Anti-creeping circuit and method in STR state

Abstract

The invention discloses an anti-creeping circuit and method in an STR state, an SOC module is bidirectionally and electrically connected with a peripheral module, the circuit comprises a master control power supply, an STR trigger module, an STR management module, a power supply management module and a peripheral management module, and the master control power supply is in electric signal connection with the SOC module; the input end of the STR management module is respectively in electric signal connection with the signal output end of the main control power supply and the output end of the STR trigger module, and the output end of the STR management module is respectively in electric signal connection with the control end of the SOC module and the control end of the power supply management module; the control end of the peripheral management module is in electric signal connection with the output end of the SOC module, and the output end of the peripheral management module is in electric signal connection with the control end of the power management module. Various problems caused by electric leakage when the SOC module enters the STR state in the design process can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of anti-leakage design, and more specifically, to an anti-leakage circuit and method in a STR state. Background Art

[0002] As the requirements for fast startup of vehicle systems are getting higher and higher, a new STR state has been added to vehicle equipment. STR-suspend to ram is a special power working mode. In this mode, all CPU CORE / controller / IP CORE will enter a special power mode. At the same time, the SOC internal bus clock is reduced to the lowest operating frequency, most of the PMIC power supply will be turned off, and the external DDR will enter the self-refresh mode. The system can only switch back to the normal power mode through external signals / interrupts AOP (ALWAYS ON PROCESSOR). In the STR state, since the GPIO power supply of the SOC is normally supplied, and the GPIO is connected to the peripherals, if the GPIO is not handled properly when entering the STR state, leakage will occur. Many peripherals share one or more power supplies. Once leakage leaks to the common power supply, leakage will occur between modules. Leakage will cause many faults and are not easy to troubleshoot. Summary of the invention

[0003] One of the purposes of the present invention is to provide an anti-leakage circuit in the STR state to solve the technical problem in the prior art that leakage may occur when the SOC enters the STR state; the second purpose of the present invention is to provide an anti-leakage method in the STR state.

[0004] In order to solve the above technical problems, the technical solution of the present invention is as follows:

[0005] The first aspect of the present invention provides an anti-leakage circuit in the STR state, which performs anti-leakage management on the SOC module and the peripheral module, the SOC module and the peripheral module are bidirectionally electrically connected, including a main control power supply, an STR trigger module, an STR management module, a power management module and a peripheral management module, wherein:

[0006] The main control power supply supplies power to the SOC module and is electrically connected to the SOC module;

[0007] The input end of the STR management module is respectively connected to the signal output end of the main control power supply and the output end of the STR trigger module by electrical signals, and the output end of the STR management module is respectively connected to the control end of the SOC module and the control end of the power management module by electrical signals;

[0008] The control end of the peripheral management module is electrically connected to the output end of the SOC module, and the output end of the peripheral management module is electrically connected to the control end of the power management module;

[0009] The peripheral management module configures the connection mode between the peripheral module and the SOC module, so that when the SOC module enters the STR state, the electrical signal with the peripheral module is disconnected, and the power supply of the SOC module does not flow to the peripheral module;

[0010] The power management module configures the connection mode between the peripheral module and the SOC module so that when the SOC module enters the STR state and disconnects the peripheral module, the power of the peripheral module will not flow to the SOC module.

[0011] In the above technical means, when the SOC module enters the STR state, the peripheral management module is started, and the peripheral management module is used to control the power management module. The power management module manages the power of the peripheral module so that the power of the peripheral module does not flow to the SOC module.

[0012] Furthermore, the STR management module is connected to the SOC module via SPI bus electrical signals.

[0013] Furthermore, it also includes a GPIO management module, and the control end of the GPIO management module is electrically connected to the output end of the peripheral management module.

[0014] Furthermore, it also includes a bus management module, and the control end of the bus management module is electrically connected to the output end of the peripheral management module.

[0015] Furthermore, it also includes a STR exception processing module, and the control end of the STR exception processing module is electrically connected to the output end of the peripheral management module.

[0016] Further, when the level of the peripheral module is the same as that of the SOC module, the power management module configures the connection mode between the peripheral module and the SOC module, including:

[0017] The power management module uses the power of the peripheral module and sets a pull-up resistor and a pull-down resistor.

[0018] Further, when the level of the peripheral module is different from that of the SOC module, the power management module configures the connection mode between the peripheral module and the SOC module, including:

[0019] A level conversion module is provided between the SOC module and the peripheral module.

[0020] A second aspect of the present invention provides a method for preventing leakage in a STR state, the method for preventing leakage is applied to the leakage prevention circuit in the STR state, and the method for preventing leakage comprises the following steps:

[0021] The STR trigger module generates a STR trigger signal and sends it to the STR management module;

[0022] The STR management module transmits the STR trigger signal to the SOC module;

[0023] After receiving the STR trigger signal, the SOC module enters the STR state and starts the peripheral management module;

[0024] After the SOC module enters the STR state, the main control power supply sends a SOC entering STR flag signal to the STR management module;

[0025] After receiving the SOC entering STR flag signal, the STR management module starts the peripheral management module;

[0026] The peripheral management module controls the power management module to configure the connection mode between the peripheral module and the SOC module.

[0027] Furthermore, when the SOC module enters the STR state, the wake-up signal trigger source is retained. When the SOC module exits the STR state, the wake-up signal trigger source sends a wake-up signal trigger signal to the STR trigger module. The STR trigger module sends an exit-STR signal to the STR management module. After the STR management module sends the wake-up signal to the SOC module, the SOC module is woken up. After the SOC module is woken up, the peripheral management module is started to power on the power supply.

[0028] Furthermore, when the SOC module is abnormal when entering or exiting the STR state, the STR abnormality processing module is used to perform diagnosis and perform recovery processing on the abnormality.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] The present invention provides an anti-leakage circuit in the STR state, which can greatly reduce various problems caused by leakage when the SOC module enters the STR state during the design process, shorten the development cycle, and effectively prevent various quality problems caused by leakage, reduce user complaints, reduce company losses, and improve customer satisfaction. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of a leakage prevention circuit structure in a STR state provided by an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of the structure of another anti-leakage circuit in the STR state provided by an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of a structure for setting a pull-up resistor and a pull-down resistor provided in an embodiment of the present invention;

[0034] Figure 4 A connection diagram of a level conversion module provided in an embodiment of the present invention;

[0035] Figure 5 A schematic flow chart of a method for preventing leakage in a STR state provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The drawings are for illustrative purposes only and should not be construed as limiting the present patent;

[0037] In order to better illustrate the present embodiment, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product;

[0038] It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0039] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0040] Example

[0041] This embodiment provides a leakage protection circuit in the STR state, such as Figure 1 and Figure 2 As shown, the SOC module and the peripheral module are managed to prevent leakage, and the SOC module is bidirectionally electrically connected to the peripheral module, including a main control power supply, an STR trigger module, an STR management module, a power management module and a peripheral management module, wherein:

[0042] The main control power supply supplies power to the SOC module and is electrically connected to the SOC module;

[0043] The input end of the STR management module is respectively connected to the signal output end of the main control power supply and the output end of the STR trigger module by electrical signals, and the output end of the STR management module is respectively connected to the control end of the SOC module and the control end of the power management module by electrical signals;

[0044] The control end of the peripheral management module is electrically connected to the output end of the SOC module, and the output end of the peripheral management module is electrically connected to the control end of the power management module;

[0045] The peripheral management module configures the connection mode between the peripheral module and the SOC module, so that when the SOC module enters the STR state, the electrical signal with the peripheral module is disconnected, and the power supply of the SOC module does not flow to the peripheral module;

[0046] The power management module configures the connection mode between the peripheral module and the SOC module so that when the SOC module enters the STR state and disconnects the peripheral module, the power of the peripheral module will not flow to the SOC module.

[0047] In a specific embodiment, the main control power supply supplies power to the SOC module, receives a notification that the SOC module enters the STR state, and sends an STR entry flag signal to the STR management module;

[0048] The STR trigger module has the ability to generate STR trigger signals and STR exit signals, and send the generated STR trigger signals and STR exit signals to the STR management module;

[0049] When the STR management module receives the STR trigger signal, it sends it to the SOC module through the SPI bus port, and at the same time receives the SOC enter STR flag signal sent by the main control power supply. When the STR management module receives the exit STR signal, it sends a wake-up signal to the SOC module;

[0050] The SOC module is the core unit of the vehicle-mounted equipment, and has three main working states: normal working state, STR working state and dormant working state. When receiving the STR trigger signal transmitted by the STR management module through the SPI bus, the SOC module will start the peripheral management module and enter the STR state;

[0051] The peripheral management module is responsible for managing the power management module;

[0052] The power management module manages the power on and off of all power modules based on a pre-set control sequence.

[0053] In a further embodiment, the power supply in the system generally includes two parts, one part of the power supply is controlled by the SOC, such as the power supply of the SOC's peripherals is generally controlled by the peripheral management module, and the other part of the power supply is controlled by the STR management module. The STR management module includes MCU, CAN and some hard-line trigger signals, such as the trigger signal for entering STR, the trigger signal for exiting STR, etc., and the MCU is mainly responsible for low-power management, controlling the main primary power supply and the PMIC power supply of the SOC.

[0054] In a further embodiment, the STR management module is connected to the SOC module via SPI bus electrical signals.

[0055] In a further embodiment, a GPIO management module is further included, and a control end of the GPIO management module is electrically connected to an output end of the peripheral management module.

[0056] In a specific embodiment, the GPIO management module is controlled and managed by the peripheral management module. After the power is turned on, all GPIOs are configured and managed. When the SOC module enters the STR state, all GPIOs are processed according to the pre-set pull-up and pull-down, input and output, or disable, specifically:

[0057] When entering STR, if there is an external pull-up, since the pull-up power supply will be turned off when entering STR, this type of SOC GPIO is generally required to be disabled when entering STR; if there is no external GPIO port with pull-up or pull-down, it is generally pulled down when entering STR; if there is an external GPIO port with pull-down processing, it is required to be disabled; if some GPIO ports use the SOC's own IO power supply for pull-up and there is no external pull-down resistor, this power supply will not be turned off when entering STR, so it is generally set to pull up and output low.

[0058] In a further embodiment, a bus management module is further included, and a control end of the bus management module is electrically connected to an output end of the peripheral management module.

[0059] In a specific embodiment, the bus management module is controlled and managed by the peripheral management module. After the power is turned on, the communication bus between the modules is configured and managed to ensure that the bus communicates normally when the bus is working normally. When entering STR, it is processed according to the pre-set bus processing method, specifically:

[0060] The bus generally has serial ports and I2C. These bus ports are generally configured as ordinary GPIOs when entering STR. The configuration of the GPIO port is the same as above, and the corresponding configuration is performed according to the external connection status and the status of the pull-up power supply.

[0061] In a further embodiment, a STR exception handling module is further included, and a control end of the STR exception handling module is electrically connected to an output end of the peripheral management module.

[0062] In a specific embodiment, the STR exception processing module is controlled and managed by the peripheral management module, performs diagnosis when entering or exiting the STR state abnormality, and performs recovery processing on the abnormality.

[0063] In a further embodiment, when the level of the peripheral module is the same as that of the SOC module, the power management module configures the connection mode between the peripheral module and the SOC module, including:

[0064] The power management module uses the power of the peripheral module and sets a pull-up resistor and a pull-down resistor.

[0065] In a specific embodiment, Figure 3 As shown, the peripheral module and the SOC module are connected through resistor R1 / resistor R2, and are pulled up to the power supply of the peripheral module through resistor R3. The pull-up power uses the power supply of the peripheral module to ensure that when entering STR, after the peripheral is powered off, it will not flow to the SOC through the pull-up resistor; at the same time, after the GPIO and bus port of the SOC are configured according to the above configuration method of the peripheral management module, the SOC power will not flow to the peripheral; it is pulled down to the ground system through resistor R4, and there is no need for a pull-up connection. Try to pull it down to the ground system through a pull-down resistor to ensure that when the SOC module enters the STR state, the level on the connection line is low.

[0066] In a further embodiment, when the level of the peripheral module is different from that of the SOC module, the power management module configures the connection mode between the peripheral module and the SOC module, including:

[0067] A level conversion module is provided between the SOC module and the peripheral module.

[0068] In a specific embodiment, Figure 4 As shown, the level conversion module converts the levels of signals with different voltages to ensure that the SOC module and the peripheral module 2 can communicate normally when the levels are different. The selected level conversion chip cannot cause leakage when there is no power supply. Specifically, the level conversion chip model 74AVCH4T245PW-Q100 can be selected.

[0069] The working principle of the whole circuit is as follows:

[0070] The STR trigger module sends out an STR entry message. After receiving the STR entry trigger signal, the STR management module passes the message to the SOC module through the SPI bus. The SOC receives the information transmitted by the bus, starts the peripheral management module, and processes the GPIO and bus connected to all peripherals of the power supply in a pre-set manner. These processes include pull-up and pull-down configurations, input and output configurations, or disable configurations to ensure that there is no leakage between the SOC and the peripherals. For the connection of the peripheral module, the pull-up power supply uses the power supply of the peripheral module to ensure that when entering STR, after the peripheral is powered off, it will not flow to the SOC through the pull-up resistor; at the same time, after configuring the GPIO and bus ports of the SOC according to the above configuration method of the peripheral management module, the SOC power supply will not flow to the peripherals;. For connections that do not require pull-up, try to pull down to the ground system through a pull-down resistor to ensure that the level on the connection line is low when entering STR. When the level of the peripheral module is inconsistent with that of the SOC module, select a level conversion chip that will not generate leakage when not powered. When entering STR, disconnect the power supply of the level conversion core to ensure that there will be no bidirectional leakage between the SOC and the peripherals. When the SOC enters STR, the wake-up signal trigger source is retained and the main power supply is notified at the same time. The main power supply sends an STR entry mark signal to the STR management module. STR will participate in power management and power off the residual power after being processed by the SOC peripheral management module. When the STR trigger module sends an exit STR message, the STR management module directly sends a wake-up signal to the SOC after receiving the exit STR message. After receiving the wake-up signal, the SOC starts the peripheral management module and powers on the power supply in a pre-set manner. The GPIO and bus are restored to the normal working mode configuration. When the exit STR state is abnormal, the STR exception handling module starts diagnosis and recovery.

[0071] This embodiment also provides a method for preventing leakage in the STR state, such as Figure 5 As shown, the anti-leakage method is applied to the anti-leakage circuit in the STR state, and the anti-leakage method includes the following steps:

[0072] The STR trigger module generates a STR trigger signal and sends it to the STR management module;

[0073] The STR management module transmits the STR trigger signal to the SOC module;

[0074] After receiving the STR trigger signal, the SOC module enters the STR state and starts the peripheral management module;

[0075] After the SOC module enters the STR state, the main control power supply sends a SOC entering STR flag signal to the STR management module;

[0076] After receiving the SOC entering STR flag signal, the STR management module starts the peripheral management module;

[0077] The peripheral management module controls the power management module to configure the connection mode between the peripheral module and the SOC module.

[0078] In a further embodiment, when the SOC module enters the STR state, the wake-up signal trigger source is retained. When the SOC module exits the STR state, the wake-up signal trigger source sends a wake-up signal trigger signal to the STR trigger module. The STR trigger module sends an exit-STR signal to the STR management module. After the STR management module sends the wake-up signal to the SOC module, the SOC module is woken up. After the SOC module is woken up, the peripheral management module is started to power on the power supply.

[0079] In a further embodiment, when an abnormality occurs in the SOC module when entering or exiting the STR state, the STR abnormality processing module is used to perform diagnosis and perform recovery processing on the abnormality.

[0080] The same or similar reference numerals correspond to the same or similar components;

[0081] The terms used in the drawings to describe positional relationships are only used for illustrative purposes and should not be construed as limiting this patent;

[0082] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A leakage prevention circuit in STR state, which performs leakage prevention management on the SOC module and the peripheral module, and the SOC module and the peripheral module are connected by bidirectional electrical signals, characterized in that: It includes main control power supply, STR trigger module, STR management module, power management module and peripheral management module, among which: The main control power supply supplies power to the SOC module and is electrically connected to the SOC module; The input end of the STR management module is respectively connected to the signal output end of the main control power supply and the output end of the STR trigger module by electrical signals, and the output end of the STR management module is respectively connected to the control end of the SOC module and the control end of the power management module by electrical signals; The control end of the peripheral management module is electrically connected to the output end of the SOC module, and the output end of the peripheral management module is electrically connected to the control end of the power management module; The peripheral management module configures the connection mode between the peripheral module and the SOC module, so that when the SOC module enters the STR state, the electrical signal with the peripheral module is disconnected, and the power supply of the SOC module does not flow to the peripheral module; The power management module configures the connection mode between the peripheral module and the SOC module so that when the SOC module enters the STR state and disconnects the peripheral module, the power of the peripheral module will not flow to the SOC module.

2. The anti-leakage circuit in the STR state according to claim 1, characterized in that: The STR management module is connected to the SOC module via SPI bus electrical signals.

3. The anti-leakage circuit in the STR state according to claim 1, characterized in that: The power management module is also controlled by the STR management module. Under the control of the peripheral management module and the STR management module, the power management module manages power on and power off of all power supplies.

4. The anti-leakage circuit in the STR state according to claim 1, characterized in that: It also includes a GPIO management module, and a control end of the GPIO management module is electrically connected to an output end of the peripheral management module.

5. The anti-leakage circuit in the STR state according to claim 1, characterized in that: It also includes a bus management module, and a control end of the bus management module is electrically connected to an output end of the peripheral management module.

6. The anti-leakage circuit in the STR state according to claim 1, characterized in that: It also includes a STR exception processing module, and the control end of the STR exception processing module is electrically connected to the output end of the peripheral management module.

7. The leakage protection circuit in the STR state according to any one of claims 1 to 6, characterized in that: When the level of the peripheral module is the same as that of the SOC module, the power management module configures the connection mode between the peripheral module and the SOC module, including: The power management module uses the power of the peripheral module and sets a pull-up resistor and a pull-down resistor.

8. The leakage protection circuit in the STR state according to any one of claims 1 to 6, characterized in that: When the level of the peripheral module is different from that of the SOC module, the power management module configures the connection mode between the peripheral module and the SOC module, including: A level conversion module is provided between the SOC module and the peripheral module.

9. A method for preventing leakage in STR state, characterized in that: The anti-leakage method is applied to the anti-leakage circuit in the STR state according to any one of claims 1 to 8, and the anti-leakage method comprises the following steps: The STR trigger module generates a STR trigger signal and sends it to the STR management module; The STR management module transmits the STR trigger signal to the SOC module; After receiving the STR trigger signal, the SOC module enters the STR state and starts the peripheral management module; After the SOC module enters the STR state, the main control power supply sends a SOC entering STR flag signal to the STR management module; After receiving the SOC entering STR flag signal, the STR management module starts the peripheral management module; The peripheral management module controls the power management module to configure the connection mode between the peripheral module and the SOC module.

10. The method for preventing leakage in STR state according to claim 8, characterized in that: When the SOC module enters the STR state, the wake-up signal trigger source is retained. When the SOC module exits the STR state, the wake-up signal trigger source sends a wake-up trigger signal to the STR trigger module. The STR trigger module sends an exit-STR signal to the STR management module. After the STR management module sends a wake-up signal to the SOC module, the SOC module is woken up. After the SOC module is woken up, the peripheral management module is started to power on the power supply.

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