Clock speed determination and adjustment based on target intent

Abstract

The power profile library includes a plurality of power profiles, where each power profile has a plurality of maximum clock speeds for a respective processor. A maximum clock speed in each power profile is selected to limit a maximum amount of heat per unit time co-generated by the processors. A developer computer system selects segments of a final application for a consumer device and selects a target intent for each segment. The power profile lookup uses the target intent to determine a power profile for each segment.

Description

[0001] This application is a divisional application of the Chinese patent application "Target intent-based clock speed determination and adjustment to limit the total heat generated by multiple processors" with application number 202080018865.4 (filing date February 6, 2020).

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 802,140, ​​filed on February 6, 2019, the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0004] The invention relates to a structured application development system. Background Art

[0005] Consumer devices (such as personal computers, smartphones, stereoscopic viewers, mixed reality viewers, etc.) have storage media for storing applications and one or more processors that execute routines of the applications. Such applications include operating systems and other applications that perform a variety of tasks (such as games, browsers, etc.).

[0006] A multi-core processor chip includes more than one processor core. These processor cores may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), vector processing, etc. When an application developer develops an application for running on multiple processors, the developer programs the clock speeds of the various processors.

[0007] Each processor generates heat per unit time, which increases as the clock speed rises. A multi-processor chip can usually release all the heat of a processor running at 100% of its maximum clock speed. However, when all processors are running at 100% of their maximum clock speed, the multi-core processor chip may not be able to release all the heat generated by all processors, which may cause damage to the circuits of the processors of the multi-core processor chip. There may be a specification for the clock speed of a multi-core processor chip, which details how the clock speed should be limited to limit the maximum heat generated per unit time by all processors. There is a risk that developers may ignore the specification, which will cause damage to the multi-core processor chip. Summary of the invention

[0008] According to one aspect of the present invention, a host computer system is provided, which includes a host computer processor, a computer-readable medium connected to the host computer processor, and an instruction set on the computer-readable medium, the instruction set being readable by the host computer processor and including a structured application development system, the structured application development system having a power profile database on the computer-readable medium, the power profile database including: a first reference intent; a first power profile associated with the first reference intent and having a corresponding first maximum clock speed for the first processor and a corresponding second maximum clock speed for the second processor; a second reference intent; and a second power profile associated with the second reference intent and having a corresponding first maximum clock speed for the first processor and a corresponding second maximum clock speed for the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile.

[0009] The present invention also provides a method for operating a host computer system, comprising: storing a power profile database on a computer-readable medium, the power profile database comprising: a first reference intent; a first power profile associated with the first reference intent and having a corresponding first maximum clock speed for a first processor and a corresponding second maximum clock speed for a second processor; a second reference intent; and a second power profile associated with the second reference intent and having a corresponding first maximum clock speed for the first processor and a corresponding second maximum clock speed for the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile.

[0010] The present invention also provides a consumer device, which includes: a multi-core processor chip having a main body and multiple processors on the main body; a computer-readable medium connected to the processor; and an application on the computer-readable medium, the application having: a first segment, the first segment having a first routine executable by the processor, and a first power profile having a corresponding maximum clock speed for each processor; and a second segment, the second segment having a second routine executable by the processor and a second power profile, the second power profile having a corresponding maximum clock speed for each processor, so that at least one processor has a maximum clock speed that changes from the first segment to the second segment, wherein the processors jointly generate a first heat per unit time during the first segment and jointly generate a second heat during the second segment, and the difference between the second heat and the first heat is less than 10%.

[0011] The present invention also provides a method for operating a consumer device, comprising: storing an application on a computer-readable medium, the computer-readable medium being connected to a plurality of processors on a body of a multi-core processor chip, the application having a first segment and a second segment; executing the first segment with the processor, the first segment having a first routine executable by the processor, and a first power profile having a corresponding maximum clock speed for each processor; and executing the second segment with the processor, the second segment having a second routine executable by the processor, and a second power profile having a corresponding maximum clock speed for each processor, so that at least one processor has a maximum clock speed that changes from the first segment to the second segment, wherein the processors collectively generate a first heat per unit time during the first segment and collectively generate a second heat during the second segment, and the difference between the second heat and the first heat is less than 10%.

[0012] The present invention also provides a consumer device, comprising: a first processor and a second processor; a computer-readable medium connected to the processors; and an application on the computer-readable medium, the application having: a first segment, the first segment having a first routine executable by the first processor and the second processor, and a first power profile having a first maximum clock speed and a second maximum clock speed for the first processor and the second processor; and a second segment, the second segment having a second routine executable by the first processor and the second processor, and a second power profile having a first maximum clock speed and a second maximum clock speed for the first processor and the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile, and the second maximum clock speed of the first power profile being different from the second maximum clock speed of the second power profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention is further described by way of example with reference to the accompanying drawings, in which:

[0014] Figure 1 is a block diagram illustrating a network environment according to an embodiment of the present invention, the network environment having a host computer system and a developer computer system connected to each other through a network in the form of the Internet;

[0015] Figure 2 The download interface is similar to Figure 1 Block diagram of

[0016] Figure 3 It is a block diagram of the developer's computer system and the consumer's device;

[0017] Figure 4 is a block diagram illustrating the functionality of an application on a consumer device;

[0018] Figure 5 is a block diagram illustrating other functionality of an application on a consumer device;

[0019] Fig. 6A , Figure 6B and Figure 6C is a graph showing power curves for three different processors;

[0020] Fig. 7A , Figure 7B and Figure 7C is a graph showing three different power profiles;

[0021] Fig. 8A , Figure 8B and Figure 8C It is shown that Fig. 7A , Figure 7B and Figure 7C The heat generated by the power profile in;

[0022] Fig. 9 is a block diagram of a machine in the form of a computer system forming part of a network environment. DETAILED DESCRIPTION

[0023] Figure Figure 1 A network environment 10 is shown according to an embodiment of the present invention, which includes a host computer system 12 and a developer computer system 14 connected to each other via a network in the form of the Internet 16. Most of the data and logic reside on the host computer system 12, and the developer computer system 14 is permitted to access only certain components on the host computer system 12 via the Internet 16 using a browser application resident on the developer computer system 14. In another embodiment, all data and functionality may reside on the developer computer system 14, thus eliminating the need for the host computer system 12 - the developer computer system 14 effectively becomes the host computer system. However, preferably, certain controls reside on the host computer system 12 and are not accessible to the developer at the developer computer system 14. Another embodiment may include certain data and functionality on the host computer system 12, particularly such data and functionality that should be under the control of the host computer system 12, while the remaining data and functionality may reside on the developer computer system 14.

[0024] The host computer system 12 includes a structured application development system 18. The structured application development system 18 initially resides on a storage medium of the host computer system 12. Components of the structured application development system 18 are loaded into the memory of the host computer system 12 when needed. The components of the structured application development system 18 include select data 52 that resides on the memory and various logic components that are executable by a host computer processor of the host computer system 12 connected to the memory.

[0025] The structured application development system 18 includes a power profile database 20, a structured intent system 22, a development toolkit 24, and an application being developed 26. The application 26 may not initially form part of the structured application development system 18. However, it is shown as part of the structured application development system 18 because it is built by the other components of the structured application development system 18 in conjunction with the choices made by the developer on the developer computer system 14.

[0026] The power profile database 20 has a first reference intent 28 and a second reference intent 30. For example, the first reference intent 28 may be "graphics intensive" and the second reference intent 30 may be "startup" or any other label designated to characterize the demand or load on a device included in the system in which the program is running. The first reference intent 28 has a first power profile 32 associated with it. The first power profile 32 has a first clock speed 34 for a first processor and a second clock speed 36 for a second processor. The first processor may be, for example, a graphics processing unit (GPU) and the second processor may be a central processing unit (CPU). If the first reference intent 28 is a graphics intensive intent, the first clock speed 34 for the GPU will be set high and the second clock speed 36 for the CPU will be set low. The clock speeds are selected in such a way that the maximum heat per unit time generated by the first processor and the second processor together on the multi-core processor chip will be limited while at the same time each processor is operated at the optimal clock speed under the first reference intent 28.

[0027] The second reference intent 30 has a second power profile 38 associated therewith. The second power profile 38 has a first clock speed 40 for the first processor and a second clock speed 42 for the second processor. By way of example, the second reference intent 30 is a boot intent. For boot purposes, if the first processor is a GPU, the first clock speed 40 is set relatively low, and if the second processor is a CPU, the second clock speed 42 is set relatively high. If the first processor and the second processor are on the same multi-core processor chip, the first clock speed 40 and the second clock speed 42 are preemptively determined to keep the heat generated by the first processor and the second processor below the maximum heat per unit time. It should be noted that the first clock speed 34 of the first power profile 32 may be higher than the first clock speed 40 of the second power profile 38, and the second clock speed 36 of the first power profile 32 may be lower than the second clock speed 42 of the second power profile 36.

[0028] The power profile database 20 has only the first power profile 32 and the second power profile 38. However, it should be understood that the power profile database 20 may include more power profiles, for example four power profiles, each power profile being associated with a respective reference intent.

[0029] In addition, the first power profile 32 and the second power profile 38 include clock speeds for only the first processor and the second processor. Each power profile may also include clock speeds for a third processor, a fourth processor, and so on.

[0030] The structured intent system 22 includes a target intent set 46 , an intent selection interface 48 , a power profile lookup 50 , and selection data 52 .

[0031] The target intent set 46 includes a first target intent 56 and a second target intent 58. The first target intent 56 may be, for example, "graphics intensive" and the second target intent 58 may be "startup", thus being similar to the first reference intent 28 and the second reference intent 30 in the power profile database 20.

[0032] A developer at the developer computer system 14 uses a browser resident on the developer computer system 14 to access the intent selection interface 48 via the Internet 16. The intent selection interface 48 may be, for example, an interactive web page that may be downloaded by a browser application from the host computer system 12 to the developer computer system 14 via the Internet 16 and may be viewed within a browser window on a display of the developer computer system 14. The intent selection interface 48 allows the developer to select segments of the application and select target intents for the corresponding segments.

[0033] At 60, the developer selects the first segment 62 that will eventually form part of the application. The structured intent system 22 displays the first target intent 58 as the first target intent 64 and the second target intent 58 as the second target intent 66 in the intent selection interface 48. Then, the developer is prompted to select the first target intent 64 or the second target intent 66 for association with the first segment 62. Note that the developer is not allowed to select both the first target intent 64 and the second target intent 66. The first target intent 64 and the second target intent 66 can be presented in the intent selection interface 48, for example, as a drop-down list that allows only one of the first target intent 64 and the second target intent 66 to be selected and does not allow the selection of the other target intent. At 70, the developer chooses to associate the second target intent (which is the same as the second target intent 58) with the first segment 62. Therefore, the first segment 62 has the second target intent 66 associated with it, and the second target intent 66 is a launch intensive target intent. Arrow 72 indicates the association of the second target intent 66 with the first segment 62.

[0034] At 74, the developer makes a selection for the second segment 76 of the final application. The structured intent system 22 displays the first target intent 56 as a first target intent 78 and the second target intent 58 as a second target intent 80 so that the developer can select between the first target intent 78 and the second target intent 80. Again, the developer is only allowed to select one of the first target intent 78 and the second target intent 80, while excluding the other. At 82, the developer selects to associate the first target intent (which is the same as the first target intent 56) with the second segment 76. Arrow 84 indicates the association of the first target intent 78 with the second segment 76.

[0035] The power profile lookup 50 uses the second target intent 66 of the first segment 62 to determine a reference intent within the power profile database 20. In this example, the second target intent 66 matches the second reference intent 30 because they are both startup intensive intents. The power profile lookup 50 then extracts the second power profile 38 from the power profile database 20, which includes the first clock speed 40 and the second clock speed 42. The power profile lookup 50 then stores the second power profile 38 in the selection data 52 as a second power profile 86. The power profile lookup 50 stores the first segment 62 as the first segment 88. The power profile lookup 50 also associates the second power profile 86 with the first segment 88. As will be understood by those skilled in the art of data structures, the first segment 88 and the first segment 62 can be exactly the same data segment. However, for illustrative purposes and ease of explanation, the first segment 62 and the first segment 88 are shown as different data segments.

[0036] Similarly, the power profile lookup 50 uses the first target intent 78 associated with the second segment 76 to look up a reference intent in the power profile database 20. In this example, the first target intent 78 matches the first reference intent 28 because they are both graphically intensive intents. The power profile lookup 50 extracts the first power profile 32 associated with the first reference intent 28, which includes the first clock speed 34 and the second clock speed 36. The power profile lookup 50 then stores the first power profile 32 in the selection data 52 as a first power profile 90. The power profile lookup 50 stores the second segment 76 in the selection data 52 as a second segment 92. The power profile lookup 50 also associates the first power profile 90 with the second segment 92 in the selection data 52.

[0037] The developer is not allowed to select clock speeds that are not represented in the corresponding power profiles 86 and 90. Therefore, it is not possible for the developer to select clock speeds that, in combination, will result in too much heat being generated per unit time on the multi-core processor chip. However, the developer is allowed to select a target intent for the corresponding segment in order to adjust the clock speeds of the individual processors without causing the processors, in combination, to generate too much heat per unit time.

[0038] The development toolkit 24 includes a tool set 96 , a tool selection interface 94 , application development logic 100 , and power limiting logic 102 .

[0039] The tool set 96 is the basic tool set required by the developer to structure the components of the various segments of the application stored on the storage device of the host computer system 12. The tool set 96 is represented as tool 1 to tool 6. The developer at the developer computer system 14 downloads the tool selection interface 94 from the host computer system 12 for display on the developer computer system 14, similar to the way the intent selection interface 48 is displayed. The tool selection interface 94 includes a first segment 104 and a second segment 106 corresponding to the first segment 88 and the second segment 92 in the selection data 52. The tools of the tool set 96 are also displayed within the tool selection interface 94. At 108, the developer selects a first tool (tool 3) for the first segment 104. The developer then continues to select other tools for the first segment 104. Therefore, the tools for the first segment 104 can be configured by the developer according to their selection and their order. The developer also selects tools for the second segment 106 in a configurable manner. The first segment 104 and its tools and the second segment 106 and its tools show the developer how the application will function in terms of the segments of the application and the functions of each segment.

[0040] The application development logic 100 creates a first section 112 and a second section 114 in the application 26. The first section 112 corresponds to the first sections 62, 88, and 104. The second section 114 corresponds to the second sections 76, 92, and 106. The application development logic 100 compiles the tools of the first section 104 into a first routine 118 and enters the first routine 118 into the first section 112 of the application 26. The application development logic 100 compiles the tools of the second section 106 into a second routine 120 and enters the second routine 120 into the second section 114.

[0041] The power limiting logic 102 retrieves the second power profile 86 corresponding to the first segment 88 from the selection data 52 and inputs the second power profile 86 as a second power profile 122 as part of the first segment 112 of the application 26. The power limiting logic 102 also retrieves the first power profile 90 corresponding to the second segment 92 in the selection data 52 and inputs the first power profile 90 in the second segment 114 as a first power profile 124. The second power profile 122 of the first segment 112 includes the first clock speed 40 for the first processor and the second clock speed 42 for the second processor. The first power profile 124 of the second segment 114 includes the first clock speed 34 for the first processor and the second clock speed 36 for the second processor. Thus, the first segment 112 and the second segment 114 each have respective routines 118 and 120 and each have respective clock speeds for the first processor and the second processor, the clock speeds being selected to be intentionally specific and limited by the power limiting logic 102 to limit the processors, in combination, from generating more than a predetermined amount of heat per unit time.

[0042] like Figure 2 As shown, the structured application development system 18 also includes a download interface 98. The developer at the developer computer system 14 obtains the download interface 98 from the host computer system 12 and displays the download interface 98 on the display of the developer computer system 14. The developer uses the developer computer system 14 to interact with the download interface 98 to download the application 26 from the host computer system 12 to the developer computer system 14. The application 26 then resides on the developer computer system 14 as the application 130.

[0043] Figure 3A developer computer system 14 and a consumer device 132 are shown. The consumer device 132 has a storage medium 134 and a multi-core processor chip 136. The multi-core processor chip 136 has a body 140 and a first processor 142 and a second processor 144 fabricated in and on the body 140. The body 140 includes semiconductor materials such as silicon, germanium, gallium arsenide, etc., and may include other components and materials generally known in the field of semiconductor packaging. The first processor 142 and the second processor 144 include transistors and other electronic components interconnected to form a logic device. The first processor 142 and the second processor 144 are connected to an external power supply and have a clock that can be set at a pre-selected clock speed. The developer uses the developer computer system 14 to create a copy of the application 130 and stores the copy of the application as an application 150 on the storage medium 134. Then, the consumer device 132 is programmed with the application 150. In a batch manufacturing process, the application 130 may first be transferred to a programmer for programming multiple consumer devices for proportional distribution.

[0044] Figure 4 and Figure 5 1 shows how application 150 executes on consumer device 132. Figure 4 , a first segment 112 of an application 150 is executed. The clock speed of the second power profile 122 is used to set the clock speed of the first processor 142 and the second processor 144. By way of example, the second power profile 122 includes a first clock speed of 39 GHz for the first processor 142 and a second clock speed of 200 GHz for the second processor 144. The first processor 142 and the second processor 144 execute a first routine 118. The segments of the first routine 118 executed by the first processor 142 are represented by first routines 118A, and the segments of the first routine 118 executed by the second processor 144 are represented by first routines 118B. The first routines 118A and 118B may be partially executed simultaneously or may have portions interleaved such that portions of the first routine 118A and the first routine 118B alternate with each other. The clock speeds at which the first routine 118A and the first routine 118B are executed by the first processor 142 and the second processor 144 are derived from Figure 1 The power profile database 20 in FIG. 1 is not provided to the developer, and the developer is prevented from selecting different clock speeds due to the logic that is and is not provided to the developer.

[0045] Figure 5Execution of the second segment 114 is shown. The first power profile 124 is used to set the clock speed of the first processor 142 and the second processor 144. For example, the first processor 142 has a clock speed of 150 GHz and the second processor 144 has a clock speed of 120 GHz. The second routine 120 is executed by the first processor 142 and the second processor 144. The component of the second routine 120 executed by the first processor 142 is represented by the second routine 120A, and the component of the second routine 120 executed by the second processor 144 is represented by the second routine 120B.

[0046] Fig. 6A , Figure 6B and Figure 6C It is shown that three different processors may have three different heat generation curves. In each figure, the heat generated per unit time in Watts is shown on the vertical axis and the performance as a percentage of the maximum clock speed is shown on the horizontal axis. Fig. 6A The heat generation curve of the processor is shown to increase slowly at first, then accelerate, and then decelerate. Figure 6B The heat generation curve of the processor is shown to increase rapidly initially and then gradually slow down. Figure 6C The heat generation curves for the processors shown increase linearly. When calculating the total heat generated by the three processors, it is necessary to consider Fig. 6A , Figure 6B and Figure 6C The heat generation curve is shown.

[0047] Fig. 7A , Figure 7B and Figure 7C Three different power profiles are shown that can be stored. Fig. 7A A power profile is shown in which priority is given to a first processor among the processors. The first processor is allowed to run at 100% of its maximum clock speed. The clock speeds of the second and third processors are reduced to less than 100% of their maximum clock speeds. Figure 7B A power profile is shown in which priority is given to a third processor. The third processor is set to run at a clock speed equal to 100% of its maximum clock speed, while the clock speeds of the first and second processors are reduced to less than 100% of their maximum clock speeds. Figure 7C A power profile is shown in which performance is balanced. The clock speeds of all three processors are reduced to less than 100% of their maximum clock speeds.

[0048] Fig. 8A , Figure 8B and 8C They are shown respectively by Fig. 7A , Figure 7B and Figure 7CThe power profile in each processor generates heat. Fig. 6A , Figure 6B and Figure 6C The total heat generated per unit time by all three processors is Fig. 8A , Figure 8B and Figure 8C Although the total amount of heat generated per unit time is the same, minor variations are possible without departing from the scope and spirit of the invention. For example, the total amount of heat generated per unit time by the first power profile may be less than 10% higher or less than the total amount of heat generated per unit time following the second power profile. The third power profile may generate less than 10% more or less heat per unit time than the first power profile.

[0049] The consumer device 132 described herein may be a mixed reality system as described in U.S. Patent Application No. 14 / 331,218, which is incorporated herein by reference.

[0050] Fig. 9 A diagrammatic representation of a machine in the exemplary form of a computer system 900 is shown, within which an instruction set for causing the machine to perform any one or more methods discussed herein can be executed. In an alternative embodiment, the machine works as a standalone device or can be connected (e.g., networked) to other machines. In a network deployment, the machine can work as a server or client machine in a server-client network environment, or work as a peer machine in a peer-to-peer (or distributed) network environment. The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a network router, a switch or a bridge, or any machine capable of executing an instruction set (sequentially or otherwise) specifying the action to be taken by the machine. Further, although only a single machine is shown, the term "machine" should also be considered to include any collection of machines that execute an instruction set (or multiple instruction sets) individually or jointly to perform any one or more methods in the method discussed herein.

[0051] The exemplary computer system 900 includes a processor 930 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both), a main memory 932 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), and a static memory 934 (e.g., flash memory, static random access memory SRAM, etc.), which communicate with each other via a bus 936.

[0052] The computer system 900 may also include a video display 938 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)). The computer system 900 also includes an alphanumeric input device 940 (e.g., a keyboard), a cursor control device 942 (e.g., a mouse), a disk drive unit 944, a signal generating device 946 (e.g., a speaker), and a network interface device 948.

[0053] The disk drive unit 944 includes a machine-readable medium 950 on which is stored one or more sets of instructions 952 (e.g., software) embodying any one or more of the methodologies or functions described herein. The software may also reside completely or at least partially within the main memory 932 and / or within the processor 930 during execution by the computer system 900, the memory 932 and the processor 930 also constituting machine-readable media. The software may also be transmitted or received over a network 954 via the network interface device 948.

[0054] Although certain exemplary embodiments have been described and shown in the drawings, it is to be understood that these embodiments are merely illustrative and not restrictive of the invention, and that the invention is not limited to the specific construction and arrangements shown and described, since modifications may be made by those skilled in the art.

Claims

1. A consumer device comprising: A multi-core processor chip having a main body and a plurality of processors on the main body; a computer readable medium coupled to said processor; as well as The application on the computer readable medium, the application having: The first paragraph has: a first routine executable by the processor; as well as a first power profile having a respective maximum clock speed for each of the processors; and The second paragraph, the second paragraph having: a second routine executable by the processor; as well as a second power profile having a respective maximum clock speed for each of the processors such that at least one of the processors has a maximum clock speed that changes from the first segment to the second segment, wherein the processors collectively generate a first amount of heat per unit time during the first segment and collectively generate a second amount of heat during the second segment, the second amount of heat differing from the first amount of heat by less than 10%.

2. The consumer device of claim 1, wherein: The second amount of heat is the same as the first amount of heat.

3. The consumer device of claim 1 , wherein: The first processor and the second processor have different heat generation curves.

4. The consumer device of claim 1, wherein: The processor includes at least a first processor and a second processor, the second processor generates less heat per unit time than the first processor during the first period and generates more heat than the first processor during the second period, wherein the processor includes at least a third processor, the third processor generates less heat per unit time than the first processor during the first period and generates more heat than the first processor during the second period.

5. The consumer device of claim 1 , further comprising: The third paragraph comprises: a third routine executable by the processor; as well as a third power profile having a respective maximum clock speed for each of the processors such that at least one of the processors has a maximum clock speed that changes from the first segment to the third segment, wherein the processors collectively generate a third amount of heat per unit time during the third segment, and the third amount of heat differs from the first amount of heat by less than 10%.

6. A method of operating a consumer device, comprising: storing an application program on the computer-readable medium, the computer-readable medium being coupled to a plurality of processors on a body of a multi-core processor chip, the application program having a first segment and a second segment; Executing the first segment with the processor, the first segment having: a first routine executable by the processor; as well as a first power profile having a respective maximum clock speed for each of the processors; as well as Executing the second section with the processor, the second section having: a second routine executable by the processor; as well as a second power profile having a respective maximum clock speed for each of the processors such that at least one of the processors has a maximum clock speed that changes from the first segment to the second segment, wherein the processors collectively generate a first amount of heat per unit time during the first portion and generate a second amount of heat during the second portion, and the second amount of heat differs from the first amount of heat by less than 10%.

7. A consumer device comprising: a first processor and a second processor; a computer readable medium coupled to said processor; as well as The application on the computer readable medium, the application having: The first paragraph has: a first routine executable by said first and second processors; as well as a first power profile having a first maximum clock speed and a second maximum clock speed for the first processor and the second processor; as well as The second paragraph, the second paragraph having: a second routine executable by the first processor and the second processor; as well as a second power profile having a first maximum clock speed and a second maximum clock speed for the first processor and the second processor, the first maximum clock speed of the first power profile being different from the first maximum clock speed of the second power profile, and the second maximum clock speed of the first power profile being different from the second maximum clock speed of the second power profile.

8. The consumer device of claim 7, further comprising: A multi-core processor chip holds the first processor and the second processor.

9. The consumer device of claim 7, wherein: The first processor and the second processor have different heat generation curves.

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