Data read-write processing method and device, equipment and medium

Abstract

The embodiment of the invention provides a data read-write processing method and device, equipment and a medium, and relates to the technical field of computers.The method comprises the steps that a data processing request is received and analyzed, and a request type and address information in the data processing request are extracted; the request type comprises a data reading request and a data writing request; when the request type is a data reading request and the address information meets a preset number of data reading rules, a data prefetching operation is triggered, target data is read from the cache, and the target data is prefetched from a memory and loaded into the cache; and / or, when the request type is a data write-in request and the address information meets a preset number of data write-in rules, triggering a data merging operation, and writing the cache line into the cache or the memory. According to the scheme, the time for reading the data from the memory or replacing the data when the request arrives can be shortened, and the read-write processing efficiency of the data is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data reading and writing processing method, device, equipment and medium. Background Art

[0002] With the continuous development of computer technology, memory is a key component for storing data and instructions required by programs when running. As applications become more and more complex, the requirements for memory access speed and efficiency are also increasing. Especially in the fields of big data processing, high-performance computing, real-time systems, etc., reading and writing large amounts of data from memory quickly and efficiently is called one of the key factors to improve the overall performance of the system. Therefore, it is particularly important to study how to read and write data.

[0003] At present, in the related technology, when the cache control module receives a read request, it needs to check whether there is the requested data in the local cache. If the data exists in the cache, the data is obtained from the cache and returned to the upstream requester; if the requested data is not in the cache, the data is read from the lower storage layer or main memory. When the cache control module receives a write request, if this batch of write requests does not completely cover a complete cache line, it is necessary to first read the existing data from the cache, and then replace only the bytes at the corresponding position according to the specific content of the write request, while keeping those parts that have not been requested to change unchanged, to obtain the updated cache line, and finally write the updated cache line back to the cache. However, in the process of relocating a large amount of data with continuous addresses, the processing flow of this scheme is relatively cumbersome, resulting in low efficiency in reading and writing data. Summary of the invention

[0004] The embodiments of the present application provide a data reading and writing processing method, device, equipment and medium.

[0005] A first aspect of an embodiment of the present application provides a data reading and writing processing method, comprising: Receive and parse a data processing request, and extract a request type and address information from the data processing request; the request type includes a data read request and a data write request; When the request type is a data read request and the address information satisfies a preset quantity data read rule, a data prefetch operation is triggered, and target data is read from the cache, wherein the target data is prefetched from the memory and loaded into the cache; and / or, When the request type is a data write request and the address information satisfies a preset quantity data write rule, a data merge operation is triggered to write the cache line into the cache or memory.

[0006] In an optional embodiment of the present application, the preset number of data reading rules include: continuous addresses, increasing addresses, the same size of data read each time, the same address attributes, and continuous reading of a preset number of bytes; The preset number of data writing rules include: continuous addresses, increasing addresses, the same size of data written each time, the same address attributes, and continuous writing of a preset number of bytes.

[0007] In an optional embodiment of the present application, triggering a data read operation and reading target data from the cache includes: Calculate the prefetch address and the number of cache lines according to the pre-configured register prefetch configuration information; According to the pre-fetch address and the number of cache lines, target data is read from a memory and loaded into the cache.

[0008] In an optional embodiment of the present application, the acquisition timestamp of the pre-fetched address is smaller than the acquisition timestamp of the address information.

[0009] In an optional embodiment of the present application, triggering a data merge operation to write a cache line into the cache or memory includes: Merge configuration information according to pre-configured registers to obtain data for multiple burst units; The data of the multiple burst units are merged to obtain a cache line, and the cache line is written into the cache or memory.

[0010] In an optional embodiment of the present application, before receiving and parsing the data processing request, the method further includes: Obtain register prefetch configuration information; the register prefetch configuration information includes any one of the following: a prefetch address, a number of cache lines to be prefetched, a number of bytes to be prefetched, an advance amount of an acquisition timestamp of the prefetch address and an acquisition timestamp of the address information; The cache is configured according to the register pre-fetch configuration information.

[0011] In an optional embodiment of the present application, before receiving and parsing the data processing request, the method further includes: Acquire register merging configuration information; the register merging configuration information includes: the number of bytes that trigger the merging; The cache is configured according to the register merging configuration information.

[0012] A second aspect of an embodiment of the present application provides a data reading and writing processing device, including: A receiving module, used to receive and parse a data processing request, and extract a request type and address information from the data processing request; the request type includes a data read request and a data write request; a reading module, configured to trigger a data pre-fetch operation and read target data from the cache when the request type is a data read request and the address information satisfies a preset quantity of data read rules, wherein the target data is pre-fetched from the memory and loaded into the cache; and / or, The writing module is used to trigger a data merging operation and write the cache line into the cache or memory when the request type is a data writing request and the address information satisfies a preset quantity of data writing rules.

[0013] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0014] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0015] In an embodiment of the present application, a data processing request is received and parsed to extract the request type and address information in the data processing request, where the request type includes a data read request and a data write request. When the request type is a data read request and the address information satisfies a preset number of data read rules, a data prefetch operation is triggered, and target data is read from the cache, where the target data is prefetched from the memory and loaded into the cache; and / or, when the request type is a data write request and the address information satisfies a preset number of data write rules, a data merge operation is triggered to write the cache line into the cache or the memory. The technical solution in the present application can determine in real time whether it is a large number of data read operations with continuous addresses by checking whether a preset number of data read rules are met. When it is a large number of data read operations, a data pre-fetch operation is triggered, so that the target data is pre-fetched and loaded into the cache in advance, so as to facilitate real-time acquisition of data when a request arrives, reduce the time for reading data from the memory when a request arrives, and improve the data reading efficiency; when it is a data write operation and it is a large number of data write operations, there is no need to read and replace data from the memory or cache each time. By directly triggering the data merge operation, multiple data are written to the cache or memory only after the merge is completed, which reduces the data replacement time for each burst unit, thereby improving the data writing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of the structure of a computer device provided in one embodiment of the present application; Figure 2 A flowchart of a data reading and writing processing method provided by an embodiment of the present application; Figure 3 A schematic diagram of a method for triggering a data read operation and reading target data from the cache provided by an embodiment of the present application; Figure 4 A schematic diagram of the interface structure of a read data stream control module ReadStream provided in one embodiment of the present application; Figure 5 A flowchart of a method for triggering a data merge operation and writing a cache line into the cache or memory provided by another embodiment of the present application; Figure 6 A schematic diagram of the interface structure of a write data stream control module WriteStream provided in one embodiment of the present application; Figure 7 A schematic diagram of the structure of a data reading and writing processing device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0017] In the process of implementing the present application, the inventors found that in the process of relocating a large amount of data with continuous addresses, the processing flow is relatively complicated, resulting in low efficiency in reading and writing data.

[0018] At present, in the related art, when the cache control module receives a read request (read transaction), it first checks whether the requested data is hit in the local cache. If the data exists in the cache, the data is obtained from the cache and returned to the upstream requester; if the requested data is not in the cache, the data is read from the lower storage layer (downstream cache) or the main memory (memeory). When the cache control module receives a write request (write transaction), it generally receives the write request sent by the upstream in burst units. If this write request does not completely fill a complete cache line (cacheline), it is necessary to first read the existing data with the same address from the cache cache, and then replace only the bytes at the corresponding position of the cache line (cacheline) according to the specific content (byte) of the write request, and keep those bytes that have not been changed by the request unchanged, to obtain the updated cache line (cacheline), and finally write the updated cache line back to the cache. However, in the process of relocating a large amount of data with continuous addresses, the processing flow of this scheme is relatively cumbersome, resulting in low efficiency in data reading and writing.

[0019] Based on the above-mentioned defects, the embodiment of the present application provides a data reading and writing processing method. Compared with the prior art, the technical solution in the present application can determine in real time whether it is a large number of data reading operations with continuous addresses by checking whether a preset number of data reading rules are met. When it is a large number of data reading operations, a data prefetch operation is triggered, so that the target data is prefetched and loaded into the cache in advance, so as to facilitate real-time acquisition of data when a request arrives, reduce the time of reading data from the memory when a request arrives, and improve the data reading efficiency; when it is a data writing operation and it is a large number of data writing operations, there is no need to read and replace data from the memory or cache each time. By directly triggering the data merging operation, multiple data are written to the cache or memory only after the merging is completed, which reduces the data replacement time for each burst unit, thereby improving the data writing efficiency.

[0020] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0021] The following is a brief description of the application environment of the data reading and writing processing method provided in the embodiment of the present application: Optionally, the data reading and writing processing method provided by the present application can be applied to a computer device, wherein the scheme in the embodiment of the present application can be implemented in various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0022] See also Figure 1 , a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 1 As shown, the computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium can be, for example, a disk. The non-volatile storage medium stores files (which can be files to be processed or processed files), an operating system and a computer program, etc. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data reading and writing processing method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0023] See also Figure 2 The following embodiments take the above-mentioned computer device as the execution subject, and apply the data reading and writing processing method provided by the embodiment of the present application to the above-mentioned computer device to perform instruction processing as an example for specific description. The data reading and writing processing method provided by the embodiment of the present application includes the following steps 201-203: Step 201: Receive and parse a data processing request, and extract the request type and address information in the data processing request; the data type includes a data read request and a data write request.

[0024] It should be noted that the above data processing request may be sent by the upstream operator through the physical layer interface (FAPI), which is an interface in the physical layer used to connect and transmit data, ensuring that data can be correctly transmitted between different devices. Data processing requests may include data read requests and data write requests. Address information includes physical address, virtual address, address attributes, transaction size, burst length, access type, protection attributes, and address space identifier. Physical address is the actual address in memory, which is used to directly access data in memory; virtual address is the address in the address space provided by the operating system for the process, and the virtual address is converted to the physical address through the page table; address attributes describe some characteristics of the memory area, such as whether it is cacheable, bufferable, executable, etc.; transaction size indicates the amount of data requested in a single request, usually in bytes; for example, a read request may involve 4 bytes (a 32-bit integer) or 8 bytes (a 64-bit integer); burst length indicates the number of data blocks transmitted continuously, which is an efficient data transmission method that can transmit multiple data units in one request. Access type indicates the nature of the request, such as whether it can be a read request or a write request; protection attributes indicate the access rights to the memory area, such as whether reading, writing, or execution is allowed; address space identifier is used to distinguish the address spaces of different processes, and the feature is in operating systems that support multitasking.

[0025] After receiving the data processing request, a preset parsing algorithm may be used to parse the data processing request to obtain the request type and address information.

[0026] Step 202: When the request type is a data read request and the address information satisfies a preset quantity of data read rules, a data pre-fetch operation is triggered, and target data is read from the cache. The target data is pre-fetched from the memory and loaded into the cache.

[0027] It should be noted that the above-mentioned preset number of data reading rules can be customized according to actual needs, the preset number can be a preset number of bytes, and the preset number of data reading rules can be reading rules set according to address information. For example, it can include whether the address is continuous, whether the address is increasing, whether the address attributes are the same, etc. The target data refers to the data loaded into the cache.

[0028] As an implementation method, when the request type is a data read request, it is necessary to check whether the data read request meets the preset number of data read rules. When the preset number of data read rules are met, the data pre-fetch mechanism can be triggered, and after the data pre-fetch mechanism is executed, the target data is read from the cache. The data pre-fetch mechanism refers to reading the target data from the memory in advance and storing it in the cache.

[0029] Step 203: When the request type is a data write request and the address information satisfies a preset quantity of data write rules, a data merge operation is triggered to write the cache line into the cache or memory.

[0030] It should be noted that the above-mentioned preset number of data writing rules can be customized according to actual needs, the preset number can refer to a preset number of bytes, and the preset number of data reading rules can be writing rules set according to address information. The preset number of data writing rules can include whether the addresses are continuous, whether they are increasing, whether the attributes are the same, etc.

[0031] As another implementation method, when the request type is a data write request, address information is obtained, and it is determined whether a preset number of data write rules are met based on the address information. When the preset number of data write rules are met, a data merging mechanism is triggered. When the data merging mechanism is completed, the cache line obtained after the processing is completed is written into the cache or memory.

[0032] It is understandable that, since data is generally written in burst units during the writing process, the data merging mechanism refers to merging data in multiple burst units into one cache line.

[0033] In an embodiment of the present application, a data processing request is received and parsed to extract the request type and address information in the data processing request, where the request type includes a data read request and a data write request. When the request type is a data read request and the address information satisfies a preset number of data read rules, a data prefetch operation is triggered, and target data is read from the cache, where the target data is prefetched from the memory and loaded into the cache; and / or, when the request type is a data write request and the address information satisfies a preset number of data write rules, a data merge operation is triggered to write the cache line into the cache or the memory. The technical solution in the present application can determine in real time whether it is a large number of data read operations with continuous addresses by checking whether a preset number of data read rules are met. When it is a large number of data read operations, a data pre-fetch operation is triggered, so that the target data is pre-fetched and loaded into the cache in advance, so as to facilitate real-time acquisition of data when a request arrives, reduce the time for reading data from the memory when a request arrives, and improve the data reading efficiency; when it is a data write operation and it is a large number of data write operations, there is no need to read and replace data from the memory or cache each time. By directly triggering the data merge operation, multiple data are written to the cache or memory only after the merge is completed, which reduces the data replacement time for each burst unit, thereby improving the data writing efficiency.

[0034] In an optional embodiment of the present application, the rules for reading the preset number of data include: continuous addresses, increasing addresses, the same data size each time read, the same address attributes, and continuous reading of a preset number of bytes; the rules for writing the preset number of data include: continuous addresses, increasing addresses, the same data size each time written, the same address attributes, and continuous writing of a preset number of bytes.

[0035] It should be noted that the above-mentioned preset number of data read rules and preset number of data write rules are to identify and optimize the data relocation behavior of a large number of consecutive addresses. These preset number of data read rules are to ensure that the system can effectively detect read requests that meet specific patterns and take corresponding optimization measures, such as pre-fetching data to reduce the probability of cache misses. These preset number of data write rules are to ensure that the system can effectively detect write requests that meet specific patterns and take corresponding optimization measures, such as performing merge data processing.

[0036] Among them, address continuity means that the addresses of the read requests are continuous without interruption. For example: if the address of the first read request is 0x1000, the address of the second read request is 0x1004, and the address of the third read request is 0x1008, then these addresses are continuous. Address continuity ensures that data is stored continuously in the memory, which is convenient for efficient pre-fetching and batch processing. Address increment means that the address of each read request is incremented relative to the previous address, and the increment is fixed. For example: if the address of each read request is 4 bytes higher than the previous address (for example, 0x1000, 0x1004, 0x1008), then these addresses are incremented. It is used to ensure that the data access pattern is linear, which is convenient for predicting the next address to be accessed, so as to perform effective pre-fetching. The same data size written each time means that the data size of each read request is the same, for example, each read request reads 4 bytes of data, which is used to ensure the consistency of each read operation, which is convenient for batch processing and pre-fetching optimization.

[0037] The same address attributes means that the address attributes of each read request are the same. Address attributes include cache attributes, buffer attributes, protection attributes, etc. For example: if the address of each read request is cacheable, bufferable, and has the same protection level (such as read-only or writable), then the address attributes are the same. It is used to ensure that all read requests are handled in a consistent manner to avoid complexity and performance loss caused by different attributes. Continuously reading a preset number of bytes means that the total number of bytes read continuously within a period of time reaches or exceeds a preset number. For example: assuming the preset number is 512 bytes, if the system detects that a series of read requests have read at least 512 bytes of data in total, then this condition is met. It is used to identify large-scale data relocation behavior by setting a threshold, thereby triggering optimization mechanisms (such as prefetching).

[0038] Specifically, when a data read request is received, it can be parsed to obtain address information, and based on the address information, it is checked whether the address is continuous, the address is incremented, the data size read each time is the same, the address attributes are the same, and a preset number of bytes are read continuously. When the following conditions are met: the address is continuous, the address is incremented, the data size read each time is the same, the address attributes are the same, and a preset number of bytes are read continuously, then the representation complies with the preset number of data reading rules. When any of the following conditions is not met: the address is continuous, the address is incremented, the data size read each time is the same, the address attributes are the same, and a preset number of bytes are read continuously, then the representation does not comply with the preset number of data reading rules. Similarly, the preset number of data writing rules are similar to the preset number of data reading rules, except that the request type is different.

[0039] In this embodiment, by setting a preset quantity data reading rule and quantity data writing rule, it is possible to effectively identify whether the current data request is a data relocation behavior of a large number of consecutive addresses, thereby further improving the efficiency and performance of data reading.

[0040] In an optional embodiment of the present application, see Figure 3 As shown, triggering a data read operation and reading target data from the cache includes the following method steps: Step 301 : Calculate the prefetch address and the number of cache lines according to pre-configured register prefetch configuration information.

[0041] Step 302: Read the target data from the memory and load it into the cache according to the pre-fetch address and the number of cache lines.

[0042] Please note that, see Figure 4 As shown, Figure 4 A schematic diagram of the interface structure of a read data stream control module (ReadStream) provided in an embodiment of the present application, wherein the ReadStream module includes multiple interfaces, each of which corresponds to a different meaning. For example, each interface may include: prefetch valid, prefetch addr, prefetch advance amount configuration, prefetch cache line number configuration, byte number configuration, arvalid, arcache, araddr, and arsize.

[0043] It can be understood that the above process of triggering data prefetching is based on bus protocols such as bus AXI (Advanced Xtensible Interface). Among them, the prefetch advance configuration refers to configuring the advance amount of the prefetch address relative to the address information of the current read request. This is a configurable value set through a register; it is used to ensure that the prefetched data can be prepared before the upstream is actually accessed, thereby reducing the probability of cache misses. The configuration of the number of prefetch cachelines refers to configuring the number of cache lines read in each prefetch operation. This is also a configurable value set through a register; it is used to adjust the number of prefetches according to the application scenario to achieve optimal performance. The byte number configuration refers to configuring the number of bytes required to read continuously to trigger the prefetch behavior. This is a configurable value set through a register; it is used to detect when the prefetch mechanism is started, that is, when a certain amount of bytes are read continuously, it is considered that this is a large number of continuous address data relocation behaviors.

[0044] The above interface may also include AXI bus protocol related signals, which may include: arvalid, arcache, araddr, and arsize. Among them, arvalid (Address Read Valid) indicates that the address information on the current read address channel is valid, which is used to indicate that the master device (such as the CPU) has placed a valid read address on the bus and is waiting for a response from the slave device (such as a memory controller). arcache indicates the cache attribute of the read transaction. It contains some flag bits, such as whether caching is allowed, whether buffering is allowed, etc., which are used to help the slave device understand how to handle the read transaction and how to manage cache consistency. araddr (Address Read Address) indicates the target address of the read transaction, which is used to tell the slave device from which memory address to start reading data. arsize (Address Read Size) indicates the size of the read transaction, that is, the data width of each transmission (for example, 1 byte, 2 bytes, 4 bytes, etc.), which is used to help the slave device determine the amount of data transmitted each time so as to correctly read and return data.

[0045] Prefetch valid is used to indicate whether the current prefetch request is valid. When this signal is high, it means that a valid prefetch operation is being processed. It is used to control the state of the prefetch operation to ensure that prefetching is performed only when required. Prefetch addr is used to indicate the memory address of the data to be prefetched, which is provided to the memory controller or DMA engine to start reading data from the specified memory address.

[0046] It can be understood that prefetch valid and prefetch addr are used to start the prefetch operation and indicate the starting address of the prefetch. The prefetch advance configuration and the prefetch cacheline number configuration are used to optimize the prefetch mechanism to ensure that the prefetched data can reach the cache in time. The byte number configuration is used to detect when to start the prefetch mechanism. arvalid, arcache, araddr and arsize are signals used for read transactions in the AXI bus protocol, indicating the validity of the read address, cache attributes, target address and data width respectively.

[0047] Specifically, when it is detected that the addresses are continuous, the addresses are increasing, the data size read each time is the same, the address attributes are the same, and a preset number of bytes are read continuously, it is determined that the preset number of data reading rules are met, then this is a data relocation row operation with a large number of continuous addresses, and the data read operation can be triggered. The prefetch advance amount and the number of cache lines prefetched each time are obtained from the register prefetch configuration information, and based on the advance amount and the number of cache lines prefetched each time, the target data is read from the memory and loaded into the cache.

[0048] In this embodiment, by triggering a data read operation, the prefetch address and the number of cache lines are first calculated, and then the data is read back from the memory in advance and pre-stored in the cache based on the prefetch address and the number of cache lines. When the upstream sends a data read request, the data can be directly obtained from the cache, saving the time of reading data from the memory and improving the data reading efficiency.

[0049] In an optional embodiment of the present application, the acquisition timestamp of the pre-fetched address is smaller than the acquisition timestamp of the address information.

[0050] It should be noted that the acquisition timestamp of the pre-fetch address refers to the time corresponding to the acquisition of the pre-fetch address, and the acquisition timestamp of the address time refers to the time corresponding to the acquisition of the data read request. The acquisition timestamp of the pre-fetch address is smaller than the acquisition timestamp of the address information, which can be understood as: the acquisition time of the pre-fetch address is earlier than the acquisition time of the address information.

[0051] It is understandable that since it takes a long time to read data from the memory, the prefetch address must be ahead of the corresponding address information in the current upstream data read request read transaction by a certain amount. This advance amount can be configured through a register. Otherwise, when the prefetched data is stored in the cache, the upstream has already accessed the cache and has started to search for data from the memory, which results in a lot of time being wasted.

[0052] Optionally, if the current address in the data read request (read transaction) sent from the upstream is smaller than the advance amount set in the register than the last address of this prefetch, then the starting address of the next prefetch can be connected to the last address of this prefetch.

[0053] In this embodiment, by setting the acquisition timestamp of the pre-fetch address to be smaller than the acquisition timestamp of the address information, it is possible to avoid wasting time by reading data from the memory when a data read request arrives, thereby ensuring that data is obtained from the cache in real time, thereby improving data reading efficiency.

[0054] In an optional embodiment of the present application, the above triggers the data merge operation to write the cache line into the cache or memory, see Figure 5 As shown, the method comprises the following steps: Step 401: Acquire data of multiple burst units according to pre-configured register merging configuration information.

[0055] Step 402: Merge data of multiple burst units to obtain a cache line, and write the cache line into a cache or memory.

[0056] Please note that, see Figure 6 As shown, in this embodiment, an interface diagram of a write data stream control module (WriteStream) is provided. The WriteStream module includes multiple interfaces, each of which corresponds to a different meaning. For example, each interface may include: byte quantity configuration, arstorb, awvalid, awcache, awaddr, awsize, and write data stream (writestream) training success flag. The WriteStream module is designed to optimize data writing operations for a large number of consecutive addresses. By merging multiple bursts into a complete cacheline and then writing, the steps of reading existing data from the cache or memory can be reduced, thereby improving efficiency.

[0057] Among them, Byte Count Configuration refers to the number of bytes that need to be written continuously to trigger the WriteStream behavior. It is used to start the WriteStream mechanism when the system detects that the total number of bytes written continuously reaches or exceeds this preset value. For example, if it is configured as 512 bytes, WriteStream will only be started when at least 512 bytes of data are written continuously.

[0058] arstorb (Address Read Store Buffer) is a signal indicating whether the current write request needs to be stored in the address read store buffer. It is used to handle special situations such as write combining to ensure that the write operation can be performed correctly. For example, if it is set to a high level, it means that the current write request needs to be stored in the address read store buffer. awvalid (Address Write Valid) indicates that the address information on the current write address channel is valid. It is used to indicate that the master device (such as the CPU) has placed a valid write address on the bus and is waiting for a response from the slave device (such as a memory controller). For example, if it is set to a high level, it means that the current write address is valid. awcache (Address Write Cache) indicates the cache attribute of the write transaction. It contains some flags, such as whether caching is allowed, whether buffering is allowed, etc., to help the slave device understand how to handle the write transaction and how to manage cache consistency. For example, it can include flags such as cache enable (C), buffer enable (B), and write allocation (W). awaddr (Address Write Address) indicates the target address of the write transaction, which is used to tell the slave device to which memory address to write data. For example, if the target address of the write transaction is 0x1000, the value of awaddr is 0x1000. awsize (Address Write Size) indicates the size of the write transaction, that is, the width of the data transferred each time (for example, 1 byte, 2 bytes, 4 bytes, etc.), which is used to help the slave device determine the amount of data transferred each time so as to write the data correctly. For example, if 4 bytes of data are written each time, the value of awsize is 2 (indicating 32 bits / 4 bytes).

[0059] The WriteStream Training Success Flag indicates whether the WriteStream module has been successfully trained and is ready for optimized write operations. It is used to ensure that the WriteStream module has completed the necessary initialization and calibration process before enabling it. For example: if it is set to a high level, it means that the WriteStream module has been successfully trained and can start optimized write operations.

[0060] It is understandable that, since the data write request transmits data in burst units, after receiving the data write request, the data may be written in burst length, which is used to characterize the number of data blocks transmitted continuously. Burst transmission is an efficient data transmission method that can transmit multiple data units in one request. It is used to improve bus utilization and reduce control overhead. For example, a burst transmission may contain 4 or 8 data units.

[0061] Specifically, when it is detected that a certain amount of bytes (the specific number of bytes can be configured by the register) of data is continuously read in a data write request with continuous addresses, increasing addresses, the same read size in each beat, and the same address attributes, it is considered that this is a large amount of data relocation behavior with continuous addresses. According to the pre-configured register merge configuration information, the data of multiple burst units are obtained, the data of multiple burst units are merged to obtain a cache line cacheline, and the cache line is written into the cache or memory memory.

[0062] In this embodiment, data of multiple burst units are obtained, the data of multiple burst units are merged to obtain a cache line, and then the cache line is written into the cache or memory, thereby reducing the steps of reading data from the memory and updating data, and improving data writing efficiency.

[0063] In an optional embodiment of the present application, before receiving and parsing the data processing request, the method further includes the following method steps: Obtain register prefetch configuration information; the register prefetch configuration information includes any one of the following: prefetch address, number of cache lines to be prefetched, number of bytes to be prefetched, advance amount of acquisition timestamp of prefetch address and acquisition timestamp of address information; configure cache according to the register prefetch configuration information.

[0064] It should be noted that in order to achieve efficient memory data prefetching, it is necessary to prefetch configuration information of the cache configuration register through registers before receiving the data processing request. The above-mentioned prefetch address refers to the memory starting address where the data to be prefetched is located, and is used to read data from the specified memory starting address. The number of cache lines prefetched refers to the number of cache lines read in each prefetch operation. The number of prefetches can be adjusted according to the application scenario to achieve optimal performance. The number of bytes prefetched refers to the total number of bytes read in each prefetch operation. It is similar to the number of cache lines prefetched, but the number of bytes is directly specified for more fine-grained control. The lead time of the acquisition timestamp of the prefetch address and the acquisition timestamp of the address information (Prefetch Lead Time) refers to the difference between the timestamp of the prefetch address and the timestamp of the current data read request address, which is used to ensure that the prefetched data can be prepared before the actual upstream access, reducing the probability of cache misses.

[0065] Specifically, when the system starts, register pre-fetch configuration information may be obtained, and according to the register pre-fetch configuration information, cache may be configured through firmware or an operating system driver, thereby implementing a configuration operation.

[0066] In this embodiment, register prefetch configuration information is obtained and cache is configured according to the register prefetch configuration information, which helps to optimize data relocation behavior of a large number of consecutive addresses, thereby improving the overall performance of the system.

[0067] In an optional embodiment of the present application, before receiving and parsing the data processing request, the method further includes the following steps: Acquire register merging configuration information; the register merging configuration information includes: the number of bytes that trigger merging; and perform configuration processing on the cache according to the register merging configuration information.

[0068] It should be noted that in order to optimize the data writing operation of a large number of consecutive addresses, the system needs to obtain register merging configuration information and configure the cache accordingly based on this information.

[0069] The number of bytes that trigger the merge (Trigger Byte Count) means that when it is detected that the total number of bytes written continuously reaches or exceeds this preset value, the merge mechanism is started to ensure that the merge operation is started only when the data volume is large enough to reduce unnecessary overhead and improve efficiency.

[0070] Specifically, in the process of performing configuration operations on the cache, register merging configuration information may be obtained through a hardware interface (such as MMIO), and the number of bytes triggering the merging may be parsed, and then the cache management module and other related modules may be configured according to the number of bytes triggering the merging.

[0071] In this embodiment, by obtaining register merging configuration information and performing configuration processing on the low cache according to the register merging configuration information, it can help optimize data writing operations for a large number of consecutive addresses, reduce unnecessary read operations, improve the overall performance of the system, and thus improve data writing efficiency.

[0072] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0073] In another embodiment provided in the present application, a data reading and writing processing device is also provided, see Figure 7 As shown, the device comprises: The receiving module 810 is used to receive and parse the data processing request, and extract the request type and address information in the data processing request; the request type includes a data read request and a data write request; The reading module 820 is used to trigger a data pre-fetch operation and read target data from the cache when the request type is a data read request and the address information satisfies a preset quantity of data read rules, where the target data is pre-fetched from the memory and loaded into the cache; and / or, The write module 830 is used to trigger a data merge operation and write the cache line into the cache or memory when the request type is a data write request and the address information meets a preset quantity of data write rules.

[0074] Optionally, the preset number of data reading rules include: continuous addresses, increasing addresses, the same size of data read each time, the same address attributes, and continuous reading of a preset number of bytes; The rules for writing the preset number of data include: continuous addresses, increasing addresses, the same size of data written each time, the same address attributes, and continuous writing of a preset number of bytes.

[0075] Optionally, the reading module 820 is specifically configured to: Calculate the prefetch address and the number of cache lines according to the pre-configured register prefetch configuration information; Based on the prefetch address and cache line number, the target data is read from the memory and loaded into the cache.

[0076] Optionally, the acquisition timestamp of the pre-fetch address is smaller than the acquisition timestamp of the address information.

[0077] Optionally, the writing module 830 is specifically used for: Merge configuration information according to pre-configured registers to obtain data for multiple burst units; The data of multiple burst units are merged to obtain a cache line, and the cache line is written into the cache or memory.

[0078] Optionally, the above device is also used for: Obtain register prefetch configuration information; the register prefetch configuration information includes any one of the following: a prefetch address, a number of cache lines to be prefetched, a number of bytes to be prefetched, an advance amount of an acquisition timestamp of the prefetch address and an acquisition timestamp of the address information; The cache is configured according to the register prefetch configuration information.

[0079] Optionally, the above device is also used for: Obtain register merging configuration information; the register merging configuration information includes: the number of bytes that trigger the merging; The cache is configured based on the register merge configuration information.

[0080] For the specific definition of the above-mentioned data reading and writing processing device, please refer to the definition of the data reading and writing processing method above, which will not be repeated here. Each module in the above-mentioned data reading and writing processing device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0081] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 1 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data reading and writing processing method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the data reading and writing processing method as described above is implemented.

[0082] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above data reading and writing processing method can be implemented.

[0083] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0084] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0085] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0086] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0087] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0088] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data reading and writing processing method, characterized in that: The data reading and writing processing method comprises: Receive and parse a data processing request, and extract a request type and address information from the data processing request; the request type includes a data read request and a data write request; When the request type is a data read request and the address information satisfies a preset quantity data read rule, a data prefetch operation is triggered, and target data is read from the cache, wherein the target data is prefetched from the memory and loaded into the cache; and / or, When the request type is a data write request and the address information satisfies a preset quantity data write rule, a data merge operation is triggered to write the cache line into the cache or memory.

2. The method according to claim 1, characterized in that The preset number of data reading rules include: continuous addresses, increasing addresses, the same size of data read each time, the same address attributes, and continuous reading of a preset number of bytes; The preset number of data writing rules include: continuous addresses, increasing addresses, the same size of data written each time, the same address attributes, and continuous writing of a preset number of bytes.

3. The method according to claim 1, characterized in that Triggering a data read operation and reading target data from the cache, including: Calculate the prefetch address and the number of cache lines according to the pre-configured register prefetch configuration information; According to the pre-fetch address and the number of cache lines, target data is read from a memory and loaded into the cache.

4. The method according to claim 3, characterized in that The acquisition timestamp of the pre-fetch address is smaller than the acquisition timestamp of the address information.

5. The method according to claim 1, characterized in that: Triggering a data merge operation to write a cache line into the cache or memory, including: Merge configuration information according to pre-configured registers to obtain data for multiple burst units; The data of the multiple burst units are merged to obtain a cache line, and the cache line is written into the cache or memory.

6. The method according to claim 3, characterized in that Before receiving and parsing the data processing request, the method further includes: Obtain register prefetch configuration information; the register prefetch configuration information includes any one of the following: a prefetch address, a number of cache lines to be prefetched, a number of bytes to be prefetched, an advance amount of an acquisition timestamp of the prefetch address and an acquisition timestamp of the address information; The cache is configured according to the register pre-fetch configuration information.

7. The method according to claim 4, characterized in that Before receiving and parsing the data processing request, the method further includes: Acquire register merging configuration information; the register merging configuration information includes: the number of bytes that trigger the merging; The cache is configured according to the register merging configuration information.

8. A data reading and writing processing device, characterized in that: The data reading and writing processing device comprises: A receiving module, used to receive and parse a data processing request, and extract a request type and address information from the data processing request; the request type includes a data read request and a data write request; a reading module, configured to trigger a data pre-fetch operation and read target data from the cache when the request type is a data read request and the address information satisfies a preset quantity of data read rules, wherein the target data is pre-fetched from the memory and loaded into the cache; and / or, The writing module is used to trigger a data merging operation and write the cache line into the cache or memory when the request type is a data writing request and the address information satisfies a preset quantity of data writing rules.

9. A computer device comprising: A memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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