Compiling configuration method and system, compiler and many-core processor

Abstract

The invention discloses a compiling configuration method and system, a compiler and a many-core processor, the configuration method comprises an architecture mapping method, and the architecture mapping method comprises the following steps: mapping a first service component of a programming platform to a second service component of the many-core processor; working groups and working items, used for organizing parallel computing tasks, of the programming platform are mapped to an execution unit for many-core processing; and various memories of the programming platform are mapped to a memory structure of the many-core processor. Based on the compiling configuration method, the platform architecture, the execution architecture and the memory architecture of the general programming platform are mapped to the many-core processors, so that a source program provided by a high-level programming platform can be correctly and efficiently executed on any one of the many-core processors. Therefore, by means of the configuration method, any many-core processor can support the heterogeneous computing program provided by the universal programming platform, and the development cost of programming based on the many-core processor oriented to the heterogeneous architecture is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of heterogeneous computing program compilation, and in particular to a compilation configuration method, system, compiler and many-core processor. Background Art

[0002] With the continuous growth of computing demand and the expansion of data processing scale, heterogeneous computing platforms play an increasingly important role in modern computing systems. Heterogeneous computing combines different types of processors, such as CPU, GPU and many-core processors, to give full play to their respective advantages and achieve efficient parallel computing. Many-core processors, as an important component of heterogeneous computing platforms, have a large number of computing cores and high parallel processing capabilities, and are widely used in high-performance computing, artificial intelligence, image processing and other fields. However, the programming complexity of heterogeneous computing and the differences between different hardware platforms have brought huge challenges to program development and compilation.

[0003] SYCL (Single Source Code Multi-Device Programming) is an open parallel programming standard and model that aims to simplify the development of heterogeneous computing programs. SYCL allows developers to use a unified code framework to write parallel computing programs so that they can be executed on different computing devices. Although current mainstream GPU manufacturers (such as AMD, Intel, etc.) have provided SYCL implementations based on their GPUs to reduce the difficulty for developers to develop heterogeneous computing programs, they have not yet provided complete SYCL support for some heterogeneous multi-core processors. When facing heterogeneous multi-core processors, the existing SYCL compiler solution does not support SYCL program compilation for heterogeneous multi-core processor computing devices, which brings inconvenience to program development for multi-core processors through SYCL. Summary of the invention

[0004] The object of the present invention is to provide a compilation configuration method, system, compiler and many-core processor that enable a many-core processor to adapt to a general programming platform.

[0005] In order to achieve the above-mentioned object, the present invention discloses a compilation configuration method based on heterogeneous architecture parallel processing, which is used to compile a source program provided by a general programming platform for a multi-core processor based on a heterogeneous architecture, including an architecture mapping method, and the architecture mapping method includes:

[0006] Mapping a first service component of the programming platform to a second service component of the many-core processor;

[0007] Mapping workgroups and work items of the programming platform for organizing parallel computing tasks onto execution units of the many-core processing;

[0008] Various types of memory of the programming platform are mapped to the memory structure of the many-core processor.

[0009] Preferably, the first service component includes a host side and a device side, the host side is a control core for processing program branches and logics, and the device side is a core for performing parallel computing; the many-core processor includes a plurality of core groups, the second service component includes a management core and a computing core corresponding to each of the core groups, the computing core includes a plurality of computing management units, and the computing management units are used to allocate and schedule parallel computing tasks;

[0010] The host end is mapped to the management core, and the device end is mapped to the computing core.

[0011] Preferably, the execution unit includes a calculation management unit for allocating and scheduling parallel computing tasks and a calculation unit for executing specific computing tasks, the work group is mapped to the calculation management unit, and the work item is mapped to the calculation unit.

[0012] Preferably, the host memory, global memory, and constant memory of the programming platform are mapped to the main memory of the many-core processor, the local memory of the programming platform is mapped to the local memory of the many-core processor, and the private memory of the programming platform is mapped to the register of the many-core processor.

[0013] Preferably, it also includes a compilation optimization method for optimizing the intermediate files generated during the compilation process, and the compilation optimization method includes one or more of the following four optimization methods;

[0014] Optimization method 1:

[0015] Obtaining an intermediate representation code containing a nested loop in the intermediate file to obtain a first code to be processed;

[0016] Scan each memory access operation in the first code, and record the accessed memory address, access frequency and mode to generate an analysis report of the memory access mode;

[0017] Based on the analysis report and in combination with the first code, determining data blocks that need to be transferred using direct memory access (DMA) to formulate a DMA transfer strategy;

[0018] According to the loop structure in the first code, the large data block to be transmitted is divided into small blocks suitable for DMA transmission to generate a block strategy;

[0019] Performing address mapping according to the memory address information in the first code, replacing the original memory address with the on-chip memory address to generate a new memory address mapping table;

[0020] updating the storage mode of the intermediate file in the on-chip memory according to the analysis report, the DMA transfer strategy, the block measurement and the memory address mapping table to generate a new intermediate representation code;

[0021] Optimization method 2:

[0022] Merging several single kernels in the computing program recorded in the intermediate file, each of which is used to execute different computing tasks; and / or,

[0023] When a single kernel for executing a certain computing task in the computing program recorded in the intermediate file is called multiple times by iteration, merging the computing tasks of the multiple iterations into one kernel call;

[0024] Optimization method three:

[0025] Perform the same operation on multiple data elements through the SIMD instruction set;

[0026] Using registers inside the many-core processor to exchange data;

[0027] Optimization method 4:

[0028] The computational data is vectorized and data storage and loading are performed using a single instruction multiple data approach.

[0029] The present invention also provides a compiler for compiling a source program provided by a general programming platform into a multi-core processor based on a heterogeneous architecture, the compiler comprising a mapping module, the mapping module comprising a first mapping unit, a second mapping unit and a third mapping unit;

[0030] The first mapping unit is used to map the first service component of the programming platform to the second service component of the many-core processor;

[0031] The second mapping unit is used to map the work group and work item of the programming platform for organizing parallel computing tasks to the execution unit of the many-core processing, the work group is used to manage and schedule computing tasks, and the work item is used to process a specific computing task;

[0032] The third mapping unit is used to map various types of memory of the programming platform to the memory structure of the many-core processor.

[0033] Preferably, the first service component includes a host side and a device side, the host side is a control core for processing program branches and logics, and the device side is a core for performing parallel computing; the many-core processor includes a plurality of core groups, the second service component includes a management core and a computing core corresponding to each of the core groups, the computing core includes a plurality of computing management units, and the computing management units are used to allocate and schedule parallel computing tasks;

[0034] The first mapping unit is used to map the host end to the management core, and map the device end to the computing core.

[0035] Preferably, the execution unit includes an operation management unit for allocating and scheduling parallel computing tasks and an operation unit for executing specific computing tasks, and the second mapping unit is used to map the work group to the operation management unit and map the work item to the operation unit.

[0036] Preferably, the third mapping unit is used to map the host memory, global memory, and constant memory of the programming platform to the main memory of the many-core processor, and to map the local memory of the programming platform to the local memory of the many-core processor, and to map the private memory of the programming platform to the registers of the many-core processor.

[0037] Preferably, it further comprises an optimization module, wherein the optimization module is used to optimize the intermediate files generated during the compilation process, and the optimization module comprises one or more of a first optimization unit, a second optimization unit, a third optimization unit, and a fourth optimization unit;

[0038] The first optimization unit includes a preprocessing unit, a memory access analysis unit, a storage access decision unit, a blocking unit, an address replacement unit and an update unit;

[0039] The preprocessing unit is used to obtain the intermediate representation code containing the nested loop in the intermediate file to obtain the first code to be processed;

[0040] The memory access analysis unit is used to scan each memory access operation in the first code and record the accessed memory address, access frequency and mode to generate an analysis report of the memory access mode;

[0041] The storage access decision unit is used to determine the data blocks that need to be transferred using direct memory access (DMA) based on the analysis report and in combination with the first code, so as to formulate a DMA transfer strategy;

[0042] The block division unit is used to divide the large data blocks to be transmitted into small blocks suitable for DMA transmission according to the loop structure in the first code, so as to generate a block division strategy;

[0043] The address replacement unit is used to perform address mapping according to the memory address information in the first code, and replace the original memory address with the on-chip memory address to generate a new memory address mapping table;

[0044] The updating unit updates the storage mode of the intermediate file in the on-chip memory according to the analysis report, the DMA transmission strategy, the block measurement and the memory address mapping table to generate a new intermediate representation code;

[0045] The second optimization unit is used to merge several single kernels respectively used to execute different computing tasks in the computing program recorded in the intermediate file; and / or,

[0046] When a single kernel for executing a certain computing task in the computing program recorded in the intermediate file is called multiple times by iteration, merging the computing tasks of the multiple iterations into one kernel call;

[0047] The third optimization unit is used to execute the same operation of multiple data elements through a single instruction multiple data instruction set, and to exchange data using registers inside the many-core processor;

[0048] The fourth optimization unit is used to vectorize the calculation data and perform data storage and loading through single instruction multiple data.

[0049] The present invention also provides an acceleration device, which includes a multi-core processor based on a heterogeneous architecture and a compiler, wherein the compiler compiles and configures the multi-core processor based on the compilation configuration method as described above.

[0050] The present invention also provides a compilation configuration system based on heterogeneous architecture parallel processing, which includes:

[0051] one or more processors;

[0052] Memory;

[0053] and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the programs include instructions for executing the compilation configuration method as described above.

[0054] The present invention also provides a computer-readable storage medium, which includes a computer program, and the computer program can be executed by a processor to complete the compilation configuration method as described above.

[0055] The present invention also provides a computer program product, including a computer program, which implements the above-mentioned compilation configuration method when executed by a processor.

[0056] Compared with the prior art, the compilation configuration method provided by the above technical solution of the present invention maps the platform architecture, execution architecture and memory architecture of the general programming platform to the many-core processor, so that the source program provided by the high-level programming platform can be correctly and efficiently executed on any many-core processor. It can be seen that through the above configuration method, any many-core processor can support the heterogeneous computing program provided by the general programming platform, reducing the development cost of programming based on many-core processors for heterogeneous architectures. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic diagram of hardware architecture mapping in an embodiment of the present invention.

[0058] Figure 2 This is a schematic diagram of the service architecture mapping principle in an embodiment of the present invention.

[0059] Figure 3 It is a schematic diagram of the execution architecture mapping in an embodiment of the present invention.

[0060] Figure 4 This is a schematic diagram of the memory architecture mapping principle in an embodiment of the present invention.

[0061] Figure 5 This is a flow chart of on-chip storage optimization in an embodiment of the present invention.

[0062] Figure 6 This is an optimization flowchart for merging different inner loops in an embodiment of the present invention.

[0063] Figure 7 This is an optimization flow chart for merging different iteration times of the same inner loop in an embodiment of the present invention.

[0064] Figure 8 This is a flow chart of the compilation principle of a multi-core processor in an embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0066] Many-core processors based on heterogeneous architecture are the main components of computing acceleration devices. Since many-core processors have multiple core groups running in parallel, acceleration devices can execute programs on them in parallel to reduce computing time.

[0067] Since general programming platforms (such as the single-source heterogeneous computing C++ programming platform, also known as the SYCL platform) have powerful and standard program development capabilities, they are generally favored by program developers. Developers are more willing to use such programming platforms to develop programs for many-core processors. However, since programming platforms and different many-core processors have their own design characteristics and operating methods in hardware architecture, such programming platforms cannot be directly used to develop programs for any many-core processor.

[0068] To solve the above problems, the present embodiment discloses a compilation configuration method based on heterogeneous architecture parallel processing, which is used to configure the compilation environment for compiling a source program provided by a universal programming platform for a many-core processor based on a heterogeneous architecture, so that the source program can be executed on the many-core processor. The compilation configuration method includes an architecture mapping method, such as Figure 1 The architecture mapping method includes the following steps:

[0069] S10: Mapping the first service component of the programming platform to the second service component of the many-core processor to complete the service architecture mapping between the programming platform and the many-core processor;

[0070] S11: Mapping the workgroup and work item of the programming platform for organizing parallel computing tasks to the execution unit of the many-core processor to complete the execution architecture mapping between the programming platform and the many-core processor, the workgroup is used to manage and schedule computing tasks, and the work item is used to process a specific computing task;

[0071] S12: Mapping various types of memory of the programming platform to the memory structure of the many-core processor, and mapping the memory architecture between the programming platform and the many-core processor.

[0072] It should be noted that there is no requirement for the execution order of the above steps S10, S11, and S12.

[0073] In this embodiment, the platform architecture, execution architecture, and memory architecture of the general programming platform are mapped to the many-core processor, so that the source program provided by the high-level programming platform can be correctly and efficiently executed on any many-core processor. It can be seen that through the above configuration method, any many-core processor can support the heterogeneous computing program provided by the general programming platform, reducing the development cost of programming based on many-core processors for heterogeneous architectures.

[0074] like Figure 2 The first service component includes a host side and a device side. The host side is a control core for processing program branches and logics, and the device side is a core for executing parallel operations.

[0075] The many-core processor includes several core groups. The second service component includes a management core MPE and computing cores CPEs corresponding to each core group. The computing cores CPEs include several computing management units CPE. The computing management units CPE are used to allocate and schedule parallel computing tasks.

[0076] The host side is mapped to the management core MPE, and the device side is mapped to the computing core CPEs, so that the host tasks and device tasks in the source program provided by the programming platform can be executed on the specific many-core processor.

[0077] like Figure 3 The execution unit includes a computing management unit CPE for allocating and scheduling parallel computing tasks and a computing unit PE for executing specific computing tasks. The work group is mapped to the computing management unit CPE, and the work item is mapped to the computing unit PE. In this way, the parallel computing tasks in the source program provided by the programming platform can be executed on the execution unit on the specific many-core processor.

[0078] In the programming platform, a work group is a collection of multiple work items. It is the middle level in the programming platform, which groups a large number of work items for easy management and scheduling.

[0079] CPE is the computing unit in the multi-core processor. It has complete control logic and execution capabilities and can independently perform complex computing tasks. CPE is usually composed of multiple PEs to form a computing cluster. CPE is responsible for allocating and scheduling parallel tasks in the multi-core processor and dividing these tasks into more fine-grained subtasks to be executed by the internal PEs.

[0080] PE is a smaller and more fine-grained computing unit inside CPE, equivalent to a thread or subtask, responsible for specific computing operations. In hardware implementation, PEs share the control logic and memory resources of CPE, but have greater independence when executing tasks.

[0081] CPE and PE together constitute the computing architecture of the many-core processor. CPE is responsible for decomposing tasks and assigning them to PE for execution, while PE completes the actual computing tasks through parallel computing.

[0082] like Figure 4 , map the host memory, global memory, and constant memory of the programming platform to the main memory of the many-core processor, map the local memory of the programming platform to the local memory of the many-core processor, and map the private memory of the programming platform to the register of the many-core processor. In this way, the memory operations in the source program provided by the programming platform can be executed on the memory structure of the specific many-core processor.

[0083] On the other hand, the compilation configuration method of the present invention also includes a compilation optimization method for optimizing the intermediate files generated during the compilation process, and the working efficiency of the multi-core processor is improved by optimizing the intermediate files. The compilation optimization method in this embodiment includes one or more of the following four optimization methods.

[0084] Optimization method 1, such as Figure 5 , including the following steps:

[0085] Obtaining nested loop IR (intermediate representation code): obtaining the intermediate representation code containing the nested loop in the intermediate file to obtain the first code to be processed.

[0086] Memory access analysis: Scan each memory access operation in the first code and record the accessed memory address, access frequency and mode to generate an analysis report of the memory access mode, providing basic information on data access behavior for subsequent optimization;

[0087] DMA decision: Based on the analysis report and in combination with the first code, determine the data blocks that need to be transferred using direct memory access DMA to formulate a DMA transfer strategy;

[0088] DMA block division: according to the loop structure in the first code, the large data block to be transmitted is divided into small blocks suitable for DMA transmission to generate a block division strategy;

[0089] Address replacement: performing address mapping according to the memory address information in the first code, replacing the original memory address with the on-chip memory address to generate a new memory address mapping table;

[0090] Code update: Update the storage method of intermediate files in on-chip memory based on the analysis report, DMA transfer strategy, block measurement, and memory address mapping table to generate new intermediate representation code.

[0091] Based on this optimization method 1, the following improvements can be made to the many-core processor:

[0092] 1. Improve data access speed

[0093] By analyzing memory access and optimizing data locality and reuse, the latency of memory access can be reduced.

[0094] By replacing addresses, frequently accessed data is placed in on-chip memory, significantly improving data access speed.

[0095] 2. Reduce bus bandwidth requirements

[0096] Through DMA blocking, large data is divided into small blocks and transmitted block by block, reducing the time of each transmission and thus reducing the demand for bus bandwidth.

[0097] Through DMA decision-making, data transfer path and timing are optimized to further reduce bus burden.

[0098] 3. Optimize computing resource utilization

[0099] By obtaining the nested loop IR and performing optimization to generate the optimized SPM IR (SPM is an on-chip storage resource, usually used as fast temporary data storage), the on-chip storage resources can be fully utilized by rearranging and blocking the data to improve the parallelism and efficiency of data processing.

[0100] 4. Reduce CPU burden

[0101] Through the use of DMA decision and DMA block, the data transmission can be handled by the DMA controller, reducing the burden on the CPU, and the CPU can focus on computing tasks instead of data movement.

[0102] 5. Improve overall system performance

[0103] Comprehensively utilize on-chip storage optimization technology to reduce memory access latency, improve data transmission efficiency, optimize computing resource utilization, and ultimately improve the computing performance of the entire many-core processor.

[0104] The second optimization method is kernel merging optimization, which includes two main methods: merging different kernels and merging different iterations of the same kernel. The following is a detailed description of these two merging optimizations.

[0105] 1. Merging of different kernels

[0106] In heterogeneous computing programs, multiple kernels usually perform different computing tasks. In the traditional execution model, these kernels are called separately to perform corresponding computing tasks. However, this approach may lead to frequent kernel calls and context switches, increase the number of data transfers between memory and processor, and thus lead to performance degradation. Figure 6 , Computational program 1 and computational program 2 represent a parallel computational program respectively, which are combined into one parallel computational program after kernel merging and optimization, i.e., a fused computational program. Figure 6 In the program, tmp represents a temporary variable used in the program.

[0107] Therefore, several single cores respectively used to execute different computing tasks in the computing programs recorded in the intermediate files can be merged to improve the performance of the multi-core processor.

[0108] Specifically, the kernel calls in the computing program are analyzed to determine which kernel computing tasks can be merged, which usually includes dependency analysis to ensure that the merged kernels can still be executed correctly.

[0109] In this optimization method, the codes of different kernels are integrated into a larger kernel. This requires refactoring the kernel code to ensure that the logic of the integrated code is correct. For example, kernel A and kernel B execute task 1 and task 2 respectively, and they are merged into kernel C to execute task 1 and task 2.

[0110] By merging different kernels, the number of kernel calls is reduced and the context switching overhead is reduced. This can reduce the number of data transfers and optimize the locality of data access.

[0111] 2. Merging different iterations of the same kernel

[0112] In many computing tasks, such as neural network training, a kernel may be called multiple times. Each time the kernel is called, there is an initialization and cleanup overhead. This overhead will accumulate in large-scale iterations and affect the overall performance. Figure 7 , output(i) represents the output result of the i-th iteration of the parallel computing program; tmp(i) represents the value of the temporary variable tmp at the i-th iteration, that is, the output result of the i-th iteration of the auxiliary program that assists the running of the parallel computing program; the fused computing program represents the fused parallel computing program after the kernel merging optimization.

[0113] Therefore, when a single kernel for executing a certain computing task in a computing program recorded in an intermediate file is called multiple times by iteration, the computing tasks of the multiple iterations are merged into one kernel call.

[0114] In addition, merging the computational tasks of multiple iterations into one kernel call requires refactoring the kernel code so that it can handle tasks of multiple iterations.

[0115] It should be noted that, for the above two kernel merging optimization methods, one or both of them can be selected for use.

[0116] Optimization method three is on-chip communication optimization, which includes the following two aspects:

[0117] 1. Execute the same operation on multiple data elements through the single instruction multiple data instruction set SIMD, realize the same operation on multiple data elements, realize parallel calculation of data, reduce execution time, and improve data processing speed;

[0118] 2. Use registers inside the multi-core processor to exchange data to reduce dependence on external memory, thereby reducing communication latency.

[0119] For optimization method 4, it is mainly inter-thread vectorization, including:

[0120] Vectorize the computational data and perform data storage and loading through SIMD to improve program execution performance.

[0121] In summary, the compilation configuration method based on heterogeneous architecture parallel processing of the present invention includes the mapping of the hardware architecture and the optimization of the intermediate file compilation process, so that any multi-core processor can support a general programming platform (such as the SYCL platform), thereby comprehensively improving the computing power and efficiency of the multi-core processor.

[0122] The following describes in detail the use process of the above compilation configuration method.

[0123] like Figure 8 After receiving the heterogeneous computing program provided by the SYCL platform through the front end, the many-core processor processes the computing program into an intermediate code representation IR, and divides it into two parts, namely the program Host IR executed on the host side and the parallel program Kernel IR executed on the device side.

[0124] For Host IR, it is converted into a binary target program host.o through llc.

[0125] Among them, llc is a component in LLVM (low-level virtual machine), which can compile LLVM IR into binary target files.

[0126] For Kernel IR, through the above hardware architecture mapping relationship, the many-core processor enables corresponding functional components to run to generate an intermediate code representation Kernel2IR that is compatible with the hardware architecture of the many-core processor.

[0127] Then, Kernel2 IR is optimized by the above optimization method to obtain the optimized program Kernel3IR.

[0128] Next, llc is used to convert Kernel3IR into a binary target program Kernel.o.

[0129] Finally, the binary target program host.o, Kernel.o and the library files of the SYCL platform are linked into an executable file through the Linker to generate a binary executable file EXE.

[0130] Among them, Linker is the linker in the compiler that is responsible for linking the compiled target files and library files into executable files.

[0131] Another preferred embodiment of the present invention further discloses a compiler for compiling a source program provided by a general programming platform into a multi-core processor based on a heterogeneous architecture. The compiler includes a mapping module, and the mapping module includes a first mapping unit, a second mapping unit and a third mapping unit.

[0132] The first mapping unit is used to map the first service component of the programming platform to the second service component of the many-core processor.

[0133] The second mapping unit is used to map the working group and work item of the programming platform for organizing parallel computing tasks to the execution unit of the multi-core processing, the working group is used to manage and schedule computing tasks, and the work item is used to process a specific computing task.

[0134] The third mapping unit is used to map various types of memory of the programming platform to the memory structure of the many-core processor.

[0135] On the other hand, the first service component includes a host side and a device side, the host side is a control core for processing program branches and logics, and the device side is a core for performing parallel computing; the many-core processor includes a plurality of core groups, the second service component includes a management core and a computing core corresponding to each core group, the computing core includes a plurality of computing management units, and the computing management units are used to allocate and schedule parallel computing tasks;

[0136] The first mapping unit is used to map the host end to the management core and map the device end to the computing core.

[0137] The execution unit includes an operation management unit for allocating and scheduling parallel computing tasks and an operation unit for executing specific computing tasks. The second mapping unit is used to map the work group to the operation management unit and map the work item to the operation unit.

[0138] On the other hand, the third mapping unit is used to map the host memory, global memory, and constant memory of the programming platform to the main memory of the many-core processor, and to map the local memory of the programming platform to the local memory of the many-core processor, and to map the private memory of the programming platform to the register of the many-core processor.

[0139] On the other hand, the compiler further includes an optimization module, which is used to optimize the intermediate files generated during the compilation process, and the optimization module includes one or more of a first optimization unit, a second optimization unit, a third optimization unit, and a fourth optimization unit;

[0140] A first optimization unit, including a preprocessing unit, a memory access analysis unit, a storage access decision unit, a blocking unit, an address replacement unit and an update unit;

[0141] A preprocessing unit, used for obtaining an intermediate representation code containing a nested loop in an intermediate file to obtain a first code to be processed;

[0142] A memory access analysis unit, used to scan each memory access operation in the first code, and record the accessed memory address, access frequency and mode, so as to generate an analysis report of the memory access mode;

[0143] A storage access decision unit, configured to determine, based on the analysis report and in combination with the first code, a data block that needs to be transferred using direct memory access (DMA) so as to formulate a DMA transfer strategy;

[0144] A block division unit, for dividing a large data block to be transmitted into small blocks suitable for DMA transmission according to a loop structure in the first code, so as to generate a block division strategy;

[0145] An address replacement unit, used for performing address mapping according to the memory address information in the first code, replacing the original memory address with the on-chip memory address to generate a new memory address mapping table;

[0146] An updating unit, which updates the storage method of the intermediate file in the on-chip memory according to the analysis report, the DMA transmission strategy, the block measurement, and the memory address mapping table to generate a new intermediate representation code;

[0147] A second optimization unit is used to merge several single kernels respectively used to execute different computing tasks in the computing program recorded in the intermediate file; and / or,

[0148] When a single kernel for executing a certain computing task in the computing program recorded in the intermediate file is called multiple times in iterations, the computing tasks of the multiple iterations are merged into one kernel call;

[0149] A third optimization unit, configured to execute the same operation of multiple data elements through a single instruction multiple data instruction set, and to exchange data using registers inside the many-core processor;

[0150] The fourth optimization unit is used to vectorize the calculation data and perform data storage and loading through single instruction multiple data.

[0151] It is worth noting that the working principle and working process of the compiler in this embodiment are detailed in the above-mentioned compilation configuration method, which will not be repeated here.

[0152] In another preferred embodiment of the present invention, an acceleration device is also disclosed, which includes a multi-core processor based on a heterogeneous architecture and a compiler, and the compiler compiles and configures the multi-core processor based on the compilation configuration method in the above embodiment.

[0153] The present invention also discloses a compilation configuration system, which includes one or more processors, a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by the one or more processors, and the program includes instructions for executing the compilation configuration method as described above. The processor can adopt a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, for executing related programs to implement the functions required to be executed by the modules in the compilation configuration system of the embodiment of the present application, or to execute the compilation configuration method of the method embodiment of the present application.

[0154] The present invention also discloses a computer-readable storage medium, which includes a computer program, and the computer program can be executed by a processor to complete the compilation configuration method as described above. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium can be a read-only memory (ROM), or a random access memory (RAM), or a magnetic medium, such as a floppy disk, a hard disk, a tape, a magnetic disk, or an optical medium, such as a digital versatile disc (DVD), or a semiconductor medium, such as a solid state drive (SSD).

[0155] The embodiment of the present application also discloses a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of an electronic device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the electronic device executes the above-mentioned compilation configuration method.

[0156] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A compilation configuration method based on heterogeneous architecture parallel processing, used for compiling a source program provided by a general programming platform for a multi-core processor based on a heterogeneous architecture, characterized in that: A method for architecture mapping is included, the method for architecture mapping comprising: Mapping a first service component of the programming platform to a second service component of the many-core processor; Mapping a work group and a work item of the programming platform for organizing parallel computing tasks to an execution unit of the many-core processing, wherein the work group is used to manage and schedule computing tasks, and the work item is used to process a specific computing task; Various types of memory of the programming platform are mapped to the memory structure of the many-core processor.

2. The compilation configuration method according to claim 1, characterized in that: The first service component includes a host side and a device side, the host side is a control core for processing program branches and logics, and the device side is a core for performing parallel computing; the many-core processor includes a plurality of core groups, the second service component includes a management core and a computing core corresponding to each of the core groups, the computing core includes a plurality of computing management units, and the computing management unit is used to allocate and schedule parallel computing tasks; The host end is mapped to the management core, and the device end is mapped to the computing core.

3. The compilation configuration method according to claim 1, characterized in that: The execution unit includes a calculation management unit for allocating and scheduling parallel computing tasks and a calculation unit for executing specific computing tasks. The work group is mapped to the calculation management unit, and the work item is mapped to the calculation unit.

4. The compilation configuration method according to claim 1, characterized in that: The host memory, global memory and constant memory of the programming platform are mapped to the main memory of the many-core processor, the local memory of the programming platform is mapped to the local memory of the many-core processor, and the private memory of the programming platform is mapped to the register of the many-core processor.

5. The compilation configuration method according to claim 1, characterized in that: It also includes a compilation optimization method for optimizing the intermediate files generated during the compilation process, wherein the compilation optimization method includes one or more of the following four optimization methods; Optimization method 1: Obtaining an intermediate representation code containing a nested loop in the intermediate file to obtain a first code to be processed; Scan each memory access operation in the first code, and record the accessed memory address, access frequency and mode to generate an analysis report of the memory access mode; Based on the analysis report and in combination with the first code, determining data blocks that need to be transferred using direct memory access (DMA) to formulate a DMA transfer strategy; According to the loop structure in the first code, the large data block to be transmitted is divided into small blocks suitable for DMA transmission to generate a block strategy; Performing address mapping according to the memory address information in the first code, replacing the original memory address with the on-chip memory address to generate a new memory address mapping table; updating the storage mode of the intermediate file in the on-chip memory according to the analysis report, the DMA transfer strategy, the block measurement and the memory address mapping table to generate a new intermediate representation code; Optimization method 2: Merging several single kernels in the computing program recorded in the intermediate file, each of which is used to execute different computing tasks; and / or, When a single kernel for executing a certain computing task in the computing program recorded in the intermediate file is called multiple times by iteration, merging the computing tasks of the multiple iterations into one kernel call; Optimization method three: Perform the same operation on multiple data elements through the SIMD instruction set; Using registers inside the many-core processor to exchange data; Optimization method 4: The computational data is vectorized and data storage and loading are performed using a single instruction multiple data approach.

6. A compiler for compiling a source program provided by a general programming platform into a multi-core processor based on a heterogeneous architecture, characterized in that: The compiler comprises a mapping module, wherein the mapping module comprises a first mapping unit, a second mapping unit and a third mapping unit; The first mapping unit is used to map the first service component of the programming platform to the second service component of the many-core processor; The second mapping unit is used to map the work group and work item of the programming platform for organizing parallel computing tasks to the execution unit of the many-core processing, the work group is used to manage and schedule computing tasks, and the work item is used to process a specific computing task; The third mapping unit is used to map various types of memory of the programming platform to the memory structure of the many-core processor.

7. The compiler according to claim 6, characterized in that The first service component includes a host side and a device side, the host side is a control core for processing program branches and logics, and the device side is a core for performing parallel computing; the many-core processor includes a plurality of core groups, the second service component includes a management core and a computing core corresponding to each of the core groups, the computing core includes a plurality of computing management units, and the computing management unit is used to allocate and schedule parallel computing tasks; The first mapping unit is used to map the host end to the management core, and map the device end to the computing core.

8. The compiler according to claim 6, characterized in that The execution unit includes an operation management unit for allocating and scheduling parallel computing tasks and an operation unit for executing specific computing tasks. The second mapping unit is used to map the work group to the operation management unit and map the work item to the operation unit.

9. The compiler according to claim 6, characterized in that The third mapping unit is used to map the host memory, global memory, and constant memory of the programming platform to the main memory of the many-core processor, and to map the local memory of the programming platform to the local memory of the many-core processor, and to map the private memory of the programming platform to the register of the many-core processor.

10. The compiler according to claim 6, characterized in that It also includes an optimization module, which is used to optimize the intermediate files generated during the compilation process, and the optimization module includes one or more of a first optimization unit, a second optimization unit, a third optimization unit, and a fourth optimization unit; The first optimization unit includes a preprocessing unit, a memory access analysis unit, a storage access decision unit, a blocking unit, an address replacement unit and an update unit; The preprocessing unit is used to obtain the intermediate representation code containing the nested loop in the intermediate file to obtain the first code to be processed; The memory access analysis unit is used to scan each memory access operation in the first code and record the accessed memory address, access frequency and mode to generate an analysis report of the memory access mode; The storage access decision unit is used to determine the data blocks that need to be transferred using direct memory access (DMA) based on the analysis report and in combination with the first code, so as to formulate a DMA transfer strategy; The block division unit is used to divide the large data blocks to be transmitted into small blocks suitable for DMA transmission according to the loop structure in the first code, so as to generate a block division strategy; The address replacement unit is used to perform address mapping according to the memory address information in the first code, and replace the original memory address with the on-chip memory address to generate a new memory address mapping table; The updating unit updates the storage mode of the intermediate file in the on-chip memory according to the analysis report, the DMA transmission strategy, the block measurement and the memory address mapping table to generate a new intermediate representation code; The second optimization unit is used to merge several single kernels respectively used to execute different computing tasks in the computing program recorded in the intermediate file; and / or, When a single kernel for executing a certain computing task in the computing program recorded in the intermediate file is called multiple times by iteration, merging the computing tasks of the multiple iterations into one kernel call; The third optimization unit is used to execute the same operation of multiple data elements through a single instruction multiple data instruction set, and to exchange data using registers inside the many-core processor; The fourth optimization unit is used to vectorize the calculation data and perform data storage and loading through single instruction multiple data.

11. An acceleration device, characterized in that: It comprises a multi-core processor based on a heterogeneous architecture and a compiler, wherein the compiler compiles and configures the multi-core processor based on the compilation and configuration method according to any one of claims 1 to 5.

12. A compilation configuration system based on heterogeneous architecture parallel processing, characterized in that: include: one or more processors; Memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for executing the compilation configuration method according to any one of claims 1 to 5.

13. A computer-readable storage medium, characterized in that: The method comprises a computer program, wherein the computer program can be executed by a processor to complete the compilation configuration method according to any one of claims 1 to 5.

14. A computer program product, comprising a computer program, which, when executed by a processor, implements the compilation configuration method according to any one of claims 1 to 5.

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