Instruction processing method, processor and electronic device

Abstract

At least one embodiment of the invention provides an instruction processing method, a processor and an electronic device. The instruction processing method comprises the steps that an object instruction is extracted according to an instruction prefetching request, and the extracted object instruction is cached in an instruction cache queue; in response to instruction release information from a pipeline of the processor core, the object instruction is filled from the instruction cache queue into an instruction cache unit, and the instruction cache unit is configured to be directly accessed by the processor core. According to the instruction processing method, pollution of the instruction pre-fetched based on branch prediction to the instruction cache unit can be reduced, and the performance of the processor is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an instruction processing method, a processor, and an electronic device. Background Art

[0002] The processor cores of a single-core processor or a multi-core processor improve instruction level parallelism through pipeline technology.

[0003] Figure 1 A schematic diagram of a pipeline of a processor core is shown.

[0004] like Figure 1 As shown in FIG. 1 , the processor core includes multiple pipeline stages. The dotted lines with arrows in the figure represent redirected instruction flows. For example, after the pipeline feeds program counters from various sources and selects the next program counter (PC) through the multiplexer (Mux), the instruction corresponding to the program counter must go through branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, instruction termination, etc. Decoupling queues are set between each pipeline stage as needed, and these queues are usually first-in-first-out (FIFO) queues. For example, after the branch prediction unit, a branch prediction (BP) FIFO queue is provided to store branch prediction results; after the instruction fetch unit, an instruction cache unit (IC) FIFO is provided to cache the fetched instructions; after the instruction decoding unit, a decoding (DE) FIFO is provided to cache the decoded instructions; after the instruction distribution and renaming unit, a termination (RT) FIFO is provided to cache instructions waiting for confirmation of release after execution.

[0005] At the same time, the pipeline of the processor core also includes an instruction queue to cache instructions waiting for the instruction execution unit to execute after the instruction is distributed and renamed. In order to support high operating frequencies, each pipeline stage may contain multiple pipeline stages (clock cycles). Although each pipeline stage performs limited operations, each clock can be as short as possible, and the performance of the CPU core can be improved by increasing the operating frequency of the CPU. Each pipeline stage can also further improve the performance of the processor core by accommodating more instructions (i.e. superscalar technology). Summary of the invention

[0006] At least one embodiment of the present disclosure provides an instruction processing method, which includes: extracting object instructions according to an instruction prefetch request, and caching the extracted object instructions in an instruction cache queue; in response to instruction release information from a pipeline of a processor core, filling the object instructions from the instruction cache queue into an instruction cache unit, wherein the instruction cache unit is configured to be directly accessed by the processor core.

[0007] At least one embodiment of the present disclosure provides a processor, the processor comprising: a control logic, an instruction fetch unit, an instruction release unit, an instruction cache unit and an instruction cache queue. The instruction fetch unit is configured to fetch an object instruction according to an instruction prefetch request, and cache the fetched object instruction in the instruction cache queue; the instruction release unit is configured to provide instruction release information; the control logic is configured to, in response to the instruction release information, fill the object instruction from the instruction cache queue into the instruction cache unit, wherein the instruction cache unit is configured to be directly accessed by the instruction fetch unit.

[0008] At least one embodiment of the present disclosure provides an electronic device, wherein the electronic device includes a processor according to any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0010] Figure 1 A schematic diagram of a pipeline of a processor core is shown.

[0011] Figure 2 A schematic diagram of an instruction fetch part involving branch prediction in a processor core is shown.

[0012] Figure 3 A schematic diagram of a processor core according to at least one embodiment of the present disclosure is shown.

[0013] Figure 4 An exemplary flow chart of an instruction processing method according to at least one embodiment of the present disclosure is shown.

[0014] Figure 5 A flow chart of a L2 cache backfill operation according to at least one embodiment of the present invention is shown.

[0015] Figure 6 An exemplary operation flow chart of updating an instruction cache unit in an instruction processing method according to at least one embodiment of the present disclosure is shown.

[0016] Figure 7An exemplary operation flow chart of a monitoring operation in an instruction processing method according to at least one embodiment of the present disclosure is shown.

[0017] Figure 8 An exemplary flow chart of an instruction processing method according to at least another embodiment of the present disclosure is shown.

[0018] Fig. 9 A schematic diagram showing a processor front-end architecture according to an embodiment of the present disclosure is shown.

[0019] Fig.10 A schematic diagram showing the relationship between various queues included in a processor core in at least one embodiment of the present disclosure.

[0020] Fig.11 A schematic diagram of an electronic device provided according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0022] Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] In the existing processor (also referred to as processor core or CPU core in this disclosure) architecture, programs and data are stored in memory (such as DRAM), so there are a large number of memory read instructions (Load instructions) in the program. Since the operating frequency of the processor core is much higher than the operating frequency of the memory, it takes hundreds of processor core clocks to obtain data from the memory, which often causes the processor core to idle due to the inability to continue to run related instructions, resulting in performance loss. High-performance processor cores usually include multiple levels of cache (Cache) (such as L1 cache, L2 cache, etc.) to shorten the delay of memory access and speed up the operation speed of the processor core, but when reading data that has never been accessed or data that is kicked out due to cache size limitations, the processor core still needs to wait for dozens or even hundreds of clock cycles, which will cause performance loss.

[0024] Among the multi-level caches, the first-level cache (L1 Cache) is usually directly integrated into the processor core and directly operated by the processor core; the first-level cache L1 is very fast, but the capacity is relatively small, usually between a few KB and tens of KB, and is also divided into instruction cache (IC, used to store instructions to be executed) and data cache (DC, used to store data being processed), which is used to store the data and instructions most frequently accessed by the processor core to reduce the number of times data is read from the slower cache or memory. The second-level cache (L2 Cache, or L2 for short) may be integrated into the processor core or located outside the processor core; the speed of the second-level cache is slower than the first-level cache, but it is still very fast and can quickly respond to the CPU's read and write requests. The capacity of the second-level cache is larger than the first-level cache, and it is usually no longer subdivided into instruction cache and data cache. It is used to store data and instructions that cannot be found in the first-level cache but have been used recently or may be used again soon. The third-level cache (L3 Cache) is usually located inside the CPU package, but may be separated from the processor core or shared in a multi-core processor; the speed of the third-level cache is slower than the second-level cache, but still much faster than the main memory; the capacity of the third-level cache is larger than the second-level cache, usually between a few MB and tens of MB, further expanding the capacity of the cache to store data that cannot be found in the second-level cache but may be accessed again in the near future. In a multi-core processor, the third-level cache is usually designed as a shared cache for access by all cores to reduce cache consistency issues.

[0025] For example, each cache may include a cache miss queue. For the cache, when a read / write request or a prefetch request is not in the cache, it is necessary to go to the next level cache or read from the memory. The request and its corresponding attributes are stored in the cache miss queue until the next level cache or memory returns the data or instructions targeted by the request.

[0026] In addition, high-performance processor cores not only contain a multi-level cache architecture to save recently accessed data, but also use prefetchers to discover the processor core's access rules to data and instructions, and prefetch the data and instructions to be accessed into the cache in advance. If instructions are prefetched, the corresponding operation is called instruction prefetch, and the corresponding prefetcher is an instruction prefetcher; if data is prefetched, it is called data prefetch, and the corresponding prefetcher is a data prefetcher. The latter can be further subdivided into L1 prefetchers (prefetch to the first-level cache), L2 prefetchers (prefetch to the second-level cache), LLC data prefetchers (prefetch to the last-level cache), etc. according to the target cache location.

[0027] At present, there are many methods for instruction prefetching, such as continuous prefetching of N cache lines or continuous prefetching of +1 cache line, branch prediction method using branch prediction, instruction prefetching method for capturing specific patterns, prefetching method based on the characteristics of the cache level where the instruction is located, etc. Some processors use the instruction prefetching method based on branch prediction (Fetch-Directed Instruction Prefetch, FDIP), which can send instruction prefetch requests more accurately.

[0028] Figure 2 A schematic diagram of an instruction fetch part involving branch prediction in a processor core is shown.

[0029] like Figure 2 As shown, the front end of the processor core includes an instruction fetch unit, a decoding unit, an execution unit, an instruction release unit, a branch prediction unit, an instruction cache unit (a first-level (L1) instruction cache), a control logic, etc., and other components are omitted; the control logic is, for example, respectively arranged at locations where corresponding controls need to be implemented, such as the branch prediction address queue write control, branch prediction address queue release control, prefetch control, instruction fetch control, instruction write back control, miss instruction fetch control, etc. to be mentioned later; the processor core may include a built-in L2 cache unit (L2 Cache), or be coupled to an external L2 cache unit.

[0030] The instruction fetch unit fetches instructions based on the branch prediction unit, and obtains instruction data and provides it to the decoding unit. After decoding by the decoding unit, it is provided to the execution unit for execution. The execution unit provides execution information to the instruction release unit, and the instruction release unit provides instruction release information based on the relevant information submitted by the instruction, so as to control whether to release the instruction branch prediction address information queue.

[0031] like Figure 2As shown, the branch prediction unit is coupled to the instruction release unit and the instruction fetch unit, receives instruction release information from the instruction release unit, and provides the branch prediction information to the instruction fetch unit after performing branch prediction. For example, the branch prediction unit includes a branch prediction component and a branch prediction address information queue, and the control logic provides a branch prediction address queue release control and a branch prediction address queue write control accordingly. In the branch prediction unit, the branch prediction component performs branch prediction, and stores the branch prediction fragment, i.e., the virtual address of the instruction fragment, obtained by the branch prediction, into the branch prediction address information queue based on the branch prediction address queue write control. In addition, the physical address after address translation can also be stored in the branch prediction address information queue at the same time. While the branch prediction address information is written into the branch prediction address information queue, it will also be passed to the instruction fetch unit as instruction fetch information.

[0032] like Figure 2 As shown, the instruction fetch unit is coupled to the instruction cache unit, including an instruction fetch information queue, an instruction fetch request queue, etc., and the corresponding control logic provides instruction fetch control, prefetch control, miss instruction fetch control, etc.

[0033] After receiving the branch prediction address information from the branch prediction unit, the instruction fetch unit fills the instruction fetch information into the instruction fetch information queue, and when filling the instruction fetch information queue, a prefetch operation can be performed based on the prefetch control. In addition, whether it is an instruction prefetch operation or an instruction fetch request to the L2 cache unit (L2 Cache) caused by a miss in querying the instruction cache unit during the normal instruction fetch process, it is stored in the instruction fetch request queue and then waits for the L2 cache itself or a lower-level cache or memory to return the required instruction data; the instruction fetch request caused by a miss in querying the instruction cache unit is performed based on the miss instruction fetch control.

[0034] When the secondary cache unit obtains instruction data and fills the instruction data back to the instruction cache unit through instruction write-back control, the instruction fetch information queue is awakened by the information stored in the instruction fetch request queue, so that the instruction read operation corresponding to the instruction fetch information at the head of the instruction fetch information queue can obtain the instruction data from the instruction backfill bus. On the contrary, if the currently backfilled instruction data is not at the head of the instruction fetch information queue, the instruction data will be backfilled into the instruction cache unit; after that, the instruction data will be read out from the instruction cache unit again to complete the corresponding instruction fetch operation.

[0035] In the above-mentioned architecture design of the instruction prefetching method based on branch prediction, the instruction data is either taken from the instruction backfill bus of the secondary cache unit or read from the storage array (i.e., SRAM array) of the secondary cache unit itself. In theory, the best way is to take the instruction data directly from the backfill bus of the secondary cache unit, which can not only reduce the power consumption of the instruction accessing the storage array of the secondary cache unit itself, but also read the instruction data earlier, thereby improving the efficiency of instruction fetching. However, in reality, due to branch prediction, most of the instruction data is stored in the cache early, so that the cache has to be read repeatedly in order to obtain the instruction data. This not only increases the power consumption of the read operation, but also reduces the efficiency of instruction fetching of the CPU core. Moreover, branch prediction errors will also frequently occur in the processor, so it is difficult for the instruction prefetching based on branch prediction to avoid the instruction prefetching of the wrong path of the branch prediction error, resulting in the pollution of the instruction cache, thereby causing more cache query misses. Furthermore, the pollution caused by aggressive prefetching operations to the instruction cache is more serious.

[0036] At least one embodiment of the present disclosure provides a processor, an instruction processing method, and an electronic device.

[0037] A processor according to at least one embodiment of the present disclosure includes a control logic, an instruction fetch unit, an instruction release unit, an instruction cache unit L, and an instruction cache queue L0. The instruction fetch unit is configured to fetch a target instruction according to an instruction prefetch request, and cache the fetched target instruction in the instruction cache queue L0; the instruction release unit is configured to provide instruction release information; and the control logic is configured to fill the target instruction from the instruction cache queue L0 into the instruction cache unit L1 in response to the instruction release information.

[0038] Accordingly, the instruction processing method according to at least one embodiment of the present disclosure includes: extracting the object instruction according to the instruction prefetch request, and caching the extracted object instruction in the instruction cache queue L0; in response to the instruction release information from the processor pipeline, filling the object instruction from the instruction cache queue L0 into the instruction cache unit L1.

[0039] Here, "object instruction" is used to refer to any possible instruction as a description object; the instruction cache unit L1 is configured to be directly accessed by the processor core, and correspondingly, the secondary cache is not directly accessed by the processor core. For example, when the processor core is in the process of fetching instructions, if the query instruction cache unit does not hit, the instruction cache unit will request to read the required instruction data from the secondary cache, and return it to the processor core after obtaining the required instruction data from the secondary cache, that is, the processor core accesses the secondary cache through the instruction cache unit.

[0040] The above-mentioned embodiments of the present disclosure further add an instruction cache queue (for example, understood here as "level zero (L0) instruction cache") in addition to the instruction cache unit in the processor (or processor core), and in at least one example of the embodiment, there are further provisions for the time to fill instructions back into the instruction cache unit, thereby improving the efficiency of instruction fetching and avoiding the pollution of the instruction cache unit due to pre-fetched instructions. Here, since the instruction cache queue is added to the front end of the processor core, the control logic of the processor is also increased accordingly. These control logics in the processor core of each embodiment of the present disclosure involve the implementation of various functions in the processor, which can be centralized or distributed.

[0041] The processor according to the embodiment of the present disclosure may include, for example, a single processor core or multiple processor cores, and may be provided in the form of a separately packaged processor, or may be integrated with other functional components to provide a system-on-chip (SOC) form. For example, the processor core may adopt the micro-architecture required by the x86, ARM, RISC-V, or MIPS instruction set, and the embodiment of the present disclosure is not limited to this.

[0042] The processor and instruction processing method according to the embodiment of the present disclosure will be described below with reference to specific examples.

[0043] Figure 3 A schematic diagram of a processor core according to at least one embodiment of the present disclosure is shown, and the figure mainly shows the front end of the processor core, which involves the instruction fetching part of branch prediction.

[0044] like Figure 3 As shown, the processor core includes an instruction fetch unit, a decoding unit, an execution unit, an instruction release unit, a branch prediction unit, an instruction cache unit, an instruction cache queue, a control logic, etc., while other components are omitted; the control logic is, for example, respectively arranged at locations where corresponding control needs to be implemented, such as the branch prediction address queue write control, branch prediction address queue release control, prefetch control, instruction fetch control, instruction cache independent write back control, instruction cache write back control, miss instruction fetch control, etc. to be mentioned later; the processor core may include a built-in secondary cache unit (or simply "secondary cache"), or be coupled to a secondary cache unit outside the processor core.

[0045] The instruction fetch unit fetches instructions based on the branch prediction unit, and obtains instruction data and provides it to the decoding unit. After decoding by the decoding unit, it is provided to the execution unit for execution. The execution unit provides instruction execution end information to the instruction release unit. The instruction release unit provides instruction release information based on the relevant information submitted by the instruction, so as to control whether to release the instruction branch prediction address information queue.

[0046] In the embodiments of the present disclosure, the control logic can be implemented by microprogram or hard wiring, and the embodiments of the present disclosure are not limited to this. The execution unit includes multiple different types of functional units to process different types of operations, such as integer operations, floating-point operations, vector operations, etc. For example, the execution unit may include an arithmetic logic unit (ALU), a floating-point operation unit (FPU), a vector execution unit (Vector Execution Unit), a load / store execution unit (LSU), a special function execution unit (Special Function Execution Unit), etc., and the embodiments of the present disclosure are not limited to this.

[0047] like Figure 3 As shown, the branch prediction unit is coupled to the instruction release unit and the instruction fetch unit, receives instruction release information from the instruction release unit, and provides the branch prediction information to the instruction fetch unit after performing branch prediction. For example, the branch prediction unit includes a branch prediction component and a branch prediction address information queue, and the control logic provides a branch prediction address queue release control and a branch prediction address queue write control accordingly. In the branch prediction unit, the branch prediction component performs branch prediction, and stores the branch prediction fragment, i.e., the virtual address of the instruction fragment, obtained by the branch prediction, into the branch prediction address information queue based on the branch prediction address queue write control. In addition, the physical address after address translation can also be stored in the branch prediction address information queue at the same time. While the branch prediction address information is written into the branch prediction address information queue, it will also be passed to the instruction fetch unit as instruction fetch information.

[0048] like Figure 3 As shown, the instruction fetch unit is coupled to the instruction cache unit and the instruction cache queue, and includes an instruction fetch information queue, an instruction fetch request queue, etc. Correspondingly, the control logic provides instruction fetch control, prefetch control, miss instruction fetch control, etc.

[0049] The instruction cache unit and the instruction cache queue are coupled to each other, and are both used to cache instruction data (rather than application data processed during the instruction execution process); the instruction cache queue is also coupled to the secondary cache unit, and further, as needed, the instruction cache unit can also be coupled to the secondary cache unit, so that the instruction cache unit and the instruction cache queue can directly receive backfilled instructions from the secondary cache unit. Correspondingly, the control logic provides instruction cache unit write-back control and instruction cache queue write-back control, the former is used to backfill instruction data from the instruction cache queue to the instruction cache unit, and the latter is used to backfill instruction data from the secondary cache unit to the instruction cache queue.

[0050] For example, in at least one embodiment of the present disclosure, the instruction cache unit and the secondary cache unit can be implemented in a usual manner, and the instruction cache queue can be implemented in the same manner (including structure and control) as a usual cache unit, for example, including a static random access memory (SRAM), with a cache line as the basic data storage unit, and the address mapping method can be direct mapping, fully associative and set associative mapping, etc. The embodiments of the present disclosure do not limit the implementation method of the instruction cache queue, the instruction cache unit and the secondary cache unit.

[0051] After receiving the branch prediction address information from the branch prediction unit, the instruction fetch unit fills the instruction fetch information into the instruction fetch information queue, and when filling the instruction fetch information queue, a prefetch operation can be performed based on the prefetch control. In addition, whether it is an instruction prefetch operation or an instruction fetch request to the L2 cache unit (L2 Cache) caused by a miss in querying the instruction cache unit during the normal instruction fetch process, it is stored in the instruction fetch request queue and then waits for the L2 cache itself or a lower-level cache or memory to return the required instruction data; the instruction fetch request caused by a miss in querying the instruction cache unit is performed based on the miss instruction fetch control.

[0052] When the secondary cache unit obtains instruction data and fills the instruction data back to the instruction cache unit through instruction write-back control, the instruction fetch information queue is awakened by the information stored in the instruction fetch request queue, so that the instruction read operation corresponding to the instruction fetch information at the head of the instruction fetch information queue can obtain the instruction data from the instruction backfill bus. On the contrary, if the currently backfilled instruction data is not at the head of the instruction fetch information queue, the instruction data will be backfilled into the instruction cache unit; after that, the instruction data will be read out from the instruction cache unit again to complete the corresponding instruction fetch operation.

[0053] For example, the instruction processing method according to at least one embodiment of the present disclosure further includes: generating an instruction prefetch request according to a branch prediction result. For example, a branch prediction component of a branch prediction unit of a processor generates an instruction prefetch request according to a branch prediction result.

[0054] For example, in a processor and an instruction processing method according to at least one embodiment of the present disclosure, an object instruction is extracted according to an instruction prefetch request, including: obtaining an instruction prefetch address according to the instruction prefetch request; in response to an instruction prefetch operation according to the instruction prefetch address, sending an access request to the secondary cache L2 using the instruction prefetch address; in response to an instruction data backfill operation of the secondary cache L2, writing the object instruction corresponding to the instruction prefetch address into the instruction cache queue L0.

[0055] For example, in a processor and an instruction processing method according to at least one embodiment of the present disclosure, extracting a target instruction according to an instruction prefetch request further includes: determining whether to perform an instruction prefetch operation according to a prefetch algorithm.

[0056] For example, the instruction processing method according to at least one embodiment of the present disclosure further includes: obtaining the object instruction from the instruction cache unit L1 or the instruction cache queue L0 according to the instruction fetch request, and then sending the object instruction to the decoding unit, and dispatching it to the execution unit. For example, the decoding unit of the processor decodes the object instruction after receiving it, and then provides the decoding result to the corresponding execution unit for execution. The decoding result includes microinstructions, and the microinstructions are dispatched by the emission unit (not shown) to the execution unit for execution.

[0057] For example, in a processor and an instruction processing method according to at least one embodiment of the present disclosure, an object instruction is obtained from an instruction cache unit L1 or an instruction cache queue L0 according to an instruction fetch request, including: writing the instruction fetch request to an instruction fetch information queue; and querying the instruction cache unit L1 or the instruction cache queue L0 to obtain the object instruction according to the instruction fetch information queue.

[0058] The above processor and instruction processing method are described below in conjunction with specific embodiments.

[0059] Figure 4 An exemplary flow chart of an instruction processing method according to at least one embodiment of the present disclosure is shown.

[0060] like Figure 4 As shown, first, (1) the branch prediction unit receives instruction release information from the instruction release unit, and the branch prediction component generates a branch prediction result according to the branch prediction algorithm, obtains a new instruction address, and stores the new instruction address in the branch prediction address information queue.

[0061] Afterwards, (2) based on the new instruction address, determine whether to perform a prefetch operation according to the instruction prefetch algorithm. If a prefetch operation is performed, assign an instruction Miss queue to the prefetch request, and store the instruction prefetch address corresponding to the expected request in the instruction Miss queue. Then, initiate an instruction fetch request operation to the secondary cache and wait for the response of the secondary cache.

[0062] At the same time, (3) the instruction fetch information corresponding to the new instruction address is stored in the instruction fetch information queue. The instruction fetch information at the head of the instruction fetch information queue is the oldest instruction fetch information.

[0063] Afterwards, (4) the instruction fetch information is read at the head of the instruction fetch information queue to determine whether the current instruction fetch operation occupies the instruction Miss queue.

[0064] (5) Based on the result of (4), if the instruction miss queue is not occupied, the instruction cache queue will be searched.

[0065] (6) Based on the result of (4), if the instruction miss queue is occupied, continue to determine whether the instruction data to be extracted by the current instruction fetch operation is in the backfill process or backfill completion state of the secondary cache.

[0066] (7) Based on the result of (6), if the instruction data to be extracted by the current instruction fetch operation is not in the backfill process or backfill completion state of the secondary cache, the current instruction fetch operation will be stopped and the instruction fetch information will not be read out from the instruction fetch information queue.

[0067] (8) Based on the result of (6), if the instruction data to be extracted by the current instruction fetch operation is in the backfill process or the backfill completed state of the secondary cache, it is determined whether the instruction data is in the backfill completed state.

[0068] Further, (9) based on the result of (8), if the currently required instruction data is in a backfilled state, the instruction cache queue is queried and the entry storing the instruction information corresponding to the instruction fetch address in the instruction cache queue is obtained by indexing, and the required instruction data is read from the instruction cache queue; conversely, (10) based on the result of (8), if the currently required instruction data is not in a backfilled state, the instruction data required for reading is directly obtained from the backfill bus that is backfilled from the secondary cache L2 to the instruction cache unit.

[0069] (11) Based on the above two situations (9) and (10), it is determined that the instruction fetch is successful and the instruction fetch operation is completed.

[0070] In addition, in the above operation, (12) is based on the result of (4). If the current instruction fetch operation does not occupy the instruction Miss queue, the instruction cache queue is searched. At this time, if the query instruction cache queue hits, that is, no query miss (Miss) occurs, it also means that the instruction fetch is successful and the current instruction fetch operation is completed.

[0071] On the contrary, (13) is based on the result of (4). If the query instruction cache queue does not hit, that is, a query miss occurs, then the instruction cache unit L1 is further searched; if the query instruction cache unit L1 hits, it also means that the instruction fetch is successful and the instruction fetch operation is completed; otherwise, (14) is based on the result of (13), a memory access request is sent to the instruction miss queue.

[0072] (15) Regardless of the case of sending a memory access request to the instruction Miss queue in (2) or (14) above, it is necessary to read the memory access request from the instruction Miss queue and send the memory access request to the secondary cache.

[0073] In the above operation, if a memory access request is sent to the instruction Miss queue and then an instruction fetch operation is initiated to the secondary cache, after receiving the response from the secondary cache, the above queues and instruction fetch cache units, instruction fetch cache queues, etc. need to be updated according to the response from the secondary cache.

[0074] For example, in a processor and an instruction processing method according to at least one embodiment of the present disclosure, an access request is sent to a secondary cache L2 using an instruction prefetch address, including: using the instruction prefetch address to update an instruction miss queue for an instruction cache unit, and then sending an access request to the secondary cache L2. Also, in response to an instruction data backfill operation of the secondary cache L2, an object instruction corresponding to the instruction prefetch address is written to the instruction cache queue L0, including: in response to a backfill request for the object instruction from the secondary cache L2, the instruction miss queue is awakened, and according to the record information corresponding to the object instruction in the instruction miss queue, it is determined to write the object instruction corresponding to the instruction prefetch address to the instruction cache queue L0.

[0075] For example, in a processor and an instruction processing method according to at least one embodiment of the present disclosure, the record information corresponding to the object instruction in the instruction miss queue includes whether the entry corresponding to the object instruction is valid and whether it is cacheable.

[0076] Figure 5 A flow chart of a L2 cache backfill operation according to at least one embodiment of the present invention is shown.

[0077] like Figure 5 As shown, the secondary cache backfills a requested instruction data to the instruction cache queue. (1) At this time, it is necessary to check the entry information corresponding to the instruction data to be backfilled in the instruction Miss queue, and wake up the entry in the instruction Miss queue to start the data backfill process.

[0078] Then, (2) check whether the corresponding entry in the instruction Miss queue is valid (VALID). If the entry is invalid at this time (the value of VALID is 0), the instruction data backfilled from the L2 cache will not be backfilled into the instruction cache queue.

[0079] On the contrary, (3) if the entry is valid at this time (the value of VALID is 1), it is necessary to continue to check the cache attribute of the instruction fetch request. If the cache attribute is non-cacheable (Non Cacheable), then the instruction data backfilled from the L2 cache will not be backfilled into the instruction cache queue. Otherwise, it will be backfilled into the instruction cache queue.

[0080] In addition, (4) after the corresponding entry in the instruction miss queue is awakened in (1) above, the corresponding entry in the instruction fetch information queue may be awakened.

[0081] Afterwards, (5) determine whether the awakened instruction fetch entry is at the head of the instruction fetch information queue. If so, directly obtain the instruction data from the backfill bus of the secondary cache; otherwise, perform subsequent indexing / query operations.

[0082] As described above, in the processor of the embodiment of the present disclosure, for example, Figure 2 The processor shown has added an instruction cache queue, which can be regarded as a level 0 cache. Accordingly, two cache systems, the instruction cache queue and the instruction cache unit, need to be maintained.

[0083] Figure 6 An exemplary operation flow chart of updating an instruction cache unit in an instruction processing method according to at least one embodiment of the present disclosure is shown.

[0084] like Figure 6 As shown, first, (1) the instruction release unit releases a number of branch prediction entries to the branch prediction unit, and determines whether the number of released branch prediction entries is 0. If it is 0, continue to monitor the instruction release unit; otherwise, start the update operation of the instruction cache unit.

[0085] (2) After the update operation is started, the entry in the branch prediction address information queue corresponding to the branch prediction entry released by the release unit to the branch prediction unit is determined by indexing or searching.

[0086] (3) Based on (2), for the branch prediction entry determined to be released, the instruction information corresponding to the instruction fetch request needs to be backfilled into the physical location in the instruction cache unit according to the physical address.

[0087] Afterwards, (4) based on (2), according to the branch prediction entry to be released, wake up the entry corresponding to the branch prediction entry in the instruction Miss queue.

[0088] (5) The "backfill process flag" in the corresponding entry in the instruction Miss queue is set high (ie, 1, in the backfill process).

[0089] Afterwards, (6) check whether there is an entry in the instruction Miss queue whose "backfill process" and "valid bit" are both 1, and the "shared" flag is 0 (as the number of shared instruction fetch requests decreases, the "shared" flag is adaptively determined to be set to 0).

[0090] (7) According to the result of (6), if such an entry exists, an entry of the instruction miss queue to be backfilled into the instruction cache unit is determined, and the "backfill process" flag of the entry is set to low (i.e., 0, completing the backfill process).

[0091] Afterwards, (8) according to the set index of the instruction cache unit stored in the instruction Miss queue entry, the way information that needs to be backfilled to the instruction cache unit is determined.

[0092] Then, (9) the corresponding instruction data in the instruction cache queue is backfilled to the specified position in the instruction cache unit.

[0093] Afterwards, (10) the entry corresponding to the instruction Miss queue is released.

[0094] In the processor of the embodiment of the present disclosure, due to the existence of the instruction cache queue, the snoop (SNOOP) management control system can be updated. The snoop (SNOOP) operation is mainly used in the cache consistency protocol to ensure the consistency of data in a multi-processor or multi-cache system. The snoop mechanism allows the cache controller to snoop on the communication between other caches or memory controllers, so that modifications to shared data can be detected and its own cache copy can be updated as needed. This ensures that the data seen by all processors is the latest and avoids problems caused by inconsistencies.

[0095] The MESI protocol is a commonly used cache consistency protocol, and its name comes from the four possible states: Modified, Exclusive, Shared, and Invalid. These states help manage the state of cache blocks in different processor caches to ensure data consistency.

[0096] For example, according to the MESI protocol, when a cache attempts to modify a shared data, it sends a "Modify" request to the bus. After other cache controllers hear this request, they check whether they hold a copy of the data. If other caches do hold a copy of the data, they mark the copy as invalid, thus ensuring that only the cache requesting the modification can modify the data.

[0097] For example, the instruction processing method according to at least one embodiment of the present disclosure further includes: maintaining cache consistency between the instruction cache unit L1 and the instruction cache queue L0.

[0098] For example, in a processor and an instruction processing method according to at least one embodiment of the present disclosure, maintaining cache consistency between an instruction cache unit L1 and an instruction cache queue L0 includes: maintaining cache consistency by issuing a snoop operation through a secondary cache L2. For example, the control logic of the secondary cache includes performing a snoop operation to maintain cache consistency.

[0099] For example, in a processor and an instruction processing method according to at least one embodiment of the present disclosure, a snoop operation is issued by the secondary cache L2 to maintain cache consistency, including: in response to the snoop operation hitting the first target entry of the instruction cache queue L0, clearing the valid bit in the first target entry, and determining whether the cleared first target entry is performing a backfill instruction cache unit operation; in response to the snoop operation hitting the second target entry of the instruction cache unit L1, clearing the valid bit in the first target entry.

[0100] Figure 7 An exemplary operation flow chart of a monitoring operation in an instruction processing method according to at least one embodiment of the present disclosure is shown.

[0101] like Figure 7 As shown, (1) a snoop (SNOOP) operation request is sent from the secondary cache L2.

[0102] Afterwards, (2) based on (1), determine whether the branch prediction address information queue is hit. If an entry in the branch prediction address information queue is hit, it means that the cache line that needs to be monitored is already in the processor pipeline. At this time, it is necessary to clear the valid bit (VALID) of the entry and flush (FLUSH) other instructions after the cache line (CACHELINE) in the processor pipeline.

[0103] (3) Based on (1), determine whether a cache line in the instruction cache queue is hit.

[0104] (4) Based on (3), if a cache line in the instruction cache queue is hit, the valid bit (VALID) of the cache line of the instruction cache queue is cleared to zero, and it is further determined whether the cache line of the instruction cache queue is performing a backfill operation of the backfill instruction cache unit. If the backfill operation is in progress, the backfill bus is refreshed, otherwise, the operation is abandoned.

[0105] (5) Based on (3), if the cache line in the instruction cache queue is not hit, the operation of clearing the valid bit (VALID) of the cache line is abandoned.

[0106] (6) Based on (1), determine whether the cache line in the instruction cache unit is hit. If the cache line in the instruction cache unit is hit, clear the valid bit corresponding to the cache line in the instruction cache unit; otherwise, abandon the snoop request operation.

[0107] In at least one embodiment of the present disclosure, due to the addition of an instruction cache queue, in some cases, the instruction fetch unit only needs to read the pre-fetched instruction from the instruction cache queue, and in other states, it needs to first search the instruction cache queue, and if it does not hit, then search the instruction cache unit. In order to better reduce the impact on timing, another embodiment of the present disclosure provides the following modified instruction processing method, and its exemplary flowchart is shown in Figure 7 .

[0108] Figure 8 An exemplary flow chart of an instruction processing method according to at least another embodiment of the present disclosure is shown. In a processor of at least one embodiment of the present disclosure, the control logic is adjusted accordingly.

[0109] like Figure 8 As shown, first, (1) the branch prediction unit receives instruction release information from the instruction release unit, and the branch prediction component generates a branch prediction result according to the branch prediction algorithm, obtains a new instruction address, and stores the new instruction address in the branch prediction address information queue.

[0110] Afterwards, (2) based on the new instruction address, determine whether to perform a prefetch operation according to the instruction prefetch algorithm. If a prefetch operation is performed, an instruction Miss queue is assigned to the prefetch request, and the instruction prefetch address corresponding to the expected request is stored in the instruction Miss queue. Then, an instruction fetch operation is initiated to the secondary cache and the response of the secondary cache is waited for.

[0111] At the same time, (3) the instruction fetch information corresponding to the new instruction address is stored in the instruction fetch information queue.

[0112] (4) Based on (2), if a pre-fetch operation is performed, the subsequent query instruction cache queue and other operations are abandoned.

[0113] (5) Based on (2), if no prefetch operation is performed, the instruction Miss queue is searched based on the instruction address.

[0114] (6) Based on the result of (5), if the instruction miss queue is not hit, the subsequent query of the instruction cache queue and other operations are abandoned; if the instruction miss queue is hit, it is marked that the instruction fetch operation occupies the instruction miss queue.

[0115] Afterwards, (7) the instruction fetch information is read at the head of the instruction fetch information queue to determine whether the current instruction fetch operation occupies the instruction Miss queue.

[0116] (8) Based on the result of (7), if the instruction miss queue is not occupied, the instruction cache unit will be searched.

[0117] (9) Based on the result of (7), if the instruction miss queue is occupied, continue to determine whether the instruction data to be extracted by the current instruction fetch operation is in the backfill process or backfill completion state of the secondary cache.

[0118] (10) Based on the result of (9), if the instruction data to be extracted by the current instruction fetch operation is not in the backfill process or backfill completion state of the secondary cache, the current instruction fetch operation will be stopped and the instruction fetch information will not be read out from the instruction fetch information queue.

[0119] (11) Based on the result of (9), if the instruction data to be extracted by the current instruction fetch operation is in the backfill process or the backfill completed state of the secondary cache, it is determined whether the instruction data is in the backfill completed state.

[0120] Further, (12) based on the result of (11), if the currently required instruction data is in a backfilled state, the instruction cache queue is queried and the entry storing the instruction information corresponding to the instruction fetch address in the instruction cache queue is indexed, and the required instruction data is read from the instruction cache queue.

[0121] On the contrary, (13) is based on the result of (11), if the currently required instruction data is not in the backfilled state, the instruction data required for reading is directly obtained from the backfill bus of the L2 cache L2 backfilled to the instruction cache unit.

[0122] (14) Based on the above two situations (12) and (13), it is determined that the instruction fetch is successful and the instruction fetch operation is completed.

[0123] In addition, in the above operation, (15) searches the instruction cache unit based on the result of (8). At this time, if the query instruction cache queue hits, that is, no query miss occurs, it also means that the instruction fetch is successful and the instruction fetch operation is completed.

[0124] On the contrary, (16) is based on the result of (4). If the query instruction cache unit does not hit, that is, a query miss occurs, then a memory access request is sent to the instruction miss queue; if the query instruction cache unit hits, it also means that the instruction fetch is successful and the instruction fetch operation is completed.

[0125] (17) Regardless of the case of sending a memory access request to the instruction Miss queue in (2) or (16) above, it is necessary to read the memory access request from the instruction Miss queue and send the memory access request to the secondary cache.

[0126] Similarly, in the above operation, if a memory access request is sent to the instruction Miss queue, and then an instruction fetch operation is initiated to the secondary cache, after receiving the response from the secondary cache, the above queues and instruction fetch cache units, instruction fetch cache queues, etc. need to be updated according to the response from the secondary cache.

[0127] Furthermore, in the above processing method, when the instruction fetch request enters the instruction fetch information queue, the instruction Miss queue is searched, so as to determine whether to read the instruction in the instruction cache queue or to read the instruction data in the instruction cache unit during the instruction fetch process. Since the speed at which the instruction fetch request enters the instruction fetch information queue is greater than the speed at which the instruction fetch request is read out of the instruction fetch information queue, this operation can be performed before entering the instruction fetch information queue.

[0128] In at least one embodiment of the present disclosure, the processor (or processor core) translates each architecture instruction (instruction) into one or more micro-instructions (micro-op, uop) within the micro-architecture, and each micro-instruction only performs limited operations, so that each pipeline stage can be kept short to increase the operating frequency of the processor core. For example, a memory read instruction (load) can be translated into an address generation micro-instruction and a memory read micro-instruction. The second micro-instruction will depend on the result of the first micro-instruction, so the second micro-instruction will not start to execute until the first micro-instruction is executed. The micro-instruction contains multiple micro-architecture-related fields, which are used to pass relevant information between pipeline stages.

[0129] Accordingly, in this embodiment, the instruction cache system at the front end of the pipeline of the processor core includes a microinstruction cache (OC) in addition to the instruction cache unit (IC) and the instruction cache queue, and in order to better improve the effective capacity of the instruction cache unit and the microinstruction cache, it is necessary to maintain an exclusive relationship between the two.

[0130] Fig. 9 FIG. 1 is a schematic diagram showing a processor front-end architecture according to an embodiment of the present disclosure. Fig. 9 As shown, the front-end architecture 10 of the processor includes a branch prediction unit 101 , a branch prediction address information queue 102 , an instruction cache unit 103 , a decoding unit 104 , a microinstruction processing module 105 , a microinstruction cache unit 106 , a microinstruction queue 107 and an issue unit 108 .

[0131] For the above front end, the corresponding instruction fetching method can be described as follows.

[0132] The branch prediction unit 101 sends the prediction information to the branch prediction address information queue 102 for buffering to wait for processing of the prediction information.

[0133] The processor core initially enables the instruction cache mode to process the prediction information. For example, first, based on the address information in the prediction information from the branch prediction address information queue 102, an attempt is made to extract the instruction data requested by the prediction information from the instruction cache unit 103, and the instruction data is sent to the decoding unit 104 for decoding. Here, the instruction data can be continuous binary data. The decoding unit 104 can decode the acquired instruction data into corresponding microinstruction groups (each microinstruction group includes one or more microinstructions), and send the microinstruction groups to the microinstruction queue 107 cache to wait for distribution ( Figure 2 not shown).

[0134] The decoding unit 104 also sends the decoded microinstruction group to the microinstruction cache unit 106 for caching. At this time, a microinstruction cache entry for storing microinstructions can be created in the microinstruction cache unit 106. One or more microinstructions in the microinstruction group are cached in the created microinstruction cache entry. For example, one microinstruction cache entry can store 8 microinstructions. When caching microinstructions, the microinstruction cache unit 106 provides judgment information on whether the microinstruction already exists in the microinstruction cache unit 106. For example, when a microinstruction already exists in the microinstruction cache unit 106, the microinstruction cache unit 106 can provide cache hit information, and when a microinstruction does not exist in the microinstruction cache unit 106, the microinstruction cache unit 106 can provide cache miss information.

[0135] The processor core determines whether to enable the microinstruction cache fetch mode according to the cache hit or cache miss information provided by the microinstruction cache unit 106. In one embodiment, for example, when the microinstruction cache unit 106 provides cache hit information indicating that several consecutive microinstruction groups are present in the microinstruction cache unit 106, the judgment result is "yes", and the microinstruction cache fetch mode is enabled; when the judgment result is "no", the prediction information continues to be processed in the instruction cache mode.

[0136] In response to enabling the microinstruction cache fetch mode, the prediction information in the branch prediction address information queue 102 is sent to the microinstruction cache fetch queue included in the microinstruction processing module 105 , and the sending of the prediction information to the instruction cache unit 103 is stopped.

[0137] The microinstruction cache unit 106 determines whether the microinstruction group corresponding to the prediction information can be extracted from the microinstruction cache unit 106 according to the address information in the prediction information. For example, in response to not being able to extract the microinstruction group corresponding to the prediction information, the system resumes processing the prediction information in the instruction cache mode, and processes the prediction information that is not currently cached in the instruction cache mode.

[0138] In response to being able to extract the microinstruction group corresponding to the prediction information, the extracted microinstruction group is sent to the microinstruction queue 107 to wait for dispatch.

[0139] The microinstruction queue 107 sequentially sends microinstruction groups from instruction cache mode or microinstruction cache mode processing to the issue unit 108 for back-end execution, such as register renaming, execution, retirement, etc.

[0140] In this embodiment, when an instruction is released, it is checked whether the corresponding cache line is fetched through the microinstruction fetch path. If it is the microinstruction fetch path, the corresponding cache line in the instruction cache queue will not be updated in the instruction cache.

[0141] For example, Figure 2 In the processor core of the embodiment of the present disclosure shown, the processor core front end includes multiple queues, for example, a branch prediction address information queue, an instruction fetch information queue, an instruction fetch request queue, and an instruction cache queue. In at least one embodiment of the present disclosure, the size of the instruction cache queue is the same as the size of the instruction fetch request queue, and the size of the instruction fetch request queue is the same as the size of the branch prediction address information queue.

[0142] Fig.10 A schematic diagram showing the relationship between various queues included in a processor core in at least one embodiment of the present disclosure.

[0143] In an embodiment of the present disclosure, entries of the branch prediction address information queue are used to store branch prediction related data, for example, including branch prediction address information, branch prediction instruction information, etc.

[0144] Here, the instruction fetch information queue can be understood as a subset of the branch prediction address information queue. In addition to being filled into the branch prediction address information queue, the branch prediction information will also be filled into the instruction fetch information queue; for example, in at least one embodiment, the index corresponding to the entry in the branch prediction address information queue where the branch prediction fragment is stored will also be stored in the instruction fetch information queue. Fig.10 As shown, each entry in the instruction fetch information queue includes the following fields: branch prediction address queue index number, instruction fetch physical address, secondary cache (L2) request queue index number, instruction cache queue backfill "complete / process" flag bit, instruction fetch request queue index, etc.

[0145] The instruction fetch request queue is used to store prefetch requests sent by the branch prediction unit or instruction cache miss requests generated by the instruction fetch unit; the relevant information assigned to the instruction fetch request queue will also be stored in the instruction fetch information queue to wake up the related instruction fetch operations, and at the same time wake up the related instruction fetch operations to the corresponding instruction cache queue to read the instruction information. Fig.10As shown, each entry in the instruction fetch request queue may include the following fields: a valid bit (Valid), a branch prediction address queue tag, a way (Way) value of the corresponding instruction cache unit (IC), a tag bit during the backfilling of the instruction cache unit, an instruction fetch address, etc.

[0146] like Fig.10 As shown, the instruction cache queue includes multiple cache lines, the size of each cache line is, for example, 32 bytes, and each instruction cache queue entry stores 1 cache line with a minimum storage granularity of 1 / 4 cache line.

[0147] In this embodiment, the branch prediction address information queue has 64 entries, the instruction fetch information queue has 16 entries, the instruction fetch request queue has 64 entries, and the instruction cache queue has 64 cache lines. At this time, the capacity (number of entries) of the branch prediction address information queue, the capacity (number of entries) of the instruction fetch request queue and the size (number of cache lines) of the instruction cache queue are the same, which helps to control the instruction backfill time.

[0148] Some embodiments of the present disclosure further provide an electronic device, which includes a processor of any of the above embodiments or an instruction processing method capable of executing any of the above embodiments.

[0149] Fig.11 A schematic diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may include but is not limited to mobile terminals such as notebook computers, PDAs (personal digital assistants), PADs (tablet computers), etc., and fixed terminals such as desktop computers.

[0150] Fig.11 The electronic device 1000 shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure. Fig.11 As shown, in some examples, the electronic device 1000 includes a processor of any embodiment of the present disclosure, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage device 1008 to the random access memory (RAM) 1003, such as the processing method of the computer program of the embodiment of the present disclosure. In the RAM 1003, various programs and data required for the operation of the computer system are also stored. The processor 1001, ROM 1002 and RAM 1003 are connected to each other through a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0151] For example, the following components may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable storage medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage device 1008 as needed.

[0152] Although Fig.11 The electronic device 1000 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0153] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0154] There are a few points to note about this disclosure:

[0155] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0156] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0157] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A command processing method, comprising: Extracting the object instruction according to the instruction prefetch request, and caching the extracted object instruction in the instruction cache queue; In response to instruction release information from the pipeline of the processor core, the object instruction is filled from the instruction cache queue into the instruction cache unit, Wherein, the instruction cache unit is configured to be directly accessed by the processor core.

2. The instruction processing method according to claim 1, further comprising: The instruction prefetch request is generated according to the branch prediction result.

3. The instruction processing method according to claim 2, wherein: The extracting the object instruction according to the instruction prefetch request comprises: Acquire an instruction prefetch address according to the instruction prefetch request; In response to performing an instruction prefetch operation according to the instruction prefetch address, sending an access request to a secondary cache using the instruction prefetch address; In response to the instruction data backfill operation of the secondary cache, the object instruction corresponding to the instruction prefetch address is written into the instruction cache queue.

4. The instruction processing method according to claim 3, wherein: The extracting the object instruction according to the instruction prefetch request further includes: Determine whether to perform the instruction prefetch operation according to a prefetch algorithm.

5. The instruction processing method according to claim 3, wherein: The step of sending an access request to a secondary cache using the instruction prefetch address comprises: updating an instruction miss queue for the instruction cache unit using the instruction prefetch address, and then sending the access request to the secondary cache; and The step of writing the object instruction corresponding to the instruction prefetch address into the instruction cache queue in response to the instruction data backfill operation of the secondary cache comprises: In response to the backfill request of the secondary cache for the object instruction, the instruction miss queue is awakened, and according to the record information corresponding to the object instruction in the instruction miss queue, it is determined to write the object instruction corresponding to the instruction prefetch address into the instruction cache queue.

6. The instruction processing method according to claim 5, wherein: The record information corresponding to the target instruction in the instruction miss queue includes whether the entry corresponding to the target instruction is valid and cacheable.

7. The instruction processing method according to claim 3, wherein: The extracting the object instruction according to the instruction prefetch request further includes: After the instruction prefetch address is generated according to the branch prediction result, the instruction prefetch address is filled into the branch prediction address information queue.

8. The instruction processing method according to claim 1, wherein: The step of filling the object instruction from the instruction cache queue into the instruction cache unit in response to the instruction release information from the processor pipeline comprises: Determining a released branch prediction entry according to instruction release information of an instruction release unit in the processor pipeline; According to the released branch prediction entry, waking up a target entry in the instruction miss queue; According to the information recorded in the target entry in the instruction missing queue, backfill the object instruction in the instruction cache queue corresponding to the target entry in the instruction missing queue into the instruction cache unit; The target entry in the instruction miss queue is released.

9. The instruction processing method according to claim 8, wherein: The step of backfilling the object instruction in the instruction cache queue corresponding to the target entry of the instruction missing queue into the instruction cache unit includes: The physical location that needs to be backfilled into the instruction cache unit is determined according to the physical address of the object instruction.

10. The instruction processing method according to claim 1, further comprising: The object instruction is obtained from the instruction cache unit or the instruction cache queue according to an instruction fetch request, and then the object instruction is sent to a decoding unit and dispatched to an execution unit.

11. The instruction processing method according to claim 10, wherein: The acquiring the object instruction from the instruction cache unit or the instruction cache queue according to the instruction fetch request includes: Writing the instruction fetch request into an instruction fetch information queue; According to the instruction fetch information queue, the instruction cache unit or the instruction cache queue is queried to obtain the object instruction.

12. The instruction processing method according to claim 11, wherein: The querying the instruction cache unit or the instruction cache queue to obtain the object instruction according to the instruction fetch information queue includes: Reading instruction fetch information from the head of the instruction fetch information queue to determine whether the current instruction fetch operation occupies the instruction missing queue; In response to the current instruction fetch operation not occupying the instruction miss queue, querying the instruction cache queue; or In response to the current instruction fetch operation occupying the instruction miss queue, a backfill operation for the secondary cache is determined, and, in response to the backfill operation for the secondary cache being completed, the instruction cache queue is queried to read the object instruction, or in response to the backfill operation for the secondary cache being incomplete, the object instruction is read from a backfill bus of the secondary cache.

13. The instruction processing method according to claim 12, wherein: The querying the instruction cache unit or the instruction cache queue to obtain the object instruction according to the instruction fetch information queue also includes: In response to a query of the instruction cache queue with no hit, querying the instruction cache unit.

14. The instruction processing method according to claim 11, wherein: The querying the instruction cache unit or the instruction cache queue to obtain the object instruction according to the instruction fetch information queue includes: In response to querying the instruction miss queue using the current instruction fetch operation and finding a hit, marking the instruction miss queue as occupied; In response to the current instruction fetch operation occupying the instruction miss queue, determining a backfill operation for the secondary cache, or, in response to the current instruction fetch operation not occupying the instruction miss queue, querying the instruction cache unit; In response to the backfill operation of the secondary cache being completed, querying the instruction cache queue to read the object instruction, or in response to the backfill operation of the secondary cache being completed, reading the object instruction from the backfill bus of the secondary cache.

15. The instruction processing method according to claim 1, further comprising: Maintaining cache coherence between the instruction cache unit and the instruction cache queue.

16. The instruction processing method according to claim 15, wherein: The maintaining cache consistency between the instruction cache unit and the instruction cache queue comprises: The cache coherence is maintained by issuing snoop operations through the secondary cache.

17. The instruction processing method according to claim 16, wherein: The maintaining the cache consistency by issuing a snoop operation through the secondary cache includes: In response to the snoop operation hitting a first target entry of the instruction cache queue, clearing a valid bit in the first target entry, and determining whether the cleared first target entry is performing a backfill operation of the instruction cache unit; In response to the snoop operation hitting the second target entry of the instruction cache unit, clearing a valid bit in the first target entry.

18. A processor, comprising: Control logic, instruction fetch unit, instruction release unit, instruction cache unit and instruction cache queue, The instruction fetch unit is configured to fetch the object instruction according to the instruction prefetch request, and cache the fetched object instruction in the instruction cache queue; The instruction release unit is configured to provide instruction release information; The control logic is configured to, in response to the instruction release information, fill the object instruction from the instruction cache queue into the instruction cache unit, Wherein, the instruction cache unit is configured to be directly accessed by the instruction fetch unit.

19. The processor of claim 18, further comprising a branch prediction unit, wherein: The branch prediction unit is configured to generate the instruction prefetch request according to the branch prediction result; The instruction fetch unit is further configured as: Acquire an instruction prefetch address according to the instruction prefetch request; In response to performing an instruction prefetch operation according to the instruction prefetch address, sending an access request to a secondary cache using the instruction prefetch address; In response to the instruction data backfill operation of the secondary cache, the object instruction corresponding to the instruction prefetch address is written into the instruction cache queue.

20. The processor according to claim 19, further comprising a branch prediction address information queue, wherein: The branch prediction unit is further configured to, after generating the instruction prefetch address according to the branch prediction result, fill the instruction prefetch address into the branch prediction address information queue, The size of the branch prediction address information queue is the same as the size of the instruction cache queue.

21. The processor of claim 18, further comprising an instruction miss queue, wherein: The control logic is also configured to: Determining a released branch prediction entry according to the instruction release information; According to the released branch prediction entry, waking up the target entry in the instruction miss queue; According to the information recorded in the target entry in the instruction missing queue, backfill the object instruction in the instruction cache queue corresponding to the target entry in the instruction missing queue into the instruction cache unit; The target entry in the instruction miss queue is released.

22. The processor of claim 18, wherein: The control logic is further configured to perform a snoop operation to maintain cache coherence between the instruction cache unit and the instruction cache queue.

23. An electronic device comprising the processor according to any one of claims 18-22.

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