Configuration method of register and computer equipment

Abstract

The invention provides a register configuration method and computer equipment, and relates to the technical field of servers. The method is applied to a BIOS (Basic Input Output System) in computing equipment, and comprises the following steps: acquiring configuration information of a target register; storing the configuration information of the target register in a preset storage area; in the starting process of the computing device, obtaining configuration information of a target register from a preset storage area of the computing device; the target register is one or more registers of a target processor in the computing device; the configuration information is used for controlling characteristics of the target processor; and configuring the target register based on the configuration information of the target register. Through the method, the configuration information in the target register is not influenced by restarting of the computing device and reinstallation of the operating system OS, so that the configuration of the target register can take effect permanently, the configuration efficiency of the configuration template register is improved, and meanwhile, the dependence on the computing device OS is eliminated.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a register configuration method and a computer device. Background Art

[0002] The central processing unit (CPU) is the core component of the server, and its characteristics directly affect the server's computing speed and responsiveness. Registers are important storage units inside the CPU, used to store key information such as data and instructions, and have a direct impact on the characteristics of the processor.

[0003] In the prior art, when users need to adjust the characteristics of the CPU according to the application requirements or workload of the server, they modify the key information in the register through the kernel parameters of the operating system (OS) or the register configuration tool installed in the OS, thereby setting the characteristics of the CPU. However, this method is dependent on the OS, and when the server is restarted or the operating system is reinstalled, the modification will fail, thereby affecting the characteristics of the CPU. Summary of the invention

[0004] The embodiments of the present application provide a register configuration method and a computer device to achieve decoupling between the configuration register and the operating system (OS), thereby avoiding the occurrence of problems such as modification failure when restarting the server or reinstalling the operating system, thereby avoiding affecting the characteristics of the CPU.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a register configuration method is provided, which is applied to a basic input output system (BIOS) in a computing device, and the method includes: first, obtaining configuration information of a target register; and storing the configuration information of the target register in a preset storage area. The target register is one or more registers of a target processor in the computing device, such as a model specific register (MSR). The configuration information is used to control the characteristics of the target processor (such as operating temperature, power consumption mode, etc.). Then, during the startup of the computing device, the target register is configured based on the configuration information of the target register, such as the effective range of the register, the value of the bit, etc.

[0007] In this solution, on the one hand, since the BIOS configures the registers according to the configuration information in the preset storage area during each startup of the computing device, it can be ensured that during the operation of the computing device each time after it is turned on, its target processor works based on the corresponding register configuration, which is equivalent to achieving the persistence of the register configuration, that is, the configuration modification of the register is not restricted by the restart of the computing device and the reinstallation of the OS; on the other hand, the configuration process does not depend on the OS, so various OSes are universal, realizing the decoupling between the configuration registers and the OS.

[0008] In a possible implementation manner, the method further includes: configuring the target register based on the configuration information of the target register.

[0009] In this implementation, when the target processor is applied to different scenarios or when the user needs are different, the characteristics of the target processor need to be adjusted. At this time, the configuration of the target register can be modified by modifying the configuration information of the target register in the preset storage area, thereby achieving the purpose of controlling the characteristics of the target processor and improving the flexibility of the configuration register. For example, when the target processor is applied to a low-power scenario, the information about power consumption in the target register in the preset configuration information can be modified to achieve the low-power consumption requirement of the computing device.

[0010] In a possible implementation, the preset storage area is a storage area of ​​a non-volatile memory in a computing device.

[0011] In this implementation, the configuration information of the target register is stored in a non-volatile memory, which can ensure that even when the computing device is shut down or suddenly loses power, the configuration information of the target register is still retained so as to be used when the computing device is restarted, thereby avoiding the occurrence of target register configuration failure due to loss of configuration information and improving the reliability of template register configuration.

[0012] In one possible implementation, during the startup of the computing device, before obtaining the configuration information of the target register from the preset storage area of ​​the computing device, the method also includes: obtaining a configuration enable flag, the configuration enable flag is used to indicate whether to perform register configuration; obtaining the configuration information of the target register from the preset storage area of ​​the computing device, including: when the configuration enable flag indicates that register configuration is required, obtaining the configuration information from the preset storage area.

[0013] In a possible implementation, the method further includes: when the configuration enable flag indicates that register configuration is not required, guiding the operating system OS of the computing device to start.

[0014] In this implementation, by setting the configuration enable flag, the user can flexibly control whether to configure the target register. When the user needs to adjust the characteristics of the target processor, that is, needs to configure the target register, the BIOS will read the configuration information from the preset storage area and configure the target register according to the configuration information. When the user does not need to adjust the characteristics of the target processor, the BIOS will skip the step of reading the configuration information from the preset storage area and directly guide the startup of the OS. It can be seen that by introducing the configuration enable flag as a prerequisite for whether to configure the register, the flexibility of the computing device startup process is enhanced and the user experience is improved.

[0015] In one possible implementation, the configuration information includes a target effective range and a target bit value of a target register; the target effective range indicates that the configuration information acts on a target processor, a thread corresponding to the target processor, and any one of a processor core; multiple bits in the target register include a target bit; obtaining the configuration information of the target register includes: receiving a user's configuration operation, the configuration operation is used to configure the target effective range and the target bit value in a register configuration interface; based on the configuration operation, determining the target effective range and the target bit value.

[0016] In this implementation, the flexibility of configuring the target register is improved by the user configuring the target effective range and the target bit value in the register configuration interface. The user can make precise adjustments according to actual needs to ensure that the characteristics of the target processor meet actual needs.

[0017] In a possible implementation, receiving a configuration operation from a user includes: obtaining effective range information; the effective range information is used to display one or more effective ranges of a target register in a register configuration interface; and receiving a user selection operation for a target effective range from the one or more effective ranges.

[0018] In this implementation, different application scenarios require different register effective ranges to be configured. By providing multiple effective range options for users to choose from, the computing device can support diverse configuration requirements. In addition, multiple effective range options are displayed to users through the register configuration interface, which simplifies the user configuration process. Users do not need to specify the configuration range through complex commands, but can directly select on the register configuration interface, improving configuration efficiency.

[0019] In a possible implementation, receiving a configuration operation of a user includes: obtaining bit information; the bit information is used to display one or more bits of a target register in a register configuration interface; and when the user selects a target bit from one or more bits, obtaining the value of the target bit selected by the user.

[0020] In this implementation, bits are used to indicate the characteristic category of the target register controlling the target processor, and multiple bits of the target register are displayed to the user in the register configuration interface. On the one hand, the user can intuitively see which bits are configurable, and this visual presentation simplifies the user's configuration process; on the other hand, the user can optimize the processor's characteristics by accurately configuring the bits, so that the target processor can meet different application scenarios.

[0021] In a possible implementation, the method further includes: obtaining an address list of registers in the target processor, the address list being used to display the addresses of one or more registers in the target processor; receiving a user selection operation for a target address in the address list, and determining the register corresponding to the target address as the target register.

[0022] In this implementation, a list containing multiple register addresses is provided to the user, so that the user can intuitively and quickly locate the register to be configured, thereby improving the convenience of the configuration operation. By directly selecting the address of the target register from the address list, the user avoids errors that may be caused by manual address entry, thereby improving configuration efficiency and user experience.

[0023] In one possible implementation, the configuration information includes a target effective range, and the target effective range indicates that the configuration information acts on any one of the target processor, the thread corresponding to the target processor, and the processor core; based on the configuration information of the target register, the target register is configured, including: based on the target effective range, determining a first target interface; the first target interface is used to configure the effective range of the target register as the target effective range; different effective ranges of the target register correspond to different setting interfaces; and by calling the first target interface, the effective range of the target register is configured.

[0024] In this implementation, different effective ranges correspond to different target interfaces. The user selects an appropriate effective range according to actual needs, determines the first target interface through the target effective range, and calls the interface to configure the effective range of the target register, which simplifies the configuration process. The user does not need to understand the configuration details of the underlying registers in the computing device. He only needs to select the corresponding effective range on the register configuration interface to complete the register configuration. Through automated interface calls, the configuration process improves configuration efficiency.

[0025] In one possible implementation, the configuration information includes the value of a target bit; multiple bits in a target register include the target bit; the target register is configured based on the configuration information of the target register, including: determining a second target interface based on the value of the target bit; the second target interface is a first setting interface, or a second setting interface; the first setting interface is used to assign a first bit value to the target bit; the second setting interface is used to assign a second bit value to the target bit; and the value of the target bit of the target register is configured by calling the second target interface.

[0026] In this implementation, the value of the target bit is set to the first bit (for example, 1) through the first setting interface, and the value of the target bit is set to the second bit (for example, 0) through the second setting interface. A predefined interface and configuration process are used to simplify the user's operation of configuring the bits of the target register.

[0027] In a possible implementation, the configuration information of the target register is determined based on a target characteristic of the target processor; the target characteristic is a performance degradation of the target processor caused by performing a microcode upgrade.

[0028] In this implementation, considering that the microcode upgrade will affect the performance of the target processor, the configuration information of the target register is adjusted to reduce unnecessary performance loss caused by the microcode update, ensuring that the target processor can still maintain good performance after the microcode upgrade, achieving fine control of processor performance, and enhancing user experience.

[0029] In a second aspect, a register configuration device is provided, which is applied to a basic input / output system BIOS in a computing device, and the device includes: a functional unit for executing any one of the methods provided in the first aspect, and the actions performed by each functional unit are implemented by hardware or by hardware executing corresponding software. For example, the register configuration device may include: a first acquisition unit and a first configuration unit; during the startup of the computing device, the first acquisition unit is used to obtain configuration information of a target register from a preset storage area of ​​the computing device; the target register is one or more registers of a target processor in the computing device; the configuration information is used to control the characteristics of the target processor; the first configuration unit is used to configure the target register based on the configuration information of the target register.

[0030] In a third aspect, a computer device is provided, comprising: a processor and a memory, wherein the processor is connected to the memory, the memory is used to store computer-executable instructions, and the processor executes the computer-executable instructions stored in the memory, thereby implementing any one of the methods provided in the first aspect.

[0031] In a fourth aspect, a chip is provided, the chip comprising: a processor and an interface circuit; the interface circuit is used to receive code instructions and transmit them to the processor; the processor is used to run the code instructions to execute any one of the methods provided in the first aspect above.

[0032] In a fifth aspect, a computer-readable storage medium is provided, which stores computer execution instructions. When the computer execution instructions are executed on a computer, the computer executes any one of the methods provided in the first aspect.

[0033] In a sixth aspect, a computer program product is provided, comprising computer execution instructions, which, when executed on a computer, enable the computer to execute any one of the methods provided in the first aspect.

[0034] Among them, the technical effects brought about by any implementation method in the second to sixth aspects can refer to the technical effects brought about by different implementation methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A system architecture diagram of a computing device provided in an embodiment of the present application;

[0036] Figure 2 A flowchart of a register configuration method provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of a register configuration interface provided in an embodiment of the present application;

[0038] Figure 4 is a flowchart showing a startup process of a computing device according to an exemplary embodiment;

[0039] Figure 5 is a flowchart of another register configuration method according to an exemplary embodiment;

[0040] Figure 6 A flowchart of obtaining configuration information of a target register provided in an embodiment of the present application;

[0041] Figure 7 A schematic diagram of another register configuration interface provided in an embodiment of the present application;

[0042] Figure 8 is a schematic diagram of another register configuration interface according to an exemplary embodiment;

[0043] Fig. 9 is a schematic diagram of yet another register configuration interface according to an exemplary embodiment;

[0044] Fig.10A schematic diagram of a register configuration device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0046] In the description of this application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship between associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0047] Furthermore, in the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0048] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0049] The following is an introduction to the terms involved in the embodiments of the present application.

[0050] Microcode: It is a low-level code that controls the behavior of the CPU at the hardware level. It is located between hardware operations and machine language instructions and is used to implement a higher-level machine instruction set architecture (ISA). As a key component in CPU design, microcode defines how the CPU responds to each instruction. In related technologies, when there are defects in the CPU (such as hardware defects, vulnerability defects), the microcode is usually upgraded to fix the above CPU defects, thereby avoiding the manufacturer from replacing the CPU. For example, when the CPU has a hardware defect such as a packaging problem, the above hardware defect can be fixed by adjusting the CPU's power management strategy and lowering the CPU's operating temperature through microcode.

[0051] Model specific register (MSR): usually refers to the register used to store and control status information and configuration information related to a specific processor model in the x86 architecture CPU. As a special register inside the CPU, MSR allows software (such as operating system, application) to directly access and modify the above status information and configuration information. In programming, especially in operating system development or system-level programming, MSR is often used to tune CPU performance, manage power, detect hardware, and enable or disable specific CPU functions. Generally, accessing MSR requires a high level of permissions, because improper use of MSR may cause instability or security issues in computing devices. In the x86 architecture CPU, accessing MSR is generally completed through the read MSR (read MSR, RDMSR) instruction and the write MSR (write, WRMSR) instruction. Each MSR has a 32-bit address identifier, which can be used to distinguish MSRs. The MSRs supported by different CPU models may not be the same.

[0052] First, the application scenarios of the embodiments of the present application are exemplarily introduced.

[0053] The CPU is a core component in computing devices (such as various servers), and its performance directly determines the computing speed and responsiveness of the computing device when performing computing tasks. In the CPU, registers play a pivotal role. Registers are high-speed storage areas inside the CPU that are used to store data and instructions processed by the CPU. Taking MSR as an example, MSR, as a special register inside the CPU, can be used to control CPU characteristics. For example, by adjusting the register value (also called the value of the bit) in the MSR, the CPU's working strategy at different temperatures can be set (such as triggering fan acceleration when the preset temperature is exceeded), thereby ensuring that the CPU operates within a safe temperature range. For another example, by adjusting the register value to set the CPU's energy-saving mode, different power consumption modes can be switched according to the power status and energy-saving requirements.

[0054] When there is a defect in the CPU (such as a hardware defect or a vulnerability defect), the defect is usually fixed by upgrading the microcode. Specifically, the operating system (OS) in the computing device obtains a new version of the microcode and loads the new version of the microcode into the CPU to fix the defect in the CPU.

[0055] However, upgrading the microcode may cause some CPU performance to degrade. For example, in order to fix security vulnerabilities, upgrading the microcode will introduce additional security check mechanisms, and these security check mechanisms increase the CPU load, resulting in CPU performance degradation. In this case, the CPU's security performance can be adjusted by configuring the MSR, such as setting the register value in the MSR to disable the security check mechanism. For another example, there are both hardware defects and vulnerability defects in the CPU. Hardware defects and vulnerability defects can be fixed by upgrading the microcode, but upgrading the microcode fixes the vulnerability defects by changing the CPU's power consumption mode from low power consumption mode to high power consumption mode. If the user needs to fix the hardware defects and does not want to change the low power consumption mode of the CPU, after upgrading the microcode, the CPU's power consumption mode can be set to low power consumption mode by configuring the MSR, so as to fix the CPU hardware defects while maintaining its low power consumption mode.

[0056] The embodiment of the present application provides a register configuration method, which is applied to the BIOS in a computing device. When the computing device is started, the BIOS obtains the configuration information of the register from a preset storage area (such as the storage area of ​​the non-volatile memory of the computing device), and uses the configuration information of the register to configure the register, thereby realizing the control of the CPU characteristics. In this way, on the one hand, since the BIOS will configure the register according to the configuration information in the preset storage area during each startup process of the computing device, it can be ensured that the CPU of the computing device works based on the corresponding register configuration during the operation process after each startup, which is equivalent to realizing the persistence of the register configuration, that is, the configuration modification of the register is not restricted by the restart of the computing device and the reinstallation of the OS; on the other hand, the configuration process does not depend on the OS, so the decoupling between the configuration register and the OS is realized.

[0057] In some embodiments, in the configuration method provided by the embodiment of the present application, during the startup process of the computing device, first, the BIOS obtains the configuration information of the target register from the preset storage area of ​​the computing device. The target register is one or more registers of the target processor in the computing device, such as one MSR in a group of MSRs corresponding to the target processor. Then, based on the configuration information of the target register, the target register is configured, such as the effective range of the register, the value of the bit, etc.

[0058] The following is an exemplary introduction to the system architecture of the embodiments of the present application.

[0059] The embodiment of the present application provides a computing device, which may be a network device or a terminal device. The network device may include a server, etc. The server may be a physical server, or may be two or more physical servers with different responsibilities. In this case, the physical servers with different responsibilities cooperate with each other to realize the functions of the server.

[0060] Exemplarily, the server may be a blade server, a high-density server, a rack server or a tower server, etc. The terminal device may include a personal digital assistant (PDA), an ultra-mobile personal computer (UMPC), a notebook computer, a netbook, a desktop computer, an all-in-one computer, etc.

[0061] It should be noted that the embodiments of the present application do not limit the device form of the computing device. The system architecture of the computing device provided in the embodiments of the present application is described below using a server as an example.

[0062] like Figure 1, which is a system architecture diagram of a computing device provided in an embodiment of the present application. The hardware part of the computing device includes one or more processors, a BIOS chip, an out-of-band controller, and a memory, and the software part mainly includes a BIOS, an out-of-band management module, and an operating system (OS).

[0063] The processor may include a central processing unit (CPU), which includes one or more CPU cores. The CPU's data processing operations are all performed by the CPU cores. The more CPU cores included in the CPU, the faster the data processing speed.

[0064] The CPU also includes registers. Registers are high-speed storage areas inside the CPU, used to store data and instructions processed by the CPU. Registers can be MSRs (see the description in the terminology section for details), instruction registers (used to store the instructions currently being executed by the CPU), stack pointer registers (used to point to the top of the stack to support stack operations), etc.

[0065] Taking MSR as an example, MSR contains multiple bits. Bits are used to indicate the characteristic category of the CPU. For example, when MSR contains 32 bits, the four bits 0-3 are used to control the power consumption mode of the CPU, and the four bits 4-7 are used to control the temperature mode of the CPU. Among them, the power consumption mode refers to how the CPU manages its energy consumption under different loads. The power consumption mode can be a low power consumption mode (the corresponding value of the 0-3 bits is 0000), a high power consumption mode (the corresponding value of the 0-3 bits is 1111), etc. The temperature mode focuses on how the CPU manages the heat generated when it is running to ensure the stability and reliability of the computing device. The temperature mode can be an automatic temperature control mode (that is, the CPU automatically adjusts the power consumption according to the data collected by the temperature sensor to keep the temperature within a safe range, and the corresponding value of the 4-7 bits is 0000), a temperature limit mode (that is, when the temperature of the CPU reaches a preset threshold, the CPU reduces the operating frequency to reduce heat generation, and the corresponding value of the 4-7 bits is 1111).

[0066] The BIOS chip is set on the motherboard of the computing device and is used to initialize and detect various hardware devices of the computing device during the startup process of the computing device. The BIOS chip includes a flash memory area. The BIOS chip can be a serial peripheral interface (SPI) flash memory chip, a parallel flash memory (Parallel NorFlash) chip, etc.

[0067] The non-volatile memory is used as a preset storage area to store configuration information of a target register, wherein the target register can be any register in the CPU.

[0068] Of course, at least a part of the flash memory area in the BIOS chip may also be used as a preset storage area, that is, the configuration information of the target register is stored in the flash memory area in the BIOS chip.

[0069] Memory, also known as internal memory or main memory, is installed in the memory slot on the motherboard of a computing device. It is a temporary storage device used to temporarily store running programs and data. Memory can be specifically a memory bar, which is composed of memory chips, circuit boards, etc.

[0070] BIOS is a set of programs fixed to the BIOS chip. The main function of BIOS is to provide the lowest-level and most direct hardware settings and controls for computing devices. In the embodiment of the present application, during the startup of the computing device, BIOS will configure the target register according to the configuration information in the preset storage area. Among them, the configuration information is used to control the characteristics of the target processor in the computing device, so as to meet the user's requirements for the characteristics of the target processor. Among them, the target processor is any processor in the computing device.

[0071] In a possible implementation, the configuration information of the register includes a target effective range. The target effective range indicates that the configuration information acts on any one of a CPU (package), a thread (thread) corresponding to the CPU, and a processor core (core).

[0072] Among them, one CPU corresponds to at least one processor core, and each processor core is an independent computing unit in the CPU. Thread is the basic unit of CPU scheduling and the smallest unit that the operating system can perform computing scheduling. Each processor core corresponds to at least one thread, that is, each processor core can process one or more threads at the same time.

[0073] Optionally, when the target effective range indicates that the configuration information acts on the CPU, the configuration information of the register is used to control the characteristics of the entire CPU. At this time, the configuration information of the target register includes global characteristic parameters, such as the voltage and frequency of the CPU. Global characteristic parameters will affect the characteristics of the entire CPU. Exemplarily, when the user needs to set the CPU to automatically reduce the voltage and frequency of the CPU when it is idle to save energy, and increase the voltage and frequency of the CPU when the load is high to obtain better characteristics, the above user needs will correspond to the configuration information and will be written into the register, so that it will take effect on the entire CPU.

[0074] Optionally, when the target effective range indicates that the configuration information acts on the thread corresponding to the processor, the register configuration information is used to control the characteristics of the thread in the CPU. For example, the register configuration information includes the concurrency capability of the thread. The concurrency capability of a thread refers to the ability of a thread to process multiple tasks at the same time. Taking a multi-threaded web server as an example, each thread can concurrently process requests from different users. For another example, the register configuration information includes the response time of the thread. The response time of a thread refers to the time required from when the thread receives a task to when it completes the task and returns the result.

[0075] Optionally, when the target effective range indicates that the configuration information acts on the processor core, the configuration information of the register is used to control the characteristics of the processor core in the CPU. For example, the configuration information in the register is used to set the cache size of the processor core. For a processor core that performs a large number of floating-point operations, the cache size required by the processor core needs to be large enough to improve the computing characteristics of the processor core. At this time, the cache requirements of the processor core can be met by setting the configuration information in the register.

[0076] Optionally, by calling the first target interface, the effective range of the target register is configured as the target effective range. Taking the target effective range as the processor core as an example, assuming that the target effective range is processor core 2. By calling the target interface corresponding to processor core 2, the configuration information in the register is applied to processor core 2.

[0077] In a possible implementation, the configuration information of the register includes a target bit value, wherein the target bit is one or more bits in the target register, and the target bit value may be a first bit value (such as 1) or a second bit value (such as 0).

[0078] Exemplarily, the value of the target bit of the target register is configured by calling the second target interface. The second target interface is the first setting interface, or the second setting interface. The first setting interface is used to assign the first bit value to the target bit. The second setting interface is used to assign the second bit value to the target bit.

[0079] Optionally, in the case where the computing device is a terminal device, it may also include a display terminal, also referred to as a display; the display terminal is used to display the register configuration interface of the BIOS. In this interface, a configuration enable switch may be displayed, and the user determines the configuration enable flag by turning on or off the configuration enable switch, thereby indicating whether to configure the register. For example, when the user turns on the configuration enable switch, the configuration enable flag is set to a first flag value (such as 1), indicating that register configuration is to be performed. When the user turns off the configuration enable switch, the configuration enable flag is set to a second flag value (such as 0), indicating that register configuration is not required. During the startup process of the computing device, when the configuration enable flag indicates that register configuration is required, the BIOS obtains configuration information from a preset storage area. When the configuration enable flag indicates that register configuration is not required, the BIOS guides the OS of the computing device to start.

[0080] Optionally, when the computing device is a server, the function of the display terminal in the above-mentioned terminal device can be implemented through an external display device, which is not elaborated here.

[0081] The out-of-band management module is located in the out-of-band controller, and the OS is located in the processor.

[0082] The out-of-band management module may be a management unit of a non-business module. For example, the out-of-band management module may remotely maintain and manage a computing device through a dedicated data channel. The out-of-band management module is completely independent of the operating system of the computing device and may communicate with the BIOS and OS (or OS management unit) through the out-of-band management interface of the computing device.

[0083] OS is a computer program that manages and controls the hardware and software resources of a computing device. Any other software must be supported by the operating system to run. After the computing device is powered on, the BIOS first starts a series of operations such as self-test and initialization, then configures the target registers, and finally guides the OS to start, so that the user can use the computing device normally.

[0084] Exemplarily, the out-of-band management module may include a management unit for computing device operation status, a management system in a management chip, a computing device motherboard management unit (baseboard management controller, BMC), a system management module (system management mode, SMM), etc. It should be noted that the embodiments of the present application do not limit the specific form of the out-of-band management module, and the above is only an exemplary description. In the following embodiments, only the out-of-band management module is taken as an example for description.

[0085] It should be noted that in the following embodiments, the execution subject of the configuration method is the CPU, and the BIOS in the CPU is used as an example. Of course, the execution subject of the configuration method can also be the BMC.

[0086] It should be noted that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0087] For ease of understanding, the following is an exemplary introduction to the register configuration method provided by the present application in conjunction with the accompanying drawings. The method is applicable to Figure 1 The computing device shown.

[0088] The following embodiments of the present application will be divided into three parts to exemplarily introduce the scheme of the register configuration method.

[0089] Part I: Combination Figures 2 to 5 , introduces the configuration method provided in an embodiment of the present application, aiming to introduce the overall process of configuring the target register during the startup process of the computing device.

[0090] Part II: Combination Figures 6 to 9 , introduces the configuration method provided in the embodiment of the present application, aiming to introduce the implementation process of obtaining the configuration information of the CPU characteristics that meet the user's needs when the user needs to adjust the target register configuration.

[0091] The third part introduces the configuration method provided in the embodiment of the present application, aiming to introduce the implementation process of configuring the target register based on the configuration information of the target register.

[0092] In some embodiments, during the startup process of the computing device, the BIOS configures the target register based on the configuration information in the preset storage area, and controls the characteristics of the target processor through the configuration information, thereby meeting the user's requirements for the characteristics of the target processor. The configuration method provided in the embodiment of the present application configures the registers during each startup process of the computing device to achieve persistence of the register configuration, that is, it is not restricted by the restart of the computing device and the reinstallation of the OS, while reducing the dependence on the OS, improving the configuration efficiency of the registers, and enhancing the user experience.

[0093] Figure 2 1 is a flow chart of a register configuration method according to an exemplary embodiment. Exemplarily, the method includes the following S201-S202.

[0094] S201: During the startup of a computing device, the BIOS obtains first configuration information of a target register from a preset storage area of ​​the computing device.

[0095] In one possible implementation, the startup process of a computing device includes power on self-test (POST), initializing hardware devices, configuring target registers, and booting the OS. Among them, the power on self-test refers to the BIOS checking whether the hardware devices (such as CPU, memory, hard disk, etc.) in the computing device are normal, so as to ensure that the computing device can run stably. Initializing the hardware device refers to providing the necessary hardware environment for OS loading and running by setting the CPU's working mode, the hard disk's interface type, etc. Configuring the target register refers to configuring the register based on the configuration information in the preset storage area, so as to achieve the purpose of controlling the characteristics of the CPU. Booting the OS startup refers to loading the core files of the OS through the boot loader, thereby starting the OS.

[0096] In a possible implementation, the computing device includes one or more processors, the target processor is any processor in the computing device, the target processor includes one or more registers, and the target register is one or more registers of the target processor in the computing device.

[0097] In a possible implementation, the preset storage area is a storage area of ​​a non-volatile memory in the computing device. Storing the first configuration information of the target register in the non-volatile memory can ensure that even when the computing device is shut down or suddenly loses power, the first configuration information of the target register is still retained so as to be used when the computing device is restarted, thereby avoiding the occurrence of a target register configuration failure due to the loss of the first configuration information and improving the reliability of the target register configuration.

[0098] Of course, the preset storage area may also be a partial area in the flash memory area in the BIOS chip, and in this case, the configuration information of the target register is stored in the BIOS chip.

[0099] In one possible implementation, the first configuration information in the preset storage area can be used to control the characteristics of the target processor. The characteristics of the target processor include but are not limited to operating frequency, power consumption, security characteristics, etc. For example, the first configuration information controls the operating frequency of the target processor by setting the configuration parameters of the clock generator (such as clock frequency). For another example, the first configuration information manages the power consumption of the target processor by setting the power consumption mode of the target processor (such as high power consumption mode, low power consumption mode, etc.). For another example, the first configuration information controls the security characteristics of the target processor by turning on or off the security protection mechanism.

[0100] In a possible implementation, the first configuration information in the preset storage area is determined based on the target characteristics of the target processor. The target characteristics are the performance of the target processor that is reduced when the microcode is upgraded. This is because, considering that the microcode upgrade will affect the performance of the target processor, the first configuration information of the target register is adjusted to reduce unnecessary performance loss caused by the microcode update, ensuring that the target processor can still maintain good performance after the microcode upgrade, achieving fine control of the processor performance, and enhancing the user experience.

[0101] For example, the microcode not only solves the vulnerability defects but also reduces the power consumption of the target processor. However, the power consumption of the target processor is reduced by reducing the maximum frequency of the target processor, which directly affects the processing power of the target processor, that is, the performance of the target processor in processing complex tasks or high-load scenarios is significantly affected, such as slower response speed and longer task completion time. At this time, if the user does not want to reduce the maximum frequency of the target processor, the first configuration information of the target register can be set to limit the maximum frequency of the target processor through the first configuration information, so as to maintain the processing power of the target processor.

[0102] In a possible implementation, the first configuration information includes a target effective range and a target bit value. The target effective range indicates that the first configuration information acts on any one of the target processor, the thread corresponding to the target processor, and the processor core. The target bit is one or more bits in the target register. The target effective range and the target bit value have been described in the above system architecture section and will not be repeated here.

[0103] Of course, the first configuration information of the target register may also be the values ​​of a plurality of target bits in the target register. In this case, the number of the target bits may be determined according to actual conditions.

[0104] In a possible implementation, during the startup of the computing device, before obtaining the first configuration information from a preset storage area of ​​the computing device, the BIOS obtains a configuration enable flag and determines whether to configure the register according to the configuration enable flag.

[0105] Optionally, when the configuration enable flag indicates that register configuration is required, the first configuration information is obtained from a preset storage area.

[0106] Optionally, when the configuration enable flag indicates that register configuration is not required, the operating system OS of the computing device is booted.

[0107] For example, Figure 3A register configuration interface is provided for the present application. The register configuration interface can be set under the BIOS setup interface. A configuration enable switch is provided in the register configuration interface. The user can turn on or off the configuration enable switch as needed, thereby determining the configuration enable flag to indicate whether the BIOS needs to perform register configuration. The specific method for determining the configuration enable flag based on the configuration enable switch refers to the description in the above system architecture, which is not repeated here. Among them, the register configuration interface is displayed through a display terminal in a computing device, or through an external display device of the computing device. Exemplarily, when the configuration enable flag corresponding to the configuration enable switch indicates that the target register is to be configured, the BIOS obtains the first configuration information from a preset storage area, and configures the target register based on the first configuration information; when the configuration enable flag corresponding to the configuration enable switch indicates that register configuration is not required, the BIOS guides the OS in the computing device to start according to the original computer startup process.

[0108] Exemplarily, the configuration enable switch can be set at a preset position in the computing device. After the computing device is started, it is only necessary to detect the configuration enable switch to determine the configuration enable flag to indicate whether the BIOS adjusts the configuration of the register. Whether the user configures the register is determined by the user turning the configuration enable switch on or off. The position of the configuration enable switch is not specifically limited here, and the configuration enable switch can be set according to the user's operating habits, the design of the computing device, etc. For example, a physical button is set on the body of the computing device, and the user quickly turns on or off the configuration enable switch by pressing a specific button without entering a complex interface, further simplifying the operation and improving the overall user experience.

[0109] In this way, by setting the configuration enable flag, the user can flexibly control whether to configure the target register. When the user needs to adjust the characteristics of the target processor, that is, needs to configure the target register, the BIOS will read the first configuration information from the preset storage area and configure the target register according to the first configuration information. When the user does not need to adjust the characteristics of the target processor, the BIOS will skip the step of reading the first configuration information from the preset storage area and directly guide the startup of the OS. It can be seen that by introducing the configuration enable flag as a prerequisite for whether to configure the register, the flexibility of the computing device startup process is enhanced and the user experience is improved.

[0110] In one possible implementation, the configuration enable flag may not be set, and the configuration process of the register provided in this application may be directly entered. In this way, the user does not need to perform switch operations, which simplifies the entire configuration process, reduces user operation steps, shortens configuration time, and improves configuration efficiency.

[0111] S202: The BIOS configures the target register based on the first configuration information of the target register.

[0112] Take the configuration of MSR as an example. Figure 4 is a schematic diagram of the startup process of a computing device. Figure 4 As shown, the startup process of the computing device specifically includes the following S401-S406:

[0113] S401: After the computing device is powered on, the BIOS performs a power on self test (POST).

[0114] In a possible implementation, during the power-on self-test process, the BIOS is responsible for checking whether key hardware in the computing device is in a normal working state. For example, the BIOS checks whether the memory capacity matches, whether a graphics card exists, and so on.

[0115] S402: BIOS initializes hardware devices.

[0116] In one possible implementation, the BIOS initializes the hardware device by setting the parameters of the hardware device (such as the CPU operating mode, the resolution of the graphics card, etc.), allocating resources to the hardware device (such as interrupt resources, memory resources, etc.), and loading the device driver of the hardware device to ensure that the hardware device is in the correct configuration state before the OS is loaded.

[0117] S403: The BIOS determines whether register configuration is required according to the configuration enable flag.

[0118] S404: When the configuration enable flag indicates that register configuration is required, the BIOS configures one or more target MSRs based on the first configuration information in the preset area.

[0119] The number of target MSRs may be determined based on actual conditions.

[0120] S405: BIOS determines whether all target MSRs are configured.

[0121] S406: After the BIOS completes the configuration of each target MSR, the BIOS loads and starts the OS in the computing device.

[0122] In a possible implementation, when the BIOS completes configuration of all target MSRs, the BIOS loads and starts the OS based on a boot program in a boot device (such as a hard disk, etc.) to complete the startup of the computing device.

[0123] It should be noted that, when the configuration enable flag indicates that register configuration is not required, the BIOS will skip the register configuration and load the OS in the boot computing device.

[0124] In a possible implementation, the BIOS configures the target MSR after initializing the hardware device and before starting the OS. This is because the configuration information in the target MSR may be adjusted during the hardware device initialization process, such as the CPU settings involved in the hardware device initialization process. Therefore, the BIOS completes the configuration of the target MSR after initializing the hardware device and before starting the OS to avoid modifying the configuration information of the target MSR during the hardware device initialization process, and ensures that the configuration information of the final target MSR is the configuration information in the preset storage area.

[0125] In a possible implementation, after the computing device is started, when the user needs to modify the first configuration information of the target register, the configuration method provided in the embodiment of the present application further includes the following S203-S205, such as Figure 5 As shown:

[0126] S203: BIOS obtains second configuration information of the target register.

[0127] At this time, the second configuration information is the configuration information that needs to be updated for the target register. The first configuration information is the configuration information currently stored in the preset storage area.

[0128] It should be noted that the specific implementation method of obtaining the second configuration information will be described in the second part of the embodiment of the present application and will not be repeated here.

[0129] S204: BIOS replaces the first configuration information with the second configuration information of the target register and stores the second configuration information in a preset storage area.

[0130] S205: The BIOS configures the target register based on the second configuration information.

[0131] It should be noted that the specific implementation of the above S202 and S205 will be described in the third part of the embodiments of the present application and will not be repeated here.

[0132] In a possible implementation, when the user configures the target register for the first time, the configuration information (referred to as the third configuration information) for the first configuration of the target register is obtained in the same manner as the second configuration information, which is not described in detail here. After obtaining the third configuration information, the third configuration information is stored in a preset storage area. During the startup of the computing device, the BIOS completes the first configuration of the target register based on the third configuration information.

[0133] In this way, when the target processor is applied to different scenarios or when the user needs are different, the characteristics of the target processor need to be adjusted. At this time, the configuration of the target register can be modified by modifying the configuration information of the target register in the preset storage area, so as to achieve the purpose of controlling the characteristics of the target processor and improve the flexibility of the configuration register. For example, when the target processor is applied to a low-power scenario, the information about power consumption in the target register in the preset configuration information can be modified to achieve the low-power consumption requirement of the computing device.

[0134] In the first part of the embodiment of the present application, compared with the related art, which relies on the OS to configure the registers, after the computing device is restarted, the OS configuration information of the registers will become invalid and the registers need to be reconfigured. During the startup of the computing device, this solution uses the pre-stored configuration information of the target registers to configure the target registers, so that the configuration information in the target registers is not affected by the restart of the computing device and the reinstallation of the OS, so that the configuration of the target registers can be persistent and effective, thereby improving the configuration efficiency of the configuration template registers, and at the same time getting rid of the dependence on the computing device OS, realizing the decoupling between the configuration registers and the OS.

[0135] The above is the first part of the embodiment of this application. Figures 6 to 9 , describes a process of obtaining configuration information of CPU characteristics that meet user needs when a user needs to adjust a target register configuration.

[0136] In some embodiments, the BIOS displays a register configuration interface to the user, and obtains the configuration information of the target register through the user's configuration operation in the register configuration interface. The graphical register configuration interface makes the register configuration process more intuitive, helps to simplify the configuration operation, reduce the configuration difficulty, and improve the configuration efficiency.

[0137] Figure 6 The flowchart of obtaining configuration information of a target register according to an exemplary embodiment is shown. Exemplarily, the method includes the following S601-S602.

[0138] S601: BIOS receives a configuration operation from a user.

[0139] The configuration operation is used to configure the target effective range and the target bit value in the register configuration interface.

[0140] S602: The BIOS determines a target validity range and a target bit value based on the configuration operation.

[0141] In the implementation of the present application, receiving the user's configuration operation includes multiple implementation methods. The following is an exemplary description through methods 1 to 3.

[0142] Mode 1: When the configuration information includes the target effective range of the target register, a configuration operation of the user is received.

[0143] The target effective range indicates that the configuration information acts on any one of the target processor, the thread corresponding to the target processor, and the processor core.

[0144] In one example, the above S601 is specifically implemented in the following manner:

[0145] First, the BIOS obtains the effective range information.

[0146] The effective range information is used to display one or more effective ranges of the target register in the register configuration interface.

[0147] Optionally, the effective range information includes at least one of a target processor, a thread corresponding to the target processor, and a processor core corresponding to the target processor.

[0148] Exemplarily, when the effective range information is a target processor, the effective range indicates that the configuration information acts on the target processor.

[0149] Exemplarily, when the effective scope is a thread corresponding to the target processor, the effective scope indicates that the configuration information acts on the thread corresponding to the target processor.

[0150] Exemplarily, when the effective scope is a processor core corresponding to the target processor, the effective scope indicates that the configuration information acts on the processor core corresponding to the target processor.

[0151] In a possible implementation, the BIOS may send an instruction to a target processor in the computing device to request a selectable effective range of a target register, and after receiving the instruction, the target processor sends effective range information of the target register to the BIOS.

[0152] In a possible implementation, after acquiring the effective range information, the BIOS displays the effective range information on the register configuration interface, so that the user can select a target effective range of a target register after viewing the effective range information.

[0153] Optionally, after acquiring the effective range information, the BIOS sends the effective range information to a display in the computing device or an external display device, and displays the effective range information in the register configuration interface to the user through the display or the external display device.

[0154] Exemplarily, the display format of the effective range information in the register configuration interface is not specifically limited here. It can be in a list form, or an information set consisting of effective range information in any form such as a table. The information set can display one or more effective ranges of the target register.

[0155] Then, the BIOS receives a user's selection operation on a target effective range among the one or more effective ranges.

[0156] Figure 7 It is a configuration interface, and this application is a register configuration interface. This interface is triggered and displayed when the configuration enable flag indicates that register configuration is required, and is used by the user to select the target effective range of the target register. In the embodiment of this application, the effective range information includes the target processor, the thread corresponding to the target processor, and the processor core corresponding to the target processor. Figure 7 As shown in the figure, the interface displays a drop-down menu of effective range information. The drop-down menu displays the effective range that the target register can be used to configure, that is, the target processor, the thread corresponding to the target processor, and the processor core corresponding to the target processor. Figure 7 As shown, the user selects the target processor as the target effective range.

[0157] In method 1, different application scenarios require different register effective ranges to be configured. By providing multiple effective range options for users to choose from, it helps computing devices to support diverse configuration requirements. In addition, multiple effective range options are displayed to users through the register configuration interface, which simplifies the user configuration process. Users do not need to specify the configuration range through complex commands, but can directly select on the register configuration interface, improving configuration efficiency.

[0158] Mode 2: When the configuration information includes the value of the target bit of the target register, a configuration operation of the user is received.

[0159] The target bit is one or more bits in the target register.

[0160] In one example, the above S601 specifically receives the user's configuration operation in the following manner:

[0161] First, the BIOS obtains the bit information.

[0162] The bit information is used to display one or more bits of the target register in the register configuration interface.

[0163] In a possible implementation manner, the bit information includes multiple bits of the target register.

[0164] In a possible implementation, the BIOS may send an instruction to a target processor in the computing device to request selectable bits of a target register, and after receiving the instruction, the target processor sends bit information of the target register to the BIOS.

[0165] In a possible implementation, after acquiring the bit information, the BIOS displays the bit information on the register configuration interface, so that the user can select the target bit of the target register and the value of the target bit after viewing the bit information.

[0166] Optionally, after acquiring the bit information, the BIOS sends the bit information to a display in the computing device or an external display device, and displays the bit information in the register configuration interface to the user through the display or the external display device.

[0167] Exemplarily, the display format of the bit information in the register configuration interface is not specifically limited here, and can be in the form of a list, or an information set consisting of bit information in any form such as a table, which can display one or more bits of the target register.

[0168] Then, when the user selects a target bit from one or more bits, the BIOS obtains the value of the target bit selected by the user. Exemplarily, the value of the bit may be 0 or 1. Of course, the user may also manually input the value of the target bit.

[0169] Figure 8 It is a configuration interface, and this application is a register configuration interface. This interface is triggered and displayed when the configuration enable flag indicates that register configuration is required, and is used by the user to select the target bit value of the target register. Figure 8 As shown, the interface displays bit information, wherein the bit information includes multiple bits. The interface includes two drop-down menus. The drop-down menu of the bit displays multiple bits that can be used for configuration in the target register. The drop-down menu of the bit value displays the value (1 or 0) of each bit that the user can select. Figure 8 As shown, the user sets the value of the 5th bit to 1.

[0170] In method 2, bits and bit values ​​are used to control the characteristics of the target processor. Multiple bits of the target register are displayed to the user in the register configuration interface. On the one hand, the user can intuitively see which bits are configurable. This visual presentation simplifies the user's configuration process. On the other hand, the user can optimize the processor's characteristics by accurately configuring the bits, so that the target processor can meet different application scenarios.

[0171] Mode 3: When the configuration information includes the address of the target register, a configuration operation of the user is received.

[0172] In one example, the above S601 is specifically implemented in the following manner:

[0173] First, the BIOS obtains a list of addresses of registers in the target processor.

[0174] The address list is used to display the addresses of one or more registers in the target processor.

[0175] Illustratively, the address list may be as shown in Table 1.

[0176] Table 1

[0177] address register XXXX1 Register A XXXX2 Register B XXXX3 Register C

[0178] In Table 1, in the computing device, the address of register A is XXXX1, the address of register B is XXXX2, and the address of register C in the computing device is XXXX3.

[0179] In a possible implementation, the BIOS may send an instruction to a target processor in the computing device to request the addresses of registers that can be configured. After receiving the instruction, the target processor sends an address list of each register to the BIOS.

[0180] In a possible implementation, after acquiring the address list, the BIOS displays the address list on the register configuration interface so that the user can select a target register after viewing the address list.

[0181] Optionally, after acquiring the address list, the BIOS sends the address list to a display in the computing device or an external display device, and displays the address list in the register configuration interface to the user through the display or the external display device.

[0182] It is understandable that the manner of displaying the register address is not limited to the form of a list, but may also be any form of information set consisting of addresses such as a table, and the information set may display the address of one or more registers in the computing device.

[0183] Then, the BIOS receives a selection operation of the user for the target address in the address list, and determines the register corresponding to the target address as the target register.

[0184] Fig. 9 It is a configuration interface, and in this application it is a register configuration interface. Specifically, the configuration information includes the address of the target register. This interface is triggered and displayed when the configuration enable flag indicates that the register needs to be configured, and is used by the user to select the target register to be configured. Fig. 9 As shown, the interface includes a drop-down menu of registers. The registers corresponding to the addresses displayed in the drop-down menu are various registers in the computing device. The user determines the target register by selecting an address in the drop-down menu. Fig. 9 In the drop-down menu, the user selects the register corresponding to address XXXX2 as the target register.

[0185] In method 3, a list containing multiple register addresses is provided to the user, so that the user can intuitively and quickly locate the register to be configured, thereby improving the convenience of the configuration operation. The user directly selects the address of the target register from the address list, thereby avoiding errors that may be caused by manual address entry, thereby improving configuration efficiency and user experience.

[0186] The above embodiment obtains the configuration information of the target register by adding a register configuration interface in the BIOS setup interface. In addition, the configuration information of the target register can also be obtained through the in-band configuration tool of the OS in the CPU. Exemplarily, the OS uses the register corresponding to the target address selected by the user as the target register by calling the in-band configuration tool; then, the target effective range and the target bit value of the target register input by the user are obtained, and the target effective range and the target bit value are determined as the configuration information of the target register, and the configuration information of the target register is sent to the BIOS, so that the BIOS configures the target register based on the configuration information. Of course, the configuration information of the target register can also be obtained through the redfish interface configuration tool of the BMC. The specific process of the BMC obtaining the configuration information using the redfish interface configuration tool is similar to the process of the OS obtaining the configuration information mentioned above, which will not be repeated here. This application does not specifically limit the specific implementation method for obtaining the configuration information, and can be set according to actual conditions.

[0187] In the second part of the embodiment of the present application, the flexibility of configuring the target register is improved by the user configuring the target effective range and the target bit value in the register configuration interface. The user can make precise adjustments according to actual needs to ensure that the characteristics of the target processor meet actual needs.

[0188] The above is the second part of the embodiment of the present application. The following describes the process of configuring the target register based on the configuration information of the target register.

[0189] In the implementation of the present application, the target register is configured based on the configuration information of the target register, including multiple implementation methods, which are exemplified by methods a and b below. Among them, the configuration information in method a is obtained through the configuration operation in the above method 1, and the configuration information in method b is obtained through the configuration operation in the above method 2.

[0190] Mode a: The configuration information includes a target effective range. The target effective range indicates that the configuration information acts on any one of the target processor, the thread corresponding to the target processor, and the processor core. The above S202 includes the following a1-a2:

[0191] a1: BIOS determines the first target interface based on the target effective range.

[0192] The first target interface is used to configure the effective range of the target register as the target effective range. Different effective ranges of the target register correspond to different setting interfaces.

[0193] a2: BIOS configures the effective range of the target register by calling the first target interface.

[0194] For example, taking the target effective range as the processor core as an example, assuming that the target effective range is processor core 2. The BIOS will apply the configuration information in the register to processor core 2 by calling the target interface corresponding to processor core 2.

[0195] In this way, different effective ranges correspond to different target interfaces. The user selects the appropriate effective range according to actual needs, determines the first target interface through the target effective range, and calls the interface to configure the effective range of the target register, which simplifies the configuration process. The user does not need to understand the configuration details of the underlying registers in the computing device. He only needs to select the corresponding effective range on the register configuration interface to complete the register configuration. Through automated interface calls, the configuration efficiency of the configuration process is improved.

[0196] Mode b: The configuration information includes the value of the target bit. The target bit is one or more bits in the target register. The above S202 includes the following b1-b2:

[0197] b1: BIOS determines the second target interface based on the value of the target bit.

[0198] The second target interface is the first setting interface, or the second setting interface. The first setting interface is used to assign the first bit value to the target bit. The second setting interface is used to assign the second bit value to the target bit.

[0199] Exemplarily, when the first bit value is 1, the first setting interface is used to perform a "set" (or 1) operation. The BIOS reads the current value of the target bit, inputs the current value to the first setting interface, and modifies the current value of the target bit to the value (1) of the target bit in the configuration information through the "set" (or 1) operation of the first setting interface.

[0200] Exemplarily, when the second bit value is 0, the second setting interface is a "clear" (and 0) operation. The BIOS reads the current value of the target bit, inputs the current value to the second setting interface, and modifies the current value of the target bit to the value (0) of the target bit in the configuration information through the "clear" (and0) operation of the second setting interface.

[0201] b2: The BIOS configures the value of the target bit of the target register by calling the second target interface.

[0202] In this way, the value of the target bit is set to the first bit (for example, 1) through the first setting interface, and the value of the target bit is set to the second bit (for example, 0) through the second setting interface. The predefined interface and configuration process are used to simplify the user's operation of configuring the bits of the target register.

[0203] In some embodiments, the configuration information of the target register may also be integrated into the BIOS, and the configuration of the target register may be achieved by having the manufacturer release the BIOS with the target register configuration information integrated therein.

[0204] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. In order to achieve the above functions, the configuration device of the register includes a hardware structure and / or software module corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0205] The embodiment of the present application can divide the register configuration device into functional modules according to the above method. For example, the register configuration device can include various functional modules corresponding to the various functional divisions, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation.

[0206] For example, Fig.10A possible structural schematic diagram of a register configuration device involved in the above embodiment is shown, and the register configuration device includes: a first acquisition unit 1001 and a first configuration unit 1002; during the startup of the computing device, the first acquisition unit 1001 is used to obtain configuration information of the target register from a preset storage area of ​​the computing device; the target register is one or more registers of the target processor in the computing device; the configuration information is used to control the characteristics of the target processor; the first configuration unit 1002 is used to configure the target register based on the configuration information of the target register.

[0207] Optionally, the device further includes: a second acquisition unit and a storage unit. The second acquisition unit is used to acquire the configuration information of the target register. The storage unit is used to store the configuration information of the target register in a preset storage area.

[0208] Optionally, the device further includes: a second configuration unit. The second configuration unit is configured to configure the target register based on the configuration information of the target register.

[0209] Optionally, in the apparatus, the preset storage area is a storage area of ​​a non-volatile memory in a computing device.

[0210] Optionally, the device further includes: a third acquisition unit. The third acquisition unit is used to acquire a configuration enable flag, which is used to indicate whether to perform register configuration. The first acquisition unit 1001 is specifically used to acquire configuration information from a preset storage area when the configuration enable flag indicates that register configuration is required.

[0211] Optionally, the first acquisition unit 1001 is specifically configured to: guide the operating system OS of the computing device to start up when the configuration enable flag indicates that register configuration is not required.

[0212] Optionally, the configuration information includes a target effective range and a target bit value of a target register; the target effective range indicates that the configuration information acts on the target processor, the thread corresponding to the target processor, and any one of the processor cores; the multiple bits in the target register include the target bit; the second acquisition unit is specifically used to: receive a user's configuration operation, the configuration operation is used to configure the target effective range and the target bit value in the register configuration interface; based on the configuration operation, determine the target effective range and the target bit value.

[0213] Optionally, the second acquisition unit is specifically used to: acquire effective range information; the effective range information is used to display one or more effective ranges of the target register in the register configuration interface; and receive a user's selection operation on a target effective range in one or more effective ranges.

[0214] Optionally, the second acquisition unit is specifically used to: acquire bit information; the bit information is used to display one or more bits of the target register in the register configuration interface; when the user selects a target bit from one or more bits, acquire the value of the target bit selected by the user.

[0215] Optionally, the device further includes: a fourth acquisition unit and a receiving unit. The fourth acquisition unit is used to acquire an address list of each register in the target processor, and the address list is used to display the address of one or more registers in the target processor. The receiving unit is used to receive a user's selection operation for a target address in the address list, and determine the register corresponding to the target address as the target register.

[0216] Optionally, the configuration information includes a target effective range, and the target effective range indicates that the configuration information acts on any one of the target processor, the thread corresponding to the target processor, and the processor core. The first configuration unit 1002 is specifically used to: determine the first target interface based on the target effective range; the first target interface is used to configure the effective range of the target register as the target effective range; different effective ranges of the target register correspond to different setting interfaces; and configure the effective range of the target register by calling the first target interface.

[0217] Optionally, the configuration information includes the value of the target bit; the multiple bits in the target register include the target bit. The first configuration unit 1002 is specifically used to: determine the second target interface based on the value of the target bit; the second target interface is the first setting interface, or the second setting interface; the first setting interface is used to assign the first bit value to the target bit; the second setting interface is used to assign the second bit value to the target bit; and the value of the target bit of the target register is configured by calling the second target interface.

[0218] Optionally, in the device, the configuration information of the target register is determined based on the target characteristics of the target processor; the target characteristics are the performance of the target processor that is reduced when the microcode is upgraded.

[0219] For the detailed description of the above optional methods, please refer to the above method embodiments, which will not be repeated here. In addition, the explanation of any register configuration device provided above and the description of the beneficial effects can refer to the above corresponding method embodiments, which will not be repeated here.

[0220] The embodiment of the present application also provides a computer device, which includes a processor and a memory, the processor is connected to the memory, the memory stores a computer execution instruction, and the processor implements the data processing method in the above embodiment when executing the computer execution instruction. The embodiment of the present application does not impose any restrictions on the specific form of the computer device. For example, the computer device can be a terminal device or a network device. Among them, the terminal device can be called: terminal, user equipment (user equipment, UE), terminal equipment, access terminal, user unit, user station, mobile station, remote station, remote terminal, mobile device, user terminal, wireless communication device, user agent or user device, etc. The terminal device can be a mobile phone, augmented reality (augmented reality, AR) device, virtual reality (virtual reality, VR) device, tablet computer, laptop computer, ultra-mobile personal computer (ultra-mobile personal computer, UMPC), netbook, personal digital assistant (personal digital assistant, PDA), etc. The network device can be a server, etc. Among them, the server can be a physical or logical server, or it can be two or more physical or logical servers that share different responsibilities and cooperate with each other to realize the functions of the server.

[0221] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed on a computer, the computer is enabled to execute any of the methods executed by the computer devices provided above.

[0222] For the explanation of the relevant contents and description of the beneficial effects of any of the above-mentioned computer-readable storage media, reference may be made to the above-mentioned corresponding embodiments, which will not be repeated here.

[0223] The embodiment of the present application also provides a chip. The chip integrates a control circuit and one or more ports for implementing the functions of the above-mentioned computer device. Optionally, the functions supported by the chip can be referred to above and will not be repeated here. A person of ordinary skill in the art can understand that all or part of the steps of implementing the above-mentioned embodiment can be completed by instructing the relevant hardware through a program. The program can be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a random access memory, etc. The above-mentioned processing unit or processor can be a central processing unit, a general-purpose processor, an application specific integrated circuit (ASIC), a microprocessor (digital signal processor, DSP), a field programmable gate array (field programmable gatearray, FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0224] The embodiment of the present application also provides a computer program product including instructions, when the instructions are run on a computer, the computer executes any one of the methods in the above embodiments. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more servers that can be integrated with the medium. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., an SSD), etc.

[0225] It should be noted that the above-mentioned devices for storing computer instructions or computer programs provided in the embodiments of the present application, such as but not limited to the above-mentioned memories, computer-readable storage media and communication chips, etc., are all non-transitory.

[0226] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. that contains one or more servers that can be integrated with a medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0227] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other changes to the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0228] Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A register configuration method, characterized in that: A method for applying a basic input and output system BIOS in a computing device includes: Get the configuration information of the target register; Storing the configuration information of the target register in a preset storage area; During the startup of the computing device, the configuration information of the target register is obtained from the preset storage area; the target register is one or more registers of the target processor in the computing device; The target register is configured based on the configuration information of the target register.

2. The configuration method according to claim 1, characterized in that: In the process of starting the computing device, before acquiring the configuration information of the target register from the preset storage area of ​​the computing device, the method further includes: Obtaining a configuration enable flag, wherein the configuration enable flag is used to indicate whether to perform register configuration; The preset storage area of ​​the computing device obtains configuration information of the target register, including: When the configuration enable flag indicates that register configuration is required, configuration information is acquired from the preset storage area.

3. The configuration method according to claim 2, characterized in that: The method further comprises: When the configuration enable flag indicates that register configuration is not required, the operating system OS of the computing device is guided to start.

4. The configuration method according to claim 1, characterized in that: The configuration information includes a target effective range and a target bit value of the target register; the target effective range indicates that the configuration information acts on any one of the target processor, the thread corresponding to the target processor, and the processor core; The plurality of bits in the target register include the target bit; The obtaining of the configuration information of the target register includes: Receiving a configuration operation from a user, wherein the configuration operation is used to configure the target effective range and the value of the target bit in a register configuration interface; Based on the configuration operation, the target validity range and the target bit value are determined.

5. The configuration method according to claim 4, characterized in that: The receiving of the user's configuration operation includes: Acquire effective range information; the effective range information is used to display one or more effective ranges of the target register in the register configuration interface; A user selection operation on a target effective range among the one or more effective ranges is received.

6. The configuration method according to claim 4 or 5, characterized in that: The receiving of the user's configuration operation includes: Obtaining bit information; the bit information is used to display one or more bits of the target register in the register configuration interface; In case that the user selects a target bit from the one or more bits, a value of the target bit selected by the user is obtained.

7. The configuration method according to any one of claims 4 to 6, characterized in that: The method further comprises: Obtaining an address list of each register in the target processor, wherein the address list is used to display the address of one or more registers in the target processor; A selection operation of a user on a target address in the address list is received, and a register corresponding to the target address is determined as the target register.

8. The configuration method according to claim 1, characterized in that: The configuration information includes a target effective range, and the target effective range indicates that the configuration information acts on any one of the target processor, the thread corresponding to the target processor, and the processor core; The configuring the target register based on the configuration information of the target register includes: Based on the target effective range, determining a first target interface; the first target interface is used to configure the effective range of the target register to the target effective range; different effective ranges of the target register correspond to different setting interfaces; The effective range of the target register is configured by calling the first target interface.

9. The configuration method according to claim 1 or 8, characterized in that: The configuration information includes a value of a target bit; the multiple bits in the target register include the target bit; and configuring the target register based on the configuration information of the target register includes: Based on the value of the target bit, a second target interface is determined; the second target interface is a first setting interface, or a second setting interface; the first setting interface is used to assign a first bit value to the target bit; the second setting interface is used to assign a second bit value to the target bit; By calling the second target interface, the value of the target bit of the target register is configured.

10. A computer device, characterized in that: include: Processor and memory; The processor is connected to a memory, the memory is used to store computer-executable instructions, and the processor executes the computer-executable instructions stored in the memory, so that the computer device implements the method according to any one of claims 1 to 9.

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