Task execution method, device, system and equipment and storage medium

Abstract

The invention provides a task execution method, device and system, equipment and a storage medium. The method comprises the steps that under the condition that the value of a target address register in a memory is a first address value, a first instruction is sent to a processing module, so that the processing module executes a processing task corresponding to the first instruction in a first address space corresponding to the first address value; switching the value of the target address register from the first address value to a second address value; and under the condition that the value of the target address register is the second address value, a second instruction is sent to the processing module, so that the processing module executes a processing task corresponding to the second instruction in a second address space corresponding to the second address value. According to the invention, the utilization rate of hardware resources can be improved, so that the task execution efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer electronic technology, and relates to but is not limited to a task execution method, device, system, equipment and storage medium. Background Art

[0002] In the related art, after the core (Core) of the processing module is started, an address space is usually selected to execute the processing task corresponding to the instruction issued by the driver. During the operation life cycle of the processing module, usually one address space is available, that is, the task execution of the processing module is all run in the selected address space.

[0003] In this way, if you need to run a processing task corresponding to a larger data stream, it will be limited by an address space, resulting in low utilization of hardware resources, thereby affecting the efficiency of task execution. Summary of the invention

[0004] The embodiments of the present application provide a task execution method, apparatus, system, device and storage medium, which can improve the utilization rate of hardware resources and thus improve the efficiency of task execution.

[0005] The technical solution of this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a task execution method, the method comprising:

[0007] When the value of the target address register in the memory is a first address value, sending a first instruction to the processing module so that the processing module executes a processing task corresponding to the first instruction in a first address space corresponding to the first address value;

[0008] Switching the value of the target address register from the first address value to a second address value;

[0009] When the value of the target address register is the second address value, a second instruction is sent to the processing module, so that the processing module executes a processing task corresponding to the second instruction in a second address space corresponding to the second address value.

[0010] In a second aspect, an embodiment of the present application provides a task execution method, the method comprising:

[0011] In response to a first instruction sent by the driver, a processing task corresponding to the first instruction is executed in a first address space to obtain a first operation result; the first instruction is sent by the driver after setting the value of a target address register in a memory to a first address value, and the first address space corresponds to the first address value;

[0012] In response to a second instruction sent by the driver, a processing task corresponding to the second instruction is executed in a second address space to obtain a second operation result; the second instruction is sent by the driver after setting the value of the target address register to the first address value and switching to the second address value, and the second address space corresponds to the second address value.

[0013] In a third aspect, the present application provides a task execution device, the device comprising:

[0014] a sending module, configured to send a first instruction to a processing module when the value of a target address register in a memory is a first address value, so that the processing module executes a processing task corresponding to the first instruction in a first address space corresponding to the first address value;

[0015] A switching module, configured to switch the value of the target address register from the first address value to a second address value;

[0016] The sending module is further configured to send a second instruction to the processing module when the value of the target address register is the second address value, so that the processing module executes a processing task corresponding to the second instruction in a second address space corresponding to the second address value.

[0017] In a fourth aspect, the present application provides a processing module, the processing module comprising:

[0018] a receiving unit, configured to receive a first instruction, wherein the first instruction is sent by the driver after the value of the target address register in the memory is set to a first address value, and the first address space corresponds to the first address value; and receive a second instruction, wherein the second instruction is sent by the driver after the value of the target address register is set to the first address value and switched to a second address value, and the second address space corresponds to the second address value;

[0019] An execution unit is used to respond to a first instruction sent by the driver, execute a processing task corresponding to the first instruction in a first address space, and obtain a first operation result; respond to a second instruction sent by the driver, execute a processing task corresponding to the second instruction in a second address space, and obtain a second operation result.

[0020] In a fifth aspect, the present application provides a task execution system, the system comprising: a main processor, a processing module and a memory, wherein a driver is run on the main processor; wherein:

[0021] The driver is used to send a first instruction to the processing module when the value of the target address register in the memory is a first address value; switch the value of the target address register from the first address value to a second address value; and send a second instruction to the processing module when the value of the target address register is the second address value; the first address space corresponds to the first address value, and the second address space corresponds to the second address value;

[0022] The processing module is used to respond to a first instruction sent by the driver, execute a processing task corresponding to the first instruction in a first address space, and obtain a first operation result; respond to a second instruction sent by the driver, execute a processing task corresponding to the second instruction in a second address space, and obtain a second operation result;

[0023] The memory is used to store first relevant data of the processing task corresponding to the first instruction in the first address space, and to store second relevant data of the processing task corresponding to the second instruction in the second address space.

[0024] In a sixth aspect, the present application provides an electronic device, comprising: a processor and a memory, the memory being used to store a computer program, the processor being used to call and run the computer program stored in the memory to execute the method described in the first aspect; or, executing the method described in the second aspect.

[0025] In a seventh aspect, the present application provides a computer-readable storage medium, wherein the computer storage medium stores a computer program, and when the computer program is executed by at least one processor, it implements the method described in the first aspect; or, it implements the method described in the second aspect.

[0026] The embodiment of the present application provides a task execution method, device, system, equipment and storage medium, the method comprising: when the value of the target address register in the memory is a first address value, sending a first instruction to the processing module so that the processing module performs the processing task corresponding to the first instruction in the first address space corresponding to the first address value; switching the value of the target address register from the first address value to the second address value; when the value of the target address register is the second address value, sending a second instruction to the processing module so that the processing module performs the processing task corresponding to the second instruction in the second address space corresponding to the second address value. By switching the value of the target address register, the operation space of the processing module can be quickly and flexibly switched, so that the processing module can switch to execute multiple tasks in different address spaces, thereby realizing multi-processing tasks across address spaces, improving the concurrency and efficiency of the system, and improving the utilization rate of hardware resources. In addition, by switching the address space, the processing logic of different tasks can be managed separately, reducing the complexity of the system and the coupling degree of different task processing logics, and facilitating the maintenance and management of the task operation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and are used together with the specification to illustrate the technical solution of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0029] Figure 1 A schematic diagram of a VPU task execution process in a related technology provided in an embodiment of the present application Figure 1 ;

[0030] Figure 2 A schematic diagram of a VPU task execution process in a related technology provided in an embodiment of the present application Figure 2 ;

[0031] Figure 3 A flowchart of a task execution method provided in an embodiment of the present application Figure 1 ;

[0032] Figure 4 A schematic diagram of the structure of a task execution system provided in an embodiment of the present application Figure 1 ;

[0033] Figure 5 A schematic diagram of a task execution method provided in an embodiment of the present application;

[0034] Figure 6 A flowchart of a task execution method provided in an embodiment of the present application Figure 2 ;

[0035] Figure 7 An interactive schematic diagram of a task execution method provided in an embodiment of the present application;

[0036] Figure 8 A schematic diagram of the structure of a task execution system provided in an embodiment of the present application Figure 2 ;

[0037] Fig. 9 A schematic diagram of the structure of a task execution device provided in an embodiment of the present application;

[0038] Fig.10 A schematic diagram of the structure of a processing module provided in an embodiment of the present application;

[0039] Fig.11 A schematic diagram of the structure of a task execution system provided in an embodiment of the present application Figure 3 ;

[0040] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0042] In the following description, references to “some embodiments”, “embodiments of the present application”, “embodiments of the present application” and examples, etc., describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0043] If similar descriptions of "first / second" appear in the application documents, the following instructions are added. In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0045] In the related art, after the core (Core) of the processing module is started, an address space is usually selected to execute the processing task corresponding to the instruction issued by the driver. During the operation life cycle of the processing module, usually one address space is available, that is, the task execution of the processing module is all run in the selected address space.

[0046] Taking the processing module as the Vision Processing Unit (VPU) as an example, the VPU supports parallel decoding of multiple videos. If the address width of the VPU is 32 bits, the addressing space of the VPU is 4 gigabytes (G). Normally, small-resolution videos require less memory, and a 4G space can meet the operating requirements. When playing high-definition videos in large-resolution scenes, the 4G space of the VPU is insufficient, resulting in a reduction in the number of videos that can be played in parallel by a VPU. For example, the memory required to play an 8K video is about 2.4G, and a 4G space can only allocate a buffer (buf) required to meet the needs of an 8K video, which means that the VPU can only work on one 8K video stream at the same time. At startup, the VPU can set a global parameter (denoted as high_reg) to select which 4G space to work in, and during the operating life cycle of the VPU core, the VPU core can only run in this 4G space.

[0047] Figure 1 A schematic diagram of a VPU task execution process in a related technology provided in an embodiment of the present application Figure 1 ,like Figure 1As shown, when the VPU is started, the global parameter high_reg is used to indicate the working space of the VPU. For example, the storage space in the memory includes: the first address space (0-4G memory segment seg0), the second address space (4-8G memory segment seg1), the third address space (8-12G memory segment seg2) and other address spaces. When the global parameter high_reg = 0, the VPU performs related processing tasks in the first address space seg0; when the global parameter high_reg = 1, the VPU performs related processing tasks in the second address space seg1; when the global parameter high_reg = 2, the VPU performs related processing tasks in the third address space seg2. It should be noted that by setting a high register high_reg, you can choose which 4G space to run. However, this high_reg needs to be determined in the initial stage. After setting, the VPU will always run in this space. All subsequent encoding and decoding operations using this VPU will run in this space, which is inseparable from the maximum 4G space limitation.

[0048] Figure 2 A schematic diagram of a VPU task execution process in a related technology provided in an embodiment of the present application Figure 2 ,like Figure 2 As shown, the driver sends command 1 (cmd1) to the VPU. After receiving cmd1, the VPU exits the waiting state (VPU exithalt status). When the VPU exits the waiting state, the VPU executes the corresponding processing task of cmd1 in the preset address space, obtains the corresponding operation result of cmd1, and returns the corresponding operation result of cmd1 to the driver, and the VPU enters the waiting state (VPU in halt status), and the driver believes that cmd1 has been executed. Further, the driver sends command 2 (cmd2) to the VPU. After receiving cmd2, the VPU exits the waiting state. When the VPU exits the waiting state, the VPU executes the corresponding processing task of cmd2 in the preset address space, obtains the corresponding operation result of cmd2, and returns the corresponding operation result of cmd2 to the driver, and the VPU enters the waiting state, and the driver believes that cmd2 has been executed. Further, the driver sends command 3 (cmd3) to the VPU. After receiving cmd3, the VPU exits the waiting state. When the VPU exits the waiting state, the VPU executes the corresponding processing task of cmd3 in the preset address space, obtains the corresponding operation result of cmd3, and returns the corresponding operation result of cmd3 to the driver, and the VPU enters the waiting state, and the driver considers that the execution of cmd3 is completed.

[0049] In the related technology, when the processing unit is called to perform a processing task, all data buffers are in the specified address space. For example, for the scenario of decoding 8K resolution video, playing one video requires about 2.4G of space. If one more 8K video is decoded, the 4G space of this VPU cannot accommodate it, which leads to the limitation that the VPU can only decode one 8K video at the same time. For the decoding of 8K resolution scenario, although the required buffer is small, it is also limited by the number of data streams. Therefore, if you need to run a processing task corresponding to a larger data stream, it will be limited by an address space, resulting in low utilization of hardware resources, thereby affecting the efficiency of task execution.

[0050] Based on this, the embodiments of the present application provide a task execution method, device, system, equipment and storage medium, which can improve the utilization rate of hardware resources, thereby improving the efficiency of task execution. The technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0051] Figure 3 A flowchart of a task execution method provided in an embodiment of the present application Figure 1 The task execution method can be applied to a driver, which can run on a main processor of an electronic device. Figure 3 As shown, the method includes the following steps S101 to S103:

[0052] S101. When the value of a target address register in a memory is a first address value, the driver sends a first instruction to a processing module, so that the processing module executes a processing task corresponding to the first instruction in a first address space corresponding to the first address value.

[0053] In some implementations, the task execution method is applied to a task execution system. Figure 4 A schematic diagram of the structure of a task execution system provided in an embodiment of the present application Figure 1 ,like Figure 4 As shown, the task execution system includes a main processor 1001, a driver 1002 and a processing module 1003, wherein the driver 1002 runs on the main processor 1001. Exemplarily, the main processor can be a central processing unit (CPU), and the processing module can be a VPU. In the task execution system, the driver 1002 plays a scheduling role, and the driver 1002 can switch the value of the target address register so that the processing module 1003 can perform different processing tasks in different address spaces. Here, the address space can also be described as a memory segment.

[0054] In some implementations, the value of the target address register refers to the value stored in the target register, which may be the address value of at least one memory access address bit in the memory. For example, the target address register may be recorded as high_reg.

[0055] The value stored in the target address register may be written and / or updated by the driver in any suitable manner. For example, the driver may write a value to the target address register or update the value in the target address register via a Peripheral Component Interconnect (PCI) bus.

[0056] In some embodiments, the first address value corresponds to the first address space. For example, the value of the target address register being the first address value can be represented as high_reg = 0. When the value of the target address register is the first address value, the driver sends a first instruction to the processing module, and the first instruction can be represented as seg0cmd1.

[0057] Correspondingly, after receiving the first instruction, the processing module executes the processing task corresponding to the first instruction in the first address space corresponding to the first address value.

[0058] In some embodiments, the processing task corresponding to the first instruction is a processing task related to the first data stream. Exemplarily, the processing task related to the first data stream includes one or more of the following: a video processing task of the first video stream, an audio processing task of the first audio stream, data analysis processing of the first data stream, etc. The embodiment of the present application does not impose any limitation on the processing task corresponding to the first instruction.

[0059] S102 . The driver switches the value of the target address register from the first address value to the second address value.

[0060] In some implementations, after the driver sends the first instruction to the processing module, the driver switches the value of the target address register from the first address value to the second address value.

[0061] In some implementations, the value of the target address register being the second address value may be represented as high_reg=1.

[0062] In some embodiments, the first address value is different from or the same as the second address value. When the first address value is different from the second address value, the first address value and the second address value may indicate different address spaces. For example, when the first address value is 0, the first address value indicates a first address space of 0-4G, and when the second address value is 1, the second address value indicates a second address space of 4-8G. When the first address value and the second address value are the same, the first address value and the second address value may indicate the same address space.

[0063] In some implementations, the first address value is an extended address bit of the first address space, and the second address value is an extended address bit of the second address space, wherein the extended address bit may be a high address bit of the address space.

[0064] S103: When the value of the target address register is the second address value, the driver sends a second instruction to the processing module, so that the processing module executes a processing task corresponding to the second instruction in a second address space corresponding to the second address value.

[0065] In some implementations, after the driver switches the value of the target address register from the first address value to the second address value, the driver sends a second instruction to the processing module.

[0066] In some embodiments, the second address value corresponds to the second address space. For example, the value of the target address register is the second address value and can be represented as high_reg = 1. When the value of the target address register is the second address value, the driver sends a second instruction to the processing module, and the second instruction can be represented as seg1cmd1.

[0067] Correspondingly, after receiving the second instruction, the processing module executes the processing task corresponding to the second instruction in the second address space corresponding to the second address value.

[0068] In some embodiments, the processing task corresponding to the second instruction is a processing task related to the second data stream. Exemplarily, the processing task related to the second data stream includes one or more of the following: a video processing task of the second video stream, an audio processing task of the second audio stream, data analysis processing of the second data stream, etc. The embodiment of the present application does not impose any limitation on the processing task corresponding to the second instruction.

[0069] In some implementations, the value of the target address register being the second address value may be represented as high_reg=1.

[0070] In some implementations, the processing task corresponding to the first instruction and the processing task corresponding to the second instruction may correspond to the same or different data streams.

[0071] It should be noted that the first instruction and the second instruction listed above are sent by the driver to the processing module at different times, so that the processing module can execute processing tasks with different instructions in different address spaces at different times.

[0072] In some implementations, taking the example of a driver sending two instructions to a processing unit (a first instruction and a second instruction), the main idea is that the driver switches the value of the target address register so that the processing unit performs processing tasks corresponding to the instructions in different address spaces, and the core is that the processing module uses time-division multiplexing to perform different processing tasks in different address spaces. In actual application scenarios, it can also be expanded to more than two instructions and / or more than two data streams, and this application does not make any limitation on this.

[0073] Exemplarily, the processing module is used to execute the processing tasks of M data streams within one operation life cycle, and the driver sends N instructions to the processing module; wherein one operation life cycle of the processing module refers to the stage from the start to the termination of the processing module, and the task execution method includes:

[0074] During an operation life cycle of the processing unit, when the value of the target address register is the tth address value, the driver sends the nth instruction related to the mth data stream to the processing module; wherein m is a positive integer greater than or equal to 1 and less than M; n is a positive integer greater than or equal to 1 and less than N; n is greater than or equal to m; t is less than or equal to m;

[0075] When the processing module receives the nth instruction, the processing unit executes the processing task corresponding to the nth instruction in the tth address space corresponding to the tth address value, obtains the nth operation result, and returns the nth operation result to the driver;

[0076] When the driver receives the nth operation result, it switches the value of the target address register from the tth address value to the t+1th address value;

[0077] When the value of the target address register is the t+1th address value, the driver sends the n+1th instruction related to the m+1th data stream to the processing module;

[0078] When the processing module receives the n+1th instruction, the processing unit executes the processing task corresponding to the n+1th instruction in the t+1th address space corresponding to the t+1th address value, obtains the n+1th operation result, and returns the n+1th operation result to the driver;

[0079] The driver continues to switch the value of the target address register from the t+1th address value to the t+2th address value when receiving the n+1th operation result;

[0080] When the value of the target address register is the t+2th address value, the driver sends the n+2th instruction related to the m+2th data stream to the processing module;

[0081] When the processing module receives the n+2th instruction, the processing unit executes the processing task corresponding to the n+2th instruction in the t+2th address space corresponding to the t+2th address value, obtains the n+2th operation result, and returns the n+2th operation result to the driver, until the processing module completes the processing tasks corresponding to each of the N instructions, and the driver obtains N operation results, thereby completing the processing tasks corresponding to the M data streams.

[0082] In some implementations, the M data streams each correspond to a different address space; or, some of the M data streams each correspond to a different address space; or, the M data streams each correspond to the same address space.

[0083] In some embodiments, a task execution method is provided, the method comprising: when the value of the target address register in the memory is the first address value, sending a first instruction to the processing module so that the processing module executes the processing task corresponding to the first instruction in the first address space corresponding to the first address value; switching the value of the target address register from the first address value to the second address value; when the value of the target address register is the second address value, sending a second instruction to the processing module so that the processing module executes the processing task corresponding to the second instruction in the second address space corresponding to the second address value. By switching the value of the target address register, the operation space of the processing module can be quickly and flexibly switched, so that the processing module can switch to execute multiple tasks in different address spaces, thereby realizing multi-processing tasks across address spaces, improving the concurrency and efficiency of the system, and improving the utilization of hardware resources. In addition, by switching the address space, the processing logic of different tasks can be managed separately, reducing the complexity of the system and the coupling degree of different task processing logics, and facilitating the maintenance and management of the task operation process. In addition, by effectively utilizing the hardware resources of the processing module and reasonably allocating the task execution time and priority, the overall performance of the system can be optimized, the processing efficiency and throughput can be improved, and the overall performance and efficiency of the system can be improved.

[0084] In some embodiments of the present application, the first address space is determined by address mapping between a first address value and a preset address range, and the second address space is determined by address mapping between a second address value and a preset address range; the preset address range represents the addressing range of the processing module.

[0085] In some embodiments, the first address space and the second address space are determined by address mapping the first address value and the second address value to a preset address range, respectively. The preset address range represents the addressing range of the processing module, that is, the address range that can be accessed. The preset address range specifies the valid address range that the processing module can access, and addresses outside this range may be invalid or inaccessible. In other words, the preset address range actually represents the addressing capability of the processing module, that is, the memory or peripheral address range that the processing module can effectively address.

[0086] It can be understood that the first address space is obtained by address mapping the first address value (for example, 0) with the preset address range, which means that when the value of the target address register is the first address value, the address accessed by the processing module will be in the first address space. The second address space is obtained by address mapping the second address value (for example, 1) with the preset address range, which means that when the value of the target address register is the second address value, the address accessed by the processing module will be in the second address space. Among them, the storage space size of the first address space and the second address space is the same, both of which are the storage space size of the preset address range. Through such address mapping and address range setting, the system can flexibly manage and access different address spaces and realize effective utilization of storage areas.

[0087] In some embodiments of the present application, the address bit width corresponding to the preset address range is K bits, the address bit width corresponding to the first address space is K+P bits, the low K bits of the addressing address in the first address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the first address space are the first address value; the address bit width corresponding to the second address space is K+P bits, the low K bits of the addressing address in the second address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the second address space are the second address value, wherein K is a positive integer greater than 1, and P is a positive integer.

[0088] In some embodiments, the address width corresponding to the preset address range is K bits, indicating that the processing module can use a K-bit address to address the memory or peripheral. The value of K can be determined according to actual conditions and is not limited here. For example, K can be 16, 32, or 64, etc.

[0089] In some embodiments, the preset address range is related to the core architecture of the processing module. For example, when the processing module is designed based on 32-bit address width and data width, the preset address range has a 32-bit width (K=32), that is, 0x0000_0000 to 0xffff_ffff.

[0090] In some embodiments, the first address value is the high P bits of the addressing address in the first address space, for example, if P is 1 and the first address value is 0, the highest bit of the addressing address in the first address space is 0, if P is 2 and the first address is 01, the high 2 bits of the addressing address in the first address space are 01; the second address value is the high P bits of the addressing address in the second address space, for example, if P is 1 and the second address value is 1, the highest bit of the addressing address in the second address space is 1, if P is 2 and the second address is 10, the high 2 bits of the addressing address in the second address space are 10. In other words, the value of the high P bits of the addressing address in the first address space is the first address value, if the driver sets the value of the target address register to the first address value (for example, 0), the processing module performs the corresponding processing task in the first address space. The value of the high P bits of the addressing address in the second address space is the second address value, if the driver sets the value of the target address register to the second address value (for example, 1), the processing module performs the corresponding processing task in the second address space. That is, the first address value and the second address value may be used to distinguish the first address space from the second address space.

[0091] Exemplarily, when the preset address range is 0x0000_0000 to 0xffff_ffff, if the first address value is 0, the addressing range of the first address space can be expressed as 0x0_0000_0000 to 0x0_ffff_ffff. If the second address value is 1, the addressing range of the second address space can be expressed as 0x1_0000_0000 to 0x1_ffff_ffff.

[0092] It is understandable that the above addressing method allows the processing module to use the same address value in different address spaces to access corresponding addresses in different address spaces, and to distinguish different address spaces, so that more flexible address management and resource access control can be provided.

[0093] In some embodiments, the processing module may be in a waiting state when it has not received a task processing instruction and has not performed task processing. After receiving the first instruction, the processing module switches from the waiting state to the awake state. In the awake state, the processing module may perform the corresponding processing task in the first address space corresponding to the first address value according to the instruction of the first instruction. After the processing module completes the processing task corresponding to the first instruction, it obtains the first execution result and returns the first execution result to the driver or other related modules. In this way, the driver or upper module can obtain the result of the processing module executing the task and perform subsequent processing or decision-making. After the processing module returns the first execution result to the driver or other related modules, it will switch from the awake state back to the waiting state again. Similarly, after the value in the target address register switches from the first address value to the second address value, the driver sends the second instruction to the processing module. After receiving the second instruction, the processing module switches from the waiting state to the awake state. In the awake state, the processing module may perform the corresponding processing task in the second address space corresponding to the second address value according to the instruction of the second instruction. After the processing module completes the processing task corresponding to the second instruction, it obtains the second execution result and returns the second execution result to the driver or other related modules. In this way, the driver or upper module can obtain the result of the processing module executing the task and perform subsequent processing or decision-making. After returning the second execution result, the processing module switches from the awake state to the waiting state. In the waiting state, the processing module can suspend the execution of the task and wait for the next instruction or trigger event.

[0094] It is understandable that the advantage of the above processing mode is that it can flexibly execute different tasks according to different instructions, making full use of the processing capacity of the processing module. At the same time, by managing the activity state of the processing module through state switching, it is possible to effectively balance system performance and energy consumption, and improve system efficiency and reliability.

[0095] In some embodiments of the present application, the processing task corresponding to the first instruction includes the i-th first task slice in the first processing task, the first processing task corresponds to the first instruction set, and the first instruction is the i-th first instruction in the first instruction set; the processing task corresponding to the second instruction includes the j-th second task slice in the second processing task, the second processing task corresponds to the second instruction set, and the second instruction is the j-th first instruction in the second instruction set, wherein i and j are both positive integers.

[0096] In some embodiments, the first instruction set includes multiple first instructions, and the first processing task corresponding to the first instruction set is divided into multiple first task slices. The second instruction set includes multiple second instructions, and the second processing task corresponding to the second instruction set is divided into multiple second task slices.

[0097] It can be understood that a processing task is divided into multiple task slices, each of which represents a part of the function or processing flow of a processing task. This division can make the management and execution of tasks more flexible and efficient.

[0098] In some embodiments, the processing tasks corresponding to the first instruction refer to the tasks involved in executing the first instruction, and these tasks can be further subdivided into the i-th first task slice in the first processing task, which means that the i-th instruction in the first instruction set corresponds to the i-th task slice of the first processing task. Similarly, the processing tasks corresponding to the second instruction refer to the tasks involved in executing the second instruction, and can be subdivided into the j-th second task slice in the second processing task, which means that the j-th instruction in the second instruction set corresponds to the j-th task slice of the second processing task.

[0099] In some embodiments of the present application, when the value of the target address register in the memory is the first address value in S101, the implementation of sending the first instruction to the processing module may include S1011:

[0100] S1011. When the value of the target address register is the first address value, send the i-th first instruction to the processing module, so that the processing module executes the i-th first task slice in the first address space.

[0101] In some embodiments, when the value of the target address register is the first address value, the driver sending the i-th first instruction to the processing module means pointing the execution pointer of the processing module to the i-th first task slice in the first address space, so that the processing module executes the task.

[0102] In some embodiments of the present application, the implementation of switching the value of the target address register from the first address value to the second address value in S102 may include S1021:

[0103] S1021. In response to receiving the execution result of the i-th first task slice sent by the processing module, switch the value of the target address register from the first address value to the second address value.

[0104] In some embodiments of the present application, in S103, when the value of the target address register is the second address value, the implementation of sending the second instruction to the processing module may include S1031:

[0105] S1031. When the value of the target address register is the second address value, send the jth second instruction to the processing module, so that the processing module executes the jth second task slice in the second address space.

[0106] In some embodiments, when the value of the target address register is the second address value, the driver sending the jth second instruction to the processing module means pointing the execution pointer of the processing module to the jth second task slice in the second address space, so that the processing module executes the task.

[0107] In some embodiments of the present application, the first processing task is a video processing task for a first video stream, and the i-th first task slice is an image processing task for an i-th frame image in the first video stream; the second processing task is a video processing task for a second video stream, and the j-th second task slice is an image processing task for an j-th frame image in the second video stream; the image processing tasks include: encoding processing tasks and / or decoding processing tasks.

[0108] In some implementations, in order to implement image encoding and decoding processing tasks in a video processing system, the first processing task may be for a first video stream, the i-th first task slice is the image processing task for the i-th frame image in the first video stream, and similarly, the second processing task and the j-th second task slice are also processing tasks corresponding to the j-th frame image in the second video stream.

[0109] In some embodiments, the image processing task includes: an encoding processing task and / or a decoding processing task. The encoding processing task generally refers to converting the original image data into compressed encoded data so as to occupy less bandwidth or storage space during transmission or storage. The decoding processing task decompresses the encoded data and restores it to the original image data for display or subsequent processing.

[0110] In some embodiments, in S1011, when the value of the target address register is the first address value, sending the i-th first instruction to the processing module so that the processing module executes the implementation of the i-th first task slice in the first address space includes:

[0111] When the value of the target address register is the first address value, sending the i-th first instruction to the processing module, so that the processing module performs the image processing task of the i-th frame image in the first video stream under the first address space;

[0112] In some embodiments, in S1031, when the value of the target address register is the second address value, sending the jth second instruction to the processing module so that the processing module executes the implementation of the jth second task slice in the second address space includes:

[0113] When the value of the target address register is the second address value, the jth second instruction is sent to the processing module, so that the processing module performs the image processing task of the jth frame image in the second video stream in the second address space.

[0114] It is understandable that the processing module automatically switches to the task of processing the j-th frame image of the second video stream after completing the i-th first task slice. This automatic switching can effectively manage the execution flow of the processing module, so that it can smoothly process the image data of different video streams. Exemplarily, assuming that the processing module needs to perform a series of operations when processing the i-th frame image of the first video stream, when these operations are completed, by switching the value of the target address register to the second address value, it can automatically switch to the task of processing the j-th frame image of the second video stream without manual intervention. This can improve processing efficiency and the degree of automation of the system. In general, it can help the processing module automatically switch to different processing tasks, so as to better meet the needs of the video processing system and improve processing efficiency and flexibility.

[0115] For example, the following takes the processing of two video streams as an example for explanation. Figure 5 A schematic diagram of a task execution method provided in an embodiment of the present application is shown as follows: Figure 5 As shown in the figure, assume that there are two 8K video streams, video stream 0 (video0) and video stream 1 (video1). The buffers required by these two video streams are created in different 4G spaces (address spaces), where video stream 0 corresponds to the first address space (seg0) and video stream 1 corresponds to the second address space (seg1). The processing module uses time-division multiplexing to perform processing tasks in different 4G segments (address spaces). For example, the processing module first encodes and decodes a frame of video stream 1 in the first address space (seg0), and then drives to change the value of the target address register so that the processing module encodes and decodes a frame of video stream 2 in the second address space (seg1), and then drives to switch the value of the target address register back to seg0. In this way, although the performance of the processing module in processing one video stream is reduced, the number of channels that the processing module can support in parallel increases, and even address spaces such as seg0\seg1\seg2\seg3\.. can be used to perform processing tasks.

[0116] It can be understood that, when the processing module receives the i-th first instruction, the processing module performs the encoding processing task or decoding processing task of the i-th frame image in the first video stream under the first address space, and when the processing module receives the j-th second instruction, the processing module performs the encoding processing task or decoding processing task of the j-th frame image in the second video stream under the second address space. In this way, the processing module can perform processing tasks of different data streams under different address spaces, thereby improving the hardware resource utilization of the processing module and improving the efficiency of task execution.

[0117] In some embodiments of the present application, the task execution method further includes S401 and S402:

[0118] S401, in response to receiving the execution result of the j-th second task slice sent by the processing module, switching the value of the target address register from the second address value to the first address value;

[0119] S402: When the value of the target address register is the first address value, send the (i+1)th first instruction to the processing module, so that the processing module executes the (i+1)th first task slice in the first address space.

[0120] In some embodiments, after the driver receives the execution result of the jth second task slice returned by the processing module, the driver may also switch the value of the target address register from the second address value to the third address value, and send the i-th third instruction to the processing module, so that the processing module executes the w-th third task slice in the third address space, where w is a positive integer. The processing task corresponding to the third instruction includes the w-th third task slice in the third processing task, the third processing task corresponds to the third instruction set, and the third instruction set includes the i-th third instruction.

[0121] In some embodiments, taking the example of a processing module executing a processing task of two data streams, the first data stream corresponds to a first instruction set including multiple first instructions, and the second data stream corresponds to a second instruction set including multiple second instructions. The processing module executes a first processing task related to the first data stream under a first address space, and executes a second processing task related to the second data stream under a second address space. The first processing task includes multiple first task slices, and the second processing task includes multiple second task slices. The processing module executes processing tasks related to the first data stream and the second data stream in a time-division multiplexing manner. When the value of the target address register is the first address value, the driver sends the i-th first instruction to the processing module. After receiving the i-th first instruction, the processing module executes the i-th first task slice under the first address space corresponding to the first address value, and returns the i-th first operation result to the driver. After the driver receives the i-th first operation result, the driver switches the value of the target address register from the first address value to the second address value, and then the driver sends the j-th second instruction to the processing module. After the processing module receives the j-th second instruction, the processing module executes the j-th second task slice in the second address space corresponding to the second address value, and returns the j-th second operation result to the driver. After receiving the j-th second operation result, the driver continues to switch the value of the target address register from the second address value to the first address value, and the driver sends the i+1-th first instruction to the processing module. After receiving the i+1-th first instruction, the processing module executes the i+1-th first task slice in the first address space corresponding to the first address value, and returns the i+1-th first operation result to the driver, until the processing module completes the execution of multiple first task slices and multiple second task slices, so that the processing module completes the processing tasks related to the first data stream and the second data stream.

[0122] It should be noted that the above embodiment is described using the first data stream and the second data stream as an example. In actual application scenarios, it can be expanded to multiple data streams. The principle is similar to that of the two data streams, that is, time division multiplexing is used to perform processing tasks. The embodiments of the present application do not impose any limitations on this.

[0123] It is understandable that the processing module automatically switches to the next task slice for processing the first video stream after completing the j-th second task slice. On the one hand, the resources of the processing module can be better utilized to ensure that the resources are reasonably allocated and utilized during the switching process between different tasks, avoiding idle waste of resources. On the one hand, automatic switching enables the processing module to flexibly respond to the processing requirements of different tasks, making the system more adaptable and flexible. In addition, the need for manual intervention can be reduced, saving time and energy for switching tasks, thereby improving the processing efficiency of the processing module. In general, the automatic switching method can improve the processing efficiency, resource utilization and flexibility of the system, while enhancing the degree of automation of the system.

[0124] Figure 6 A flowchart of a task execution method provided in an embodiment of the present application Figure 2 , applied to processing modules, such as Figure 6 As shown, the method includes S201 to S202:

[0125] S201. In response to a first instruction sent by a driver, a processing task corresponding to the first instruction is executed in a first address space to obtain a first operation result; the first instruction is sent by the driver after setting the value of a target address register in a memory to a first address value, and the first address space corresponds to the first address value.

[0126] In some embodiments, when the value of the target address register is a first address value, the driver sends a first instruction to the processing module. After receiving the first instruction, the processing module executes a processing task corresponding to the first instruction in the first address space, obtains a first operating result, and returns the first operating result to the driver.

[0127] It should be noted that, for the description of S201, reference may be made to the description of S101 above.

[0128] S202, in response to a second instruction sent by the driver, executing a processing task corresponding to the second instruction in a second address space to obtain a second operation result; the second instruction is sent by the driver after setting the value of the target address register to the first address value and switching it to the second address value, and the second address space corresponds to the second address value.

[0129] In some embodiments, when the driver receives the first operation result returned by the processing module, the driver switches the first address value of the target address register to the second address value. When the value of the target address register is the second address value, the driver sends a second instruction to the processing module. After receiving the second instruction, the processing module executes the processing task corresponding to the second instruction in the second address space, obtains the second operation result, and returns the second operation result to the driver.

[0130] It should be noted that, for the description of S202, reference may be made to the description of S102 above, which will not be repeated here.

[0131] In some embodiments of the present application, in S201, in response to the first instruction sent by the driver, executing the processing task corresponding to the first instruction in the first address space to obtain the first operation result may include:

[0132] In response to a first instruction sent by the driver, a first memory access request is sent to the memory, so that the memory performs a memory access operation corresponding to the first memory access request in a first address space, and returns a first access response to the processing module; the first address space is determined by the memory through address mapping according to a preset address range and a first address value in the first memory access request; the first access response includes first relevant data of the processing task corresponding to the first instruction; the preset address range represents the addressing range of the processing module;

[0133] According to the first related data, a processing task corresponding to the first instruction is executed to obtain a first operation result.

[0134] In some embodiments, after receiving the first instruction, the processing module starts to execute the processing task corresponding to the first instruction, and during the processing of the task, sends a first memory access request to the memory to read or write data related to the processing task from the memory. The first memory access request carries a preset address range.

[0135] In some embodiments, the relevant data for processing tasks are data related to execution instructions, and the relevant data for processing tasks include the current execution site, task requirement data, resource data, risk and problem data, etc. The embodiments of the present application do not impose any limitations on this.

[0136] In some embodiments of the present application, the address bit width corresponding to the preset address range is K bits, the address bit width corresponding to the first address space is K+P bits, the low K bits of the addressing address in the first address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the first address space are the first address value; the address bit width corresponding to the second address space is K+P bits, the low K bits of the addressing address in the second address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the second address space are the second address value, wherein K is a positive integer greater than 1, and P is a positive integer.

[0137] In some implementations, the first memory access request includes: a first read request and a first write request.

[0138] Exemplarily, when the first memory access request is a first read request, first, the memory performs address mapping according to a preset address range and a first address value to determine a first address space. Then, the memory reads the first relevant data of the processing task corresponding to the first instruction in the first address space, for example, the first relevant data includes the current first execution site, task requirement data related to the first instruction, resource data, etc. Finally, the memory sends the acquired first relevant data to the processing module, and the processing module can execute the processing task corresponding to the first instruction based on the first relevant data (such as the current first execution site) to obtain a first operation result.

[0139] Exemplarily, in the case where the first memory access request is a first write request, the first write request also carries the first data to be stored, for example, the first data to be stored includes the current first execution scene after the first instruction is executed, first, the memory performs address mapping according to the preset address range and the first address value to determine the first address space. Then, the memory stores the current first execution scene in the first address space for easy acquisition by the subsequent processing module.

[0140] In some embodiments of the present application, in S202, in response to the second instruction sent by the driver, executing the processing task corresponding to the second instruction in the second address space to obtain the second operation result may include:

[0141] In response to the second instruction sent by the driver, a second memory access request is sent to the memory, so that the memory performs a memory access operation corresponding to the second memory access request in the second address space, and returns a second access response to the processing module; the second address space is determined by the memory through address mapping according to a preset address range and a second address value in the second memory access request; the second access response includes second related data of the processing task corresponding to the second instruction;

[0142] According to the second related data, a processing task corresponding to the second instruction is executed to obtain a second operation result.

[0143] In some embodiments, after receiving the second instruction, the processing module starts to execute the processing task corresponding to the second instruction, and during the processing of the task, sends a second memory access request to the memory to read or write the relevant data of the processing task from the memory. The second memory access request carries a preset address range.

[0144] In some implementations, the second memory access request includes: a second read request and a second write request.

[0145] Exemplarily, when the second memory access request is a second read request, first, the memory performs address mapping according to the preset address range and the second address value to determine the second address space. Then, the memory reads the second relevant data of the processing task corresponding to the second instruction in the second address space, for example, the second relevant data includes the current second execution site, task requirement data related to the second instruction, resource data, etc. Finally, the memory sends the acquired second relevant data to the processing module, and the processing module can execute the processing task corresponding to the second instruction based on the second relevant data (such as the current second execution site) to obtain the second operation result.

[0146] Exemplarily, when the second memory access request is a second write request, the second write request also carries the second data to be stored, such as the second data to be stored includes the current first execution scene after the second instruction is executed. First, the memory performs address mapping according to the preset address range and the second address value to determine the second address space. Then, the memory stores the current second execution scene in the second address space for easy acquisition by the subsequent processing module.

[0147] In some embodiments of the present application, in response to the first instruction sent by the driver, executing the processing task corresponding to the first instruction in the first address space to obtain the first operation result in S201 may include S2011 and S2012:

[0148] S2011, in response to the first instruction, after switching from the waiting state to the awakening state, executing a processing task corresponding to the first instruction in a first address space corresponding to the first address value, obtaining and returning a first execution result to the driver;

[0149] S2012: After returning the first execution result, switch from the awake state to the waiting state.

[0150] In some embodiments, after the processing module receives the first instruction, the processing module switches from the waiting state to the awake state. After the processing module returns the first execution result to the driver, the processing module switches from the awake state to the waiting state to achieve the effect of reducing power consumption.

[0151] In some embodiments of the present application, in response to a first instruction, after switching from a waiting state to a wake-up state, a preset interrupt program is called to obtain the current first execution scene from the first address space based on a preset address; based on the current first execution scene, a processing task corresponding to the first instruction is executed in the first address space corresponding to the first address value, and a first execution result is obtained and returned to the driver.

[0152] In some implementations, the preset address is a pre-set address value. For example, the preset address is 0000_0100. For the first address space, the address value for storing the current first execution site is 0x0_0000_0100.

[0153] In some embodiments of the present application, the implementation of switching from the awake state to the waiting state after returning the first execution result in S2012 may include S20121 and S20122:

[0154] S20121. After returning the first execution result, based on a preset address, save the current first execution scene to the first address space;

[0155] S20122. After saving the current first execution scene to the first address space, switch from the wake-up state to the waiting state.

[0156] In some implementations, after the processing module returns the first execution result to the driver, the processing module saves the current first execution scene after executing the first instruction to a preset address in the first address space to update the scene status.

[0157] In some implementations, after saving the current first execution scene to the first address space, the processing module refreshes the cache to ensure memory consistency.

[0158] In some embodiments of the present application, in response to the second instruction sent by the driver, executing the processing task corresponding to the second instruction in the second address space to obtain the second operation result in S202 may include S2021 and S2022:

[0159] S2021, in response to the second instruction, after switching from the waiting state to the awakening state, executing a processing task corresponding to the second instruction in a second address space corresponding to the second address value, and obtaining and returning a second execution result to the driver;

[0160] S2022: After returning the second execution result, switch from the awake state to the waiting state.

[0161] In some embodiments, after the processing module receives the second instruction, the processing module switches from the waiting state to the awake state. After the processing module returns the second execution result to the driver, the processing module switches from the awake state to the waiting state to achieve the effect of reducing power consumption.

[0162] In some embodiments of the present application, in response to a second instruction, after switching from a waiting state to a wake-up state, a preset interrupt program is called to obtain the current second execution scene from a second address space based on a preset address; based on the current second execution scene, a processing task corresponding to the first instruction is executed in a second address space corresponding to the second address value, and a second execution result is obtained and returned to the driver.

[0163] In some implementations, the preset address is a pre-set address value. For example, the preset address is 0000_0100. For the second address space, the address value for storing the current second execution site is 0x1_0000_0100.

[0164] In some embodiments of the present application, the implementation of switching from the awake state to the waiting state after returning the second execution result in S2022 may include S20221 and S20222:

[0165] S20221. After returning the second execution result, based on a preset address, save the current second execution scene to the second address space;

[0166] S20222: After saving the current second execution scene into the second address space, switch from the awake state to the waiting state.

[0167] In some implementations, after the processing module returns the second execution result to the driver, the processing module saves the current second execution scene after executing the second instruction to a preset address in the second address space to update the scene status.

[0168] In some implementations, after saving the current second execution scene to the second address space, the processing module refreshes the cache to ensure memory consistency.

[0169] In some embodiments of the present application, the processing module includes a preset memory, and the preset memory is used to store a preset interrupt program for use during context switching.

[0170] In some embodiments of the present application, the processing task corresponding to the first instruction includes the i-th first task slice in the first processing task, the first processing task corresponds to the first instruction set, the first instruction is the i-th first instruction in the first instruction set, the processing task corresponding to the second instruction includes the j-th second task slice in the second processing task, the second processing task corresponds to the second instruction set, and the second instruction is the j-th first instruction in the second instruction set, wherein i and j are both positive integers; the method includes S301 to S302:

[0171] S301, in response to the i-th first instruction, executing the i-th first task slice in the first address space to obtain the running result of the i-th first task slice;

[0172] S302. In response to the jth second instruction, execute the jth second task slice in the second address space to obtain the running result of the jth second task slice.

[0173] In some embodiments of the present application, the method further includes S303:

[0174] S303. In response to the i+1th first instruction sent by the driver, execute the i+1th first task slice in the second address space to obtain the running result of the i+1th first task slice; wherein the i+1th first instruction is sent by the driver after receiving the execution result of the jth second task slice sent by the processing module, and switching the value of the target address register from the second address value to the first address value.

[0175] In some embodiments of the present application, the first processing task is a video processing task of a first video stream, and the i-th first task slice is an image processing task of an i-th frame image in the first video stream; the second processing task is a video processing task of a second video stream, and the j-th second task slice is an image processing task of a j-th frame image in the second video stream; the image processing task includes: an encoding processing task and / or a decoding processing task;

[0176] In S301, in response to the i-th first instruction, the i-th first task slice is executed in the first address space to obtain the implementation of the operation result of the i-th first task slice, including:

[0177] In response to the i-th first instruction, an image processing task of the i-th frame image in the first video stream is executed in the first address space to obtain a running result of the image processing task of the i-th frame image;

[0178] In response to the j-th second instruction in S302, the j-th second task slice is executed in the second address space to obtain the implementation of the running result of the j-th second task slice, including:

[0179] In response to the j-th second instruction, an image processing task for the j-th frame image in the second video stream is executed in the second address space to obtain a running result of the image processing task for the j-th frame image.

[0180] It should be noted that, for the description of S301 and S302, reference may be made to the description of S1011, S1021 and S1031 in the previous text.

[0181] The task execution method provided by the present application is described below in an exemplary embodiment.

[0182] The embodiment of the present application provides a task execution method, specifically a method for 32-bit VPU virtualization access to arbitrary address space. The embodiment of the present application breaks through the limitation that a 32-bit VPU core can only run in a 4G space, so that 2 or more 8K video streams can run in parallel on a VPU Core at the same time, making the best use of hardware resources.

[0183] In the embodiment of the present application, each 4G segment (equivalent to the address space) has its own independent operating environment program of the VPU, also called the code area code (equivalent to a process), and each code area can only see its own things (each code area does not know the existence of other address spaces, and thinks that it is the exclusive VPU Core). The driver switches high_reg (equivalent to the value of the target address register) at the appropriate time to cut the computing power of the VPU Core to the target code area for operation. The original code area will suspend operation and wait for the next time the driver switches high_reg back.

[0184] Figure 7 An interactive schematic diagram of a task execution method provided in an embodiment of the present application, such as Figure 7As shown, the processing module is VPU as an example for explanation. The 0-4G address space (seg0) is the first address space, and the 4-8G address space (seg1) is the second address space. In the starting state, the value of the target address register high_reg = 0 (the first address value is 0). At this time, the driver sends the seg0-related instruction 1 (cmd1) to the VPU. After the VPU receives the seg0-related cmd1, the VPU exits the waiting state, and the VPU executes the corresponding processing task of cmd1 under seg0 to obtain the corresponding running result of cmd1. The VPU returns the corresponding running result of cmd1 to the driver, and the VPU enters the waiting state. Furthermore, after the driver receives the running result corresponding to cmd1, the driver believes that the execution of the seg0-related cmd1 is completed, the driver switches high_reg from 0 to 1, and the driver sends the seg1-related instruction 1 (cmd1) to the VPU. After the VPU receives the cmd1 related to seg1, the VPU exits the waiting state, executes the corresponding processing task of cmd1 under seg1, obtains the corresponding running result of cmd1, returns the corresponding running result of cmd1 to the driver, and enters the waiting state. Further, after the driver receives the running result corresponding to cmd1, the driver considers that the execution of cmd1 related to seg1 is completed, the driver switches high_reg from 1 to 0, and the driver sends instruction 2 (cmd2) related to seg0 to the VPU. After the VPU receives the cmd2 related to seg0, the VPU exits the waiting state, executes the corresponding processing task of cmd2 under seg0, obtains the corresponding running result of cmd2, returns the corresponding running result of cmd2 to the driver, and enters the waiting state. The driver and the VPU are cyclically scheduled according to the above process to complete the processing tasks.

[0185] In the embodiment of the present application, high_reg=0 at the beginning, the driver sends a command (seg0 cmd1), the VPU receives the command, and the VPU wakes up from halt. Because high_reg=0, all address bus and data bus memory access behaviors issued during the operation of the VPU are automatically sent to the address space of seg0[0G, 4G]. The VPU executes commands in this space, exits after execution, and enters halt again. After the driver receives the result of seg0cmd1, it has its own scheduling algorithm and thinks that it is seg1's turn to run. The driver switches high_reg to 1. The driver then organizes the commands to be executed by seg1 and sends them to the VPU (the command sending interface is not affected by different address segments through the APB bus). The VPU receives the command and wakes up from halt. Because high_reg=1, the VPU is running at this time, and all address bus and data bus memory access behaviors issued are automatically sent to the address space of seg1[4G, 8G]. The VPU executes commands in this space, exits after execution, and enters halt again.

[0186] Figure 8 A schematic diagram of the structure of a task execution system provided in an embodiment of the present application Figure 2 ,like Figure 8 As shown, the task execution system includes: a driver 2001, a VPU 2002 and a memory 2004. The VPU 2002 has a preset memory 2003, and the driver 2001 runs on a main processor (such as a CPU). The preset memory 2003 (such as a RAM) is used to store a preset interrupt program for context switching. The driver 2001 communicates with the VPU 2002 through an Advanced Peripheral Bus (APB). The driver 2001 communicates with the memory 2004 through a Peripheral Component Interconnect (PCI) bus. The VPU 2002 communicates with the memory 2004 through an Advanced eXtensible Interface (AXI) bus.

[0187] In the embodiment of the present application, the lower 32-bit addresses of the code areas of each 4G segment are the same. For example: the seg0 segment is in the 1M space from 0x0000_0000 to 0x0010_0000. The Seg1 segment is in the 1M space from 0x1_0000_0000 to 0x1_0010_0000. In this way, the lower 32 bits of the addresses of the global variables of the program are the same. This is convenient for saving or restoring the environment when halting to enter or exit. The driver sends commands to the VPU through the APB bus. This bus is sent directly to the VPU, no matter which 4G segment the VPU is running in. The VPU executes the code areas of different 4G segments and operates the buf required for encoding and decoding through the AXI bus.

[0188] In the embodiment of the present application, the process of the VPU from entering the waiting state to exiting the waiting state includes the following steps:

[0189] Step 1: After the VPU completes the currently executed task, save the scene r0-r15 (general registers), pc (program register, pointing to the address of the currently executed instruction), lr (link register, used to save the return address of the function call), sp (stack pointer, pointing to the address of the current stack top) and special registers (see the specific arch architecture). Save the scene to the code area of ​​the current 4G segment (for example, the location is 0x0000_0100, but high_reg=0, the corresponding real storage address in the memory is 0x0_0000_0100), where the memory can be a double data rate (Double Data Rate, DDR) memory;

[0190] Step 2: The VPU refreshes the cache to ensure memory consistency; the cache is used to store data frequently accessed by the computer processor to speed up data access. This ensures that the cache inside the VPU is consistent with the data in the DDR, avoiding data inconsistency after wakeup. The VPU performs a cache refresh operation, writes the data in the cache back to the DDR, and clears unnecessary data in the cache, so that when the VPU wakes up, it can read the latest and consistent data from the DDR.

[0191] Step 3: VPU enters halt mode and waits for the driver to send a command to wake it up;

[0192] Step 4: The driver switches the value high_reg in the high address register from 0 to 1;

[0193] Here, the high address register may correspond to the target address register in the aforementioned embodiment.

[0194] Step 5: The driver sends a command to the VPU via the APB bus, and the VPU wakes up to respond to the interrupt. The interrupt code (equivalent to the preset interrupt program in the aforementioned embodiment) and the stack are placed in a preset memory, and the stacking operation cannot be performed when the interrupt is responded to; wherein, the preset memory may be a 4K memory area in the VPU;

[0195] Step 6. During the process of VPU executing the preset interrupt program, VPU sends a read request to the memory. After receiving the read request, the memory obtains relevant data (for example, the execution site) at the preset address (for example, 0x0000_0100) in the address space corresponding to high_reg=1. Then, the memory sends the relevant data to VPU so that VPU performs the corresponding processing task based on the relevant data in the address space corresponding to high_reg=1. Among them, since high_reg=1, the memory obtains the relevant data at the address 0x1_0000_0100, and the relevant data includes the execution site saved when seg1 entered halt last time;

[0196] Step 7: After the VPU completes the execution of the preset interrupt program, that is, the VPU interrupt response exits, the VPU obtains the relevant data (including the execution scene) sent by the memory;

[0197] Step 8: According to the relevant data, the VPU obtains various parameters required for the current command execution from cmd and starts to execute the processing task, that is, the VPU continues to run the processing task at the position where seg1 last entered halt. In this process, the VPU executes the corresponding processing task in the address space corresponding to high_reg=1 (4G-8G segment).

[0198] Step 9: After the VPU completes the processing task, steps 1 to 8 are executed in a loop, wherein for step 3, the driver switches the value high_reg in the high address register from 1 to 0, so that the VPU can execute different processing tasks in different address spaces.

[0199] The embodiment of the present application breaks through the limitation that a 32-bit VPU can only run in a 4G space, so that 2-way 8K or even more-way 8K can run in parallel on a VPU core, making the best use of hardware resources. It should be noted that the embodiment of the present application is not limited to the VPU core, and any similar 32-bit processor core or other 32-bit processor core that wants to access a larger address space can adopt this solution.

[0200] In the embodiment of the present application, the VPU can support cross-4G operation without changing the digital circuit unit, the address allocation space is larger, and the flexibility is increased. In addition, it has strong practicality and feasibility in actual software and hardware engineering.

[0201] The preferred embodiments of the present application are described in detail above in conjunction with the accompanying drawings. However, the present application is not limited to the specific details in the above embodiments. Within the technical concept of the present application, the technical solution of the present application can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the present application. For example, the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present application will not further explain various possible combinations. For another example, the various different embodiments of the present application can also be arbitrarily combined, as long as they do not violate the idea of ​​the present application, they should also be regarded as the contents disclosed in the present application. For another example, under the premise of no conflict, the various embodiments and / or the technical features in the various embodiments described in the present application can be arbitrarily combined with the prior art, and the technical solution obtained after the combination should also fall within the protection scope of the present application.

[0202] It should be understood that in the various method embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0203] Based on the same inventive concept as the above embodiments, Fig. 9 A schematic diagram of the structure of a task execution device provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the task execution device 10 includes: a sending module 11 and a switching module 12; wherein,

[0204] The sending module 11 is used for sending a first instruction to the processing module when the value of the target address register in the memory is a first address value, so that the processing module performs a processing task corresponding to the first instruction in a first address space corresponding to the first address value;

[0205] The switching module 12 is used to switch the value of the target address register from the first address value to the second address value;

[0206] The sending module 11 is further configured to send a second instruction to the processing module when the value of the target address register is the second address value, so that the processing module executes a processing task corresponding to the second instruction in a second address space corresponding to the second address value.

[0207] In some embodiments, the first address space is determined by address mapping between the first address value and a preset address range, and the second address space is determined by address mapping between the second address value and the preset address range; the preset address range represents the addressing range of the processing module.

[0208] In some embodiments, the address bit width corresponding to the preset address range is K bits, the address bit width corresponding to the first address space is K+P bits, the low K bits of the addressing address in the first address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the first address space are the first address value; the address bit width corresponding to the second address space is K+P bits, the low K bits of the addressing address in the second address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the second address space are the second address value, wherein K is a positive integer greater than 1, and P is a positive integer.

[0209] In some embodiments, the processing task corresponding to the first instruction includes the i-th first task slice in the first processing task, the first processing task corresponds to a first instruction set, the first instruction is the i-th first instruction in the first instruction set, the processing task corresponding to the second instruction includes the j-th second task slice in the second processing task, the second processing task corresponds to a second instruction set, and the second instruction is the j-th first instruction in the second instruction set, wherein i and j are both positive integers; the sending module 11 is also used to send the i-th first instruction to the processing module when the value of the target address register is the first address value, so that the processing module executes the i-th first task slice in the first address space; the switching module 12 is also used to switch the value of the target address register from the first address value to the second address value in response to receiving the execution result of the i-th first task slice sent by the processing module; the sending module 11 is also used to send the j-th second instruction to the processing module when the value of the target address register is the second address value, so that the processing module executes the j-th second task slice in the second address space.

[0210] In some embodiments, the switching module 12 is also used to switch the value of the target address register from the second address value to the first address value in response to receiving the execution result of the j-th second task slice sent by the processing module; when the value of the target address register is the first address value, send the i+1th first instruction to the processing module, so that the processing module executes the i+1th first task slice under the first address space.

[0211] In some embodiments, the first processing task is a video processing task for a first video stream, and the i-th first task slice is an image processing task for an i-th image frame in the first video stream; the second processing task is a video processing task for a second video stream, and the j-th second task slice is an image processing task for an j-th image frame in the second video stream; the sending module 11 is also used to, when the value of the target address register is a first address value, send the i-th first instruction to the processing module so that the processing module executes the image processing task for the i-th image frame in the first video stream under the first address space; and when the value of the target address register is a second address value, send the j-th second instruction to the processing module so that the processing module executes the image processing task for the j-th image frame in the second video stream under the second address space.

[0212] Those skilled in the art should understand that the relevant description of the above-mentioned task execution device in the embodiment of the present application can be understood by referring to the relevant description of the task execution method in the embodiment of the present application.

[0213] Based on the same inventive concept as the above embodiments, Fig.10 A schematic diagram of the composition structure of a processing module provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, the processing module 20 includes: a receiving unit 21 and an execution unit 22; wherein,

[0214] The receiving unit 21 is configured to receive a first instruction, which is sent by the driver after the value of the target address register in the memory is set to a first address value, and the first address space corresponds to the first address value; and receive a second instruction, which is sent by the driver after the value of the target address register is set to the first address value and switched to a second address value, and the second address space corresponds to the second address value;

[0215] The execution unit 22 is used to respond to a first instruction sent by the driver, execute a processing task corresponding to the first instruction in a first address space, and obtain a first operation result; respond to a second instruction sent by the driver, execute a processing task corresponding to the second instruction in a second address space, and obtain a second operation result.

[0216] In some embodiments, the execution unit 22 is further used to send a first memory access request to the memory in response to a first instruction sent by the driver, so that the memory performs a memory access operation corresponding to the first memory access request in a first address space, and returns a first access response to the processing module; the first address space is determined by the memory according to the preset address range in the first memory access request and the first address value through address mapping; the first access response includes first relevant data of the processing task corresponding to the first instruction; the preset address range represents the addressing range of the processing module; according to the first relevant data, the processing task corresponding to the first instruction is executed to obtain the first operation result; in response to a second instruction sent by the driver, send a second memory access request to the memory, so that the memory performs a memory access operation corresponding to the second memory access request in a second address space, and returns a second access response to the processing module; the second address space is determined by the memory according to the preset address range in the second memory access request and the second address value through address mapping; the second access response includes second relevant data of the processing task corresponding to the second instruction; according to the second relevant data, the processing task corresponding to the second instruction is executed to obtain the second operation result.

[0217] In some embodiments, the address bit width corresponding to the preset address range is K bits, the address bit width corresponding to the first address space is K+P bits, the low K bits of the addressing address in the first address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the first address space are the first address value; the address bit width corresponding to the second address space is K+P bits, the low K bits of the addressing address in the second address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the second address space are the second address value, wherein K is a positive integer greater than 1, and P is a positive integer.

[0218] In some embodiments, the execution unit 22 is also used to respond to the first instruction, after switching from the waiting state to the awake state, execute the processing task corresponding to the first instruction in the first address space corresponding to the first address value, obtain and return the first execution result to the driver; after returning the first execution result, switch from the awake state to the waiting state; respond to the second instruction, after switching from the waiting state to the awake state, execute the processing task corresponding to the second instruction in the second address space corresponding to the second address value, obtain and return the second execution result to the driver; after returning the second execution result, switch from the awake state to the waiting state.

[0219] In some embodiments, the execution unit 22 is also used to respond to the first instruction, after switching from the waiting state to the awake state, by calling the preset interrupt program, based on the preset address, obtain the current first execution scene from the first address space; based on the current first execution scene, execute the processing task corresponding to the first instruction in the first address space corresponding to the first address value, and obtain and return the first execution result to the driver; respond to the second instruction, after switching from the waiting state to the awake state, by calling the preset interrupt program, based on the preset address, obtain the current second execution scene from the second address space; based on the current second execution scene, execute the processing task corresponding to the second instruction in the second address space corresponding to the second address value, and obtain and return the second execution result to the driver.

[0220] In some embodiments, the execution unit 22 is also used to save the current first execution scene in the first address space based on the preset address after returning the first execution result; after saving the current first execution scene in the first address space, switch from the wake-up state to the waiting state; after returning the second execution result, save the current second execution scene in the second address space based on the preset address; after saving the current second execution scene in the second address space, switch from the wake-up state to the waiting state.

[0221] In some embodiments, the processing module includes a preset memory, and the preset memory is used to store the preset interrupt program.

[0222] In some embodiments, the processing task corresponding to the first instruction includes the i-th first task slice in the first processing task, the first processing task corresponds to a first instruction set, the first instruction is the i-th first instruction in the first instruction set, and the processing task corresponding to the second instruction includes the j-th second task slice in the second processing task, the second processing task corresponds to a second instruction set, and the second instruction is the j-th first instruction in the second instruction set, wherein i and j are both positive integers; the execution unit 22 is also used to respond to the i-th first instruction, execute the i-th first task slice in the first address space, and obtain the running result of the i-th first task slice; respond to the j-th second instruction, execute the j-th second task slice in the second address space, and obtain the running result of the j-th second task slice.

[0223] In some embodiments, the execution unit 22 is also used to execute the i+1th first task slice in the second address space in response to the i+1th first instruction sent by the driver, and obtain the running result of the i+1th first task slice; wherein the i+1th first instruction is sent by the driver after switching the value of the target address register from the second address value to the first address value after receiving the execution result of the jth second task slice sent by the processing module.

[0224] In some embodiments, the first processing task is a video processing task for a first video stream, and the i-th first task slice is an image processing task for an i-th image frame in the first video stream; the second processing task is a video processing task for a second video stream, and the j-th second task slice is an image processing task for an j-th image frame in the second video stream; the execution unit 22 is further used to respond to the i-th first instruction, execute the image processing task for the i-th image frame in the first video stream under the first address space, and obtain the running result of the image processing task for the i-th image frame; respond to the j-th second instruction, execute the image processing task for the j-th image frame in the second video stream under the second address space, and obtain the running result of the image processing task for the j-th image frame.

[0225] Those skilled in the art should understand that the relevant description of the above-mentioned processing task module in the embodiment of the present application can be understood by referring to the relevant description of the task execution method in the embodiment of the present application.

[0226] Fig.11 This is a schematic diagram of the composition structure of a task execution system provided in an embodiment of the present application. Figure 3 .like Fig.11 As shown, the task execution system 30 includes: a main processor 31, a processing module 32 and a memory 33, and a driver 311 is run on the main processor 31; wherein,

[0227] The driver 311 is used to send a first instruction to the processing module when the value of the target address register in the memory is a first address value; switch the value of the target address register from the first address value to a second address value; and send a second instruction to the processing module when the value of the target address register is the second address value; the first address space corresponds to the first address value, and the second address space corresponds to the second address value;

[0228] The processing module 32 is used to respond to a first instruction sent by the driver, execute a processing task corresponding to the first instruction in a first address space, and obtain a first operation result; respond to a second instruction sent by the driver, execute a processing task corresponding to the second instruction in a second address space, and obtain a second operation result;

[0229] The memory 33 is used to store first relevant data of the processing task corresponding to the first instruction in the first address space, and to store second relevant data of the processing task corresponding to the second instruction in the second address space.

[0230] It should be noted that the processing module 32 is the same as the processing module 20 .

[0231] Fig.12 is a schematic structural diagram of an electronic device 40 provided in an embodiment of the present application. Fig.12 As shown, the electronic device 40 includes a processor 41 and a memory 42. The memory 42 can store a computer program, and the processor 41 can call and run the computer program from the memory 42 to implement the method in the embodiment of the present application.

[0232] The memory 42 may be a separate device independent of the processor 41 , or may be integrated into the processor 41 .

[0233] In some embodiments of the present application, Fig.12 As shown, the electronic device 40 may further include a transceiver 43, and the processor 41 may control the transceiver 43 to communicate with other devices, specifically, to send information or data to other devices, or to receive information or data sent by other devices.

[0234] The transceiver 43 may include a transmitter and a receiver. The transceiver 43 may further include an antenna, and the number of the antennas may be one or more.

[0235] It can be understood that the processor of the embodiment of the present application may be an integrated circuit chip with information processing capabilities. In the implementation process, each step of the above method embodiment can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (DigitalSignal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, and other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0236] It can also be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (DR RAM). It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0237] An embodiment of the present application also provides a computer-readable storage medium for storing a computer program.

[0238] In some embodiments of the present application, the computer-readable storage medium can be applied to the task execution device in the embodiments of the present application, and when the computer program is executed by at least one processor, it implements the corresponding processes implemented by the task execution device in the various methods of the embodiments of the present application. For the sake of brevity, they will not be repeated here.

[0239] In some embodiments of the present application, the computer-readable storage medium can be applied to the processing module in the embodiments of the present application, and when the computer program is executed by at least one processor, it implements the corresponding processes implemented by the processing module in the various methods of the embodiments of the present application. For the sake of brevity, they are not repeated here.

[0240] An embodiment of the present application also provides a computer program product, including computer program instructions.

[0241] In some embodiments of the present application, the computer program product can be applied to the task execution device in the embodiments of the present application, and the computer program instructions enable the computer to execute the corresponding processes implemented by the task execution device in the various methods of the embodiments of the present application. For the sake of brevity, they will not be repeated here.

[0242] In some embodiments of the present application, the computer program product can be applied to the processing module in the embodiments of the present application, and the computer program instructions enable the computer to execute the corresponding processes implemented by the processing module in the various methods of the embodiments of the present application. For the sake of brevity, they will not be repeated here.

[0243] The embodiment of the present application also provides a computer program.

[0244] In some embodiments of the present application, the computer program can be applied to the task execution device in the embodiments of the present application. When the computer program runs on a computer, the computer executes the corresponding processes implemented by the task execution device in the various methods of the embodiments of the present application. For the sake of brevity, they will not be repeated here.

[0245] In some embodiments of the present application, the computer program can be applied to the processing module in the embodiments of the present application. When the computer program runs on a computer, the computer executes the corresponding processes implemented by the processing module in the various methods of the embodiments of the present application. For the sake of brevity, they will not be repeated here.

[0246] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0247] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0248] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0249] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0250] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0251] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0252] It should be noted that, in this application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0253] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0254] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0255] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0256] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0257] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A task execution method, characterized in that: The method comprises: When the value of the target address register in the memory is a first address value, sending a first instruction to the processing module so that the processing module executes a processing task corresponding to the first instruction in a first address space corresponding to the first address value; Switching the value of the target address register from the first address value to a second address value; When the value of the target address register is the second address value, a second instruction is sent to the processing module, so that the processing module executes a processing task corresponding to the second instruction in a second address space corresponding to the second address value.

2. The method according to claim 1, characterized in that The first address space is determined by address mapping between the first address value and a preset address range, and the second address space is determined by address mapping between the second address value and the preset address range; the preset address range represents an addressing range of the processing module.

3. The method according to claim 2, characterized in that The address bit width corresponding to the preset address range is K bits, the address bit width corresponding to the first address space is K+P bits, the low K bits of the addressing address in the first address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the first address space are the first address value; The address bit width corresponding to the second address space is K+P bits, the low K bits of the addressing address in the second address space are the corresponding addressing address in the preset address range, and the high P bits of the addressing address in the second address space are the second address value, where K is a positive integer greater than 1, and P is a positive integer.

4. The method according to any one of claims 1 to 3, characterized in that: The processing task corresponding to the first instruction includes the i-th first task slice in the first processing task, the first processing task corresponds to a first instruction set, and the first instruction is the i-th first instruction in the first instruction set; the processing task corresponding to the second instruction includes the j-th second task slice in the second processing task, the second processing task corresponds to a second instruction set, and the second instruction is the j-th first instruction in the second instruction set, wherein i and j are both positive integers; The switching the value of the target address register from the first address value to the second address value comprises: In response to receiving the execution result of the i-th first task slice sent by the processing module, the value of the target address register is switched from the first address value to the second address value.

5. The method according to claim 4, characterized in that The method further comprises: In response to receiving the execution result of the j-th second task slice sent by the processing module, switching the value of the target address register from the second address value to the first address value; When the value of the target address register is the first address value, the (i+1)th first instruction is sent to the processing module, so that the processing module executes the (i+1)th first task slice in the first address space.

6. The method according to claim 4, characterized in that The first processing task is a video processing task for a first video stream, and the i-th first task slice is an image processing task for an i-th frame image in the first video stream; the second processing task is a video processing task for a second video stream, and the j-th second task slice is an image processing task for a j-th frame image in the second video stream; The image processing task includes: an encoding processing task and / or a decoding processing task.

7. A task execution method, characterized in that: Applied to a processing module, the method comprises: In response to a first instruction sent by the driver, a processing task corresponding to the first instruction is executed in a first address space to obtain a first operation result; the first instruction is sent by the driver after setting the value of a target address register in a memory to a first address value, and the first address space corresponds to the first address value; In response to a second instruction sent by the driver, a processing task corresponding to the second instruction is executed in a second address space to obtain a second operation result; the second instruction is sent by the driver after setting the value of the target address register to the first address value and switching to the second address value, and the second address space corresponds to the second address value.

8. The method according to claim 7, characterized in that In response to the first instruction sent by the driver, executing a processing task corresponding to the first instruction in the first address space to obtain a first operation result includes: In response to a first instruction sent by the driver, a first memory access request is sent to the memory, so that the memory performs a memory access operation corresponding to the first memory access request in a first address space, and returns a first access response to the processing module; the first address space is determined by the memory through address mapping according to a preset address range in the first memory access request and the first address value; the first access response includes first relevant data of the processing task corresponding to the first instruction; the preset address range represents the addressing range of the processing module; executing, according to the first relevant data, a processing task corresponding to the first instruction to obtain the first operating result; In response to the second instruction sent by the driver, executing the processing task corresponding to the second instruction in the second address space to obtain a second operation result includes: In response to a second instruction sent by the driver, a second memory access request is sent to the memory, so that the memory performs a memory access operation corresponding to the second memory access request in a second address space, and returns a second access response to the processing module; the second address space is determined by the memory through address mapping according to a preset address range in the second memory access request and the second address value; the second access response includes second relevant data of the processing task corresponding to the second instruction; According to the second related data, a processing task corresponding to the second instruction is executed to obtain the second operation result.

9. The method according to claim 7 or 8, characterized in that: In response to the first instruction sent by the driver, executing a processing task corresponding to the first instruction in the first address space to obtain a first operation result includes: In response to the first instruction, after switching from the waiting state to the awakening state, executing a processing task corresponding to the first instruction in a first address space corresponding to the first address value, obtaining and returning a first execution result to the driver; After returning the first execution result, switching from the awake state to the waiting state; In response to the second instruction sent by the driver, executing the processing task corresponding to the second instruction in the second address space to obtain a second operation result includes: In response to the second instruction, after switching from the waiting state to the awakening state, executing a processing task corresponding to the second instruction in a second address space corresponding to the second address value, obtaining and returning a second execution result to the driver; After returning the second execution result, the awakening state is switched to the waiting state.

10. The method according to claim 9, characterized in that The step of switching from the waiting state to the awakening state in response to the first instruction, executing a processing task corresponding to the first instruction in the first address space corresponding to the first address value, obtaining and returning the first execution result to the driver, comprises: In response to the first instruction, after switching from the waiting state to the awakening state, a preset interrupt program is called to obtain the current first execution scene from the first address space based on a preset address; Based on the current first execution scene, executing a processing task corresponding to the first instruction in a first address space corresponding to the first address value, obtaining and returning the first execution result to the driver; The step of switching from the waiting state to the awakening state in response to the second instruction, executing the processing task corresponding to the second instruction in the second address space corresponding to the second address value, obtaining and returning the second execution result to the driver, comprises: In response to the second instruction, after switching from the waiting state to the awakening state, the current second execution scene is acquired from the second address space based on a preset address by calling the preset interrupt program; Based on the current second execution scene, a processing task corresponding to the second instruction is executed in a second address space corresponding to the second address value, and the second execution result is obtained and returned to the driver.

11. The method according to claim 9, characterized in that After returning the first execution result, switching from the awake state to the waiting state includes: After returning the first execution result, based on a preset address, saving the current first execution scene to the first address space; After saving the current first execution scene into the first address space, switching from the awake state to the waiting state; After returning the second execution result, switching from the awake state to the waiting state includes: After returning the second execution result, based on the preset address, saving the current second execution scene to the second address space; After the current second execution scene is saved in the second address space, the awake state is switched to the waiting state.

12. The method according to claim 10 or 11, characterized in that: The processing module includes a preset memory, and the preset memory is used to store the preset interrupt program.

13. A task execution device, characterized in that: The device comprises: a sending module, configured to send a first instruction to a processing module when the value of a target address register in a memory is a first address value, so that the processing module executes a processing task corresponding to the first instruction in a first address space corresponding to the first address value; A switching module, configured to switch the value of the target address register from the first address value to a second address value; The sending module is further configured to send a second instruction to the processing module when the value of the target address register is the second address value, so that the processing module executes a processing task corresponding to the second instruction in a second address space corresponding to the second address value.

14. A processing module, characterized in that: The processing module comprises: a receiving unit, configured to receive a first instruction, wherein the first instruction is sent by the driver after the value of the target address register in the memory is set to a first address value, and the first address space corresponds to the first address value; and receive a second instruction, wherein the second instruction is sent by the driver after the value of the target address register is set to the first address value and switched to a second address value, and the second address space corresponds to the second address value; An execution unit is used to respond to a first instruction sent by the driver, execute a processing task corresponding to the first instruction in a first address space, and obtain a first operation result; respond to a second instruction sent by the driver, execute a processing task corresponding to the second instruction in a second address space, and obtain a second operation result.

15. A task execution system, characterized in that: The system comprises: a main processor, a processing module and a memory, and a driver is run on the main processor; wherein, The driver is used to send a first instruction to the processing module when the value of the target address register in the memory is a first address value; switch the value of the target address register from the first address value to a second address value; and send a second instruction to the processing module when the value of the target address register is the second address value; the first address space corresponds to the first address value, and the second address space corresponds to the second address value; The processing module is used to respond to a first instruction sent by the driver, execute a processing task corresponding to the first instruction in a first address space to obtain a first operation result; respond to a second instruction sent by the driver, execute a processing task corresponding to the second instruction in a second address space to obtain a second operation result; The memory is used to store first relevant data of the processing task corresponding to the first instruction in the first address space, and to store second relevant data of the processing task corresponding to the second instruction in the second address space.

16. An electronic device, characterized in that: include: A processor and a memory, the memory being used to store a computer program, the processor being used to call and run the computer program stored in the memory to execute the method as claimed in any one of claims 1 to 6; or, to execute the method as claimed in any one of claims 7 to 12.

17. A computer-readable storage medium, characterized in that: The computer storage medium stores a computer program, and when the computer program is executed by at least one processor, the method according to any one of claims 1 to 6 is implemented; or the method according to any one of claims 7 to 12 is implemented.

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