Method for allocating memory resources

Abstract

The invention discloses a method for allocating memory resources. The method is used for solving the problem that a central processing unit and a direct memory access controller compete for the memory resources. According to the scheme, the method comprises the steps that the mapping relation between the memory physical address and the memory internal address of the target electronic equipment is obtained, the memory physical address is the address used by an access main body for executing access to the memory, and the access main body is a direct memory access controller or a central processing unit of the target electronic equipment; determining at least one target binary bit from the memory physical address based on the mapping relationship, wherein the at least one target binary bit points to the memory internal address; determining an available memory unit binary bit from the at least one target binary bit, the bit of the available memory unit binary bit in the memory physical address being higher than the bit of the page size bit of the memory physical address; and allocating memory resources associated with the memory unit pointed by the binary bit of the available memory unit to an access main body of the target electronic equipment.

Description

Technical Field

[0001] The present application relates to the field of terminals, and in particular to a method for allocating memory resources. Background Art

[0002] In modern computer systems, the DMA (Direct Memory Access) controller does not rely on the CPU (Central Processing Unit) and can directly complete the data transfer operation to the memory, freeing the CPU computing power from IO (Input / Output) operations, thereby achieving the purpose of improving CPU efficiency.

[0003] However, as the main memory access subjects, the DMA controller and the CPU are both master devices of the memory bus, that is, they can both initiate IO operation requests to the bus. Therefore, when the IO requests of these two access subjects fall on the same physical memory unit Bank within a period of time, they will compete for the unique line cache of the Bank, which will increase the response delay of the CPU memory access request, thereby increasing the uncertainty of the CPU memory access time.

[0004] How to improve the rationality of allocating memory resources to improve the memory access certainty of the access subject is the technical problem to be solved by this application. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a method for allocating memory resources to solve the problem of a central processing unit and a direct memory access controller competing for memory resources.

[0006] In a first aspect, a method for allocating memory resources is provided, comprising:

[0007] Acquire a mapping relationship between a memory physical address of a target electronic device and an internal address of the memory, wherein the memory physical address is an address used by an access subject to access the memory, and the access subject is a direct memory access controller or a central processing unit of the target electronic device;

[0008] Determine at least one target binary bit from the memory physical address based on the mapping relationship, the at least one target binary bit pointing to the memory internal address;

[0009] Determine an available memory unit binary bit from the at least one target binary bit, wherein the available memory unit binary bit is located at a position higher than the position of the page size bit of the memory physical address in the memory physical address;

[0010] The memory resource associated with the memory unit pointed to by the binary bit of the available memory unit is allocated to the access subject of the target electronic device.

[0011] In a second aspect, a device for allocating memory resources is provided, comprising:

[0012] An acquisition module is used to acquire a mapping relationship between a memory physical address of a target electronic device and an internal address of the memory, wherein the memory physical address is an address used by an access subject to access the memory, and the access subject is a direct memory access controller or a central processing unit of the target electronic device;

[0013] A first determining module determines at least one target binary bit from the memory physical address based on the mapping relationship, wherein the at least one target binary bit points to the memory internal address;

[0014] A second determination module determines an available memory unit binary bit from the at least one target binary bit, wherein a position of the available memory unit binary bit in the memory physical address is higher than a position of a page size bit of the memory physical address;

[0015] An allocation module allocates memory resources associated with the memory unit pointed to by the binary bit of the available memory unit to an access subject of the target electronic device.

[0016] According to a third aspect, an electronic device is provided. The electronic device comprises a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the steps of the method according to the first aspect are implemented.

[0017] According to a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method according to the first aspect are implemented.

[0018] In an embodiment of the present application, by obtaining the mapping relationship between the memory physical address of the target electronic device and the internal address of the memory, wherein the memory physical address is the address used by the access subject to access the memory, and the access subject is the direct memory access controller or central processing unit of the target electronic device; then, based on the mapping relationship, at least one target binary bit is determined from the memory physical address, and at least one target binary bit points to the internal address of the memory; then, the available memory unit binary bit is determined from at least one target binary bit, wherein the position of the available memory unit binary bit in the memory physical address is higher than the position of the page size bit of the memory physical address; finally, the memory resource associated with the memory unit pointed to by the available memory unit binary bit is allocated to the access subject of the target electronic device. This scheme can realize the allocation of memory resources to the access subject, wherein the allocated memory resources are available memory units determined based on the page size bits of the memory physical address, which can ensure that the complete memory unit is allocated to the access subject, avoiding the contention of the same memory unit between different access subjects. By allocating memory resources to the access subject, the access subject can use the determined memory resources, thereby improving the certainty of the access subject to access the memory, making the memory resources reasonably allocated, and helping to improve the efficiency of memory access request processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 This is a schematic diagram of various CPUs and DMAs in a computer system competing for the only row cache of the same bank;

[0021] Figure 2a This is one of the flowcharts of a method for allocating memory resources in one embodiment of the present application;

[0022] Figure 2b This is a schematic diagram of the basic principle of mapping a physical memory address to a DRAM internal address in one embodiment of the present application;

[0023] Figure 2c It is a schematic diagram of the position of the 21st bit of the Bank in the memory physical address according to an embodiment of the present application;

[0024] Figure 2d It is a schematic diagram of the position of the PAGE bit and the memory unit bit in the physical memory address of an embodiment of the present application;

[0025] Figure 3 This is a second flow chart of a method for allocating memory resources according to an embodiment of the present application;

[0026] Figure 4 This is a flowchart of a method for allocating memory resources according to an embodiment of the present application;

[0027] Figure 5 This is a fourth flowchart of a method for allocating memory resources according to an embodiment of the present application;

[0028] Figure 6a This is a flowchart of a method for allocating memory resources according to an embodiment of the present application;

[0029] Figure 6b It is a schematic diagram of allocating memory resources to DMA and CPU respectively through a universal memory allocator in one embodiment of the present application;

[0030] Figure 7a This is a sixth flowchart of a method for allocating memory resources according to an embodiment of the present application;

[0031] Figure 7b This is a flowchart of a method for allocating memory resources according to an embodiment of the present application;

[0032] Figure 8 This is a flowchart of a method for allocating memory resources according to an embodiment of the present application;

[0033] Fig. 9 It is a schematic diagram of the structure of a device for allocating memory resources according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application. The numbering of the drawings in this application is only used to distinguish the various steps in the scheme, and is not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0035] The present invention can be applied to fields that have relatively high requirements on the determinism of computer systems, such as partitioned operating systems, safety-critical systems, and other scenarios.

[0036] like Figure 1As shown in the figure, in a computer system, both CPU and DMA are master devices. For the sake of convenience, in this example, it is assumed that the CPU is bus master 1 and DMA is bus master 2. When they access DRAM memory through addresses, they may compete for the only row cache of the same bank, causing the row cache locality of the bank to fail.

[0037] Specifically, the CPU can access DRAM memory through virtual addresses, where the virtual address is mapped to the real address through the memory management unit (MMU), and then the physical address of the memory is obtained. Then based on the last level cache (LLC), the address bus Bus is used to map the physical address of the memory to the DRAM address through the DRAM memory controller. Finally, the DRAM memory is accessed through the DRAM address. Among them, the DRAM address may include specific addresses such as Channel, Rank, Bank, and Row.

[0038] On the other hand, DMA can also complete the mapping of virtual address to real address through memory management unit, and then obtain the physical address of memory, or DMA can directly use the physical address of memory. Then, based on the physical address of memory, the mapping of physical address of memory to DRAM address is completed through address bus Bus and DRAM memory controller. Finally, DRAM memory is accessed through DRAM address.

[0039] In terms of software technology, in order to alleviate the impact of DMA on CPU memory access, the CPU and DMA operations can be divided into time periods to avoid conflicts caused by CPU and DMA accessing memory in parallel at the same time. The main disadvantage of this method is that it sacrifices efficiency and does not fully utilize the characteristics of DMA and CPU in parallel. At the same time, this solution is not very versatile and requires careful time division for specific scenarios.

[0040] Another method is to add the delay under DMA interference to the estimated CPU memory access time during the CPU memory access time estimation. The main disadvantage of this method is that the estimation of CPU memory access time is too pessimistic, resulting in insufficient utilization of CPU computing power. In addition, it is also difficult to accurately estimate the CPU memory access time under DMA interference, which is often affected by specific scenarios and hardware.

[0041] In terms of hardware technology, RDT (Resource Director Technology) technology or MPAM (Memory System Resource Partitioning and Monitoring) technology can be applied to introduce an ID (Identity document) for each IO request through hardware, and then implement memory flow control, priority and bandwidth control based on the ID in the hardware related to the memory access path. However, these solutions rely on hardware function support on newer hardware and are not suitable for more mature older systems, so their applicability is limited. In addition, if these hardware functions are introduced in safety-critical areas, the hardware itself also needs to be certified, which will bring additional costs.

[0042] In order to solve the problems existing in the prior art, the embodiment of the present application provides a method for allocating memory resources. The present invention can be applied to partition operating systems, high-determinism operating systems, and safety-critical operating systems that require the use of DMA devices. The executor of this solution can be an electronic device. Figure 2a As shown, the method provided in the embodiment of the present application includes:

[0043] S21: Obtain a mapping relationship between a memory physical address of a target electronic device and an internal address of the memory, wherein the memory physical address is an address used by an access subject to access the memory, and the access subject is a direct memory access controller or a central processing unit of the target electronic device.

[0044] When the CPU and DMA in the system use the memory physical address of the memory to access the DRAM memory, since the DRAM memory has its own storage structure, the memory physical address of the memory needs to be converted to the internal address of the DRAM through the memory controller before it can be accessed. Therefore, there is a mapping relationship between the memory physical address of the memory and the internal address of the DRAM. This mapping relationship is usually maintained by the memory controller. Among them, the memory physical address can also be called the physical memory address.

[0045] In this step, a mapping relationship between a physical address of a memory of a target electronic device and an internal address of a memory is obtained. The target electronic device is an electronic device including a DMA and a CPU, such as a computer. The above mapping relationship can be obtained from a memory controller, and the mapping relationship can be preset.

[0046] Among them, the direct memory access DMA controller is a unique peripheral that transfers data within the system. It can be regarded as a controller that can connect internal and external memory to each DMA-capable peripheral through a set of dedicated buses. It is a peripheral because it performs transfers under the programming control of the processor. The central processing unit CPU is the computing and control core of the computer system and is the final execution unit for information processing and program running.

[0047] In this instance, the memory can specifically refer to DRAM memory, which is the main type of main memory in computer systems. It uses capacitors to store data, which are organized in rows and columns in the memory chip. Each storage cell has a unique address that can be read and written by the memory controller.

[0048] The internal address of DRAM memory usually includes five parts: Channel, Rank, Bank, Row, and Column. Among these five parts, DRAM memory can execute independently and in parallel at the Channel, Rank, and Bank levels, so these three parts can uniquely identify a memory unit.

[0049] Specifically, the memory internal address can refer to the address of the memory unit, that is, the internal address of the DRAM memory. The memory unit refers to the smallest physical hardware unit in the DRAM memory that can be parallelized on the hardware. The memory unit can be configured in advance according to the DRAM hardware and memory control implementation. Different memory units can be formed as follows:<Channel,Rank,Bank> The triple is represented by , where Bank is required and Channel and Rank are optional.

[0050] The above-mentioned Channel refers to an independent path or interface for data transmission. Usually, each channel is associated with a memory module or a memory component, and each channel can perform read and write operations independently.

[0051] The above-mentioned Rank refers to the memory block on the memory module. Each Rank contains a group of memory chips that can independently perform data read and write operations. Usually, a Rank contains multiple Banks.

[0052] The above-mentioned Bank refers to an array in a memory chip. A Bank is usually composed of a group of memory cells. Banks can be accessed in parallel, and each Bank has its own independent row buffer (ie, Row Buffer).

[0053] Figure 2bThe following is a basic diagram of the mapping of physical memory addresses to DRAM internal addresses. The virtual address is looked up through the TLB (Translation Lookaside Buffer) to determine the corresponding physical address of the memory. Then, through the LLC Miss, the specific memory chip Location on Chip is located based on the multiple IDs (Channel ID, Rank ID, Bank ID, Row ID, Column ID) in the bit permutation.

[0054] S22: Determine at least one target binary bit from the memory physical address based on the mapping relationship, and the at least one target binary bit points to the memory internal address.

[0055] In a memory physical address, there are often specific multiple binary bits used to point to an internal address of the memory. Optionally, the at least one target binary bit includes a Channel bit, a Rank bit, and a Bank bit. In practical applications, there can be one or more of the three target binary bits, the Channel bit, the Rank bit, and the Bank bit. For example, there is 1 Channel bit, 2 Rank bits, and 2 Bank bits in a memory physical address.

[0056] In this example, a triplet including a Channel bit, a Rank bit, and a Bank bit can represent a memory unit, and different memory units correspond to different triplet.

[0057] In this solution, the memory controller can determine the above mapping relationship through the value of a specific bit in the memory physical address, so that a definite mapping relationship to the memory unit in the DRAM is established for each memory physical address in the system.

[0058] Based on this mapping relationship, this step can determine the corresponding relationship between the bits in the memory physical address and the memory physical address. In other words, this step determines which bits in the memory physical address point to the Channel, Rank and Bank of the internal address of the memory. Figure 2c For example, among the 0th to 31st bits of the memory physical address, the 21st bit is used to point to the bank. Correspondingly, the bits pointing to the channel and rank are also determined, thereby pointing to the target binary bits of the internal address.

[0059] S23: Determine an available memory unit binary bit from the at least one target binary bit, wherein the available memory unit binary bit is located at a position higher than the page size bit of the memory physical address in the memory physical address.

[0060] In this solution, the physical memory can be managed and allocated with fixed-size pages PAGE through the operating system memory allocator. To facilitate the management of memory units, this solution discards the target binary bits of Channel, Rank, and Bank that are smaller than the physical memory address PAGE bit, and only retains the binary bits corresponding to the physical memory larger than the PAGE unit, so as to allocate memory resources to the access subject with PAGE as the allocation unit. This can avoid the problem that the memory of the same PAGE is allocated to different access subjects, which may cause different access subjects to compete for the same PAGE memory resources.

[0061] Combine the following Figure 2d To illustrate this scheme, Figure 2d This is a schematic diagram of the location of the PAGE bit and the memory unit bit in the physical memory address. In this example, it is assumed that the PAGE size is 4KB, and the PAGE bit is the 11th bit in the 0th to 31st bits of the memory physical address. The Bank bit0 and channel bit that are smaller than the PAGE bit are discarded in this step, leaving only the Bank bit1 and bit2, and the Rank bit0 and bit1 as available memory unit binary bits.

[0062] S24: Allocate the memory resources associated with the memory unit pointed to by the binary bit of the available memory unit to the access subject of the target electronic device.

[0063] After determining the available memory unit binary bits, you can<Channel,Rank,Bank> Triples are assigned different memory units. Optional, based on<Channel,Rank,Bank> A triplet can uniquely identify a memory unit. In this example, a memory unit bitmap is used to manage all available memory units in the system. Each bit in the bitmap represents a memory unit, and the total number of bits in the bitmap is the maximum memory unit supported by the system.

[0064] like Figure 2d In the memory storage system shown, since the Channel bit and Bank bit0 are unavailable, it can be determined that the number of available memory cells in the system is 4 (2-bit Bank bit) × 4 (2-bit Rank bit) = 16.

[0065] After determining the number of available memory units, the available memory units can be allocated to the access subject. In practical applications, the required memory units can be allocated to the DMA according to the physical memory utility information of the DMA. After the memory units are allocated, the corresponding bit positions of the memory units allocated to the DMA in the memory unit bitmap are set to 1, thereby recording that these memory units are in the state of being allocated to the DMA for use.

[0066] Correspondingly, the memory units allocated to the CPU can also be recorded through a bitmap. If the target electronic device only includes two access subjects, the CPU and the DMA, then only the memory allocated to one of the access subjects needs to be recorded to achieve the distinction of the memory units of the two access subjects.

[0067] Optionally, different memory units may be distinguished by using memory unit IDs, so as to record the allocation and usage status of different memory units. In practical applications, the memory unit ID (DRAM UNIT ID) may be a positive integer.

[0068] Through the scheme provided by the embodiment of the present application, the allocated memory resources are available memory units determined based on the page size bits of the memory physical address, which can ensure that a complete memory unit is allocated to the access subject, avoiding competition between different access subjects for the same memory unit. By allocating memory resources to the access subject, the access subject can use certain memory resources, thereby improving the certainty of the access subject's memory access, making the memory resources reasonably allocated, and helping to improve the efficiency of memory access request processing.

[0069] After allocating memory resources through the embodiment of the present application, DMA and CPU can operate in parallel, no longer need to be performed in time-sharing, and can make full use of DMA hardware characteristics. Moreover, since this solution improves the certainty of CPU access to memory, it can be helpful to accurately estimate the CPU memory access time without overly considering the impact of DMA on the CPU memory access time. This solution does not need to rely on the latest hardware features, is applicable to a wide range of hardware, and does not require additional hardware certification costs. By executing memory resource allocation through this solution, the impact of DMA on the certainty of CPU memory access can be effectively reduced, which is conducive to improving the overall certainty of the system.

[0070] In different application scenarios, this solution can also achieve additional technical effects, making the operating system's memory manager aware of the underlying memory hardware unit, which is conducive to taking more customized optimization strategies according to specific business scenarios and improving the competitiveness of the system. For example, between partitioned operating systems or virtual machines, isolating and alleviating the impact of DMA on CPU memory access determinism is conducive to improving system determinism and performance. In a highly deterministic system, DMA and CPU can operate in parallel, no longer in time-sharing to meet deterministic needs, and can fully utilize the DMA hardware characteristics.

[0071] Based on the solution provided in the above embodiment, optionally, Figure 3 As shown, before the above step S24, that is, before allocating the memory resource associated with the memory unit pointed to by the binary bit of the available memory unit to the access subject of the target electronic device, it also includes:

[0072] S31: Acquire configuration information of the direct memory access controller, where the configuration information includes at least one of the following items of the direct memory access controller: a device identifier, a required memory capacity, and a physical memory start address.

[0073] The above step S24, allocating the memory resources associated with the memory unit pointed to by the binary bit of the available memory unit to the access subject of the target electronic device, includes:

[0074] S32: When the access subject is a direct memory access controller of the target electronic device, based on configuration information of the direct memory access controller, memory resources associated with the memory unit pointed to by the binary bit of the available memory unit are allocated to the direct memory access controller of the target electronic device.

[0075] In this example, the DMA information configuration device can be used to collect relevant information about the use of memory by DMA to be used as the configuration information of the DMA controller. In a partitioned operating system, memory is usually statically configured through an XML (Extensible Markup Language) file. The specific configuration content may include: DMA device ID, the physical memory starting address and size that the DMA device needs to use, and a DMA device can configure multiple segments of physical memory. If the DMA device can use any physical memory address of the target electronic device, it only needs to configure the physical memory size, and there is no need to configure the physical memory starting address.

[0076] In addition, for DMA information configuration, a dynamic configuration method may be adopted, such as the operating system providing a callback function, and the BSP (Board Support Package) configuring the DMA information in the callback function.

[0077] In this example, the DMA requirement can be determined based on the configuration information of the DMA controller, and then the memory resources related to the binary bits of the available memory units are allocated to the DMA to meet the memory requirement expressed by the configuration information of the DMA controller.

[0078] Based on the solution provided in the above embodiment, optionally, Figure 4As shown, the above step S32, based on the configuration information, allocates the memory resources associated with the memory unit pointed to by the binary bit of the available memory unit to the direct memory access controller of the target electronic device, including:

[0079] S41: Allocate the memory resources associated with the memory unit pointed to by the binary bit of the available memory unit to the direct memory access controller of the target electronic device through the memory allocator of the direct memory access controller, so as to allocate memory resources of a memory capacity that meets the required usage to the direct memory access controller corresponding to the device identifier of the direct memory access controller.

[0080] In the solution provided in the embodiment of the present application, the memory allocation of the direct memory access controller is used to perform memory allocation for DMA, and the controller is called a DMA memory allocator in this example. Specifically, the DMA memory allocator receives the input of the DMA device number in advance, and then allocates the required physical memory to the DMA device according to the configuration information of the DMA.

[0081] Among them, the DMA memory allocator manages according to the physical page size. For devices that directly use the physical address of the memory, the DMA memory allocator can return the physical address of the memory. If the DMA controller supports virtual addresses, the DMA memory allocator returns the virtual address accordingly. The virtual address can be pre-specified by the user or automatically selected by the DMA memory allocator.

[0082] In addition, in actual applications, the memory allocated to DMA by the DMA memory allocator is used as the source address or destination address by the DMA controller during the transmission process, and may eventually be used by the CPU operation. However, this part of the memory is time-sharing, that is, the CPU only uses this memory when it is notified by DMA that a DMA operation is completed, and is separated from the DMA operation period in time. Before the CPU notifies DMA that it has completed the operation, DMA will no longer use this segment of memory. At this time, if DMA has new memory requirements, it needs to be allocated through the DMA memory allocator, thereby avoiding the situation where the CPU and DMA compete for memory.

[0083] Based on the solution provided in the above embodiment, optionally, Figure 5 As shown, the above step S24, allocating the memory resource associated with the memory unit pointed to by the binary bit of the available memory unit to the access subject of the target electronic device, includes:

[0084] S51: When the access subject is the central processing unit of the target electronic device, the memory resource associated with the memory unit pointed to by the binary bit of the available memory unit is allocated to the central processing unit of the target electronic device through the memory allocator of the central processing unit.

[0085] In the embodiment of the present application, the memory allocator of the central processing unit is referred to as the CPU memory allocator. Among them, the memory used by the CPU is uniformly allocated through the CPU memory allocator. The CPU memory allocator manages the physical memory of the system with the PAGE size. During the initialization process of the CPU memory allocator, it can receive the input of the memory unit bitmap used by DMA, and remove the PAGE page corresponding to the memory unit used by DMA from the manager, so that only the memory unit not allocated to DMA is retained. When the CPU needs to allocate memory resources later, it uniformly uses the CPU memory allocator to allocate the memory physical address page corresponding to the virtual address, thereby realizing the allocation of memory resources to the CPU.

[0086] In this solution, memory is managed through two memory allocators, CPU memory allocator and DMA memory allocator, ultimately achieving the purpose of alleviating the interference of DMA on CPU memory access.

[0087] Based on the solution provided in the above embodiment, optionally, Figure 6a As shown, the above step S24, allocating the memory resource associated with the memory unit pointed to by the binary bit of the available memory unit to the access subject of the target electronic device, includes:

[0088] S61: Allocate memory resources associated with the memory unit pointed to by the available memory unit binary bit to the access subject of the target electronic device through a universal memory allocator based on a preset memory unit bitmap, wherein the preset memory unit bitmap represents the correspondence between the memory resources and the allocated access subject.

[0089] In the solution provided in the embodiment of the present application, a memory allocator is used to perform memory allocation for the CPU and DMA respectively. In order to ensure that there is no memory conflict between the two devices, this solution uses a memory unit bitmap to implement maintenance. In addition to receiving the size and virtual address of the requested memory allocation, the general allocator also needs to receive an additional memory unit bitmap, which is used to require that the memory allocated by the allocator must belong to one or more memory units specified in the bitmap. The memory unit bitmap is used to distinguish the memory resources allocated to the CPU from the memory resources allocated to the DMA, thereby avoiding competition for memory resources between the CPU and the DMA.

[0090] like Figure 6bAs shown, memory resources are allocated to DMA and CPU respectively through a general memory allocator (shown as a memory allocator in the figure). Among them, any memory unit corresponds to a triple<Channel,Rank,Bank> . Memory resources in DRAM memory are allocated to CPU or DMA in units of PAGE. For example, the general memory allocator allocates memory resources corresponding to memory unit 0 and memory unit 1 to DMA based on the DMA memory configuration information. And memory resources such as memory unit 2, memory unit 3, memory unit 4... memory unit N that are not allocated to DMA are allocated to CPU for use, thereby ensuring that CPU and DMA use different memory resources and avoiding memory resource competition between CPU and DMA.

[0091] In the solution provided in the embodiment of the present application, S22 determines at least one target binary bit, and two specific implementation methods are provided below.

[0092] Based on the solution provided in the above embodiment, optionally, Figure 7a As shown, the above step S22, determining at least one target binary bit from the memory physical address based on the mapping relationship, includes:

[0093] S71: Determine at least one target binary bit from the memory physical address based on a mapping relationship pre-configured by a memory controller of the target electronic device.

[0094] In this example, the mapping relationship between the memory physical address and the memory internal address can be pre-set by the memory controller. Specifically, the specific configuration of the memory controller related registers in the system can be used to determine which bits in the memory physical address point to the channel, rank and bank, so as to determine these bits as the target binary bits.

[0095] Based on the solution provided in the above embodiment, optionally, Figure 7b As shown, the above step S22, determining at least one target binary bit from the memory physical address based on the mapping relationship, includes:

[0096] S72: Based on a preset recognition algorithm, traverse and measure each binary bit in the memory physical address to obtain a measurement time length corresponding to the binary bit.

[0097] In this example, each binary bit in the memory physical address is traversed and identified through a preset identification algorithm. This solution is based on the local characteristics of the memory unit and reads multiple times to obtain the measurement duration of the binary bit. The measurement duration of the target binary bit pointing to the memory unit is affected by locality and will be shorter than the measurement duration of the binary bit of the non-memory unit. Based on this, each binary bit in the memory physical address is identified one by one through a preset identification algorithm.

[0098] S73: Determine the binary bit whose measured duration is less than the preset reference duration as the target binary bit.

[0099] Specifically, the measurement duration corresponding to each binary bit can be counted first, and the measurement durations corresponding to multiple binary bits can be classified. The preset reference duration can be an average value of the measurement duration, or a duration pre-set based on the measurement duration of the non-memory unit.

[0100] In this step, the binary bit whose measured duration is less than the preset reference duration is determined as the target binary bit, that is, the binary bit pointing to the memory unit.

[0101] Based on the solution provided in the above embodiment, optionally, Figure 8 As shown, the above step S72, based on a preset recognition algorithm, traverses and measures each binary bit in the memory physical address to obtain the measurement time corresponding to the binary bit, including:

[0102] S81: Generate a pair of measurement addresses based on the binary bits to be measured in the memory physical address, wherein the values ​​of the binary bits to be measured in the pair of measurement addresses are different.

[0103] In the process of traversing each bit in the memory physical address, a pair of addresses with two bits of 0 and 1 is generated for any binary bit to be tested. For example, suppose a memory physical address containing 32 bits is measured. Then, in this step, the first bit is determined as the binary bit to be tested, the first bit is set to 0, and the values ​​of the other 31 bits are retained to generate an address with the first bit of 0. Correspondingly, the first bit is set to 1, and the values ​​of the other 31 bits are retained to generate another address with the first bit of 0, and a pair of addresses corresponding to the first bit is obtained.

[0104] S82: Perform multiple measurement operations based on the pair of measurement addresses to obtain a measurement duration corresponding to the binary bit to be measured.

[0105] Then, the time of this pair of addresses is measured multiple times to determine whether the bit is a memory unit bit. The principle applied here is that if the bit is a memory unit bit, the locality of the Row Buffer is still there because different memory units are used and two RowBuffers are used twice. Therefore, the time of measuring the memory unit bit is faster than that of the non-memory unit bit.

[0106] Optionally, for the screening of available memory unit bits, the mapping settings of the memory controller can be adjusted to avoid discarding and improve the availability of memory units. Specifically, in the physical address of the memory, for the target binary bits that are smaller than the page size bit (i.e., the right side of the PAGE bit), the memory controller can perform mapping modification to modify the target binary bits on the right side of the page size bit to the left side of the page size bit, thereby ensuring that the allocated memory resources are allocated to the access subject in units of PAGE. In other words, the memory resources of any PAGE are allocated to one access subject. Avoid the situation where part of the memory resources of a PAGE are allocated to one access subject, and the other part are allocated to another access subject.

[0107] This is because a page corresponds to multiple memory cells. The originally discarded memory cells can be artificially adjusted to the left of the page bit (that is, larger than the page bit), but this will lose a certain amount of performance. This performance loss is not considered in this solution. Generally speaking, the number of usable memory cells is relatively small. The purpose of this is to make full use of the memory cells.

[0108] In order to solve the problems existing in the prior art, the embodiment of the present application further provides a device 90 for allocating memory resources, such as Fig. 9 As shown, including:

[0109] An acquisition module 91 acquires a mapping relationship between a memory physical address of a target electronic device and an internal address of the memory, wherein the memory physical address is an address used by an access subject to access the memory, and the access subject is a direct memory access controller or a central processing unit of the target electronic device;

[0110] A first determining module 92 determines at least one target binary bit from the memory physical address based on the mapping relationship, wherein the at least one target binary bit points to the memory internal address;

[0111] A second determination module 93 determines an available memory unit binary bit from the at least one target binary bit, wherein the available memory unit binary bit is located at a position higher than the page size bit of the memory physical address in the memory physical address;

[0112] The allocation module 94 allocates the memory resources associated with the memory unit pointed to by the binary bit of the available memory unit to the access subject of the target electronic device.

[0113] Through the device provided by the embodiment of the present application, the mapping relationship between the memory physical address of the target electronic device and the internal address of the memory is obtained, wherein the memory physical address is the address used by the access subject to access the memory, and the access subject is the direct memory access controller or central processing unit of the target electronic device; then, at least one target binary bit is determined from the memory physical address based on the mapping relationship, and at least one target binary bit points to the internal address of the memory; then, the available memory unit binary bit is determined from the at least one target binary bit, wherein the position of the available memory unit binary bit in the memory physical address is higher than the position of the page size bit of the memory physical address; finally, the memory resource associated with the memory unit pointed to by the available memory unit binary bit is allocated to the access subject of the target electronic device. This scheme can realize the allocation of memory resources to the access subject, wherein the allocated memory resources are available memory units determined based on the page size bits of the memory physical address, which can ensure that the complete memory unit is allocated to the access subject, avoiding the contention of the same memory unit between different access subjects. By allocating memory resources to the access subject, the access subject can use the determined memory resources, thereby improving the certainty of the access subject to access the memory, making the memory resources reasonably allocated, and helping to improve the efficiency of memory access request processing.

[0114] Among them, the above modules in the device provided by the embodiment of the present application can also implement the method steps provided by the above method embodiment. Alternatively, the device provided by the embodiment of the present application can also include other modules in addition to the above modules to implement the method steps provided by the above method embodiment. And the device provided by the embodiment of the present application can achieve the technical effects that can be achieved by the above method embodiment.

[0115] Preferably, an embodiment of the present application also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the various processes of the above-mentioned embodiment of a method for allocating memory resources are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0116] The embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of the above-mentioned method for allocating memory resources is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0117] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0118] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0119] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0120] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0121] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0122] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0123] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0124] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0125] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0126] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for allocating memory resources, characterized in that: include: Acquire a mapping relationship between a memory physical address of a target electronic device and an internal address of the memory, wherein the memory physical address is an address used by an access subject to access the memory, and the access subject is a direct memory access controller or a central processing unit of the target electronic device; Determine at least one target binary bit from the memory physical address based on the mapping relationship, the at least one target binary bit pointing to the memory internal address; Determine an available memory unit binary bit from the at least one target binary bit, wherein the available memory unit binary bit is located at a position higher than the position of the page size bit of the memory physical address in the memory physical address; The memory resource associated with the memory unit pointed to by the binary bit of the available memory unit is allocated to the access subject of the target electronic device.

2. The method according to claim 1, characterized in that Before allocating the memory resource associated with the memory unit pointed to by the binary bit of the available memory unit to the access subject of the target electronic device, the method further includes: Acquire configuration information of the direct memory access controller, the configuration information including at least one of the following items of the direct memory access controller: device identification, required memory capacity, and physical memory start address; The method of allocating the memory resource associated with the memory unit pointed to by the binary bit of the available memory unit to the access subject of the target electronic device includes: When the access subject is the direct memory access controller of the target electronic device, based on the configuration information of the direct memory access controller, the memory resources associated with the memory unit pointed to by the binary bit of the available memory unit are allocated to the direct memory access controller of the target electronic device.

3. The method according to claim 2, characterized in that Based on the configuration information, allocating memory resources associated with the memory unit pointed to by the binary bit of the available memory unit to a direct memory access controller of the target electronic device includes: The memory resources associated with the memory unit pointed to by the binary bit of the available memory unit are allocated to the direct memory access controller of the target electronic device through the memory allocator of the direct memory access controller, so as to allocate memory resources of memory capacity that meets the required usage to the direct memory access controller corresponding to the device identifier of the direct memory access controller.

4. The method according to claim 3, characterized in that Allocating memory resources associated with the memory unit pointed to by the binary bit of the available memory unit to an access subject of the target electronic device, comprising: In the case where the access subject is the central processor of the target electronic device, the memory resources associated with the memory unit pointed to by the binary bit of the available memory unit are allocated to the central processor of the target electronic device through the memory allocator of the central processor.

5. The method according to claim 1, characterized in that Allocating memory resources associated with the memory unit pointed to by the binary bit of the available memory unit to an access subject of the target electronic device, comprising: Through a universal memory allocator, memory resources associated with the memory unit pointed to by the available memory unit binary bit are allocated to the access subject of the target electronic device based on a preset memory unit bitmap, wherein the preset memory unit bitmap represents the correspondence between the memory resources and the allocated access subject.

6. The method according to any one of claims 1 to 5, characterized in that: Determining at least one target binary bit from the memory physical address based on the mapping relationship includes: At least one target binary bit is determined from the memory physical address based on a mapping relationship preconfigured by a memory controller of the target electronic device.

7. The method according to any one of claims 1 to 5, characterized in that: Determining at least one target binary bit from the memory physical address based on the mapping relationship includes: Based on a preset recognition algorithm, traverse and measure each binary bit in the memory physical address to obtain a measurement time corresponding to the binary bit; The binary bit whose measured duration is less than the preset reference duration is determined as the target binary bit.

8. The method according to claim 7, characterized in that Based on a preset recognition algorithm, traverse and measure each binary bit in the memory physical address to obtain a measurement time corresponding to the binary bit, including: generating a pair of measurement addresses based on the binary bit to be measured in the memory physical address, wherein the values ​​of the binary bit to be measured in the pair of measurement addresses are different; A plurality of measurement operations are performed based on the pair of measurement addresses to obtain a measurement duration corresponding to the binary bit to be measured.

9. The method according to any one of claims 1 to 5, characterized in that: The at least one target binary bit includes a Channel bit, a Rank bit, and a Bank bit.

10. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the method according to any one of claims 1 to 9 when executed by the processor.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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