Apparatus and method for multiple types of alarms along alarm bus

Abstract

The invention relates to devices, systems, and methods for multiple types of alarms along an alarm bus. The memory device may detect various types of alarms and signal the alarms to the controller using alarm signals along the alarm bus. Different pulse widths of the alarm signal may be used to indicate the alarm type. For example, if the alarm signal is at an active level between a first duration and a second duration, it may indicate a first type of alarm, and if the alarm signal is active between a third duration and a fourth duration, it may indicate a second type of alarm. If the alarm signal remains valid for a time longer than a threshold amount of time, it may indicate a third type of alarm.

Description

Technical Field

[0001] The present application relates to apparatus and methods for multiple types of alarms along an alarm bus. Background Art

[0002] Information may be stored on memory cells of a memory device. Memory cells may be organized at the intersection of word lines (rows) and bit lines (columns). Information in a memory cell may decay over time. For example, information may be stored as a charge on a capacitor that may decay over time. A memory device may perform a refresh operation to restore information and prevent information loss.

[0003] There may be situations where the memory detects an error or other problem. The memory may signal a controller or host device operating the memory, such as by providing an alert signal along an alert pin. In response to the alert signal, the controller may note the error and / or take one or more actions to mitigate, correct, and / or otherwise resolve the error. Summary of the invention

[0004] In one aspect, the present disclosure relates to a device comprising: an alarm terminal; at least one alarm source circuit configured to provide a first alarm detection signal in response to a first type of alarm or to provide a second alarm detection signal in response to a second type of alarm; and an alarm generator circuit configured to provide an alarm signal to the alarm terminal at an effective level for a first duration in response to the first alarm detection signal or to provide the alarm signal to the alarm terminal at the effective level for a second duration in response to the second alarm detection signal.

[0005] In another aspect, the present disclosure relates to a system comprising: an alarm bus; a memory configured to provide an alarm signal along the alarm bus at an effective level within a time period; and a controller configured to determine a duration of the time period and determine an alarm type based on the duration of the alarm signal.

[0006] In another aspect, the present disclosure relates to a method comprising: detecting a first type of alarm or a second type of alarm; activating an alarm signal at a first time in response to the first type of alarm or the second type of alarm; deactivating the alarm signal at a second time in response to the first type of alarm; and deactivating the alarm signal at a third time in response to the second type of alarm, wherein the third time is after the second time. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a set of timing diagrams representing the different types of alarms that can be provided along the alarm bus.

[0009] Figure 3 is a block diagram of a memory system according to some embodiments of the present disclosure.

[0010] Figure 4 is a timing diagram of alarm types according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of a method of providing multiple types of alerts along an alert bus according to some embodiments of the present disclosure.

[0012] Figure 6 is a flow chart of a method of determining an alarm type along an alarm bus with a controller according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] The following description of certain embodiments is merely exemplary and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof and that show by way of illustration specific embodiments in which the described system and method may be practiced. These embodiments are described in sufficient detail to enable a person skilled in the art to practice the presently disclosed system and method, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the sake of clarity, when certain features are obvious to a person skilled in the art, their detailed description will not be discussed so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the present disclosure is defined solely by the appended claims.

[0014] Information in the memory array may be accessed by one or more access operations, such as a read or write operation, etc. During an example access operation, a word line may be activated based on a row address, and then information of selected memory cells along that active word line may be read or written based on which bit lines are accessed, which may be based on a column address.

[0015] The memory may include various circuits that monitor and / or attempt to protect the integrity of the data in the array. For example, the memory may include error correction code circuitry that checks information read from the memory array to determine if there are errors in the information (e.g., altered bits) and corrects the errors if possible. The memory may include refresh control circuitry that performs various refresh operations to ensure that the information in the array does not decay over time to the point where the information is lost.

[0016] If the memory device detects an error, a fault, or other type of problem, a signal may be provided to the controller indicating that an error has been detected. The memory may use an alarm bus that is coupled from the alarm pin of the memory to the controller. To save space, because alarms may generally be relatively rare, the alarm bus may be a single conductive element, and the alarm signal may be a binary signal (e.g., valid or invalid). However, as memory devices become more complex, it may be desirable to increase the number of types of alarms that may be communicated to the controller along the alarm bus. It may therefore be desirable to use an alarm signal along the alarm bus to signal multiple alarm types.

[0017] The present disclosure relates to apparatus, systems and methods for multiple types of alarms along an alarm bus. A memory device uses the pulse width of an alarm signal along the alarm bus to indicate multiple types of alarms. The memory may determine that the alarm signal should be sent, and then the alarm generator circuit of the memory may drive the alarm pin (and the alarm bus) to an active level. The length of time that the alarm signal is kept at the active level depends on the type of alarm. For example, the memory may keep the alarm signal active for a first number of clock cycles for a first type of alarm or for a second type of alarm. Some types of alarms may remain active until a controller performs an action. The controller has an alarm logic circuit coupled to the alarm bus. When the alarm signal becomes active (e.g., the alarm bus is detected to be at an active level), the alarm logic circuit may begin counting clock cycles. Based on when (and whether) the alarm signal returns to an inactive level, the alarm type may be determined. For example, if the count is between a first value and a second value, it may be an alarm of the first type. If the count is between a third value and a fourth value, it may be an alarm of the second type. If the alarm signal is still active after a threshold amount of time (eg, after counting a fifth value of clock cycles), it may be determined to be a third type of alarm.

[0018] Terms such as fault, error, and alarm may be used herein to refer to any detected condition and / or event within the memory that the memory wishes to communicate to the controller along the alarm bus. Alarm types do not necessarily include problems that cause problems or require intervention from the controller. Some types of alarms may simply provide information. Some types of alarms may indicate that data integrity is at risk or has been damaged. Some types of errors may require correction or other actions by the controller. The controller may determine what action to take (if any) based on the determined alarm type. The different types of alarms that are communicated and what actions the controller takes may be based on the specific implementation of the memory and / or controller. Although example implementations of alarms with example types are discussed herein, the present disclosure is not limited to these specific types of alarms.

[0019] In an example embodiment, a first type of alarm may indicate that an error has been detected by the error correction circuit. A second type of alarm may indicate that an error has occurred in a refresh operation of the memory, but not an error that requires intervention. A third type of alarm may indicate that an error has occurred in a refresh operation that requires intervention. In response to the third type of alarm, the controller may provide a refresh management command to the memory. In response to receiving the refresh management command, the memory device may return the alarm signal to an inactive level.

[0020] Figure 1 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. The memory device may be operated by a host or a controller 150. The controller 150 may provide various signals to operate the memory, such as by writing data to the memory device 100 and reading data from the memory device 100.

[0021] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1 In the embodiment of the present invention, the memory array 118 is shown to include 8 memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL (rows), a plurality of bit lines BL (columns), and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL.

[0022] The selection of the word line WL is performed by the row decoder 108, and the selection of the bit line BL is performed by the column decoder 110. Figure 1 In the embodiment of the present invention, the row decoder 108 includes a corresponding row decoder for each memory bank, and the column decoder 110 includes a corresponding column decoder for each memory bank. The bit line BL is coupled to a corresponding sense amplifier (SAMP). The read data from the bit line BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 120 through the complementary local data line (LIOT / B), the transfer gate (TG) and the complementary main data line (MIOT / B). Conversely, the write data output from the read / write amplifier 120 is transmitted to the sense amplifier SAMP through the complementary main data line MIOT / B, the transfer gate TG and the complementary local data line LIOT / B, and is written in the memory cell MC coupled to the bit line BL.

[0023] The semiconductor device 100 may employ a plurality of external terminals (e.g., pins) including a command and address (C / A) terminal coupled to a command and address bus to receive a command and address and a CS signal, a clock terminal for receiving clocks CK and / CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. The device 100 also includes an alarm terminal. Each of the external terminals may typically be coupled to a respective bus that couples the terminal to the controller 150. For example, the data terminal DQ may be coupled to the controller 150 along the data bus, and the alarm terminal Alert may be coupled to the controller 150 along the alarm bus, etc. In some embodiments, a plurality of memory devices may be coupled together (e.g., in a memory module), and the bus may be shared by a plurality of devices. For example, each memory in a module may be commonly coupled to the same alarm bus.

[0024] The clock terminal is supplied with external clocks CK and / CK provided by the controller 150 to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 110 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the circuit operation included in the input / output circuit 122, for example, to the data receiver to time the reception of the write data.

[0025] The memory address may be supplied to the C / A terminal by the controller 150. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded memory bank address BADD, which may indicate the memory bank of the memory array 118 containing the decoded row address XADD and the column address YADD. The C / A terminal may be supplied with a command by the controller 150. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., a read command for performing a read operation and a write command for performing a write operation), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and memory bank addresses BADD to indicate the memory cells to be accessed.

[0026] The command may be provided as an internal command signal to a command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuits for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0027] The memory 100 may use an Alert terminal or an alarm pin (and an alarm bus) to provide an alarm signal to the controller 150. The alarm signal may generally be used to indicate that the memory 100 has failed, but other reasons for using the alarm signal may also be used. In some embodiments, the alarm signal may be a binary signal and the alarm bus may be a single conductive element. Therefore, the alarm signal may be at an active level or an inactive level. For example, a voltage representing a low logic level may represent an active alarm signal and a voltage representing a high logic level may represent an inactive alarm signal, or vice versa. The memory 100 may have multiple types of alarms that may be communicated to the controller along the alarm terminal / alarm bus. The alarm generator circuit 140 may receive a signal indicating the type of alarm and then activate the alarm signal (e.g., by driving the alarm terminal and the alarm bus to a voltage representing an active level). The alarm generator circuit 140 may use a pulse width to indicate the type of alarm, and may therefore keep the alarm signal at an active level for a certain amount of time based on the type of alarm being communicated.

[0028] In some embodiments, the memory 100 may include a mode register 142. The mode register may include various information and / or settings stored in different registers for the operation of the memory. In response to detecting a fault, an error code and / or information about the fault may be written to a register of the mode register 142. In response to receiving an alarm signal, the controller 150 may perform a mode register read operation to retrieve information about the cause of the alarm signal. In some embodiments, the controller 150 may determine which register to perform the read operation on based on the type of the alarm signal (e.g., based on the time the alarm signal remains valid).

[0029] The present disclosure is generally described with error correction and refresh operations used as examples of types of failures that may result in different types of alert signals. Thus, the memory device 100 is described with respect to an embodiment that includes error correction circuitry 120 and refresh control circuitry 116 that performs certain types of refresh tracking. However, the present disclosure is not limited to these types of failures or alert signals, and other alert sources may be used in other example embodiments. In some embodiments, other forms of error correction and / or refresh may be used, or error correction and / or refresh may not be used.

[0030] In an example write operation, the controller 150 provides a write command and a bank, column and row address and data to be written. The write data is supplied to the data terminal DQ and is written to the memory cell corresponding to the row, column and bank address in the memory array 118. The write command is received by the command decoder 106, which provides an internal command so that the write data is received by the data receiver in the input / output circuit 122. The write clock may also be provided to the external clock terminal to time the reception of the write data by the data receiver of the input / output circuit 122. The write data is supplied to the error correction circuit 120 that generates a parity bit based on the write data via the input / output circuit 122. The data and parity are written to the memory array 118 at the location specified by the address.

[0031] In an example read operation, the controller 150 may provide a read command and a bank, column, and row address. In response to the read command and address, the memory 100 reads data from a memory cell in the memory array 118 corresponding to the row address XADD and the column address YADD. The read command is received by the command decoder 106, which provides an internal command so that the read data and parity from the memory array 118 are provided to the error correction circuit 120. The error correction circuit 120 detects and / or corrects errors in the data based on the parity. The corrected read data is output to the outside from the data terminal DQ via the input / output circuit 122.

[0032] Because the information in the array 118 may decay over time, the memory 100 performs refresh operations to maintain data integrity. The refresh operation may be in response to a command received from the controller 150 (e.g., auto-refresh or refresh management), in response to a command generated within the memory (e.g., self-refresh), or a combination thereof. A refresh signal REF, which may be generated internally or based on a command from the controller, may be used to control the timing of the refresh operation. In response to the refresh signal REF, the refresh control circuit 116 performs one or more refresh operations by issuing an internal refresh command and a refresh address RXADD. In response to the internal refresh command and the address RXADD, the row decoder 108 may refresh the memory cells along the word line associated with RXADD.

[0033] The refresh control circuit 116 may perform a sequential refresh operation or a targeted refresh operation. During a sequential refresh operation, a refresh address RXADD is generated based on refreshing the word lines of the array in sequence. For example, a counter circuit may increment the previous refresh address to generate the next refresh address. A sequential refresh operation may typically cycle through all addresses in the array 118 at a rate such that no information decay is expected.

[0034] Certain access patterns may increase the decay rate such that refreshes need to be performed faster than the rate of sequential refresh. For example, repeated accesses to a row or row hammering may increase the decay rate along memory cells near (e.g., adjacent) the hammered row. The accessed row may be referred to as an aggressor row, and the row with the increased decay rate may be referred to as a victim row. The refresh control circuit 116 includes logic to identify the aggressor row and generate a refresh address based on the victim row as part of a targeted refresh operation. The refresh control circuit 116 includes an identified aggressor queue, and when a targeted refresh operation is invoked (e.g., invoked by internal logic or due to a refresh management command from the controller 150), the refresh address of the victim row is calculated and provided as RXADD.

[0035] In an example embodiment, the memory device 100 may use per row hammer tracking (PRHT), where each row has an associated access count value XCount. Memory cells along each row, called counter memory cells 126, may be set aside for storing the count value XCount for that row. When that row is accessed (e.g., as part of a read or write operation), the value XCount is read out to the refresh control circuit (where Xcount is compared to a threshold), altered based on the comparison, and then written back to the counter memory cell 126. For example, if the count is below the threshold, the count value XCount may be incremented and then written back. If the count is at or above the threshold, the count value may be reset to an initial value (e.g., 0), and the row address XADD may be stored in the aggressor queue as an identified aggressor address. When a targeted refresh is performed, the address may be removed from the aggressor queue.

[0036] In an embodiment using error correction, the count value XCount may be read out together with one or more pieces of redundant information. The refresh address control circuit 116 may include a count error correction circuit. Based on the redundant information, when the count value XCount is read out to the refresh address control circuit 116, it may be corrected. For example, the refresh control circuit 116 may locate and correct errors in all or part of the count value XCount before updating the count value and determining that the updated count value has exceeded a threshold. The updated count value and the updated redundant information may be written back to the counter memory unit 126. In some embodiments, the count value in the counter memory unit 126 may also be protected by error correction, such as by strong redundant information in the counter memory unit (e.g., a redundant copy of all or part of the bits of the count value XCount) and / or by associating one or more count values ​​together with a set of parity bits and using the error correction circuit 120.

[0037] In a first example alarm type, the error correction circuit 120 may indicate that an error has been detected in the data read from the array 118. The error correction circuit 120 may provide an alarm signal of the first type to the alarm generator circuit 140. In some embodiments, the alarm signal of the first type may be provided in response to detecting any error. In some embodiments, the alarm signal of the first type may be provided in response to the error correction circuit 120 detecting a failure in the error correction operation (e.g., an error that cannot be corrected).

[0038] In a second example alarm type, the refresh control circuit 116 may provide a second type of alarm signal in response to a failure of error correction of one of the count values ​​XCount. For example, similar to the first type of alarm, the second type of alarm may be triggered by an error that is repaired and / or by an error in the count value that cannot be repaired.

[0039] In a third example alarm type, refresh control circuit 116 may provide a third type alarm signal in response to the aggressor queue becoming full. In response to being notified of the third type alarm, controller 150 may issue a refresh management (RFM) command, and in response to the RFM command, memory 100 performs a target refresh operation.

[0040] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder circuit 108, the internal potential VARY is mainly used in the sense amplifier SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0041] Power supply potentials VDDQ and VSSQ are also supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0042] Figure 22 is a set of timing diagrams representing different types of alarms that may be provided along an alarm bus. Timing diagrams 202-208 show different types of alarm signals along the alarm bus. For example, the alarm types represented by diagrams 202-208 may represent alarms generated by an alarm generator circuit (e.g., Figure 1 140) provides an alarm signal in response to determining that a fault is detected in the memory. Figures 202 to 208 represent a set of N different types of alarms that can be signaled along the alarm bus. The N different types of alarms can correspond to the N different types of faults that the memory can signal along the alarm bus.

[0043] Each of the graphs 202-208 shows the voltage along the ALERT bus (and the ALERT pin of the memory). Figure 2 In the example of , the Alert signal along the Alert bus may be inactive at a first voltage and may be active at a second voltage less than the first voltage. For comparison, each of the diagrams 202 to 208 is aligned so that the alert generator circuit drives the alert signal to an active level at the same time. Different types of alerts each have different pulse widths (e.g., different lengths of time that the alert signal is at an active level). The duration may be, for example, Figure 1 The alarm bus may be a single conductive element (e.g., a one-bit signal) in an example embodiment, different alarms will occur at different times rather than being aligned as shown.

[0044] Graph 202 shows a first type of alarm, Alert1, in which the alarm signal is at an active level for a duration between the maximum Category 1 pulse width CAT1_PW_max and the minimum Category 1 pulse width CAT1_PW_min. Graph 204 shows a second type of alarm, Alert2, in which the alarm signal is at an active level for a duration between CAT2_PW_max and CAT2_PW_min. Graph 206 shows an alarm of the (N-1)th type, in which the alarm signal is at an active level for a duration between CATn-1_PW_max and CATn-1_PW_min. Graph 208 shows an alarm of the Nth type, in which the alarm signal is at an active level for at least a duration CATn_PW_min.

[0045] If the timing of the alarm signal is not precisely synchronized with the clock signal, then a range of possible durations can be used to help prevent ambiguous signaling. Each type of alarm has a maximum duration that is shorter than the minimum duration of the alarm type with the next longest pulse width to prevent overlap and further reduce ambiguity. For example, the duration CAT2_PW_min is longer than the duration CAT1_PW_max, and the duration CATn_PW_min is longer than the duration CATn-1_PW_max. In some embodiments, a buffer time amount can be added between the ranges of different alarm types to further reduce ambiguity. For example, CAT2_PW_min can be set to CAT1_PW_max+buffer time.

[0046] In some embodiments, the memory may set the timing (e.g., based on the memory settings) to provide the alarm signal, and the controller may use the possible time range to distinguish the alarm type. For example, in response to the second type of alarm, the memory may provide the alarm signal within the time CAT2_PW between CAT2_PW_max and CAT_PW_min. The controller may detect that the alarm signal is valid for a duration higher than CAT2_PW_min but lower than CAT2_PW_max, and thus identify the alarm type as Alert2.

[0047] The alarm type with the longest pulse width (in this example, AlertN of FIG. 208) may be open ended. In other words, the alarm signal may be active for a duration of at least CATn_PW_min, but there may not be a specified maximum amount of time that the alarm signal is active for that type of alarm. Instead, the alarm signal may remain at an active level until a command is received from the controller (or host). The alarm signal may be returned to an inactive level in response to a command from the controller. For example, if the controller determines that the alarm signal has been in an active state for a period of time that reaches or exceeds CATn_PW_min, it may identify the alarm as AlertN and respond accordingly by providing a command.

[0048] Figure 3 3 is a block diagram of a memory system according to some embodiments of the present disclosure. Memory system 300 represents certain components of a controller 310 and a memory 320 that may be used to send and receive alarm signals along an alarm bus 302. In some embodiments, controller 310 may represent Figure 1 The controller 150 and the memory 320 may represent Figure 1 For clarity, from Figure 3 The view omits some signals and components. For example, Figure 3 For example, the previous discussion on Figure 1The example memory device 100 depicts components of a memory array, row and column decoders, clock input circuits, etc.

[0049] The controller 310 includes a clock signal CK (eg, Figure 1 CK and / or CK of the alarm bus 302) is provided to the clock generator circuit 314 of the clock terminal 308 of the memory 320. The memory 320 includes various alarm sources that can issue internal alarm detection signals, each of which is associated with a different type of alarm. In this example, three alarm detection signals are shown: Alert1, Alert2, and Alert3. The alarm generator circuit 322 of the memory 320 activates the alarm signal by driving the voltage of the alarm terminal 304 and the alarm bus 302 in response to one of the alarm detection signals. The alarm generator circuit 322 maintains the alarm signal at an effective level until the clock signal CK (and / or an internal clock signal derived therefrom, such as Figure 1 The controller 312 includes an alarm logic that monitors the voltage along the alarm bus 302 and begins counting clock cycles of CK when the alarm signal becomes active. Based on the count, the alarm logic 312 determines the type of alarm.

[0050] The clock generator circuit 318 of the controller 310 provides a periodic clock signal CK. The clock signal CK may represent a system clock signal provided directly by the clock generator 318 and / or one or more signals derived therefrom. The derived clock signal may have a fixed relationship with the system clock (e.g., half the frequency, twice the frequency, with a phase delay, etc.). For example, the memory 320 may generate one or more internal clock signals based on the clock signal CK received through the clock terminal 308. For clarity only, the clock signal CK may be represented by a clock signal CK. Figure 3 A single clock signal CK is discussed.

[0051] Controller 310 includes an alarm logic circuit 312 coupled to an alarm bus 302 (e.g., via an alarm terminal of controller 310). In some embodiments, the alarm bus 302 may be coupled to a plurality of memory devices. In some embodiments, the alarm bus 302 may be coupled to a single memory device, such as 320. The alarm logic circuit 312 monitors the voltage along the alarm bus 302 to determine the level of the alarm signal. When the voltage changes (e.g., when the alarm signal changes from an inactive to an active level), a counter circuit 314 of the alarm logic circuit 312 begins counting synchronously with the clock signal CK. For example, on each rising edge of the clock signal CK, the counter circuit 314 may increment the count value.

[0052] The alarm logic circuit 312 also includes a comparator circuit 316 that compares the count value to various thresholds or values. When the alarm signal drops to an invalid level (or if the count value exceeds a final threshold), the comparator circuit checks the count value against the threshold to determine the type of alarm signal. For example, if the count is between a first threshold and a second threshold (e.g., Figure 2 If the count is between the third threshold and the fourth threshold (e.g., Figure 2 If the count value is between CAT2_PW_min and CAT2_PW_max, then a second type of alarm may be determined. Comparator circuit 316 may compare the count to the final threshold even when the count value is still changing (e.g., when the alarm signal is still at an active level). If the count value is above the final threshold (e.g., Figure 2 If the CATn_PW_min is CATn_PW_min, the final alarm type can be determined, and the controller 310 can issue a command to the memory 320. Once the alarm type is determined, the count value of the counter circuit 314 can be reset to an initial value (eg, 0).

[0053] Memory 320 (eg, Figure 1 100) includes a plurality of alarm sources 324. The alarm sources 324 represent one or more components of the memory 320 that can generate a fault that can be signaled to the controller 310 along the alarm bus 302. Figure 3 In the example of , the alarm source 324 can identify 3 different types of faults and provide 3 different alarm detection signals Alert1, Alert2 and Alert3. In response to receiving one of the alarm detection signals, the alarm generator circuit 322 drives the voltage on the alarm pin 304 (and the alarm bus 302) to a voltage representing a valid alarm signal. The alarm generator circuit 322 includes a timing circuit 332 that determines the amount of time to keep the alarm signal valid based on the type of the alarm detection signal. For example, in response to the first alarm detection signal Alert1, the timing circuit 332 can count a first number of clock cycles (e.g., rising edges of CK), and once the first number of clock cycles has been counted, the timing circuit 322 switches the alarm signal back to an inactive level (e.g., drives the alarm terminal 304 to a voltage representing an inactive level). The first number of clock cycles can be between the first threshold and the second threshold of the comparator circuit 316. Similarly, in response to the second alarm detection signal Alert2, the timing circuit 332 may maintain the alarm signal as valid for a second number of clock cycles, wherein the second number is between the third and fourth thresholds. In response to the third alarm detection signal Alert3, the alarm generator circuit 322 may maintain the alarm signal at an effective level indefinitely until the memory 320 receives a command from the controller 310.

[0054] In an example embodiment, the alarm signal may be generated by the error correction circuit 326 (eg, Figure 1 120) and refresh control circuit 328 (for example, Figure 1 116). When an uncorrectable error is detected, the error correction circuit 326 may provide a first alarm detection signal Alert1. For example, the error correction circuit 326 is capable of correcting at most one error in the associated data bit. If there are more error bits, the error correction circuit 326 may not be able to locate (and therefore correct) those errors, and therefore provide the signal Alert1.

[0055] The refresh control circuit can provide two types of alarm detection signals Alert2 and Alert3. Figure 1 The count value of the counter memory unit 126 of the access counter) can be protected by an error correction or detection scheme (e.g., parity check, redundant bits, etc.). If there is an error in one (or more) of the counts that cannot be corrected by that error correction or detection scheme, the refresh control circuit 328 can provide a second type of alarm detection signal Alert2. The refresh control circuit 328 includes an aggressor queue 329, which stores identified aggressor addresses (e.g., based on the time when the access count exceeds a threshold). If the aggressor queue 329 becomes full, it may indicate that the row is becoming problematic faster than it is addressed with a target refresh operation. If the aggressor queue 329 is completely filled, additional aggressor addresses may be missed. Therefore, if the aggressor queue 329 becomes full (e.g., an address is loaded in the last empty position of the queue), the refresh control circuit 329 may issue a signal Alert3.

[0056] The controller 310 may take various actions based on the type of alarm detected by the alarm logic circuit 312. In response to some types of alarms, the controller may take no action. In response to some types of alarms, the controller 310 may suspend access operations to the memory, may perform additional access operations, may issue a mode register read operation to determine more details, and / or may issue a command. For example, in response to determining a first type of alarm (e.g., a failure in the error correction circuit 326), the controller may perform its own error correction to repair the data and / or may write the data to the memory 320 again to recover the data. In response to a second type of alarm (parity error in the count value), the controller 310 may take no action or slow down the rate at which access commands are issued. In response to a third type of alarm (full aggressor queue), the controller 310 may issue a refresh management command to the memory 320. In response to the refresh management command, the memory 320 may perform a targeted refresh operation.

[0057] In some embodiments, memory 320 may include a mode register 330. In response to one or more of the alarm detection signals Alert1 to Alert3, mode register 330 may store information about the alarm. For example, mode register 330 may store details about the detected fault, such as which row address is associated with the fault. In some cases, controller 310 may perform a mode register read operation to retrieve additional information about the fault.

[0058] Figure 4 is a timing diagram of alarm types according to some embodiments of the present disclosure. Figure 4 The timing diagram 400 may represent the operation of a memory device, such as Figure 1 and 3 In some example embodiments, the timing diagram may be Figure 2 . The timing diagram 400 shows an example embodiment using three types of alarms, one type of alarm indicating a failure in the error correction circuit (CRC error), one type of alarm representing an error correction failure in the counter memory cell (row counter RAS event) and one type of alarm representing an aggressor queue becoming full (RH mitigation event).

[0059] The timing diagram shows each of the three types of alarms aligned so that the alarm signals become active at the same time t0. The traces of the different types of alarms are shown aligned to allow comparisons between their durations. Because the alarm bus can be a single conductive element, each alarm type can be signaled at once (e.g., sequentially) rather than in parallel as shown.

[0060] Timing diagram 400 shows clock signals CK_t and CK_c (eg, Figure 1 CK and / or Figure 3 CK) and signals along the command / address bus. Three different alarms are shown, each representing the voltage of the alarm signal along the alarm bus. All three alarms start at a first time t0 when the alarm signal becomes valid (e.g., when the voltage on the alarm pin and the bus changes to a valid level). At a second time t1, the alarm signal returns to an invalid level to signal a first type of alarm - a CRC error. At a third time t2 after t1, the alarm signal returns to an invalid level to signal a second type of alarm - a row counter RAS event. At a fourth time t3 after t2, the alarm signal remains valid. Because the alarm signal is still valid, the controller issues a refresh management RFM command. At a fifth time t4, in response to executing the RFM command, the memory returns the alarm signal to an invalid level.

[0061] Figure 5is a flow chart of a method for providing multiple types of alarms along an alarm bus according to some embodiments of the present disclosure. In some embodiments, the method 500 may be stored in a memory device (e.g., Figure 1 100 and / or Figure 3 For example, method 500 may represent generating Figure 2 And / or the method of the alarm signal mode represented in 4.

[0062] Method 500 may generally begin at block 510, which describes detecting a first type of alarm or a second type of alarm. For example, the method may include determining that a first type of error has occurred and providing a first alarm detection signal or determining that a second type of error has occurred and providing a second alarm detection signal.

[0063] Block 510 is followed by block 520, which describes activating an alarm signal at a first time in response to detecting the first or second type of alarm. Method 500 may include activating the alarm signal by driving a voltage along an alarm terminal (or alarm pin) and an alarm bus to an active level. For example, an alarm generator circuit (e.g., Figure 1 140 and / or Figure 3 322) may receive the first or second alarm detection signal and begin providing an alarm signal at an active level in response to the first or second type of alarm detection signal.

[0064] Depending on the type of alarm, block 520 is followed by block 530 or block 540. Block 530 describes deactivating the alarm signal at a second time in response to an alarm of a first type. Block 540 describes deactivating the alarm signal at a third time in response to an alarm of a second type, wherein the third time is longer than the second time. Method 500 may include activating the alarm signal for a first pulse width in response to an alarm of the first type and activating the alarm signal for a second pulse width in response to an alarm of the second type.

[0065] In some embodiments, method 500 may include detecting a third type of alarm, activating an alarm signal at a first time in response to the third type of alarm, and maintaining the alarm signal at an active level until a command is received from a controller. For example, method 500 may include determining that the address is an aggressor address and adding it to an aggressor queue (e.g., Figure 3 329), detecting a third type of alarm based on the aggressor queue becoming full, receiving a refresh management command, deactivating the alarm signal in response to the refresh management command, and performing a target refresh operation in response to the refresh management command.

[0066] The method 500 may include receiving a clock signal (e.g., CK) from a controller and counting a number of cycles of the clock signal starting at a first time. The method 500 may include deactivating the alarm signal when the number of clock cycles reaches a first value when a first type of alarm is detected and deactivating the alarm signal when the number of clock cycles reaches a second value when a second type of alarm is detected.

[0067] Figure 6 is a flow chart of a method for determining the type of alarm along an alarm bus using a controller according to some embodiments of the present disclosure. In some embodiments, method 600 may be performed by Figure 1 The controller 150 and / or Figure 3 Method 600 may represent a method for determining different types of alarms based on the pulse width of an alarm signal, such as Figure 2 and 4 In some embodiments, method 600 may describe receiving a Figure 5 The signal generated by the method.

[0068] Method 600 may generally begin at block 610, which depicts detecting a valid signal along an alarm bus at a first time. Figure 3 302) may be coupled to an alert terminal or an alert pin of the memory. Method 600 may include determining that a voltage along the alert bus has exceeded a threshold. For example, if the alert signal is inactive at a first voltage and active at a second voltage lower than the first voltage, the method may include determining that the voltage has dropped below the threshold.

[0069] Block 610 may be followed by block 620, which describes counting the number of clock cycles while the signal is active. Method 600 may include beginning to count the number of clock cycles in response to detecting that the alarm signal has become active. Counting may include counting the number of clock cycles in response to each cycle of the clock signal (e.g., each rising edge of the clock signal), for example, with Figure 3 The counter circuit 314 of the method 600 may change the count value (e.g., by incrementing it). Figure 3 The comparator circuit 316 of FIG. 310 compares the count value to a threshold value to determine whether the method should proceed to block 630 or to block 660. If the count of clock cycles is below the threshold value when the alarm signal becomes inactive, block 620 may be followed by block 630. If the count value exceeds the threshold value, block 620 may be followed by block 660.

[0070] Block 630 describes stopping the count when the alarm signal becomes inactive. For example, method 600 may include determining that the voltage on the alarm bus has exceeded an inactive level. In some embodiments, the method may include determining that the voltage is above a threshold voltage. When stopping the count value, method 600 may include comparing the stopped count value to a number of thresholds. Method 600 may include determining the alarm type based on the comparison of the stopped count value to the threshold. Figure 6 Shows two different instance alert types.

[0071] Depending on the count value, block 630 may be followed by block 640 or block 650. Block 640 describes determining a first type of alarm when the count is between a first value and a second value. Block 650 describes determining a second type of alarm when the count is between a third value and a fourth value. The second value (e.g., Figure 2 CAT1_PW_max) may be greater than the first value (eg, Figure 2 CAT1_PW_min), a third value (e.g., Figure 2 CAT2_PW_min) may be greater than the second value, and the fourth value (eg, Figure 2 CAT2_PW_max) may be greater than the third value.

[0072] If the count of clock cycles exceeds the threshold while the alarm signal is still asserted, block 620 may be followed by block 660, which describes when the count is above a fifth value (eg, Figure 2 The method 600 may include providing a command to the memory in response to determining the third type of alarm. The method 600 may include returning the alarm signal to an inactive level in response to the command.

[0073] The method 600 may include taking one or more actions based on the determined alarm type.In some embodiments, the method 600 may include performing a mode register read operation on a mode register of a memory to retrieve additional information based on the alarm type.

[0074] It should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes and / or may be separated and / or performed in separate devices or device portions according to the systems, devices, and methods of the present invention.

[0075] Finally, the above discussion is intended to be merely illustrative of the inventive system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the inventive system has been described in particular detail with reference to exemplary embodiments, it should be appreciated that numerous modifications and alternative embodiments may be devised by one of ordinary skill in the art without departing from the broader and intended spirit and scope of the inventive system as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: Alarm terminal; at least one alarm source circuit configured to provide a first alarm detection signal in response to an alarm of a first type or to provide a second alarm detection signal in response to an alarm of a second type; and An alarm generator circuit is configured to provide an alarm signal to the alarm terminal at an active level for a first duration in response to the first alarm detection signal or to provide the alarm signal to the alarm terminal at the active level for a second duration in response to the second alarm detection signal.

2. An apparatus according to claim 1, wherein the at least one alarm source circuit is further configured to provide a third alarm detection signal, and wherein in response to the third alarm detection signal, the alarm generator circuit is further configured to provide the alarm signal to the alarm terminal at the effective level until a command is received.

3. The apparatus according to claim 1, further comprising: a clock terminal configured to receive a clock signal, Wherein the alert generator circuit includes a timing circuit configured to determine the first duration and the second duration based in part on a number of cycles of the clock signal. 4 . The apparatus of claim 1 , further comprising a mode register, wherein in response to the first alarm detection signal, the mode register is configured to store information about the first type of alarm.

5. The apparatus of claim 1, further comprising: a memory array configured to store data bits and associated parity bits; and An error correction circuit is configured to correct the data bit based on the associated parity bit and to provide the first alert detection signal in response to determining that the data bit includes an error that cannot be corrected by the error correction circuit.

6. The apparatus of claim 1, further comprising: a memory array comprising a plurality of word lines, each of which is associated with a respective row address and a count value; and A refresh control circuit is configured to determine that one of the plurality of word lines is an aggressor row based on the corresponding count value and to store the corresponding row address in an aggressor queue, wherein the refresh control circuit is configured to provide the second alarm detection signal in response to detecting an error in the corresponding count value and is configured to provide a third alarm detection signal in response to the aggressor queue being full. The apparatus of claim 1 , wherein the alarm terminal is coupled to a controller via an alarm bus.

8. A system comprising: Alarm bus; a memory configured to provide an alarm signal along the alarm bus at an active level for a period of time; and A controller is configured to determine a duration of the time period and to determine an alarm type based on the duration of the alarm signal.

9. The system of claim 8, further comprising a clock bus, wherein the controller further comprises a clock generator circuit configured to provide a clock signal along the clock bus, and Wherein the memory is configured to provide the alarm signal at the active level for a number of cycles of the clock signal, wherein the number is based on the alarm type.

10. The system of claim 9, wherein the controller includes an alarm logic circuit configured to count the number of the cycles of the clock signal that start when the alarm signal changes to the active level and end when the alarm signal changes to an inactive level.

11. The system of claim 8, wherein the controller includes alarm logic circuitry configured to determine a first type of alarm when the time period is between a first value and a second value, and to determine a second type of alarm when the time period is between a third value and a fourth value, wherein the second value is longer than the first value, the third value is longer than the second value, and the fourth value is longer than the third value.

12. The system of claim 11, wherein the alarm logic circuit is further configured to determine a third type of alarm when the alarm signal remains at the active level for longer than a fifth value, wherein the fifth value is longer than the fourth value.

13. The system of claim 12, wherein in response to the determination of the third type of alarm, the controller is configured to provide a command to the memory, and wherein in response to the command, the memory is configured to provide the alarm signal at an invalid level.

14. The system of claim 8, wherein the memory includes a mode register, and wherein the controller is configured to perform a mode register read operation on the mode register in response to a first type of alert signal.

15. A method comprising: detecting a first type of alarm or a second type of alarm; activating an alarm signal at a first time in response to an alarm of the first type or the second type; deactivating the alarm signal at a second time in response to the first type of alarm; and The alarm signal is deactivated at a third time in response to the second type of alarm, wherein the third time is after the second time.

16. The method according to claim 15, further comprising: detecting a third type of alarm; activating the alarm signal at the first time in response to the third type of alarm; and The alarm signal is maintained at the active level until a command is received from a controller.

17. The method according to claim 16, further comprising: Determine that the address is an aggressor address and add it to the aggressor queue; detecting the third type of alarm based on the aggressor queue becoming full; Receive refresh management command; deactivating the alarm signal in response to the refresh management command; and A target refresh operation is performed in response to the refresh management command.

18. The method of claim 15, further comprising: receiving a clock signal; counting a number of clock cycles starting at the first time; deactivating said alarm signal when said number of clock cycles reaches a first value in response to an alarm of said first type; and The alarm signal is deactivated when the number of clock cycles reaches a second value in response to the second type of alarm.

19. The method of claim 15, further comprising: detecting said alarm signal being at said effective level; counting the time that the alarm signal is at the effective level; and The alarm type is determined based on the time.

20. The method of claim 19, further comprising: A command is provided in response to determining that the count is above a threshold and the alarm signal is still at the active level.

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